TWI353111B - Programmable integrated microphone interface circu - Google Patents

Programmable integrated microphone interface circu Download PDF

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Publication number
TWI353111B
TWI353111B TW97104269A TW97104269A TWI353111B TW I353111 B TWI353111 B TW I353111B TW 97104269 A TW97104269 A TW 97104269A TW 97104269 A TW97104269 A TW 97104269A TW I353111 B TWI353111 B TW I353111B
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TW
Taiwan
Prior art keywords
circuit
input
output
feedback
amplifier
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TW97104269A
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Chinese (zh)
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TW200935735A (en
Inventor
Holzmann Peter
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Nuvoton Technology Corp
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Priority to TW97104269A priority Critical patent/TWI353111B/en
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Publication of TWI353111B publication Critical patent/TWI353111B/en

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  • Circuit For Audible Band Transducer (AREA)
  • Amplifiers (AREA)
  • Electrostatic, Electromagnetic, Magneto- Strictive, And Variable-Resistance Transducers (AREA)

Description

96U003 26630twf.doc/n 九、發明說明： 本申請案主張於2007年6月12日 專利申請請-顧咖的優先權1專= 之内容係完整結合於本說明書中。 Θ/、斤揭路 【發明所屬之技術領域】 本發明是關於-種積體電路。更明續地說，本發明提 供-種關於麥克風介面之積體電路的方法以及裝置。 【先前技術】 *聲音以及音訊頻帶應用常常使用麥克風來自環境接收 聲音或音減量且將其轉變成電壓或電流。有―種很暢鎖 的麥克風稱為駐極體f容（eleetfeteGndenser)”型麥克 風。此麥克風通常需要直流偏壓（DCbias)來操作。圖i 中展示了習知CODEC麥克風介面電路實例之示意圖。如 圖所示，駐極體麥克風102常常需要許多晶片外（〇ff_chip) 組件來與CODEC積體電路15〇介接。舉例而言’以用於 具雜訊之DC偏壓以及電源濾波之電阻U2以及電阻ι14 以及電谷122來對麥克風1〇2加偏壓。增益級常常用於與 CODEC晶>} 150介接。在圖1中，增益級包括離散組件 (discrete components)，諸如，電容 142、電容 144、電容 146以及電容148，以及電阻132、電阻134、電阻136以 及電阻138。儘管習知介面電路技術已被廣泛使用，但其 受到許多限制，如下文更詳細論述。 因此，需要一種用於麥克風介面電路之改良的技術。 【發明内容】 1353111 96U003 26630twf.doc/n 本發明是關於積體電路。更明確地說，本發明提供一 ，關於麥克風介面之積體電路的方法以及裝置。僅以實例 •祝明之’本發明已被應用至駐極體麥克風之介面電路。但 •應體認到，本發明具有賴更加廣泛之適祕。舉例而言， 可將本發明應用至其他種類之麥克風之介面電路或其他信 號源之介面電路。 根據本發明之實施例，提供一種用於麥克風介面之積 # 體電路。積體電路包括用於接收輸入信號之輸入端子、用 於提供輸出之輸出端子以及偏壓電路。偏壓電路輛接 ^輸入端子以用於在輸入端子處提供偏壓信號且經配置以 提供感測輸入信號。積體電路亦包括具有第一輸入端、第 二輸入端以及輸出端的第一放大器電路。第一輸入端經配 置以接收感測輸入信號、第一反饋信號以及第二反饋信 號。第二輸入端經配置以接收第一參考信號，且輸出端經 配置以將輸出信號提供至輸出端子。積體電路亦包括兩個 φ f饋電路。第一反饋電路與第一放大器電路之輸出端以及 第一輸入端連通且將第一反饋信號提供至第—放大器電路 之第一輸入端。第二反饋電路與第一放大器電路之輸出端 以及第一輸入端連通且將第二反饋信號提供至第一放大器 電路之第一輸入端。第二反饋電路更包括積分器電路 (integrator circuit)。 • 在積體電路之特定實施例中，輸入端子經配置以在無 需外部組件的情況下自駐極體麥克風接收輸入信號。在實 施例中，偏壓電路包括用於提供第二參考信號之參考電 6 1353111 96U003 26630twf.doc/n 以及 號可為參考電壓或參考電流。偏壓電路包 t輸入端子以及參考電路連通之第—輸人端電阻以 [輪入端子以及第-放大器電路之第二輸人端連通之第 輸入端電阻。 …在某些實施例中，第-反饋電路包括處於並聯配置之 弟一反饋電㈣及第-反饋電容。在—些實_中，積分 裔電路包括祕至第-放大器電路之輸出賴反相放大器96U003 26630twf.doc/n IX. INSTRUCTIONS: This application claims to be filed on June 12, 2007. The content of the patent application - Gu Kai's priority 1 special = is fully integrated in this specification. Θ/, 斤揭路 [Technical Field of the Invention] The present invention relates to an integrated circuit. More specifically, the present invention provides a method and apparatus for an integrated circuit for a microphone interface. [Prior Art] * Sound and audio band applications often use a microphone to receive sound or tone reduction from the environment and convert it to voltage or current. There is a very sturdy microphone called the electret fendenser type microphone. This microphone usually requires DC bias to operate. Figure i shows a schematic diagram of a conventional CODEC microphone interface circuit. As shown, the electret microphone 102 often requires a number of off-chip (〇ff_chip) components to interface with the CODEC integrated circuit 15. For example, 'resistance for DC bias and power supply filtering with noise. U2 and resistor ι14 and valley 122 bias the microphone 1〇2. The gain stage is often used to interface with the CODEC crystal>} 150. In Figure 1, the gain stage includes discrete components, such as Capacitor 142, capacitor 144, capacitor 146, and capacitor 148, as well as resistor 132, resistor 134, resistor 136, and resistor 138. Although conventional interface circuit technology has been widely used, it suffers from a number of limitations, as discussed in more detail below. There is a need for an improved technique for a microphone interface circuit. [Abstract] 1353111 96U003 26630twf.doc/n The present invention relates to an integrated circuit. More specifically, the present invention A method and apparatus for an integrated circuit of a microphone interface are provided. By way of example only, the present invention has been applied to an interface circuit of an electret microphone. However, it should be recognized that the present invention has a broader scope. For example, the present invention can be applied to interface circuits of other types of microphones or interface circuits of other signal sources. According to an embodiment of the present invention, an integrated circuit for a microphone interface is provided. An input terminal for receiving an input signal, an output terminal for providing an output, and a bias circuit. The bias circuit is coupled to the input terminal for providing a bias signal at the input terminal and configured to provide sensing The input signal also includes a first amplifier circuit having a first input, a second input, and an output. The first input is configured to receive the sensed input signal, the first feedback signal, and the second feedback signal. The two inputs are configured to receive the first reference signal, and the output is configured to provide an output signal to the output terminal. And comprising two φ f feed circuits. The first feedback circuit is connected to the output end of the first amplifier circuit and the first input end and provides the first feedback signal to the first input end of the first amplifier circuit. The second feedback circuit and the An output of the amplifier circuit is coupled to the first input and provides a second feedback signal to the first input of the first amplifier circuit. The second feedback circuit further includes an integrator circuit. In a particular embodiment, the input terminal is configured to receive an input signal from the electret microphone without the need for an external component. In an embodiment, the biasing circuit includes a reference electrical source for providing a second reference signal 6 1353111 96U003 26630twf The .doc/n and number can be reference voltage or reference current. The bias circuit package t input terminal and the first-input terminal resistance of the reference circuit are connected to the [input terminal and the first input terminal of the first input terminal of the first amplifier circuit. ... In some embodiments, the first feedback circuit includes a feedback (four) and a feedback capacitor in a parallel configuration. In some real _, the integrated circuit includes an output to the amp-amplifier circuit

(mVertmgamplifier)以及第二放大器電路。第二放大器電 路包括第-輸人端、第二輸人端以及輸出端。第二輸入端 ，接至第三參考信號。第—反饋電路亦包純接至單位增 放，相放大器之輸出端以及第二放大器電路之第一輸入端 的第二反饋電阻，以及耦接至第二放大器電路之第一輸入 以及輸出如的苐一反饋電容。在實施例中，第二放大器 電路之輸出端經由第三反饋電阻耦接至第一放大器電路: 第二輸入端。(mVertmgamplifier) and a second amplifier circuit. The second amplifier circuit includes a first-input terminal, a second input terminal, and an output terminal. The second input is connected to the third reference signal. The first feedback circuit is also coupled to the unit add/drop, the output of the phase amplifier and the second feedback resistor of the first input of the second amplifier circuit, and the first input and output coupled to the second amplifier circuit. A feedback capacitor. In an embodiment, the output of the second amplifier circuit is coupled to the first amplifier circuit via a third feedback resistor: a second input.

在一些實施例中，積分器電路包括開關式電容電路 (switched capacitor circuit)以及第二放大器電路。開關式 電谷電路包括開關電谷（switch capacitor )以及第一開關、 第二開關、第三開關以及第四開關。第一開關以及第二開 關麵接至開關電容之第一端子，而第三開關以及第四開關 耗接至開關電容之第二端子。此外，第二開關以及第四開 關耦接至第一參考信號。第二放大器電路包括第一輸入 端、第二輸入端以及輸出端。第一輸入端與開關式電容電 路之第三開關連通。第二輸入端耦接至第一參考信號。第 7 1353111 96U003 26630twf.doc/n :==_包::::放大器電路之第-輪，及 在實施射，積體電路亦包括供 號大小上為供應m半以用於提 ^ 應電愿允許的最大信號擺動。在竿 I' 处由供 之特徵由DC迴路増益表示二;=足=In some embodiments, the integrator circuit includes a switched capacitor circuit and a second amplifier circuit. The switch type electric valley circuit includes a switch power switch and a first switch, a second switch, a third switch, and a fourth switch. The first switch and the second switch face are connected to the first terminal of the switched capacitor, and the third switch and the fourth switch are connected to the second terminal of the switched capacitor. In addition, the second switch and the fourth switch are coupled to the first reference signal. The second amplifier circuit includes a first input, a second input, and an output. The first input is in communication with a third switch of the switched capacitor circuit. The second input is coupled to the first reference signal. 7 1353111 96U003 26630twf.doc/n :==_包:::: The first round of the amplifier circuit, and in the implementation of the shot, the integrated circuit also includes the supply size for the supply of half of the half for the power supply The maximum signal swing that is allowed. The feature at 竿 I' is represented by the DC circuit; 2 ==

二:實質上等於第-參考電壓。在 =ί範圍中的Dc迴路增益表示。在-些實施例ΐ =電路之賴由大Dc迴路增益以及低交流（AC)迴路 '曰:表示從而引起輸出端子處之DC輸出電壓實質上 於第=參考電壓’且AC輸出電壓與第一反饋電路之阻抗 以及Ik過輪人端子之AC輪入電流或電壓成線性比例。在 ^-實施例令’偏壓電路提供可程式電壓或電流參考，且 第一反饋電阻以及第二反饋電阻為可程式的。Two: substantially equal to the first reference voltage. The Dc loop gain is represented in the =ί range. In some embodiments ΐ = the circuit depends on the large Dc loop gain and the low alternating current (AC) loop '曰: indicates that the DC output voltage at the output terminal is substantially at the = reference voltage' and the AC output voltage is first The impedance of the feedback circuit and the AC wheel current or voltage of the Ik wheel terminal are linearly proportional. The bias voltage circuit provides a programmable voltage or current reference in the ^-embodiment, and the first feedback resistor and the second feedback resistor are programmable.

根據本發明之另一實施例，用於提供麥克風介面之積 體電路包括分別用於接收第一差動輸入信號 (differential ipmt signal)以及第二差動輸入信號的第一輸入端子以及 第=輸入端子。積體電路亦包括分別用於提供第一差動輸 出心號（differential output signal)以及第二差動輸出信號 的第一輸出端子以及第二輸出端子。積體電路更包括兩個 偏壓電路。第一偏壓電路與第一輸入端子以及第一參考信 號連通’且提供第—感測輸入信號。第二偏壓電路與第二 輸入端子以及第二參考信號連通，且提供第二感測輸入信 8 96U003 26630twf.doc/n 號。積體電路更包括具有第一輸入端、第二輸入端以及第 三輸入端的第一放大器電路。第一輸入端接收第一感測輸 入信號，第二輸入端接收第二感測輸入信號，且第三輸入 端接收共同模式參考信號（common-mode reference signal)。第一放大器電路亦具有第一輸出端以及第二輸出 端。第一輸出端以及第二輸出端分別將第一差動輸出音訊 信號以及第二差動輸出音訊信號提供至第一輸出端子以及 第二輸出端子。此外，積體電路包括反饋電路，反饋電路 與第一放大器電路之第一輸入端以及第二輸入端以及第— 輸出端以及第二輸出端連通。 在特定實施例中，第一輸入端子以及第二輸入端子經 配置以自駐極體麥克風接收輸入信號。在實施例中，第— 偏壓電路包括與第一輸入端子以及麥克風參考信號源連通 之第三電阻以及與第一輸入端子以及第三電阻連通之第四 電阻，第四電阻提供第一感測輸入信號。在實施例中，第 二偏壓電路包括與第二輸入端子以及接地參考電壓源連通 之第五電阻，以及與第二輸入端子以及第五電阻連通之第 六電阻，第六電阻提供第二感測輸入信號。 在一些實施例中，反饋電路亦包括三個反饋電路。第 一反饋電路與第一放大器之第一輸出端以及第一輸入端連 通。在特定實例中，第一反饋電路包括並聯連接之第一電 =以及第一電容。第二反饋電路與第一放大器之第二輪出 =以及第二輪入端連通。在實例中，第二反饋電路包括並 聯連接之第二電阻以及第二電容。在實施例中，第三反饋 96U003 26630twf.doc/n 電路為差動反饋電路。差動反饋電路包括分別耦接至第一 放大器電路之第—輸出端以及第二輸出端之第一輸入端以 及第二輪入端。差動反饋電路亦包括分別耦接至第一放大 器電路之第一輸入端以及第二輸入端之第一輸出端以及第 '一輸出端。 在特定實施例中，差動反饋電路更包括以下組件。差 動放大器包括第一輪入端、第二輸入端以及第三輸入端， 以及第一輸出端以及第二輸出端。第三輸入端接收共同模 式參考信號。第一電阻連接至差動放大器之第一輸入端。 第一電阻連接至差動放大器之第一輸出端。第一電容連接 差動放大器之第一輸入端與第一輸出端。第三電阻連接至 差動放大器之第二輸入端。第四電阻連接至差動放大器之 苐一輸出端。弟二電容連接差動放大器之第二輸入端與第 二輸出端。在實施例中，積體電路亦包括供應電壓。共同 模式參考信號大小上為供應電壓之約一半以用於提供輸出 端子處由供應電壓允許的最大信號擺動。 根據本發明之替代性實施例，用於麥克風介面之積體 電路包括用於接收輸入信號的輸入端子、用於提供輸出信 唬的輸出端子以及用於提供偏壓信號的可程式參考電路。 積體電路亦包括具有第一輸入端、第二輸入端，以及輸出 端的第一放大器電路。第一輸入端經配置以接收偏壓信 號、第一反饋信號，以及第二反饋信號。第二輸入端經配 置以接收第一參考信號。輸出端經配置以提供輸出信號至 輸出端子。積體電路更包括兩個反饋電路。第一反饋電路 96U003 26630twf.doc/n 與第-放大5電路之輸出端以及第—輸人端連通且將第 一反饋信號提供至第—放大器電路之第—輸人端。第二反 饋電路與帛纟大器電路之輪出端以及第—輸人端連通， ^將第二反饋信號提供至第—放大器電路之第—輸入端。 弟二反饋電路亦包括積分器電路。 在以上積體電路之特定實施例中，輸入端子經配置以 在無需外部組件的情況下自駐極體麥克風接收輸入信號。 在實施=中’偏壓電路包括用於提供第二參考信號之參考 電路第—參考彳3號可為參考電壓或參考電流。偏壓電路 包括與輸人端子以及參考電路連通之第—輸人端電阻，以 及與輸入端子以及第一放大器電路之第二輸入端連通之第 二輪入端電阻。 ^在某些實施例中，第一反饋電路包括處於並聯配置之 第一反饋電阻以及第一反饋電容。在一些實施例中，積分 β電路包括耦接至第一放大器電路之輸出端的反相放大器 以及第二放大器電路。第二放大器電路包括第一輸入端、 U第二輸入端以及輸出端。第二輸入端耦接至第三參考信 號。第一反饋電路亦包括耦接至單位增益反相放大器之輸 出端以及第二放大器電路之第一輸入端的第二反饋電阻， 以及耦接至第二放大器電路之第一輸入端以及輸出端的第 二反饋電容。在實施例中，第二放大器電路之輸出端經由 第三反饋電阻耦接至第一放大器電路之第二輸入端。 在一些實施例中’積分器電路包括開關式電容電路以 及第二放大器電路。開關式電容電路包括開關電容以及第 1353111 96U003 26630twf.doc/n -開關、第二開關、第三開關以及第四開關。第一開關以 及第二開_接至開關電容之第一端子，而第三開關以及 第四開_接至開關電容之第二端子。此外，第二開關以 及第四開關耦接至第一參考信號。第二放大器電路包括第 一輸入端、弟二輸入端以及輸出端。第一輸入端與開關式 ，容電路之第三開關連通。第二輸入端耦接至第一參考信 號。第二放大器電路亦包括與第二放大器電路之第一輸入 以及輸出端連通的第二反饋電容。 在實施例中，積體電路亦包括供應電壓。第一參考信 唬大小為供應電壓之約一半以用於提供輸出端子處由供應 電壓允許的最大信號擺動。在某些實施例中，積體電路之 特徵由DC迴路增盈表示’DC迴路增益大到足以引起第一 放大器之輸出端處之電壓實質上等於第一參考電壓。在特 定實例中’積體麥克風介面電路之特徵由約8〇dB至約14〇 dB之範圍中的DC迴路增益表示。在一些實施例中，積體 電路之特徵由大DC迴路增益以及低AC迴路增益表示， 從而引起輸出端子處之DC輸出電壓實質上等於第一參考 電壓，且AC輸出電壓與第一反饋電路之阻抗以及經過輸 入端子之AC輸入電流或電壓成線性比例。在另一實施例 中’偏壓電路提供可程式電壓或電流參考，且第一反饋電 阻以及第二反饋電阻為可程式的。 在特定實施例中，本發明提供一種用於提供可程式麥 克風介面之積體電路。積體電路包括用於接收輸入信號之 輸入端子以及用於提供輸出音訊信號之輸出端子。積體電 12 1353111 96U003 26630twf.doc/n 路包括與輸入端子連通之偏壓電路。積體電路亦包括第一 放大器電路以及多個反饋電路。舉例而言’在實施例中， 積體電路包括兩個反饋電路。第一放大器電路包括第一輸According to another embodiment of the present invention, an integrated circuit for providing a microphone interface includes a first input terminal and a third input for respectively receiving a first differential input signal and a second differential input signal. Terminal. The integrated circuit also includes a first output terminal and a second output terminal for providing a first differential output signal and a second differential output signal, respectively. The integrated circuit further includes two bias circuits. The first bias circuit is coupled to the first input terminal and the first reference signal and provides a first sense input signal. The second bias circuit is in communication with the second input terminal and the second reference signal and provides a second sense input signal 8 96U003 26630twf.doc/n number. The integrated circuit further includes a first amplifier circuit having a first input, a second input, and a third input. The first input receives the first sensed input signal, the second input receives the second sensed input signal, and the third input receives the common-mode reference signal. The first amplifier circuit also has a first output and a second output. The first output end and the second output end respectively provide the first differential output audio signal and the second differential output audio signal to the first output terminal and the second output terminal. In addition, the integrated circuit includes a feedback circuit that is in communication with the first input and the second input of the first amplifier circuit and the first output and the second output. In a particular embodiment, the first input terminal and the second input terminal are configured to receive an input signal from an electret microphone. In an embodiment, the first bias circuit includes a third resistor in communication with the first input terminal and the microphone reference signal source, and a fourth resistor in communication with the first input terminal and the third resistor, the fourth resistor providing a first sense Measure the input signal. In an embodiment, the second bias circuit includes a fifth resistor in communication with the second input terminal and the ground reference voltage source, and a sixth resistor in communication with the second input terminal and the fifth resistor, the sixth resistor providing the second resistor Sensing the input signal. In some embodiments, the feedback circuit also includes three feedback circuits. The first feedback circuit is in communication with the first output of the first amplifier and the first input. In a particular example, the first feedback circuit includes a first electrical connection = and a first capacitance connected in parallel. The second feedback circuit is in communication with the second wheel of the first amplifier and the second wheel. In an example, the second feedback circuit includes a second resistor and a second capacitor connected in parallel. In an embodiment, the third feedback 96U003 26630twf.doc/n circuit is a differential feedback circuit. The differential feedback circuit includes a first input terminal coupled to the first output terminal and the second output terminal of the first amplifier circuit, and a second wheel input terminal. The differential feedback circuit also includes a first output terminal coupled to the first input terminal and the second input terminal of the first amplifier circuit, and a first output terminal. In a particular embodiment, the differential feedback circuit further includes the following components. The differential amplifier includes a first wheel input end, a second input end, and a third input end, and a first output end and a second output end. The third input receives the common mode reference signal. The first resistor is coupled to the first input of the differential amplifier. The first resistor is coupled to the first output of the differential amplifier. The first capacitor is coupled to the first input of the differential amplifier and the first output. A third resistor is coupled to the second input of the differential amplifier. The fourth resistor is coupled to the first output of the differential amplifier. The second capacitor is connected to the second input terminal and the second output terminal of the differential amplifier. In an embodiment, the integrated circuit also includes a supply voltage. The common mode reference signal is approximately half the supply voltage in size to provide the maximum signal swing allowed by the supply voltage at the output terminal. In accordance with an alternative embodiment of the present invention, an integrated circuit for a microphone interface includes an input terminal for receiving an input signal, an output terminal for providing an output signal, and a programmable reference circuit for providing a bias signal. The integrated circuit also includes a first amplifier circuit having a first input, a second input, and an output. The first input is configured to receive a bias signal, a first feedback signal, and a second feedback signal. The second input is configured to receive the first reference signal. The output is configured to provide an output signal to the output terminal. The integrated circuit further includes two feedback circuits. The first feedback circuit 96U003 26630twf.doc/n is in communication with the output of the first-amplifier 5 circuit and the first-input terminal and provides a first feedback signal to the first input terminal of the first amplifier circuit. The second feedback circuit is connected to the wheel terminal of the amplifier circuit and the first input terminal, and the second feedback signal is supplied to the first input terminal of the first amplifier circuit. The second feedback circuit also includes an integrator circuit. In a particular embodiment of the above integrated circuit, the input terminal is configured to receive an input signal from the electret microphone without the need for external components. In the implementation = middle bias circuit includes a reference circuit for providing a second reference signal - reference numeral 3 may be a reference voltage or a reference current. The biasing circuit includes a first input terminal resistance in communication with the input terminal and the reference circuit, and a second wheel end resistance in communication with the input terminal and the second input of the first amplifier circuit. In some embodiments, the first feedback circuit includes a first feedback resistor in a parallel configuration and a first feedback capacitor. In some embodiments, the integrated beta circuit includes an inverting amplifier coupled to the output of the first amplifier circuit and a second amplifier circuit. The second amplifier circuit includes a first input, a U second input, and an output. The second input is coupled to the third reference signal. The first feedback circuit also includes a second feedback resistor coupled to the output of the unity gain inverting amplifier and the first input of the second amplifier circuit, and a second input coupled to the first input of the second amplifier circuit and the output Feedback capacitor. In an embodiment, the output of the second amplifier circuit is coupled to the second input of the first amplifier circuit via a third feedback resistor. In some embodiments the 'integrator circuit includes a switched capacitor circuit and a second amplifier circuit. The switched capacitor circuit includes a switched capacitor and a 1353111 96U003 26630twf.doc/n-switch, a second switch, a third switch, and a fourth switch. The first switch and the second switch are connected to the first terminal of the switched capacitor, and the third switch and the fourth switch are connected to the second terminal of the switched capacitor. In addition, the second switch and the fourth switch are coupled to the first reference signal. The second amplifier circuit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is in communication with the switch mode and the third switch of the capacitor circuit. The second input is coupled to the first reference signal. The second amplifier circuit also includes a second feedback capacitor in communication with the first input and output of the second amplifier circuit. In an embodiment, the integrated circuit also includes a supply voltage. The first reference signal size is approximately half of the supply voltage for providing the maximum signal swing allowed by the supply voltage at the output terminals. In some embodiments, the characteristic of the integrated circuit is represented by a DC loop gain indicating that the DC loop gain is large enough to cause the voltage at the output of the first amplifier to be substantially equal to the first reference voltage. In a particular example, the feature of the integrated microphone interface circuit is represented by a DC loop gain in the range of about 8 〇 dB to about 14 〇 dB. In some embodiments, the characteristics of the integrated circuit are represented by a large DC loop gain and a low AC loop gain, thereby causing the DC output voltage at the output terminal to be substantially equal to the first reference voltage, and the AC output voltage is coupled to the first feedback circuit. The impedance and the AC input current or voltage through the input terminals are linearly proportional. In another embodiment, the bias circuit provides a programmable voltage or current reference, and the first feedback resistor and the second feedback resistor are programmable. In a particular embodiment, the present invention provides an integrated circuit for providing a programmable microphone interface. The integrated circuit includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. Integrated body 12 1353111 96U003 26630twf.doc/n The circuit includes a bias circuit in communication with the input terminal. The integrated circuit also includes a first amplifier circuit and a plurality of feedback circuits. For example, in an embodiment, the integrated circuit includes two feedback circuits. The first amplifier circuit includes a first input

入端、第二輸入端以及輸出端。在第一放大器中，第一輪 入端與第一反饋電路連通，此外，可經程式以接收輸入信 號或反饋信號。舉例而言，第一輸入端回應於第一模式控 制信號（mode control signal)接收輸入信號以及回應於第 二模式控制信號接收反饋信號。第二輸入端回應於第一模 式控制信號接收反饋信號以及回應於第二模式控制信號接 收輸入信號。輸出端將輸出信號提供至輸出端子。第一反 饋電路與第一放大器之輸出端以及第一輸入端連通，且第 一反饋電路包括並聯連接之第一電阻以及第一電容。第二 反饋電路包括與第一放大器電路之輸出端連通的積分器電 路°第二反饋電路提供反饋信號。Incoming, second input, and output. In the first amplifier, the first in turn is in communication with the first feedback circuit and, in addition, is programmed to receive an input signal or a feedback signal. For example, the first input receives the input signal in response to the first mode control signal and receives the feedback signal in response to the second mode control signal. The second input receives the feedback signal in response to the first mode control signal and receives the input signal in response to the second mode control signal. The output provides an output signal to the output terminal. The first feedback circuit is in communication with the output of the first amplifier and the first input, and the first feedback circuit includes a first resistor and a first capacitor connected in parallel. The second feedback circuit includes an integrator circuit in communication with the output of the first amplifier circuit. The second feedback circuit provides a feedback signal.

在積體電路之實施例中，積分器包括開關式電容, 路二放大器以及電容。開關式電容電路包括第二電容以及 第-開關、第二開關、第三開關以及第四開關。第一_ 以5第二開關耦接至第二電容之第—端子，且第三開關。 一第四開關搞接至第—電谷之第二端子。第—開關以及筹 回應第_脈彳§號’且第二開關以及第四開關回肩 以二！號。放大器電路包括第—輪人端、第二輸入轉 六雷2 :。第一輸入端以及第二輪入端分別與開關式零 ς電2第三開關以及第四開關連通，且第二輸入端亦途 第-，考魏信號連通。第三電容與故大器之第一輸入雜 13 1353111 96U003 26630twf.doc/n 以及輸出端連通。在實施例中，第二參考電壓信號為供應 電壓之約一半以用於提供輸出端處之最大信號擺動。 . 在特定實施例中’積體電路之特徵由大DC迴路增益 以及低AC迴路增益表示，從而引起輸出端子處之Dc輸 出電壓實質上等於第二參考電壓，且AC輸出電壓與第一 反饋電路之阻抗以及Μ過輸入端子之AC輸入電流成線性 比例。在實施例中’第三電容為M0S夾層電容（sandwich φ capacitor)。在實施例中，電壓參考電路提供可程式電壓參 考。 在另一實施例中，本發明提供積體麥克風介面電路， 積體麥克風介面電路包括用於接收輸入信號之輸入端子以 及用於提供輸出音訊信號之輸出端子。積體麥克風介面電 路包括與輸入端子連通之第一電阻以及耦接至第一電阻之 第一參考電路。積體麥克風介面電路亦包括第一放大器電 路以及兩個反饋電路。第一放大器電路包括用於接收輸入 信號之第一輸入端、第二輸入端以及用於將輸出信號提供 至輸出端子的輸出端。第一反饋電路與第一放大器之輸出 端以及第一輸入端連通。第一反饋電路包括並聯連接之第 ^電阻以及第一電容。第二反饋電路包括積分器電路且與 第—放大器之輸出端以及第二輸入端連通。在實施例中， 第—參考電壓或電流獨立於第一反饋電路以及第二反饋電 ’ 路。 在以上積體電路之實施例中，將積體電路提供於單一 積體電路晶片中。在積體麥克風介面電路之特定實施例 1353111 96U003 26630twf.doc/n 中，輸入端子經配置以在無需外部電容的情況下自駐極體 麥克風接收輸入信號。在實施例中，麥克風參考為可程式 • 的。本發明之實施例包括積分器之各種實施。在一個實例 :中，積分器包括第二放大器，第二放大器包括第一輸入端、 第二輸入端以及輸出端。第一輸入端_接至第三電阻。第 二輸入端耦接至第二參考電壓信號，第二電容輕接至放大 器之第一輸入端以及輸出端。在另一實例中，積分哭包括 • 開關式電容電路、放大器以及電容。開關式電容電路包括 第二電容以及第一開關、第二開關、第三開關以及第四開 關。第一開關以及第一開關輕接至第二電容之第一端子， 且第三開關以及第四開關_接至第二電容之第二端子。第 —開關以及第三開關回應第一時脈信號，且第二開關以及 第四開關回應第二時脈信號。放大器電路包括第一輸入 ^、弟一輸入端以及輸出端。第一輸入端以及第二輪入端 分別與開關式電容電路之第三開關以及第四開關連通，且 第二輸入端亦與第二參考電壓信號連通。第三電容與放大 器之第一輸入端以及輸出端連通。 在特定實施例中，積體電路之特徵由大Dc迴路增益 以及低AC迴路增益表示，從而引起輸出端子處之^^曰^ 出電Μ只質上等於第二參考電壓，且AC輸出電壓與第二 . 反饋電路之阻抗以及經過輸入端子之AC輸入電流成線性 比例。在實施例中，第三電容為M〇s夾層電容。在實施 例中，電壓參考電路提供可程式電壓參考。 在替代性實施例中，本發明提供積體麥克風介面電 15 1353111 96U003 26630twf.doc/n 路，積體麥克風介面電路包括用於接收輸入信號之輸入端 子以及用於提供輸出音訊信號之輸出端子。積體麥克風介 面電路包括與輸入端.子連通之第一電阻以及耦接至第一電 阻之第一參考電路。麥克風介面電路亦包括第一放大器電 路，第一放大器電路包括第一輸入端、第二輸入端以及輸 出端。在第一放大器中，第二輸入端接收輸入信號，且輸 出端將輸出信號提供至輸出端子。麥克風介面電路亦包括In an embodiment of the integrated circuit, the integrator includes a switched capacitor, a secondary amplifier, and a capacitor. The switched capacitor circuit includes a second capacitor and a first switch, a second switch, a third switch, and a fourth switch. The first _ is coupled to the first terminal of the second capacitor by the fifth switch, and the third switch. A fourth switch is connected to the second terminal of the first electricity valley. The first switch and the response _ pulse § ' and the second switch and the fourth switch back to the second! number. The amplifier circuit includes a first wheel, a second input, and a second lightning. The first input end and the second round-in end are respectively connected to the switch type zero-turn power 2 third switch and the fourth switch, and the second input end is also the first-way, and the test signal is connected. The third capacitor is connected to the first input impurity 13 1353111 96U003 26630twf.doc/n and the output terminal. In an embodiment, the second reference voltage signal is about one-half of the supply voltage for providing maximum signal swing at the output. In a particular embodiment, the feature of the integrated circuit is represented by a large DC loop gain and a low AC loop gain, thereby causing the Dc output voltage at the output terminal to be substantially equal to the second reference voltage, and the AC output voltage and the first feedback circuit. The impedance and the AC input current across the input terminals are linearly proportional. In the embodiment, the third capacitance is a MOS sandwich capacitor. In an embodiment, the voltage reference circuit provides a programmable voltage reference. In another embodiment, the present invention provides an integrated microphone interface circuit that includes an input terminal for receiving an input signal and an output terminal for providing an output audio signal. The integrated microphone interface circuit includes a first resistor in communication with the input terminal and a first reference circuit coupled to the first resistor. The integrated microphone interface circuit also includes a first amplifier circuit and two feedback circuits. The first amplifier circuit includes a first input for receiving an input signal, a second input, and an output for providing an output signal to the output terminal. The first feedback circuit is in communication with the output of the first amplifier and the first input. The first feedback circuit includes a first resistor connected in parallel and a first capacitor. The second feedback circuit includes an integrator circuit and is in communication with the output of the first amplifier and the second input. In an embodiment, the first reference voltage or current is independent of the first feedback circuit and the second feedback circuit. In the above embodiment of the integrated circuit, the integrated circuit is provided in a single integrated circuit chip. In a specific embodiment of the integrated microphone interface circuit 1353111 96U003 26630twf.doc/n, the input terminals are configured to receive an input signal from an electret microphone without the need for an external capacitor. In an embodiment, the microphone reference is programmable. Embodiments of the invention include various implementations of integrators. In one example, the integrator includes a second amplifier, the second amplifier including a first input, a second input, and an output. The first input terminal _ is connected to the third resistor. The second input is coupled to the second reference voltage signal, and the second capacitor is coupled to the first input and the output of the amplifier. In another example, integral crying includes • switched capacitor circuits, amplifiers, and capacitors. The switched capacitor circuit includes a second capacitor and a first switch, a second switch, a third switch, and a fourth switch. The first switch and the first switch are lightly connected to the first terminal of the second capacitor, and the third switch and the fourth switch are connected to the second terminal of the second capacitor. The first switch and the third switch respond to the first clock signal, and the second switch and the fourth switch respond to the second clock signal. The amplifier circuit includes a first input ^, a first input, and an output. The first input end and the second round input end are respectively connected to the third switch and the fourth switch of the switched capacitor circuit, and the second input end is also in communication with the second reference voltage signal. The third capacitor is in communication with the first input and the output of the amplifier. In a particular embodiment, the characteristics of the integrated circuit are represented by a large Dc loop gain and a low AC loop gain, such that the output terminal at the output terminal is only qualitatively equal to the second reference voltage, and the AC output voltage is Second, the impedance of the feedback circuit and the AC input current through the input terminal are linearly proportional. In an embodiment, the third capacitance is a M〇s interlayer capacitance. In an embodiment, the voltage reference circuit provides a programmable voltage reference. In an alternative embodiment, the present invention provides an integrated microphone interface circuit 15 1353111 96U003 26630 twf.doc/n, the integrated microphone interface circuit including an input terminal for receiving an input signal and an output terminal for providing an output audio signal. The integrated microphone interface circuit includes a first resistor in communication with the input terminal and a first reference circuit coupled to the first resistor. The microphone interface circuit also includes a first amplifier circuit including a first input, a second input, and an output. In the first amplifier, the second input receives the input signal and the output provides the output signal to the output terminal. Microphone interface circuit also includes

兩個反饋電路。第一反饋電路與第一放大器之輸出端以及 第一輸入端連通’且其包括並聯連接之第二電阻以及第一 電容。第二反饋電路與第一放大器之輸出端以及第一輸入 端連通，且其包括積分器電路。在實施例中，將積體電路 Φζ供於單一積體電路晶片中。在特定實施例中，輸入端子 經配置以在無需外部電容的情況下自駐極體麥克風接收輸 入信號。在另一實施例中，麥克風參考電壓或電流為可程 式的，且第一電阻以及第二電阻為可程式的。在特定實施Two feedback circuits. The first feedback circuit is in communication with the output of the first amplifier and the first input and comprises a second resistor and a first capacitor connected in parallel. A second feedback circuit is coupled to the output of the first amplifier and to the first input, and includes an integrator circuit. In the embodiment, the integrated circuit Φ is supplied to a single integrated circuit chip. In a particular embodiment, the input terminal is configured to receive an input signal from an electret microphone without the need for an external capacitor. In another embodiment, the microphone reference voltage or current is configurable and the first and second resistors are programmable. In a specific implementation

例中，麥克風參考電壓或電流獨立於第一反饋電路以及 二反饋電路。 4曰助於本發明達紐於習知技術之許多益處。舉例而 言，在特定實施例中，提供用於在無需外部組件 在皁-積體電路晶片中整合DC偏壓與交流輕 Μ coupHng)以及藉由組合Ac以及DC信號來節 封裝上之針_技術。在實_中，提供驗減電^ 偏壓雜誠及改㈣電源抑制以防▲介面電路 ㈣的技術。在實施例中，提供用以防止麥克風電壓g 16 96U003 26630twf.doc/n ，強加至放大ϋ輸出端上且限制用於大偏壓電壓要求之信 號擺動’使得輸出端處之信號可能不會在積體電路之後面 •的電路級之輪入端處飽和的技術。在一些實施例中，由本 發明所提供之方法可節約應用中之材料清單（Β〇Μ )成 本以及PCB面積。在特定實施例中，提供用以減小外部雜 訊源以及電源雜訊之影響的技術。在一些實施例中，亦提 供-種用於差動介面電路之方法。在某些實施例中，介面 # 電路之AC特徵以及DC特徵由晶片上電容以及電阻來確 定，且可使用電路佈局技術使得可達成可能產生精確增益 以及時間怪定參數的精確匹配。此等參數在諸如波束形成 (beam forming)之應用中至關重要。此外，若有需要，可 根據本發明之實施例採用調諧或校準方法。在實施例中’ 提供用於藉由改變反饋級中之開關電容之時脈頻率的可程 式音訊靜噪（squelch)的技術。視實施例而定，可達成此 等益處之一或多者。將遍及本說明書且更明確地說在下文 更詳細描述此等以及其他益處。 •參考實施方式以及以下的隨附圖式可更全面地瞭解本 發明之各種額外目標、特徵以及優勢。 【實施方式】 本發明是關於一種積體電路。更明確地說，本發明提 供一種關於麥克風介面之積體電路的方法以及裝置。僅以 實例說明之’本發明已被應用至用於駐極體麥克風之介面 電路。但應體認到’本發明具有範圍更加廣泛之適用性。 舉例而言’可將本發明應用至其他種類之麥克風之介面電 17 1353111 96U003 26630twf.doc/n 路或其他彳§號源之介面電路。 ^實施例而定，本發明包括可使 • 特徵包括以下特徵： ^竹做此寻 1. 在無需外部紐件的情況下，Dc偏壓 片上的整合。 柄。杜日曰 2. 用以選擇兩個操作模式之可程式控制； 3. 允許信號校準以制於提供輸出端紅最大信號擺 _ 動的共同模式參考電壓的供應； 4. 低針腳計數； 5. 用於減小外部雜訊源以及電源雜訊之影響的電路設 計； 6. 替代性差動介面電路設計； 7. 藉由匹配晶片上組件所提供之較佳增益以及時間怪 定控制；以及 8. 可程式靜噪。 圖2a為根據本發明之實施例之積體麥克風介面電路 鲁 2〇〇的簡化示意圖。 如圖所示’積體麥克風介面電路（MIC) 200包括用 於接收輸入信號Vin之輸入節點202以及用於傳遞輸出信 號Vout之輸出節點2〇4。MIC 200包括經由電阻225耦接 至Vin之麥克風參考電壓源208。MIC 200亦包括具有經 • 由電阻223耦接至Vin之輸入端206以及在204處耦接至 - Vout之輸出端的第一放大器213。放大器213包括耦接至 共同模式參考電壓Vc()mmcmmode之第二輸入端207。根據本 18 1353111 96U003 26630twf.doc/n 發明之實施例，MIC 200包括在放大器213之輸入端與輸 出端之間連通的反饋路徑。在圖2a中所展示之特定實例 * 中，MIC 2〇〇包括與放大器213之輪出端204以及輸入端 • 206連通之兩個反饋路徑261以及262。反饋路徑261包括 電阻222 (R2)以及電容232 (C2)之並聯組合。反饋路 徑262包括在放大器213之輸出端204與輸入端206之間 串聯連接的故大器217、積分器電路211，以及電阻224 φ (R4)。在特定實施例中，積分器電路211包括放大器215、 連接至放大器215之弟一輸入端之電阻221 (R1)，以及連 接於放大器215之第一輸入端與輪出端之間的電容231 ((：1)。在特定實施例中，參考電壓\。〇11_〇1心連接至放大 器215之第二輸入端。 在較佳實施例中’ MIC 200中之放大器213、215，以 及217可為運算放大器。但亦可使用其它適當放大器。在 本發明之特定實施例中，Vin可為來自麥克風1〇2 (例如， 駐極體麥克風）之輸出信號。舉例而言，Vin可為聲音頻 帶或音訊頻帶信號。在實施例中，可將V〇ut輕接至CODEC 之類比數位轉換器（ADC)(未圖示）。在某些實施例中， 麥克風參考電壓源208可為可程式電壓源。在特定實施例 中’晶片上（可程式）電壓參考208經由可程式晶片上電 , 阻225將DC電流提供至外部麥克風。在實施例中，電阻 223以及225形成與輸入端子202以及麥克風參考電麗源 2〇8連通的麥克風偏壓電路。偏壓電路將感測輸入信號提 供至放大器213之輸入端206。如圖2中所展示，電阻225 1353111 96U003 26630twf.doc/n 與輪入端子202以及麥克風參考電壓源208連通。類似地’ 電阻223與輸入端子202以及電阻225連通。在此實例中’ 電阻223將感測輸入信號提供至放大器213之輸入端 206。在特定實施例中，放大器217具有增益-1。當然，可 存在其它變化、修改以及替代。 根據本發明之特定實施例，可以以下方程式表示MIC 2〇〇之增益轉換函數。In the example, the microphone reference voltage or current is independent of the first feedback circuit and the two feedback circuits. 4 Assists in the many benefits of the present invention. For example, in a particular embodiment, a pin for integrating a DC bias and an AC tap in a soap-integrated circuit chip without external components is provided, and a pin is packaged by combining Ac and DC signals. technology. In the real _, provide the technology to verify the power reduction ^ bias and change (4) power supply suppression to prevent the ▲ interface circuit (4). In an embodiment, a signal swing is provided to prevent the microphone voltage g 16 96U003 26630twf.doc/n from being imposed on the output of the amplifier and limiting the signal for large bias voltages such that the signal at the output may not The technique of saturation at the wheel end of the circuit level after the integrated circuit. In some embodiments, the method provided by the present invention can save on bill of materials (Β〇Μ) cost and PCB area in an application. In a particular embodiment, techniques are provided to reduce the effects of external noise sources and power supply noise. In some embodiments, a method for a differential interface circuit is also provided. In some embodiments, the AC characteristics and DC characteristics of the interface # circuit are determined by on-wafer capacitance and resistance, and circuit layout techniques can be used to achieve an accurate match that can result in accurate gain and time-delayed parameters. These parameters are critical in applications such as beam forming. Moreover, tuning or calibration methods can be employed in accordance with embodiments of the present invention, if desired. In an embodiment, a technique for programmable squelch by varying the clock frequency of the switched capacitor in the feedback stage is provided. Depending on the embodiment, one or more of these benefits can be achieved. These and other benefits will be described in more detail throughout the specification and more specifically below. The various additional objects, features, and advantages of the present invention will be more fully understood from the description and appended claims. [Embodiment] The present invention relates to an integrated circuit. More specifically, the present invention provides a method and apparatus for an integrated circuit of a microphone interface. The present invention has been applied to an interface circuit for an electret microphone only by way of example. However, it should be recognized that the invention has a broader range of applicability. For example, the present invention can be applied to interface devices of other types of microphones, such as the interface circuit of 17 1353111 96U003 26630 twf.doc/n or other sources. Depending on the embodiment, the invention includes that the features include the following features: ^ Bamboo to do this 1. The integration of the Dc bias on the chip without the need for an external button. handle. Du Ri曰 2. Programmable control to select two operating modes; 3. Allow signal calibration to provide supply of common mode reference voltage for output red maximum signal swing; 4. Low pin count; Circuit design for reducing the effects of external noise sources and power supply noise; 6. Alternative differential interface circuit design; 7. Better gain and time-delay control by matching components on the wafer; . Programmable squelch. 2a is a simplified schematic diagram of an integrated microphone interface circuit in accordance with an embodiment of the present invention. As shown, the integrated microphone interface circuit (MIC) 200 includes an input node 202 for receiving an input signal Vin and an output node 2〇4 for transmitting an output signal Vout. The MIC 200 includes a microphone reference voltage source 208 coupled to Vin via a resistor 225. The MIC 200 also includes a first amplifier 213 having an input 206 coupled via a resistor 223 to Vin and an output coupled to -Vout at 204. Amplifier 213 includes a second input 207 coupled to a common mode reference voltage Vc() mmcmmode. According to an embodiment of the invention, the MIC 200 includes a feedback path that communicates between an input and an output of the amplifier 213. In the particular example shown in Figure 2a, the MIC 2A includes two feedback paths 261 and 262 in communication with the wheel end 204 of the amplifier 213 and the input terminal 206. Feedback path 261 includes a parallel combination of resistor 222 (R2) and capacitor 232 (C2). The feedback path 262 includes a transistor 217, an integrator circuit 211, and a resistor 224 φ (R4) connected in series between the output 204 and the input 206 of the amplifier 213. In a particular embodiment, the integrator circuit 211 includes an amplifier 215, a resistor 221 (R1) coupled to an input of the amplifier 215, and a capacitor 231 coupled between the first input and the output of the amplifier 215 ( (:1). In a particular embodiment, the reference voltage \〇11_〇1 is connected to the second input of the amplifier 215. In the preferred embodiment, the amplifiers 213, 215, and 217 in the MIC 200 can be It is an operational amplifier. However, other suitable amplifiers can be used. In a particular embodiment of the invention, Vin can be an output signal from a microphone 1〇2 (e.g., an electret microphone). For example, Vin can be a sound band. Or an audio band signal. In an embodiment, V〇ut can be lightly coupled to an analog digital converter (ADC) of the CODEC (not shown). In some embodiments, the microphone reference voltage source 208 can be a programmable voltage. In a particular embodiment, the on-wafer (programmable) voltage reference 208 is powered via a programmable wafer, and the resistor 225 provides DC current to the external microphone. In an embodiment, the resistors 223 and 225 are formed with the input terminal 202 and the microphone. Referring to the microphone bias circuit of the galvanic source 2 〇 8. The bias circuit provides a sensed input signal to the input 206 of the amplifier 213. As shown in Figure 2, the resistor 225 1353111 96U003 26630twf.doc/n and The wheeled terminal 202 and the microphone reference voltage source 208 are in communication. Similarly, the 'resistor 223 is in communication with the input terminal 202 and the resistor 225. In this example, the 'resistor 223 provides a sensed input signal to the input 206 of the amplifier 213. In a particular implementation In the example, amplifier 217 has a gain of - 1. Of course, there may be other variations, modifications, and alternatives. According to a particular embodiment of the invention, the gain transfer function of MIC 2〇〇 may be represented by the following equation.

s.Ri.Ci__s.Ri.Ci__

s2Rt.R4.C|.C2+s-^^.Ci + l V R2 J 圖2b為用於根據本發明之實施例之麥克風介面電路 的增益轉換函數之簡化圖。如圖所示，在高頻率下，增益 函數可由以下公式來近似求得。s2Rt.R4.C|.C2+s-^^.Ci + l V R2 J Figure 2b is a simplified diagram of a gain conversion function for a microphone interface circuit in accordance with an embodiment of the present invention. As shown, at high frequencies, the gain function can be approximated by the following equation.

H(s) — V〇ut(s) — 一 R4 Vin(s) R3 -1 (S，R_3，C2) 政^ 或音訊頻帶頻率範圍中，反饋迴路之此AC迴 函1而允許AC信號經過。在較低頻率下，增益 -數可由以下公式近似求得H(s) — V〇ut(s) — A R4 Vin(s) R3 -1 (S, R_3, C2) In the frequency band of the audio or audio band, the AC loop 1 of the feedback loop allows the AC signal to pass. . At lower frequencies, the gain-number can be approximated by the following formula

20 1353111 96U003 26630twf.doc/n 根據本發明之實施例，MC 2〇〇之特徵由足夠大以迫 使增益級之共囉式輸出㈣為\。__的％迴路增 进表不。舉例而言，在特定實施例令，MIC2〇〇可具有大 約80dB至140dB之DC迴路增益。 在本發明之實施例中，在無需外部組件的情況下，麥 克風"面電路（MIC) 200在單一積體電路晶片中提供DC 偏壓與AC耦合。在實施例中，提供Dc偏壓之電路獨立 =反饋電路。在特定實施例中，可藉由（例如）選擇適當 電阻以及電容來獲得所要的轉換特徵。僅作為實例，電阻 221 (R1)通常具有在1〇〇 ΜΩ至500 ΜΩ之範圍中的高電 阻，而電阻222 ( R2 )、電阻223 ( R3 )，以及電阻224 ( R4 ) 了具有1 kQ至500 kQ之範圍中的電阻。電容23i(ci)以 及電谷232 (C2)可具有3pF至600 pF之範圍中的電容。 當然，一般熟習此項技術者可認識其它變化、修改以及替 代。 圖3為根據本發明之另一實施例之積體麥克風介面電 路的簡化示意圖。如圖所示，麥克風介面電路3〇〇類似於 上文參考圖2所論述之麥克風介面電路2〇〇。在MIC 300 中’積分器電路311用於代替MIC 200中之積分器電路 211 °如圖所示，積分器電路311包括放大器315、開關式 電容電路320，以及MOS夾層電容330。此設計使得裝置 面積實質上減小。開關式電容電路320包括電容335以及 四個開關S!、S2、S3以及S4。如圖所示，S〗以及s2_接 至電容335之第一端子。S3以及S4耦接至電容335之第二 21 1353111 96U003 26630twf.doc/n =。在特定貫施例中，s2以及S4亦_至共同模式參考 電垄\。咖。麵。扣。在實施例中’81以及83回應第一時脈 號叫，而S2以及S4回應第二時脈信號①2。放大器電ς 315包括第-輸入端、第二輸入端，以及輸出端。第一輸 入端與s3連通，且第二輸人端與開關式電容電路32〇之 &以及S4連通。在積分器電路3U甲，電容33〇與放大器 之第一輸入端以及輸出端連通。20 1353111 96U003 26630twf.doc/n According to an embodiment of the invention, the characteristics of the MC 2〇〇 are sufficiently large to force the conjugate output (4) of the gain stage to be \. The % loop of __ is not shown. For example, in certain embodiments, the MIC2 can have a DC loop gain of about 80 dB to 140 dB. In an embodiment of the invention, the microphone "face circuit (MIC) 200 provides DC bias and AC coupling in a single integrated circuit die without the need for external components. In an embodiment, a circuit independent of the Dc bias is provided = feedback circuit. In a particular embodiment, the desired switching characteristics can be obtained, for example, by selecting appropriate resistors and capacitors. For example only, resistor 221 (R1) typically has a high resistance in the range of 1 Ω to 500 Ω, while resistor 222 (R2), resistor 223 (R3), and resistor 224 (R4) have 1 kQ to Resistance in the range of 500 kQ. The capacitor 23i (ci) and the valley 232 (C2) may have a capacitance in the range of 3 pF to 600 pF. Of course, those who are familiar with the art will recognize other variations, modifications, and alternatives. 3 is a simplified schematic diagram of an integrated microphone interface circuit in accordance with another embodiment of the present invention. As shown, the microphone interface circuit 3 is similar to the microphone interface circuit 2 discussed above with reference to FIG. In the MIC 300, the integrator circuit 311 is used in place of the integrator circuit 211 in the MIC 200. As shown, the integrator circuit 311 includes an amplifier 315, a switched capacitor circuit 320, and a MOS mezzanine capacitor 330. This design allows the device area to be substantially reduced. The switched capacitor circuit 320 includes a capacitor 335 and four switches S!, S2, S3, and S4. As shown, S and s2_ are connected to the first terminal of capacitor 335. S3 and S4 are coupled to the second of the capacitor 335 21 1353111 96U003 26630twf.doc/n =. In a specific embodiment, s2 and S4 are also _ to the common mode reference electric ridge\. coffee. surface. buckle. In the embodiment, '81 and 83 respond to the first clock number, and S2 and S4 respond to the second clock signal 12. The amplifier power 315 includes a first input, a second input, and an output. The first input terminal is in communication with s3, and the second input terminal is in communication with & and S4 of the switched capacitor circuit 32. In the integrator circuit 3U, the capacitor 33 is connected to the first input and the output of the amplifier.

請注意在MIC 200中之積分器級中，電阻221常常為 大電阻（例如，100ΜΩ至500ΜΩ)，其需要大的裝置面 積。在MIC 300中’此電阻由開關式電容網路32〇提供， 其可實施於積體電路中之相對小的裝置面積中。此外，由 於此為抽樣系統，故增益級上之反饋電容將提供抗混淆濾 波且大積分器電容提供平滑。在實施例中，由晶片上時脈 信號Φ!以及Φ2來控制開關式電容網路。藉由改變時脈頻 率’亦可實施靜噪功能。Note that in the integrator stage of the MIC 200, the resistor 221 is often a large resistor (e.g., 100 Ω to 500 Ω), which requires a large device area. In MIC 300, this resistor is provided by a switched capacitor network 32, which can be implemented in a relatively small device area in an integrated circuit. In addition, since this is a sampling system, the feedback capacitor at the gain stage will provide anti-aliasing filtering and the large integrator capacitance will provide smoothing. In an embodiment, the switched capacitor network is controlled by the on-wafer clock signals Φ! and Φ2. The squelch function can also be implemented by changing the clock frequency.

亦如圖3中所示，MOS夾層電容330用於MIC 300 中，代替MIC 200中之反饋電容231。反饋電容231通常 都是很大的，例如，100pF_3〇〇pF。根據本發明之實施例， 用於MIC 300中之M0S夾層電容提供較小裝置面積之優 勢。非線性對於此電容而言是小問題’因為頻帶内信號經 過此電容被高度衰減。 圖4為根據本發明之替代性實施例之積體差動麥克風 介面電路的簡化示意圖。 如圖所示，積體麥克風介面電路（MIC) 400包括用 22 1353111 96U003 26630tw£doc/n 於接收差動輸入信號Vin之差動輸入節點401以及差動輸 入節點402。MIC 400包括用於提供差動輸出信號Vout之 • 差動輸出節點403以及差動輸出節點404。在實施例中， MIC 400包括第一麥克風偏壓電路，第一麥克風偏壓電路 包括電阻423以及電阻425。麥克風參考電壓源407經由 電阻425耦接至輸入節點401。MIC 400亦包括第二麥克 風偏壓電路’第二麥克風偏壓電路包括電阻453以及電阻 φ 455。電阻455將輸入節點402耦接至接地電壓457。在替 代性實施例中，457可為另一參考電壓。MIC 400亦包括 具有分別經由電阻423以及電阻453耦接至401以及402 之輸入端441以及輸入端442的第一放大器413。亦即， 放大器413之輸入端441以及輸入端442分別接收由第一 麥克風偏壓電路以及第二麥克風偏壓電路所提供之感測輸 入信號。放大器413包括耦接至共同模式參考電壓 ^commonmode 之輸入端。根據本發明之實施例，MIC 400包 括在放大器413之輸入端與輸出端之間連通的反饋路徑。 鲁 在圖4中所展示之特定實例中，MIC 400包括各自與放大 器413之輸入端以及輸出端連通之四個反饋路徑461、 462、463以及464。舉例而言，輸出端4〇4與輸入端442 之間的反饋路徑461包括電阻422以及電容432之並聯組 合。放大器413之輸出端4〇4與輸入端441之間的反饋路 徑462包括與積分器串聯連接的電阻424，所述積分器包 . 括放大器415、電阻421以及電容431。輸出端403與輸入 端441之間的反饋路徑463包括電阻452以及電容462之 23 1353111 96U003 26630twf.doc/n 並聯組合。放大器413之輸出端403與輸入端442之間的 反饋路徑464包括與第二積分器串聯連接的電阻454，所 . 述第二積分器包括放大器415、電阻451，以及電容461。 在，定實施射’制模式參考電壓1_一連接至放 大器415之輸入端。可根據差動信號進行關kMk：4〇〇2 替代性描述。舉例而言，反饋路徑461以及反饋路徑463 將差動反饋仏號自放大器413之輸出端提供至放大器413 φ 之輸入‘，且反饋路徑462以及反饋路徑464將另一差動 反饋信號自放大器413之輪出端提供至放大器413之輸入 端。如圖4 _所示，反饋路徑462以及反饋路徑464形成 差動反饋電路411。 抑在較佳實施例中，MIC 400中之放大器413以及放大 器415可為運算放大器。但亦可使用其它適當放大器。在 本發明之特定實施例中，Vin可為來自麥克風（例如，駐 極體麥克風）之輸出信號。舉例而言，vin可為來自麥克 風之聲曰或音訊頻帶彳§號。在實施例中，可將v〇ut福接至 像是CODEC之_比數位轉換器（ADC)。在某些實施例 中，麥克風參考電壓源407可為可程式電壓源。在特定實 施例中，晶片上（可程式）電壓參考4〇7經由（可程式） 晶片上電阻425將DC電流提供至外部麥克風。 . 根據本發明之實施例’ MIC 400提供差動反饋路徑。 類似於MIC 200,在聲音或音訊頻帶頻率範圍中，ΜΙ(：4〇〇 中之反饋迴路之AC迴路增益小，從而允許Ac信號經過 輸入％子到達輸出端。根據本發明之實施例，MIC 400之 24 1353111 96U003 26630twf.doc/n 特徵由足夠大以迫使增益級之共同模式輸出電壓為 VcommomnocJe的DC迴路增益表示。舉例而言，在特定實施 例中，MIC 400可具有大約80dB至140dB之DC迴路增 益。因此’根據本發明之實施例，在無需外部組件的情況 下，麥克風介面電路400在單一積體電路晶片上提供DC 偏壓與AC耦合。在實施例中，提供DC偏壓之電路獨立 於反饋電路。 圖5為根據本發明之又一實施例之麥克風介面電路的 簡化示意圖。如圖所示，積體麥克風介面電路（MIC) 500 包括用於接收輸入信號Vin之輸入節點502以及用於傳遞 輸出信號Vout之輸出節點504。MIC 500包括麥克風參考 電壓源507。MIC 200亦包括具有輸入端541以及輸入端 542以及在504處耦接至Vout之輸出端的第一放大器 513。輸入端542耦接至Vin，且第二輸入端541耦接至麥 克風參考電壓源507。根據本發明之實施例，MIC包括在 放大器513之輸入端與輸出端之間的反饋電路。在圖5中 所展示之特定實例中，MIC 500包括與放大器513之輸入 端以及輸出端連通之兩個反饋路徑。反饋路徑561包括電 阻522以及電容532之並聯組合。反饋路徑562包括在放 大益513之輸出端與輸入端之間串聯連接的積分器電路 511以及電阻524。在特定實施例中，積分器電路511包括 放大器517、放大器515、電阻521以及電容531。電阻521 連接至放大器515之輸入端，且電容531連接於放大器515 之輸入端與輸出端之間。在特定實施例中，參考電壓 25 1353111 96U003 26630twf.doc/nAs also shown in FIG. 3, MOS interlayer capacitor 330 is used in MIC 300 instead of feedback capacitor 231 in MIC 200. The feedback capacitance 231 is typically large, for example, 100 pF_3 〇〇 pF. In accordance with an embodiment of the present invention, the MOS sandwich capacitor used in the MIC 300 provides the advantage of a smaller device area. Nonlinearity is a minor problem for this capacitor' because the signal in the band is highly attenuated by this capacitance. 4 is a simplified schematic diagram of an integrated differential microphone interface circuit in accordance with an alternative embodiment of the present invention. As shown, the integrated microphone interface circuit (MIC) 400 includes a differential input node 401 and a differential input node 402 that receive the differential input signal Vin with 22 1353111 96U003 26630 tw. The MIC 400 includes a differential output node 403 and a differential output node 404 for providing a differential output signal Vout. In an embodiment, MIC 400 includes a first microphone bias circuit that includes a resistor 423 and a resistor 425. Microphone reference voltage source 407 is coupled to input node 401 via resistor 425. The MIC 400 also includes a second microphone bias circuit. The second microphone bias circuit includes a resistor 453 and a resistor φ 455. Resistor 455 couples input node 402 to ground voltage 457. In an alternate embodiment, 457 can be another reference voltage. The MIC 400 also includes a first amplifier 413 having an input 441 coupled to 401 and 402 via a resistor 423 and a resistor 453, and an input 442, respectively. That is, the input 441 and the input 442 of the amplifier 413 receive the sensed input signals provided by the first microphone bias circuit and the second microphone bias circuit, respectively. Amplifier 413 includes an input coupled to a common mode reference voltage ^commonmode. In accordance with an embodiment of the present invention, MIC 400 includes a feedback path that communicates between an input and an output of amplifier 413. In the particular example shown in FIG. 4, MIC 400 includes four feedback paths 461, 462, 463, and 464 each coupled to an input and an output of amplifier 413. For example, the feedback path 461 between the output terminal 4〇4 and the input terminal 442 includes a parallel combination of a resistor 422 and a capacitor 432. The feedback path 462 between the output terminal 4〇4 of the amplifier 413 and the input terminal 441 includes a resistor 424 connected in series with the integrator, which includes an amplifier 415, a resistor 421, and a capacitor 431. The feedback path 463 between the output 403 and the input 441 includes a resistor 452 and a capacitor 462 of 23 1353111 96U003 26630twf.doc/n in parallel combination. The feedback path 464 between the output 403 of the amplifier 413 and the input 442 includes a resistor 454 coupled in series with the second integrator, the second integrator including an amplifier 415, a resistor 451, and a capacitor 461. The reference mode voltage 1_ is connected to the input of the amplifier 415. The kMk:4〇〇2 alternative description can be performed based on the differential signal. For example, the feedback path 461 and the feedback path 463 provide the differential feedback signal from the output of the amplifier 413 to the input ' of the amplifier 413 φ ', and the feedback path 462 and the feedback path 464 carry the other differential feedback signal from the amplifier 413 The wheel end is provided to the input of amplifier 413. As shown in FIG. 4, the feedback path 462 and the feedback path 464 form a differential feedback circuit 411. In the preferred embodiment, amplifier 413 and amplifier 415 in MIC 400 can be operational amplifiers. However, other suitable amplifiers can also be used. In a particular embodiment of the invention, Vin may be an output signal from a microphone (e.g., a relay microphone). For example, vin can be from the vocal or audio band of the microphone. In an embodiment, the V〇ut can be connected to a digital converter such as a CODEC. In some embodiments, the microphone reference voltage source 407 can be a programmable voltage source. In a particular embodiment, the on-wafer (programmable) voltage reference 4〇7 provides DC current to the external microphone via a (programmable) on-wafer resistor 425. The MIC 400 provides a differential feedback path in accordance with an embodiment of the present invention. Similar to the MIC 200, in the frequency range of the sound or audio band, the AC loop gain of the feedback loop in ΜΙ(:4〇〇 is small, allowing the Ac signal to pass through the input % to the output. According to an embodiment of the invention, the MIC 400 24 1353111 96U003 26630twf.doc/n The characteristic is represented by a DC loop gain that is large enough to force the common mode output voltage of the gain stage to be VcommomnocJe. For example, in a particular embodiment, the MIC 400 can have approximately 80 dB to 140 dB. DC loop gain. Thus, in accordance with an embodiment of the present invention, the microphone interface circuit 400 provides DC bias and AC coupling on a single integrated circuit die without the need for external components. In an embodiment, a DC bias is provided. The circuit is independent of the feedback circuit.Figure 5 is a simplified schematic diagram of a microphone interface circuit in accordance with yet another embodiment of the present invention. As shown, the integrated microphone interface circuit (MIC) 500 includes an input node 502 for receiving an input signal Vin. And an output node 504 for transmitting an output signal Vout. The MIC 500 includes a microphone reference voltage source 507. The MIC 200 also includes an input 541. And an input 542 and a first amplifier 513 coupled to the output of Vout at 504. The input 542 is coupled to Vin, and the second input 541 is coupled to the microphone reference voltage source 507. According to an embodiment of the invention, The MIC includes a feedback circuit between the input and output of amplifier 513. In the particular example shown in Figure 5, MIC 500 includes two feedback paths in communication with the input and output of amplifier 513. Feedback path 561 A parallel combination of resistor 522 and capacitor 532 is included. Feedback path 562 includes an integrator circuit 511 and a resistor 524 connected in series between the output and input of amplifier 513. In a particular embodiment, integrator circuit 511 includes amplifier 517. An amplifier 515, a resistor 521, and a capacitor 531. The resistor 521 is coupled to the input of the amplifier 515, and the capacitor 531 is coupled between the input and the output of the amplifier 515. In a particular embodiment, the reference voltage is 25 1353111 96U003 26630twf.doc /n

Vcommonmode連接至放大器515之輸入端0 在較佳實施例中，MIC 500中之放大器可為運算放大 . 器。但亦可使用其它適當放大器。在本發明之特定實施例 • 中’ Vin可為來自麥克風（例如，駐極體麥克風）之輪出 信號。舉例而言’ Vin可為來自麥克風之聲音或音訊頻帶 信競。在實施例中，可將vout耦接至像是CODEC之類比 數位轉換器（ADC)。在某些實施例中，麥克風參考電壓 φ 源507可為可程式電壓源。在實施例中，放大器517具有 增益-1。 '、 根據本發明之實施例，MIC 500包括執行類似於上文 參考圖2a所据述之MIC 200中之反饋路徑之功能的反饋 路徑561以及反饋路徑562。在MIC 500中，在聲音或音 Λ頻▼頻率範圍中，反饋迴路之AC迴路增益小，從而允 許AC信號經過輸入端子到達輸出端。根據本發明之實施 例’ MIC ’之特徵由足夠A以返使輸出電壓為共同模式 *1壓的DC迴路增益表示。舉例而言，在特定實施例中， MIC 500可具有大約8〇dB至14〇dB之Dc迴路增益因 此，根據本發明之實施例，在無需外部組件的情況下，麥 克風介面電路5〇〇在單一積體電路晶片中提供dc偏塵與 AC輕合。在實施例中，提供Dc偏壓之電路獨立於反饋電 路。 目6為根據本發明之^ —替代性實施狀積體麥克風 介面電路之簡化示意圖。如圖所示，麥克風介面電路_ 類似於參考圖5所論述之麥克風介面電路獅。請注意 26 1353111 96U003 26630twf.doc/n 600包括積分器電路611以代替MIC 5〇〇中之積分器電路 511如圖所示，積分器電路611包括開關式電容網路62〇 • 以及MOS夾層電容630。參考上文關於MIC 500以及圖5Vcommonmode is coupled to input 0 of amplifier 515. In the preferred embodiment, the amplifier in MIC 500 can be an operational amplifier. However, other suitable amplifiers can also be used. In a particular embodiment of the invention, ' Vin can be a round-trip signal from a microphone (e.g., an electret microphone). For example, ' Vin can be a voice or audio band from a microphone. In an embodiment, vout can be coupled to an analog digital converter (ADC) such as a CODEC. In some embodiments, the microphone reference voltage φ source 507 can be a programmable voltage source. In an embodiment, amplifier 517 has a gain of -1. In accordance with an embodiment of the present invention, MIC 500 includes a feedback path 561 and a feedback path 562 that perform functions similar to the feedback paths in MIC 200 described above with reference to Figure 2a. In the MIC 500, the AC loop gain of the feedback loop is small in the frequency range of the sound or chirp frequency, allowing the AC signal to pass through the input terminal to the output. The feature of the embodiment 'MIC' according to the present invention is represented by a DC loop gain sufficient to return the output voltage to the common mode *1 voltage. For example, in a particular embodiment, MIC 500 can have a Dc loop gain of approximately 8 〇 dB to 14 〇 dB. Thus, in accordance with an embodiment of the present invention, microphone interface circuit 5 is present without external components The dc dust is provided in the single integrated circuit chip to be lightly coupled with the AC. In an embodiment, the circuit that provides the Dc bias is independent of the feedback circuit. Figure 6 is a simplified schematic diagram of an integrated microphone interface circuit in accordance with the present invention. As shown, the microphone interface circuit _ is similar to the microphone interface circuit lion discussed with reference to FIG. Please note that 26 1353111 96U003 26630twf.doc/n 600 includes an integrator circuit 611 in place of the integrator circuit 511 in the MIC 5〇〇 as shown, the integrator circuit 611 includes a switched capacitor network 62〇 and a MOS mezzanine capacitor. 630. Refer to MIC 500 above and Figure 5

. 之論述可理解積分器電路611之通用操作。然而，與MIC 500相比，MIC 600具有提供較小裝置面積的優勢，可由 例如開關式電容網路以及MOS夾層電容提供。 圖7為根據本發明之又一實施例之麥克風介面電路的 φ 簡化示意圖。如圖所示，積體麥克風介面電路（MIC) 700 包括用於接收輸入信號Vin之輸入端子702以及用於提供 輸出Ισ说Vout之輸出郎點704。MIC 700包括經由電阻725 (R3)耦接至vin之麥克風參考電路708。視實施例而定， 麥克風參考電路708可提供參考電壓或參考電流。MIC 7〇〇 亦包括具有耦接至Vin以接收電流Iin之輸入端7〇6以及 搞接至輸出端子704之輸出端的第一放大器713。放大器 713包括如下文所論述自反饋電路762接收反饋信號之第 二輸入端707。根據本發明之實施例，MIC 700包括與放 ® 大器713之輸入端以及輸出端連通的反饋電路。在圖7中 所展示之特定實例中’ MIC 700包括分別與放大器713之 輸出端704以及輸入端706以及輸入端707連通之兩個反 饋路徑761以及762。反饋路徑761包括電阻722 (R2) 以及電容732 (C2)之並聯組合。反饋路徑762包括連接 • 於放大器713之輸出端704與輸入端707之間的積分器電 ' 路711。在特定實施例中，積分器電路711包括放大器715、 連接至放大器715之輸入端的電阻721 (R1)，以及連接於 27 1353111 96U003 26630twf.doc/n 放大器715之輸入端與輸出端之間的電容731( a)。在杏 施例中，電阻722以及電阻725為可程式電阻。在特定^ • 施例中，參考電壓乂^^⑽加则如連接至放大器了^之第二輸 入端。 一 3 在較佳實施例中，MIC 700中之放大器可為運算放大 器。但亦可使用其它適當放大器。在本發明之特定實施例 中，輸入端子702處之信號Vin可為來自麥克風（例如， 鲁 駐極體麥克風）之輸出信號。舉例而言，亦可使用其它類 型之麥克風。視應用而定，Vin可為聲音頻帶信號訊 頻帶信號。在實施例中，輸出信號Vout可為耦接至c〇DE(： 之類比數位轉換器（ADC)的音訊頻帶信號。在某些實施 例中，麥克風參考電路708可為可程式電壓源。在特定實 施例中，晶片上可程式參考708經由晶片上電阻725將DC 電流提供至外部麥克風。在實施例中，電阻725為可程式 電阻。因此，在實施例中，本發明提供包括電阻725以及 電壓參考源708之晶片上麥克風偏壓電路。 修 根據本發明之實施例，可由以下公式表示MIC7〇〇之 增益轉換函數。 H(s) = = —_____s-Ri-Ci • R3 ^ + ^ ^~~- + 1j ' 在高頻率下，MIC 700之增益轉換函數可由以下公式 近似求得。 28 1353111 96U003 26630twf.doc/n H⑻=The discussion of the integrator circuit 611 can be understood as a general operation. However, the MIC 600 has the advantage of providing a smaller device area than the MIC 500, and can be provided by, for example, switched capacitor networks and MOS mezzanine capacitors. 7 is a simplified schematic diagram of φ of a microphone interface circuit in accordance with yet another embodiment of the present invention. As shown, the integrated microphone interface circuit (MIC) 700 includes an input terminal 702 for receiving an input signal Vin and an output point 704 for providing an output Ισ said Vout. The MIC 700 includes a microphone reference circuit 708 coupled to vin via a resistor 725 (R3). Depending on the embodiment, the microphone reference circuit 708 can provide a reference voltage or a reference current. The MIC 7A also includes a first amplifier 713 having an input terminal 7〇6 coupled to Vin for receiving current Iin and an output terminal coupled to output terminal 704. Amplifier 713 includes a second input 707 that receives a feedback signal from feedback circuit 762 as discussed below. In accordance with an embodiment of the present invention, the MIC 700 includes a feedback circuit in communication with the input and output of the amplifier 713. In the particular example shown in Figure 7, the MIC 700 includes two feedback paths 761 and 762 that are in communication with the output 704 of the amplifier 713 and the input 706 and the input 707, respectively. Feedback path 761 includes a parallel combination of resistor 722 (R2) and capacitor 732 (C2). Feedback path 762 includes an integrator circuit 711 coupled between output 704 of amplifier 713 and input 707. In a particular embodiment, the integrator circuit 711 includes an amplifier 715, a resistor 721 (R1) coupled to the input of the amplifier 715, and a capacitor coupled between the input and output of the 27 1353111 96U003 26630twf.doc/n amplifier 715. 731(a). In the apricot embodiment, resistor 722 and resistor 725 are programmable resistors. In a particular embodiment, the reference voltage 乂^^(10) plus is connected to the second input of the amplifier. In a preferred embodiment, the amplifier in the MIC 700 can be an operational amplifier. However, other suitable amplifiers can also be used. In a particular embodiment of the invention, the signal Vin at the input terminal 702 can be an output signal from a microphone (e.g., a Lu electret microphone). For example, other types of microphones can be used. Depending on the application, Vin can be a sound band signal band signal. In an embodiment, the output signal Vout can be an audio band signal coupled to an analog digital converter (ADC). In some embodiments, the microphone reference circuit 708 can be a programmable voltage source. In a particular embodiment, on-wafer programmable reference 708 provides DC current to an external microphone via on-wafer resistor 725. In an embodiment, resistor 725 is a programmable resistor. Thus, in an embodiment, the present invention provides for including resistor 725 and On-wafer microphone bias circuit of voltage reference source 708. According to an embodiment of the invention, the gain transfer function of MIC7〇〇 can be represented by the following formula: H(s) = = —_____s-Ri-Ci • R3 ^ + ^ ^~~- + 1j ' At high frequencies, the gain transfer function of MIC 700 can be approximated by the following formula: 28 1353111 96U003 26630twf.doc/n H(8)=

Voui(s) (s· C 2) 在較低頻率下，增益函數可由以下公式近似求得。 Η⑻= V〇ut(s) Im(s) «-R2 根據本發明之實施例，在聲音或音訊頻帶頻率範圍 中，反饋迴路之AC迴路增益小，且DC迴路增益大。舉 例而言’在特定實施例中，MIC 700可具有大約80dB至 140dB之DC迴路增益。更特定言之，MIC 700之特徵由 大DC迴路增益以及低AC迴路增益表示，從而引起輸出 端子處之DC輸出電壓實質上等於第二參考電壓，且AC 輸出電壓與第一反饋電路之阻抗以及經過輸入端子之AC 輸入電流或電壓成線性比例。 在本發明之實施例中，在無需外部組件的情況下，麥 克風介面電路（MIC) 700在單一積體電路晶片中提供DC 偏壓與AC耦合。在實施例中，提供DC偏壓之電路獨立 於反饋電路。在特定實施例中，可藉由選擇適當電阻以及 電容來獲得所要的轉換特徵（諸如，麥克風偏壓、高DC 迴路增益以及低AC迴路增益）。僅作為實例，電阻721( R1) 通常具有在100 ΜΩ至500 ΜΩ之範圍中的高電阻，而電 阻722 (R2)以及電阻723 (R3)可具有1 ΙίΩ至500 kD 之範圍中的電阻。電容731(C1)以及電容732 (C2)可具有 3 pF至500 PF之範圍中的電容。 29 1353111 96U003 26630twf.doc/n 圖8為根據本發明之另一實施例之積體麥克風介面電 路的簡化示意圖。如圖所示，麥克風介面電路（MIC) 8〇〇 通吊類似於上文參考圖7所論述之麥克風介面電路700。 在圖8中’ MIC 800包括積分器電路811來代替MIC 700 中之積分器電路711。如圖所示，積分器電路811包括放 大器815、開關式電容電路82〇以及MOS夾層電容830。 此設計使得裝置面積實質上減小。開關式電容電路82〇包 括電容835以及四個開關s!、S2、S3以及S4。如圖所示， Si以及S2耦接至電容835之第一端子。S3以及S4耦接至 電容835之第二端子。在特定實施例中，S2以及S4亦耦接 至共同模式參考電壓▽。⑽喔咖如。在實施例中，Si以及S3 回應第一可程式時脈信號，而S2以及S4回應第二可程 式時脈信號Φ2。放大器電路815包括第一輸入端、第二輸 入端以及輸出端。第一輸入端與S3連通，且第二輸入端與 開關式電容電路820之S2以及S4連通。在積分器電路811 中，電容830與放大器之第一輸入端以及輸出端連通。 根據本發明之實施例，可由以下公式表示MIC 800之 增益轉換函數。 H(s)Voui(s) (s· C 2) At lower frequencies, the gain function can be approximated by the following formula. Η(8)= V〇ut(s) Im(s) «-R2 According to an embodiment of the present invention, the AC loop gain of the feedback loop is small and the DC loop gain is large in the sound or audio band frequency range. By way of example, in a particular embodiment, MIC 700 can have a DC loop gain of approximately 80 dB to 140 dB. More specifically, the characteristics of the MIC 700 are represented by a large DC loop gain and a low AC loop gain, causing the DC output voltage at the output terminal to be substantially equal to the second reference voltage, and the AC output voltage and the impedance of the first feedback circuit and The AC input current or voltage through the input terminal is linearly proportional. In an embodiment of the invention, the microphone interface circuit (MIC) 700 provides DC bias and AC coupling in a single integrated circuit die without the need for external components. In an embodiment, the circuit that provides the DC bias is independent of the feedback circuit. In a particular embodiment, the desired switching characteristics (such as microphone bias, high DC loop gain, and low AC loop gain) can be obtained by selecting appropriate resistors and capacitors. For example only, resistor 721 (R1) typically has a high resistance in the range of 100 ΜΩ to 500 Ω, while resistor 722 (R2) and resistor 723 (R3) may have a resistance in the range of 1 ΙίΩ to 500 kD. Capacitor 731 (C1) and capacitor 732 (C2) may have capacitances in the range of 3 pF to 500 PF. 29 1353111 96U003 26630twf.doc/n FIG. 8 is a simplified schematic diagram of an integrated microphone interface circuit in accordance with another embodiment of the present invention. As shown, a microphone interface circuit (MIC) 8 is similar to the microphone interface circuit 700 discussed above with respect to FIG. In Fig. 8, the 'MIC 800' includes an integrator circuit 811 instead of the integrator circuit 711 in the MIC 700. As shown, the integrator circuit 811 includes an amplifier 815, a switched capacitor circuit 82A, and a MOS mezzanine capacitor 830. This design allows the device area to be substantially reduced. The switched capacitor circuit 82 includes a capacitor 835 and four switches s!, S2, S3, and S4. As shown, Si and S2 are coupled to the first terminal of capacitor 835. S3 and S4 are coupled to the second terminal of the capacitor 835. In a particular embodiment, S2 and S4 are also coupled to a common mode reference voltage ▽. (10) 喔 如 。. In an embodiment, Si and S3 are responsive to the first programmable clock signal, and S2 and S4 are responsive to the second programmable clock signal Φ2. The amplifier circuit 815 includes a first input, a second input, and an output. The first input is in communication with S3 and the second input is coupled to S2 and S4 of the switched capacitor circuit 820. In the integrator circuit 811, a capacitor 830 is in communication with a first input and an output of the amplifier. According to an embodiment of the present invention, the gain conversion function of the MIC 800 can be expressed by the following formula. H(s)

Vout(s) Iin(S) -R2 RjTR3 'rT- 、C835 ;}Vout(s) Iin(S) -R2 RjTR3 'rT- , C835 ;}

Ci h C835 ) • R2-R3.C1.C2 Rj* R2+R3 • + s— \Ίφ Cm C1 + R2-C2 R2 + R3 在本發明之實施例中，麥克風介面電路MIC 800之操 30 1353111 96U003 26630tvvf.doc/n 作通常類似於MIC 700之操作。舉例而言，MIC8〇〇中之 反饋電路提供高DC迴路增益以及低AC迴路增益。在無 . 需外部組件的情況下，MIC 800在晶片上提供DC偏壓^ • AC耦合。此外，與MIC 700相比，MIC 800具有提供較 小裝置面積之優勢。 一如上文所論述’在MIC 700中之積分器級中，電阻721 常常為大電阻（例如，1〇〇 ΜΩ至500 ΜΩ )，其需要大的 φ 裝置面積。在MIC 80〇中，此電阻由開關式電容網路82〇 來提供，可使用比大電阻更小裝置面積實施。此外，由於 此為抽樣系統，故增益級上之反饋電容將提供抗鋸齒濾波 且大積分器電容提供平滑效果。在實施例中，由晶片上時 脈信號Φ1以及Φ2來控制開關式電容網路。藉由改變時脈 頻率’亦可實施靜嘵功能。 亦如圖8中所示，MOS夾層電容830用於MIC 800 中’代替圖7中之MIC 700中之反饋電容731。反饋電容 731通常彼大，例如，1〇〇 pF_3〇〇 pF。根據本發明之實施 • 例，用於MIC 800中之MOS夾層電容提供具有較小裝置 面積之所要的電容。 在本發明之實施例中，麥克風介面電路MIC 800之操 作通常類似於MIC 700之操作。舉例而言，MIC 800中之 反饋電路提供高DC迴路增益以及低AC迴路增益。在無 . 需外部組件的情況下，MIC 800在單一積體電路晶片中提 ’ 供DC偏壓與AC耦合。在實施例中，提供DC偏壓之電 路獨立於反饋電路。此外，與MIC 700相比，MIC 800具 31 1353111 96U003 26630twf.doc/n 有提供較小裝置面積之優勢。 圖9為根據本發明之又一實，例之積體麥克風介面電 • 路的簡化示意圖。如圖所示’積體麥克風介面電路（MIC) _ 900包括用於接收輸入信號vin之輸入端子9〇2以及用於 提供輸出信號Vout之輸出節點904。MIC 900亦包括經由 笔阻925 (R3)輕接至vin之麥克風參考908。視實施例 而定，麥克風參考908可提供參考電壓或參考電流。MIC φ 900亦包括具有耦接至Vin之輸入端907以及耦接至輸出 端子904之輸出端的第一放大器913。放大器913包括如 下文所論述自反饋電路接收反饋信號之第二輸入端9〇6。 根據本發明之實施例’ MIC 900包括在放大器913之輸入 端與輸出端之間連通的反饋電路。在圖9中所展示之特定 實例中，MIC 900包括與放大器913之輸出端9〇4以及輸 入端906以及輸入端907連通之兩個反饋路徑961以及 962。反饋路徑961包括電阻922(R2)以及電容932 (C2) 之並聯組合。反饋路徑962包括在放大器913之輸出端904 與輸入端906之間串聯連接的放大器電路917、積分器電 路911以及電阻924。在特定實施例中’積分器電路qu 包括放大器915、連接至放大器915之輸入端之電阻921 (R1)，以及連接於放大器915之輸入端與輸出端之間的電 容931 (C1)。在實施例中，電阻922以及電阻925為可程 式電阻。在特定實施例中，參考電壓▽。^^^心連接至放 ’大器915之第二輸入端。 在較佳實施例中，MIC 900中之放大器可為運算放大 32 1353111 96U003 26630twf.doc/n 态。但亦可使用其它適當放大器。在實施例中，放大器電 路917具有增益-1。在本發明之特定實施例中，輸入端子 -902可自麥克風（例如，駐極體麥克風）接收作為輸出信 號的vin。視實施例而定，亦可使用其它類型之麥克風。 視應用而定，Vin可為聲音頻帶信號或音訊頻帶信號。在 實施例中，輸出信號Vout可為耦接至CODEC之類比數位 轉換益（ADC)的音訊頻帶信號。在某些實施例中，麥克 • 風參考9〇8可為可程式電壓源。在特定實施例中，晶片上 可程式麥克風參考908經由晶片上電阻925將DC電流提 供至外部麥克風。在實施例中，電阻925為可程式電阻。 因此，在實施例中，本發明提供包括電阻925以及電壓參 考源908之晶片上麥克風偏壓電路。 根據本發明之實施例，可由以下公式表示MIC 9〇〇之 增益轉換函數。Ci h C835 ) • R2-R3.C1.C2 Rj* R2+R3 • + s— \Ίφ Cm C1 + R2-C2 R2 + R3 In an embodiment of the invention, the microphone interface circuit MIC 800 operates 30 1353111 96U003 26630tvvf.doc/n is generally similar to the operation of the MIC 700. For example, the feedback circuit in the MIC8〇〇 provides high DC loop gain and low AC loop gain. In the absence of external components, the MIC 800 provides DC bias on the wafer. In addition, the MIC 800 has the advantage of providing a smaller device area than the MIC 700. As discussed above, in the integrator stage of the MIC 700, the resistor 721 is often a large resistor (e.g., 1 〇〇 Ω to 500 Ω), which requires a large φ device area. In the MIC 80〇, this resistor is provided by a switched capacitor network 82〇, which can be implemented with a smaller device area than a large resistor. In addition, since this is a sampling system, the feedback capacitor at the gain stage provides anti-aliasing filtering and the large integrator capacitor provides smoothing. In an embodiment, the switched capacitor network is controlled by on-wafer clock signals Φ1 and Φ2. The quiet function can also be implemented by changing the clock frequency. As also shown in Figure 8, MOS mezzanine capacitor 830 is used in MIC 800 instead of feedback capacitor 731 in MIC 700 of Figure 7. The feedback capacitance 731 is usually large, for example, 1 〇〇 pF_3 〇〇 pF. In accordance with an embodiment of the present invention, the MOS interlayer capacitor used in the MIC 800 provides the desired capacitance with a smaller device area. In an embodiment of the invention, the operation of the microphone interface circuit MIC 800 is generally similar to the operation of the MIC 700. For example, the feedback circuit in the MIC 800 provides high DC loop gain and low AC loop gain. In the absence of external components, the MIC 800 provides DC bias and AC coupling in a single integrated circuit die. In an embodiment, the circuit that provides the DC bias is independent of the feedback circuit. In addition, compared to the MIC 700, the MIC 800 has a small device area of 31 1353111 96U003 26630twf.doc/n. Figure 9 is a simplified schematic diagram of an integrated microphone interface circuit in accordance with yet another embodiment of the present invention. As shown, the integrated microphone interface circuit (MIC) _ 900 includes an input terminal 9〇2 for receiving an input signal vin and an output node 904 for providing an output signal Vout. The MIC 900 also includes a microphone reference 908 that is lightly connected to the vin via the pen 925 (R3). Depending on the embodiment, the microphone reference 908 can provide a reference voltage or a reference current. The MIC φ 900 also includes a first amplifier 913 having an input 907 coupled to Vin and an output coupled to the output terminal 904. Amplifier 913 includes a second input terminal 〇6 that receives a feedback signal from a feedback circuit as discussed below. The MIC 900 includes a feedback circuit that communicates between an input and an output of the amplifier 913 in accordance with an embodiment of the present invention. In the particular example shown in FIG. 9, MIC 900 includes two feedback paths 961 and 962 that are coupled to output 9 〇 4 of amplifier 913 and input 906 and input 907. Feedback path 961 includes a parallel combination of resistor 922 (R2) and capacitor 932 (C2). Feedback path 962 includes an amplifier circuit 917, an integrator circuit 911, and a resistor 924 connected in series between output 904 of amplifier 913 and input 906. In a particular embodiment, the integrator circuit qu includes an amplifier 915, a resistor 921 (R1) coupled to the input of the amplifier 915, and a capacitor 931 (C1) coupled between the input and output of the amplifier 915. In an embodiment, resistor 922 and resistor 925 are programmable resistors. In a particular embodiment, the reference voltage ▽. The ^^^ heart is connected to the second input of the amplifier 915. In the preferred embodiment, the amplifier in the MIC 900 can be operationally amplified 32 1353111 96U003 26630twf.doc/n. However, other suitable amplifiers can also be used. In an embodiment, amplifier circuit 917 has a gain of -1. In a particular embodiment of the invention, input terminal - 902 can receive vin as an output signal from a microphone (e.g., an electret microphone). Other types of microphones may be used depending on the embodiment. Depending on the application, Vin can be a sound band signal or an audio band signal. In an embodiment, the output signal Vout can be an audio band signal coupled to an analog to digital conversion benefit (ADC) of the CODEC. In some embodiments, the microphone wind reference 9〇8 can be a programmable voltage source. In a particular embodiment, the on-wafer programmable microphone reference 908 provides DC current to the external microphone via the on-wafer resistor 925. In an embodiment, resistor 925 is a programmable resistor. Accordingly, in an embodiment, the present invention provides an on-wafer microphone bias circuit comprising a resistor 925 and a voltage reference source 908. According to an embodiment of the present invention, the gain conversion function of the MIC 9〇〇 can be expressed by the following formula.

H(s) = V^s)__ R2 + R4 Vin(s) R 2 根據本發明之實施例，在高頻率下，可由以下公式來 近似求得MIC 900之增益轉換函數。H(s) = V^s)__ R2 + R4 Vin(s) R 2 According to an embodiment of the present invention, at a high frequency, the gain conversion function of the MIC 900 can be approximated by the following formula.

Vout(s) ^n(S) 33 1353111 96U003 26630twf.doc/n 在較低頻率下，增益函數可由以下公式近似求得 根據本發明之實施例，在聲音或音訊頻帶頻率範圍 中，反饋迴路之AC迴路增益小，且DC迴路增益大。舉 # 例而言，在特定實施例中，MIC 900可具有大約80dB至 140dB之DC迴路增益。更特定言之，MIC 9〇〇之特徵由 大DC迴路增益以及低AC迴路增益表示，從而引起輸出 端子處之DC輸出電壓實質上等於第二參考電壓，且音訊 頻帶中之AC輸出電壓與以及輸入端子處之Ac輸入 電壓成線性比例。 在本發明之實施例中’在無需外部組件的情況下，麥 克風介面電路（MIC) 900在單一積體電路晶片中提供^^ 鲁 偏壓與AC耦合。在實施例中，提供DC偏壓之電路獨立 於反饋電路。在特定實施例中，可藉由選擇適當電阻以及 電容來獲得所要的轉換特徵。僅作為實例，電阻（R1)通 常具有在100 ΜΩ至500 ΜΩ之範圍中的高電阻，而電阻 922 (R2)、電阻923 (R3)以及電阻924 (R4)可具有lk Ω至500 kQ之範圍中的電阻。電容931(C1)以及電容932 ' (C2)可具有3 pF至500 pF之範圍中的電容。當然，一般 熱習此項技術者可認識其它變化、修改以及替代。 圖1〇為根據本發明之另一實施例之積體麥克風介面 34 1353111 96U003 26630twf.doc/n 電路的簡化示意圖。如圖所示，麥克風介面電路（MIC) 1000通巾鐘於上文參考圖9所論狀麥找介面電路 900。在圖1〇中，MIC 1〇〇〇包括積分器電路1〇11來代替 MIC 900中之積分盗電路911。如圖所示積分器電路顧 包括放大益1015、開關式電容電路1〇2〇 #&M〇s夾層電 合1〇3〇。此設計使得裝置面積實質上減小。開關式電容電 路1020_包括電容1〇35以及四個開關&、&、&以及S4。 如圖所示，Si以及S2耦接至電容1035之第一端子。&以 及S4耦接至電容1035之第二端子。在特定實施例中，& 以及s4亦祕至共同模式參考電壓Ve__Qde。在實施例 中，Si以及S4回應第一可程式時脈信號φι，而S2以及S3 回應第二可程式時脈信號Φ2。放大器電路1〇15包括第一 輸入端、第二輸入端，以及輸出端。第一輸入端與&連通， 且第二輸入端與開關式電容電路1020之S2以及S4連通。 在積分器電路1011中，電容1〇3〇與放大器1〇15之第一輸 入端以及輸出端連通。 根據本發明之實施例，可由以下公式表示MIC 10〇〇 之增ii轉換函數。 H(s) =Vout(s) ^n(S) 33 1353111 96U003 26630twf.doc/n At lower frequencies, the gain function can be approximated by the following equation, in accordance with an embodiment of the invention, in the frequency range of the sound or audio frequency band, the feedback loop The AC loop gain is small and the DC loop gain is large. For example, in a particular embodiment, MIC 900 can have a DC loop gain of approximately 80 dB to 140 dB. More specifically, the characteristics of the MIC 9〇〇 are represented by the large DC loop gain and the low AC loop gain, causing the DC output voltage at the output terminal to be substantially equal to the second reference voltage, and the AC output voltage in the audio band and The Ac input voltage at the input terminals is linearly proportional. In an embodiment of the invention, the microphone interface circuit (MIC) 900 provides a bias and AC coupling in a single integrated circuit wafer without the need for external components. In an embodiment, the circuit that provides the DC bias is independent of the feedback circuit. In a particular embodiment, the desired switching characteristics can be obtained by selecting appropriate resistors and capacitors. For example only, the resistor (R1) typically has a high resistance in the range of 100 ΜΩ to 500 ΜΩ, while the resistor 922 (R2), resistor 923 (R3), and resistor 924 (R4) may have a range of lk Ω to 500 kQ. Resistance in the middle. Capacitor 931 (C1) and capacitor 932 ' (C2) may have a capacitance in the range of 3 pF to 500 pF. Of course, those who are generally interested in this technology can recognize other changes, modifications, and alternatives. 1 is a simplified schematic diagram of an integrated microphone interface 34 1353111 96U003 26630twf.doc/n circuit in accordance with another embodiment of the present invention. As shown, the microphone interface circuit (MIC) 1000 is described above with reference to FIG. In Fig. 1A, the MIC 1A includes an integrator circuit 1〇11 in place of the integrating circuit 911 in the MIC 900. As shown in the figure, the integrator circuit includes amplifying benefit 1015, a switched capacitor circuit 1〇2〇 #&M〇s interlayer electrical connection 1〇3〇. This design allows the device area to be substantially reduced. The switched capacitor circuit 1020_ includes a capacitor 1 〇 35 and four switches &&,& and S4. As shown, Si and S2 are coupled to the first terminal of capacitor 1035. & and S4 are coupled to the second terminal of capacitor 1035. In a particular embodiment, & and s4 are also secret to the common mode reference voltage Ve__Qde. In an embodiment, Si and S4 are responsive to the first programmable clock signal φι, and S2 and S3 are responsive to the second programmable clock signal Φ2. The amplifier circuit 1〇15 includes a first input terminal, a second input terminal, and an output terminal. The first input is in communication with & and the second input is in communication with S2 and S4 of the switched capacitor circuit 1020. In the integrator circuit 1011, the capacitor 1〇3〇 is in communication with the first input terminal and the output terminal of the amplifier 1〇15. According to an embodiment of the present invention, the MIC conversion function of the MIC 10 可由 can be expressed by the following formula. H(s) =

Vout(S) R2 十 R4Vout(S) R2 ten R4

Vin(s) R2 S· r t®〕 、Cl035y c1.(i+s.r4.C2.R2+rJ 卜， Γ T® ) ^01035,, •R4.C 卜 C2 + S· ίΤφ ]-c,R4+il ^01035/ R2 ^ 在本發明之實施例中，麥克風介面電路MIC 1000之 35 1353111 96U003 26630twf.doc/n 操作通常類似於MIC 900之操作。舉例而言，MIC 1000 中之反饋電路提供高DC迴路增益以及低AC迴路增益。 在無需外部組件的情況下，MIC 1000在單一積體電路晶片 中提供DC偏壓與AC耦合。在實施例中，提供DC偏壓 之電路獨立於反饋電路。此外，與MIC 900相比，MIC 1000 具有提供較小裝置面積之優勢。 如上文所論述，在]VflC 900中之積分器級中，電阻921 常常為大電阻（例如，1〇〇 ΜΩ至500 ΜΩ )，其需要較大 的裝置面積。在MIC 1000中，此電阻由開關式電容網路 1020來提供’其可使用比大電阻更小的裝置面積實施。此 外’由於此為抽樣系統，故增益級上之反饋電容將提供抗 鑛齒濾波且大積分器電容提供平滑。由晶片上時脈信號 以及Φ2來控制開關式電容網路。藉由改變時脈頻率，亦可 實施靜噪功能。 亦如圖10中所示，MIC 1000包括M〇s夹層電容 1030，代替圖9中之MIC 9〇〇中之反饋電容93卜反饋電 谷931通常很大，例如，1〇〇 pF-300 pF。根據本發明之實 施例，用於MIC 1000中之MOS夾層電容提供所要的電 容，但需要較小裝置面積。 圖11為根據本發明之實施例之用於可程式麥克風介 面的積體電路之簡化示意圖。如圖所示，MIC 1100為用於 提供可程式麥克風介面之積體電路。MIC 1100包括用於接 收輸入信號Vin之輸入端子1102以及用於提供輸出音訊信 號Vout之輸出端子1104qMIC 1100亦包括與輸入端子 36 1353111 96U003 26630twf.doc/n 1102連通之偏壓電路。如圖所示，偏壓電路包括麥克風參 考電路1108以及電阻1125。在實施例中，11〇8為可程^ ， 參考電路。視實施例而定，麥克風參考電路11〇8可提供表 考電壓或參考電流。MIC 1100包括第—放大器電路lu'/, 第一放大器電路1113包括第一輸入端11〇6、第二輸入端 1107以及耦接至輸出端子11〇4之輸出端。MIC 11〇〇更包 括第一反饋電路1161，f 一反饋電路1161包括並聯連接 • 之電阻1122以及電容11%。第一反饋電路耦接放大器1113 之輸出端與第一輸入端。MIC 1100亦包括第二反饋電路 1162，第二反饋電路1162包括積分器電路llu以及電阻 1124。第二反饋電路1162於節點1163處提供反饋信號。 在實施例中，電阻1122以及電阻1125為可程式電阻。 如圖所示，積分器電路1111包括放大器1115、開關 式電容電路1120 ’以及MOS夾層電容1130。積分器電路 mi之結構以及功能通常類似於圖ίο中之積分器以 及圖8中的積分益815之結構以及功能。開關式電容電路 112()以及MOS夹層電谷1130提供所要的電阻以及電容且 消耗相對小的裝置面積。 MIC 1100中之反饋電路提供高DC迴路增益以及低 AC迴路增盃。更特定言之，MIC 1100之特徵由大DC迴 • 路增益以及低AC迴路增益表示，從而引起輸出端子處之 DC輸出電壓實質上等於第二參考電壓，且AC輸出電壓與 第一反饋電路之阻抗以及經過輪入端子之Ac輸入電流或 電壓成線性比例。根據本發明之實施例，在無需外部組件 37 1353111 96U003 26630twf.doc/nVin(s) R2 S· rt®], Cl035y c1.(i+s.r4.C2.R2+rJ 卜, Γ T® ) ^01035,, •R4.C 卜C2 + S· ίΤφ ]-c, R4+il ^01035/ R2 ^ In the embodiment of the present invention, the operation of the microphone interface circuit MIC 1000 35 1353111 96U003 26630twf.doc/n is generally similar to the operation of the MIC 900. For example, the feedback circuit in the MIC 1000 provides high DC loop gain and low AC loop gain. The MIC 1000 provides DC bias and AC coupling in a single integrated circuit die without the need for external components. In an embodiment, the circuit that provides the DC bias is independent of the feedback circuit. In addition, the MIC 1000 has the advantage of providing a smaller device area than the MIC 900. As discussed above, in the integrator stage of the VflC 900, the resistor 921 is often a large resistance (e.g., 1 〇〇 Ω to 500 Ω), which requires a large device area. In the MIC 1000, this resistor is provided by a switched capacitor network 1020, which can be implemented using a smaller device area than a large resistor. In addition, since this is a sampling system, the feedback capacitor at the gain stage will provide anti-mineral filtering and the large integrator capacitance will provide smoothing. The switched capacitor network is controlled by the clock signal on the wafer and Φ2. The squelch function can also be implemented by changing the clock frequency. As also shown in FIG. 10, the MIC 1000 includes a M〇s mezzanine capacitor 1030 instead of the feedback capacitor 93 in the MIC 9〇〇 of FIG. 9. The feedback valley 931 is usually large, for example, 1〇〇pF-300. pF. In accordance with an embodiment of the present invention, the MOS interlayer capacitor used in the MIC 1000 provides the desired capacitance, but requires a smaller device area. Figure 11 is a simplified schematic diagram of an integrated circuit for a programmable microphone interface in accordance with an embodiment of the present invention. As shown, the MIC 1100 is an integrated circuit for providing a programmable microphone interface. The MIC 1100 includes an input terminal 1102 for receiving an input signal Vin and an output terminal 1104q MIC 1100 for providing an output audio signal Vout. The bias circuit is also coupled to the input terminal 36 1353111 96U003 26630twf.doc/n 1102. As shown, the bias circuit includes a microphone reference circuit 1108 and a resistor 1125. In the embodiment, 11〇8 is a programmable circuit and a reference circuit. Depending on the embodiment, the microphone reference circuit 11A8 can provide a reference voltage or a reference current. The MIC 1100 includes a first amplifier circuit lu'/, and the first amplifier circuit 1113 includes a first input terminal 11〇6, a second input terminal 1107, and an output terminal coupled to the output terminal 11〇4. The MIC 11 further includes a first feedback circuit 1161, and a feedback circuit 1161 includes a resistor 1122 and a capacitor 11% connected in parallel. The first feedback circuit is coupled to the output end of the amplifier 1113 and the first input end. The MIC 1100 also includes a second feedback circuit 1162 that includes an integrator circuit 11u and a resistor 1124. The second feedback circuit 1162 provides a feedback signal at node 1163. In an embodiment, resistor 1122 and resistor 1125 are programmable resistors. As shown, the integrator circuit 1111 includes an amplifier 1115, a switched capacitor circuit 1120', and a MOS interlayer capacitor 1130. The structure and function of the integrator circuit mi is generally similar to the structure and function of the integrator in Fig. 8 and the integral benefit 815 in Fig. 8. Switched capacitor circuit 112() and MOS interlayer valley 1130 provide the desired resistance and capacitance and consume relatively small device area. The feedback circuit in the MIC 1100 provides high DC loop gain and low AC loop boost. More specifically, the characteristics of the MIC 1100 are represented by a large DC return gain and a low AC loop gain, thereby causing the DC output voltage at the output terminal to be substantially equal to the second reference voltage, and the AC output voltage is coupled to the first feedback circuit. The impedance and the Ac input current or voltage through the wheeled terminals are linearly proportional. According to an embodiment of the invention, no external components are required 37 1353111 96U003 26630twf.doc/n

的情況下，MIC 1100能夠在單一積體電路晶片中提供DC 偏壓與AC耦合。在實施例中，提供Dc偏壓之電路獨立 於反饋電路。 以上僅以實例說明之，本發明已被應用至用於駐極體 麥克風（electret microphone)之介面電路。但應體認到， 本發明具有範圍更加廣泛之適用性。舉例而言，可將本笋 明應用至其他種類之麥克風之介面電路或其他信號源之^ 面電路。 儘管麥克風介面電路之組件的選定群組已於上文中闡 述，但可存在許多替代、修改以及變化。舉例而言，可擴 展及/或組合一些組件。可將其它組件***至上文提及之組 件。視實施例而定，組件之配置可與代替之其他配置進行 交換。此等組件之其它細節可在本說明書全文中發現。 亦應理解，本文所描述之實例以及實施例僅為達成說 明之目的，且將向熟習此項技術者提議根據所述實例以及 實施例之各種修改或改變，且所述各種修改或改變將包括 在此s兒明書的精神以及範圍以及所附申請專利範圍之範疇 内。 【圖式簡單說明】 圖1為習知麥克風CODEC介面電路之示意圖。 圖2a為根據本發明之實施例之積體麥克風介面電路 的簡化示意圖。 圖2b為根據本發明之實施例之積體麥克風介面電路 的增益轉換函數之簡化圖。 38 1353111 96U003 2663〇twf.doc/n 圖3為根據本發明之另一會於^ 路的簡化示意圖。 力私例L克風介面電 圖4為根據本發明之替代性 介面電路㈣化示意圖。 Μ之龍差動麥克風 圖5為根據本發明之又一眚a 7 , 路的簡化示意圖。 ’之積體麥克風介面電 圖6為根據本發明之另一替代性奋 介面電路的簡化示4圖。 s ®•例之積體麥克風 圖7為根據本發明之又一實施 路的簡化示意圖。 艾積體麥克風介面電 圖8為根據本發明之另一替代 介面電路的簡化示意圖。 1施例之積體麥克風 圖9為根據本發明之又一實施 路的簡化示S®。 k㈣錢風介面電 圖10為根據本發明之另一替代性每 風介面電路的簡㈣意圖。 a例之積體麥克 圖11為根據本發明之實施例之用於 面電路的積«路之簡“賴。τ料麥克風介 【主要元件符號說明】 100 : 麥克風介面電路 102 ： 駐極體麥克風 112 ： 電阻 114 ： 電阻 122 ： 電容 39 1353111 96U003 26630twf.doc/n 132 :電阻 134 :電阻 136 :電阻 138 :電阻 142 :電容 144 :電容 146 :電容 φ 148 :電容 150 : CODEC積體電路 200 :積體麥克風介面電路 202 :輸入節點 204 :輸出節點 206 :輸入端 207 :輸入端 208 :麥克風參考電壓源 211 :積分器電路 • 213 :放大器 215 :放大器 217 :放大器 221 :電阻 222 :電阻 *' 223 :電阻 • 224 :電阻 225 :電阻 1353111 96U003 26630twf.doc/n 231 :電容 232 :電容 261 :反饋路徑 262 :反饋路徑 ' 300:麥克風介面電路 311 :積分器電路 315 :放大器 I 320:開關式電容電路 330 : MOS夾層電容 335 :電容 400 :積體麥克風介面電路 401 :輸入節點 402 :輸入節點 403 :輸出節點 404 :輸出節點 407 :麥克風參考電壓源 • 411 :差動反饋電路 413 :放大器 415 :放大器 421 :電阻 422 :電阻 • 423 :電阻 • 424 :電阻 425 :電阻 41 1353111 96U003 26630twf.doc/n 431 :電容 432 :電容 441 :輸入端 442 :輸入端 451 :電阻 452 :電阻 453 ·•電阻 454 :電阻 455 :電阻 457 :接地電壓 461 :反饋路徑、電容 462 :反饋路徑、電容 463 :反饋路徑 464 :反饋路徑 500 :積體麥克風介面電路 502 :節點 504 :輸出節點 507 :麥克風參考電壓源 511 :積分器電路 513 :放大器 515 :放大器 517 :放大器 521 :電阻 522 :電阻 42 1353111 96U003 26630twf.doc/n 524 :電阻 531 :電容 532 :電容 541 :輸入端 542 :輸入端 561 :反饋路徑 562 :反饋路徑 600 :麥克風介面電路 611 :積分器電路 620 :開關式電容網路 630 : MOS夾層電容 635 :電容 700 ··積體麥克風介面電路 702 :輸入端子 704 :輸出節點 706 :輸入端 707 :第二輸入端 708 :麥克風參考電路 711 :積分器電路 713 :放大器 715 :放大器 721 :電阻 722 :電阻 725 :電阻 43 1353111 96U003 26630twf.doc/n 731 :電容 732 :電容 761 :反饋路徑 762 :反饋電路 800 :麥克風介面電路 811 :積分器電路 815 :放大器 820 :開關式電容電路 830 : MOS夾層電容 835 :電容 900 :積體麥克風介面電路 902 :輸入端子 904 :輸出節點 906 :第二輸入端 907 :輸入端 908 :麥克風參考電路 911 :積分器電路 913 :放大器 915 :放大器 917 :放大器電路 921 :電阻 922 :電阻 924 :電阻 925 :電阻 44 1353111 96U003 26630twf.doc/n 931 :電容 932 :電容 961 :反饋路徑 962 :反饋路徑 1000 :麥克風介面電路 1011 :積分器電路 1015 :放大器 1020 :開關式電容電路 1030 : MOS夾層電容 1035 :電容 1100 :麥克風介面電路 1102 :輸入端子 1104 :輸出端子 1106 :第一輸入端 1107 ··第二輸入端 1108 :麥克風參考電路 1111 :積分器電路 1113 :放大器電路 1115 :放大器 1120 :開關式電容電路 1122 :電阻 1124 :電阻 1125 :電阻 1130 : MOS夾層電容 45 1353111 96U003 26630twf.doc/n 1132 :電容 1135 :第二電容 1141 :開關裝置 1142 :開關裝置 1161 :第一反饋電路 1162 :第二反饋電路 1163 :節點 Si ： 開關 s2 ： 開關 s3: 開關 s4: 開關In this case, the MIC 1100 is capable of providing DC bias and AC coupling in a single integrated circuit die. In an embodiment, the circuit that provides the Dc bias is independent of the feedback circuit. The above has been explained by way of example only, and the present invention has been applied to an interface circuit for an electret microphone. However, it should be appreciated that the invention has a broader range of applicability. For example, the application can be applied to other types of microphone interface circuits or other signal sources. Although a selected group of components of the microphone interface circuit have been described above, many alternatives, modifications, and variations are possible. For example, some components may be expanded and/or combined. Other components can be inserted into the components mentioned above. Depending on the embodiment, the configuration of the components can be exchanged with other configurations instead. Further details of such components can be found throughout the specification. It is also understood that the examples and embodiments described herein are for the purpose of illustration only, and that various modifications and changes in It is within the scope of the spirit and scope of the invention and the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a conventional microphone CODEC interface circuit. 2a is a simplified schematic diagram of an integrated microphone interface circuit in accordance with an embodiment of the present invention. Figure 2b is a simplified diagram of the gain transfer function of an integrated microphone interface circuit in accordance with an embodiment of the present invention. 38 1353111 96U003 2663〇twf.doc/n Figure 3 is a simplified schematic diagram of another circuit in accordance with the present invention. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 Μ之龙差声 Figure 5 is a simplified schematic diagram of another 眚a 7 road according to the present invention. Integrated Microphone Interface Electrical Figure 6 is a simplified pictorial diagram of another alternative interface circuit in accordance with the present invention. s ® • Example Integrated Microphone Figure 7 is a simplified schematic diagram of yet another embodiment of the present invention. Ai Integrated Microphone Interface Electrical Figure 8 is a simplified schematic diagram of another alternative interface circuit in accordance with the present invention. 1 Integrated Microphone of Embodiment FIG. 9 is a simplified illustration S® according to still another embodiment of the present invention. k (4) Money Wind Interface Figure 10 is a simplified (four) intent of another alternative wind interface circuit in accordance with the present invention. The integrated circuit diagram of the example a is a simplified circuit for the surface circuit according to the embodiment of the present invention. The material of the microphone is used. [Main component symbol description] 100: Microphone interface circuit 102: electret microphone 112 : Resistor 114 : Resistor 122 : Capacitor 39 1353111 96U003 26630twf.doc / n 132 : Resistor 134 : Resistor 136 : Resistor 138 : Resistor 142 : Capacitor 144 : Capacitor 146 : Capacitance φ 148 : Capacitor 150 : CODEC Integral Circuit 200 : Integrated Microphone Interface Circuit 202: Input Node 204: Output Node 206: Input 207: Input 208: Microphone Reference Voltage Source 211: Integrator Circuit • 213: Amplifier 215: Amplifier 217: Amplifier 221: Resistor 222: Resistor*' 223: resistance • 224: resistance 225: resistance 1353111 96U003 26630twf.doc/n 231: capacitor 232: capacitor 261: feedback path 262: feedback path '300: microphone interface circuit 311: integrator circuit 315: amplifier I 320: switching Capacitor circuit 330: MOS interlayer capacitor 335: capacitor 400: integrated microphone interface circuit 401: input node 402: input node 403: output node 404: output node 407 : Microphone reference voltage source • 411 : Differential feedback circuit 413 : Amplifier 415 : Amplifier 421 : Resistor 422 : Resistor • 423 : Resistor • 424 : Resistor 425 : Resistor 41 1353111 96U003 26630twf.doc/n 431 : Capacitor 432 : Capacitor 441 : Input 442 : Input 451 : Resistor 452 : Resistor 453 ·• Resistor 454 : Resistor 455 : Resistor 457 : Ground voltage 461 : Feedback path , Capacitor 462 : Feedback path , Capacitor 463 : Feedback path 464 : Feedback path 500 : Product Body microphone interface circuit 502: node 504: output node 507: microphone reference voltage source 511: integrator circuit 513: amplifier 515: amplifier 517: amplifier 521: resistor 522: resistor 42 1353111 96U003 26630twf.doc/n 524: resistor 531: Capacitor 532: Capacitor 541: Input 542: Input 561: Feedback path 562: Feedback path 600: Microphone interface circuit 611: Integrator circuit 620: Switched capacitor network 630: MOS interlayer capacitor 635: Capacitor 700 ·· Microphone interface circuit 702: input terminal 704: output node 706: input terminal 707: second input terminal 708: microphone reference circuit 711: integrator circuit 713: 715: amplifier 721: resistor 722: resistor 725: resistor 43 1353111 96U003 26630twf.doc/n 731: capacitor 732: capacitor 761: feedback path 762: feedback circuit 800: microphone interface circuit 811: integrator circuit 815: amplifier 820 Switched Capacitor Circuit 830: MOS Sandwich Capacitor 835: Capacitor 900: Integrated Microphone Interface Circuit 902: Input Terminal 904: Output Node 906: Second Input 907: Input 908: Microphone Reference Circuit 911: Integrator Circuit 913: Amplifier 915: amplifier 917: amplifier circuit 921: resistor 922: resistor 924: resistor 925: resistor 44 1353111 96U003 26630twf.doc/n 931: capacitor 932: capacitor 961: feedback path 962: feedback path 1000: microphone interface circuit 1011: integration Circuit 1015: Amplifier 1020: Switched Capacitor Circuit 1030: MOS Sandwich Capacitor 1035: Capacitor 1100: Microphone Interface Circuit 1102: Input Terminal 1104: Output Terminal 1106: First Input 1107 · Second Input 1108: Microphone Reference Circuit 1111: integrator circuit 1113: amplifier circuit 1115: amplifier 1120: switched capacitor circuit 1122: resistor 1124: Resistor 1125: Resistor 1130: MOS interlayer capacitor 45 1353111 96U003 26630twf.doc/n 1132: Capacitor 1135: Second capacitor 1141: Switching device 1142: Switching device 1161: First feedback circuit 1162: Second feedback circuit 1163: Node Si: Switch s2: switch s3: switch s4: switch

Claims (1)

13531111353111 100-7-15 十、申請專利範圍： 1. 一種用於提供麥克風介面之積體 路包括：100-7-15 X. Patent Application Range: 1. An integrated system for providing a microphone interface. 輸入端子，用於接收輸入信號； 輸出端子，用於提供輸出信號； 偏壓電路，耦接至所述輸入端子 處提供偏壓信號，所述偏壓電路經配 信號； 第-放大器電路’包括第-輪人端、第二輸入端以 士輸出端’所述第-輸人端經配置以接收所述感測輪入 L號、第一反饋彳§號以及第二反饋信號，所述第二輸入 端經配置以減第-參考信號，所述輸出端經配置以將 所述輸出信號提供至所述輸出端子； 第一反饋電路，與所述第一放大器電路之所述輸出 端以及所述第一輸入端連通，所述第一反饋電路將所述An input terminal for receiving an input signal; an output terminal for providing an output signal; a bias circuit coupled to the input terminal to provide a bias signal, the bias circuit being equipped with a signal; a first amplifier circuit The first-input terminal is configured to receive the sensing wheel-in L number, the first feedback parameter, and the second feedback signal, including a first-wheel terminal and a second input terminal Said second input is configured to reduce a first reference signal, said output being configured to provide said output signal to said output terminal; a first feedback circuit, said output of said first amplifier circuit And the first input is in communication, the first feedback circuit will 電路，所述積體電 以在所述輸入端子 置以提供感測輸入 弟一反饋彳§號提供至所述第一放大器電路之所述第一 輸入端；以及 第二反饋電路，與所述第一放大器電路之所述輸出 端以及所述第一輸入端連通，所述第二反饋電路將所述 第二反饋信號提供至所述第一放大器電路之所述第一 輪入端’所述第二反饋電路包括積分器電路。 2.如申請專利範圍第1項所述之用於提供麥克風介面 之積體電路’其中所述輸入端子經配置以在無需外部組件 的情況下自一駐極體麥克風接收輸入信號。 47 100-7-15 3. 如申請專利範圍第1項所述之用於提供麥克風介面 之積體電路，其中所述偏壓電路包括： 參考電路，用於提供第二參考信號，所述第二參考信 號包括參考電壓或參考電流； 第一輸入端電阻，與所述輸入端子以及所述參考電路 連通；以及a circuit, the integrated body is provided at the input terminal to provide a sensing input, and the feedback is provided to the first input end of the first amplifier circuit; and a second feedback circuit, The output of the first amplifier circuit is in communication with the first input, and the second feedback circuit provides the second feedback signal to the first turn-in end of the first amplifier circuit The second feedback circuit includes an integrator circuit. 2. The integrated circuit for providing a microphone interface as described in claim 1 wherein the input terminal is configured to receive an input signal from an electret microphone without the need for external components. 47 100-7-15. The integrated circuit for providing a microphone interface according to claim 1, wherein the bias circuit comprises: a reference circuit for providing a second reference signal, The second reference signal includes a reference voltage or a reference current; a first input resistor connected to the input terminal and the reference circuit; 第二輸入端電阻，與所述輸入端子以及所述第一放大 器電路之所述第二輸入端連通。 4. 如申請專利範圍第丨項所述之用於提供麥克風介面 之積體電路’其中所述第—反饋電路包括處於並聯配置之 第一反饋電阻以及第一反饋電容。 5. 如申請專利範圍第丨項所述之用於提供麥克風介面 之積體電路，其中所述積分器電路包括： 反相放大器，耦接至所述第一放大器電路之所述輪出A second input resistor is coupled to the input terminal and the second input of the first amplifier circuit. 4. The integrated circuit for providing a microphone interface as described in the scope of the patent application, wherein the first feedback circuit comprises a first feedback resistor and a first feedback capacitor in a parallel configuration. 5. The integrated circuit for providing a microphone interface according to claim </ RTI> wherein the integrator circuit comprises: an inverting amplifier coupled to the wheel of the first amplifier circuit 第一放大益電路，所述第二放大器電路包括第一輪入 =第二輸人端以及輸㈣，所述L端減至第三 參考信號； 第二反饋電阻，_至所述反減大器之輸出端以及 所述第，放大器電路之所述第—輸入端；以及 第—反饋電谷，輕接至所述第二放大器電路之所述第 —輸入端以及所述輸出端； 48 1353111 100-7-15 6.如申請專利範圍第丨項所述之用於提供麥克風介面 之積體電路’其中所述積分器電路包括： 開關式電容電路，包括開關電容以及第一開關、第二 開關、第三開關以及第四開關，所述第一開關以及所述第 二開關耦接至所述開關電容之第一端子，所述第三開關以 及所述第四開關耦接至所述開關電容之第二端子，所述第 二開關以及所述第四開關耦接至所述第一參考信號； =二放大器電路，包括第一輸入端、第二輸入端以及 輸出端，所述第一輸入端與所述開關式電容電路之所述第 二開關連通，所述第二輸入端耦接至所述第一參考信號· 以及 〆° ~ ’ 弟一反饋電容，與所述第二放大器電路之所述第一輸 入端以及所述輸出端連通。 7·如申請專娜圍第1項所狀用於提供麥克風介面 之積體電路，更包括供應電壓，其中所述第一參考信號大 小上為所述供應電壓之約一半以驗提供所 由所述供應f壓允許的最大信號鶴。 處 8·如申請專利_第丨項所述之用於提供麥克風介面 之積體電路，其中所述積體電路之特徵由DC迴路增益表 示，所述DC迴路增益大到足以引起所述第一放大器之所 述輸出端處之電壓實質上等於所述第一參考信號。 9.如申請專利範圍第8項所述之用於提供麥克風介面 之積體電路’其中所述積體麥克風介面電路之特徵由約8〇 dB至約140 dB之範圍中的DC迴路增益表示。 49 1353111 100-7-15 10.如申請專利範圍第1項所述之用於提供麥克風介 面之積體電路，其中所述積體電路之特徵由大DC迴路增 益以及低AC迴路增益表示，從而引起所述輸出端子處之 DC輸出電壓實質上等於所述第一參考信號，且AC輸出電 壓與所述第一反饋電路之阻抗以及經過所述輸入端子之 AC輸入電流或電壓成線性比例。 u. —種用於提供麥克風介面之積體電路，包括： 第一輸入端子以及第二輸入端子，分別用於接收第一 差動輸入信號以及第二差動輸入信號； 第一輸出端子以及第二輸出端子，分別用於提供第一 差動輸出信號以及第二差動輸出信號； 第一偏壓電路，與所述第一輸入端子以及第一參考信 號連通，所述第一偏壓電路提供第一感測輸入信號； 第二偏壓電路，與所述第二輸入端子以及第二參考信 號連通，所述第二偏壓電路提供第二感測輸入信號； 第一放大器電路，所述第一放大器具有第一輸入端、 第二輸入端以及第三輸人端，所述第—輸人端接收所述第 一感測輸入信號’所述第二輸入端接收第二感測輸入信 號，。所述第三輪人端接收制模式參考信號，所述第一放 大器電路亦具有第-輸出端以及第二輸出端，所述第一輸 出端以及舰第二輸出端分職所述第—差動輸出音訊信 號以及所述第二差動輸出音訊信號提供至所述第一輸出端 子以及所述第二輸出端子；以及 反饋電路，所述反饋電路與所述第一放大器電路之所 50 1353111 100-7-15 述第一輸入端以及所述第二輸入端以及所述第一輸出端以 及所述第二輸出端連通。 12. 如申請專利範圍第η項所述之用於提供麥克風介 面之積體電路’其中所述第一輸入端子以及所述第二輸入 端子經配置以在無需外部組件的情況下自一駐極體麥克風 接收輸入信號。 13. 如申請專利範圍第11項所述之用於提供麥克風介 Φ 面之積體電路，其中所述第一偏壓電路包括： 第三電阻’與所述第一輸入端子以及麥克風參考信號 源連通；以及 第四電阻’與所述第一輸入端子以及所述第三電阻連 通，所述第四電阻提供所述第一感測輸入信號。 14. 如申請專利範圍第η項所述之用於提供麥克風介 面之積體電路，其中所述第二偏壓電路包括： 第五電阻’與所述第二輸入端子以及接地參考電壓源 連通；以及 •帛六電阻’與所述第二輸人端子以及所述第五電阻連 通，所述第=電阻提供所述第二感測輸入信號。 15·如申清專利範圍第u項所述之用於提供麥克風介 面之積體電路，其中所述反饋電路更包括： 、第1饋電路，與所述第一放大器之所述第一輸出端 以及所述第冑入端連通，所述第一反饋電路包括並聯連 接之第一電阻以及第一電容； 第-反饋電路，與所述第一放大器之所述第二輸出端 51 1353111 100-7-15 以及所述第二輸入端連通’所述第二反饋電路包括並聯連 接之第二電阻以及第二電容；以及 差動反饋電路，所述差動反饋電路包括分別耦接至所 述第一放大器電路之所述第一輸出端以及所述第二輸出端 的第一輸入端以及第二輸入端，所述差動反饋電路亦包括 分別耦接至所述第一放大器電路之所述第一輸入端以及所 述第二輸入端的第一輸出端以及第二輸出端。 % 16.如申請專利範圍第15項所述之用於提供麥克風介 面之積體電路，其中所述差動反饋電路更包括： 差動放大器’具有第一輸入端、第二輸入端以及第三 輪入端以及第一輸出端以及第二輸出端，所述第三輸入端 接收所述共同模式參考信號； 第一電阻，連接至所述差動放大器之所述第一輸入端； 苐一電阻’連接至所述差動放大器之所述第一輸出端； 第一電容，連接所述差動放大器之所述第一輸入端與 g 所述第一輸出端； 第三電阻’連接至所述差動放大器之所述第二輸入端； 第四電阻，連接至所述差動放大器之所述第二輸出 端；以及 第二電容，連接所述差動放大器之所述第二輸入端與 所述第二輸出端。 Π. —種用於提供麥克風介面之積體電路，包括： 輸入端子，用於接收輸入信號； 輸出端子’用於提供輸出信號； 52 1353111 100-7-15 偏壓電路’用於提供偏壓信號； 第一放大器電路，包括第一輸入端、第二輸入端以及 輸出端，所述第一輸入端經配置以接收所述偏壓信號、第 反饋k號以及第二反饋信號，所述第二輸入端經配置以 接收第一參考信號’所述輸出端經配置以將所述輸出信號 提供至所述輪出端子；a first amplification circuit, the second amplifier circuit comprising a first wheel input = a second input terminal and a transmission (four), the L terminal being reduced to a third reference signal; and a second feedback resistor, _ to the inverse reduction The output of the device and the first input terminal of the first amplifier circuit; and the first feedback electric valley, lightly connected to the first input end of the second amplifier circuit and the output end; 48 1353111 100-7-15 6. The integrated circuit for providing a microphone interface as described in the scope of the patent application, wherein the integrator circuit comprises: a switched capacitor circuit including a switched capacitor and a first switch, a second a switch, a third switch, and a fourth switch, the first switch and the second switch are coupled to the first terminal of the switched capacitor, and the third switch and the fourth switch are coupled to the switch a second terminal of the capacitor, the second switch and the fourth switch are coupled to the first reference signal; a second amplifier circuit comprising a first input terminal, a second input terminal, and an output terminal, the first Input and location The second switch of the switched capacitor circuit is in communication, the second input end is coupled to the first reference signal and the first feedback capacitor, and the first one of the second amplifier circuit The input end and the output end are connected. 7. The application of the integrated circuit for providing a microphone interface according to Item 1 of the application, further comprising a supply voltage, wherein the first reference signal is about half of the supply voltage to provide a solution for the supply. The maximum signal crane allowed to supply f pressure. 8. The integrated circuit for providing a microphone interface, wherein the feature of the integrated circuit is represented by a DC loop gain, the DC loop gain being large enough to cause the first The voltage at the output of the amplifier is substantially equal to the first reference signal. 9. The integrated circuit for providing a microphone interface as described in claim 8 wherein the characteristic of the integrated microphone interface circuit is represented by a DC loop gain in the range of about 8 〇 dB to about 140 dB. 49 1353111 100-7-15 10. The integrated circuit for providing a microphone interface according to claim 1, wherein the characteristic of the integrated circuit is represented by a large DC loop gain and a low AC loop gain, thereby The DC output voltage at the output terminal is caused to be substantially equal to the first reference signal, and the AC output voltage is linearly proportional to the impedance of the first feedback circuit and the AC input current or voltage through the input terminal. The integrated circuit for providing a microphone interface, comprising: a first input terminal and a second input terminal, respectively for receiving the first differential input signal and the second differential input signal; the first output terminal and the Two output terminals for respectively providing a first differential output signal and a second differential output signal; a first bias circuit connected to the first input terminal and the first reference signal, the first bias current The first sensing input signal is provided; the second biasing circuit is in communication with the second input terminal and the second reference signal, the second biasing circuit provides a second sensing input signal; the first amplifier circuit The first amplifier has a first input terminal, a second input terminal, and a third input terminal, the first input terminal receives the first sensing input signal, and the second input terminal receives a second sense Measure the input signal. The third round of the human terminal receives the mode reference signal, the first amplifier circuit also has a first output end and a second output end, and the first output end and the second output end of the ship are divided into the first difference a dynamic output audio signal and the second differential output audio signal are provided to the first output terminal and the second output terminal; and a feedback circuit, the feedback circuit and the first amplifier circuit 50 1353111 100 -7-15 The first input end and the second input end are in communication with the first output end and the second output end. 12. The integrated circuit for providing a microphone interface as described in claim n, wherein the first input terminal and the second input terminal are configured to self-elect without an external component The body microphone receives the input signal. 13. The integrated circuit for providing a microphone interface according to claim 11, wherein the first bias circuit comprises: a third resistor 'and the first input terminal and a microphone reference signal a source connected; and a fourth resistor 'in communication with the first input terminal and the third resistor, the fourth resistor providing the first sense input signal. 14. The integrated circuit for providing a microphone interface according to claim n, wherein the second bias circuit comprises: a fifth resistor ′ connected to the second input terminal and a ground reference voltage source And a sixth resistor 'in communication with the second input terminal and the fifth resistor, the third resistance providing the second sensed input signal. The integrated circuit for providing a microphone interface according to the invention of claim 5, wherein the feedback circuit further comprises: a first feed circuit, and the first output end of the first amplifier And the first input terminal is connected, the first feedback circuit includes a first resistor and a first capacitor connected in parallel; a first feedback circuit, and the second output end of the first amplifier 51 1353111 100-7 And the second input terminal is connected to the second feedback circuit, wherein the second feedback circuit includes a second resistor and a second capacitor connected in parallel; and a differential feedback circuit, the differential feedback circuit includes a first coupling to the first The first output end of the amplifier circuit and the first input end and the second input end of the second output end, the differential feedback circuit also includes the first input respectively coupled to the first amplifier circuit And a first output and a second output of the second input. The integrated circuit for providing a microphone interface according to claim 15, wherein the differential feedback circuit further comprises: the differential amplifier having a first input, a second input, and a third a first input terminal and a second output end, wherein the third input terminal receives the common mode reference signal; a first resistor connected to the first input end of the differential amplifier; Connecting to said first output of said differential amplifier; a first capacitor connected to said first input of said differential amplifier and said first output; said third resistor 'connected to said a second input of the differential amplifier; a fourth resistor coupled to the second output of the differential amplifier; and a second capacitor coupled to the second input of the differential amplifier Said second output.积. An integrated circuit for providing a microphone interface, comprising: an input terminal for receiving an input signal; an output terminal 'for providing an output signal; 52 1353111 100-7-15 bias circuit 'for providing a bias a first amplifier circuit, comprising: a first input, a second input, and an output, the first input being configured to receive the bias signal, the feedback k, and the second feedback signal, The second input is configured to receive a first reference signal 'the output is configured to provide the output signal to the wheel-out terminal; 第一反饋電路，所述第一反饋電路與所述第一放大器 電路之所述輪出端以及所述第一輸入端連通，所述第一反 饋電路將所述第一反饋信號提供至所述第一放大器電路之 所述第一輸入端；以及 …第二反饋電路，所述第二反饋電路與所述第一放大器 電路之所述輪出端以及所述第一輸入端連通，所述第二反 饋電路將所述第二反饋信號提供至所述第一放大器電路之 所述第一輸入端，所述第二反饋電路包括積分器電路。a first feedback circuit, the first feedback circuit is in communication with the rounding end of the first amplifier circuit and the first input end, the first feedback circuit providing the first feedback signal to the a first input terminal of the first amplifier circuit; and a second feedback circuit, the second feedback circuit being in communication with the wheel terminal of the first amplifier circuit and the first input terminal, the first A second feedback circuit provides the second feedback signal to the first input of the first amplifier circuit, the second feedback circuit comprising an integrator circuit. 18.如申請專利範圍第π項所述之用於提供麥克風介 面之積體電路，其中所述輸入端子經配置以在益 件的情況T自駐紐麥克風触“錢。—卜^ 以如申請專利範圍帛η項所述之用於提供麥克風介 面之積體電路，其中所述偏壓電路包括： 參考電路，用於提供第二參考信號，·所述第二參考作 旒為參考電壓或參考電流； 入端子以及所述參考電路 第一輸入端電阻，與所述輸 連通；以及 入端子以及所述第一放大 第'一輸入端電阻，與所述輪 53 100-7-15 r電路之所述第一輸入端連通。 面之巾請糊範圍第17項所述之用於提供麥克風介 積體電路’其中所述第—反饋電路包括處於並聯配置 弟—反饋電阻以及第一反饋電容。 21. 如申請專利範圍帛^項所述之用於提供麥克風介 之積體電路’其中所述積分器電路包括： 反相放大^’輕接至所述第-放大器電路之所述輸出 端； 第二放大H電路，包括第—輸人端、第二輸入端以及 輸出，，所述第二輸入端耦接至第三參考信號； 、第二反饋電阻，耦接至所述反相放大器之輸出端以及 所述第二放大器電路之所述第一輸入端；以及 第一反饋電容，耦接至所述第二放大器電路之所述第 一輸入端以及所述輸出端； 其中所述第二放大器電路之所述輸出端經由第三反饋 電阻耦接至所述第一放大器電路之所述第二輸入端。 22. 如申請專利範圍第17項所述之用於提供麥克風介 面之積體電路’其中所述積分器電路包括： 開關式電容電路，包括開關電容以及第一開關、第二 開關、第二開關以及第四開關，所述第一開關以及所述第 二開關耦接至所述開關電容之第一端子，所述第三開關以 及所述第四開關耦接至所述開關電容之第二端子，所述第 二開關以及所述第四開關耦接至所述第一參考信號； 第二放大器電路，所述第二放大器電路包括第一輸入 54 1353111 100-7-15 鈿第一輸入端以及輸出端，所述第一輸入端與所述開關 式電容電路之所述第三開關連通，所述第二輸入端輕接至 所述第一參考信號；以及 第一反饋電谷，與所述第二放大器電路之所述第一輸 入端以及所述輸出端連通。 23. 如申請專利範圍第17項所述之用於提供麥克風介 面之積體電路，其中所述積體電路之特徵由DC迴路增益 表示，所述DC迴路增益大到足以引起所述第一放大器之 所述輸出端處之電壓實質上等於所述第一參考信號。 24. 如申請專利範圍第23項所述之用於提供麥克風介 面之積體電路，其中所述積體麥克風介面電路之特徵由約 80 dB至約140 dB之範圍中的DC迴路增益表示。 25. 如申請專利範圍第17項所述之用於提供麥克風介 面之積體電路，其中所述積體電路之特徵由大DC迴路增 益以及低AC迴路增益表示，從而引起所述輸出端子處之 DC輸出電壓貫質上等於所述第一參考信號，且AC輸出電 φ 壓與所述第一反饋電路之阻抗以及經過所述輸入端子之 AC輸入電流或電壓成線性比例。 5518. The integrated circuit for providing a microphone interface according to claim π, wherein the input terminal is configured to touch "money" from the resident microphone in the case of the benefit item. The integrated circuit for providing a microphone interface according to the scope of the patent, wherein the bias circuit comprises: a reference circuit for providing a second reference signal, wherein the second reference is used as a reference voltage or a reference current; an input terminal and a first input resistance of the reference circuit, in communication with the output; and an input terminal and the first amplified first input resistance, and the wheel 53 100-7-15 r circuit The first input end is connected to the surface. The surface of the surface is provided for providing a microphone dielectric circuit, wherein the first feedback circuit comprises a parallel configuration, a feedback resistor and a first feedback capacitor. 21. The integrated circuit for providing a microphone according to the scope of the patent application, wherein the integrator circuit comprises: inverting amplification to lightly connect to the output of the first amplifier circuit The second amplification H circuit includes a first input terminal, a second input end, and an output, the second input end is coupled to the third reference signal, and a second feedback resistor coupled to the inverting An output of the amplifier and the first input of the second amplifier circuit; and a first feedback capacitor coupled to the first input of the second amplifier circuit and the output; The output of the second amplifier circuit is coupled to the second input of the first amplifier circuit via a third feedback resistor. 22. The product for providing a microphone interface as described in claim 17 The integrator circuit includes: a switched capacitor circuit including a switched capacitor and a first switch, a second switch, a second switch, and a fourth switch, wherein the first switch and the second switch are coupled to a first terminal of the switched capacitor, the third switch and the fourth switch are coupled to a second terminal of the switched capacitor, and the second switch and the fourth switch are coupled to the a reference signal; a second amplifier circuit, the second amplifier circuit comprising a first input 54 1353111 100-7-15 钿 a first input and an output, the first input and the switched capacitor circuit The third switch is in communication, the second input is lightly connected to the first reference signal; and the first feedback electric valley is in communication with the first input end of the second amplifier circuit and the output end. 23. The integrated circuit for providing a microphone interface according to claim 17, wherein the characteristic of the integrated circuit is represented by a DC loop gain, the DC loop gain being large enough to cause the first amplifier The voltage at the output terminal is substantially equal to the first reference signal. 24. The integrated circuit for providing a microphone interface according to claim 23, wherein the integrated microphone interface circuit is characterized Expressed by the DC loop gain in the range of approximately 80 dB to approximately 140 dB. 25. The integrated circuit for providing a microphone interface according to claim 17, wherein the characteristic of the integrated circuit is represented by a large DC loop gain and a low AC loop gain, thereby causing the output terminal to be The DC output voltage is qualitatively equal to the first reference signal, and the AC output voltage φ is linearly proportional to the impedance of the first feedback circuit and the AC input current or voltage through the input terminal. 55
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TW97104269A TWI353111B (en) 2008-02-04 2008-02-04 Programmable integrated microphone interface circu

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TW200935735A (en) 2009-08-16

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