1342109 九、發明說明： 【發明所屬之技術領域】 ， 本發_關於直流偏移校正技術，尤指-_由比較訊號值與 預定臨界絲校正前賴狀錢雜的校正裝置及方法。 【先前技術】 -般而言’為了調整因為通道效應，因為製程、電源供應電壓、 鲁或是溫度變化，或是因其他因素所造成的直流偏移（Dc〇ffset)， 以使得所接收進來的訊號值之變動範圍能夠落在後級電路（例如 類比數位轉㈣）的_翻（dynamierange)巾，㈣免訊號 .值因飽和（saturatoO而失真，在通訊系統的接收端或是其他有 .此需求的系統中，均會設計一直流偏移校正（DCoffsetcalibmtion) 機制。 目前直流偏移校正裝置大致上可分成_，分別是線上(〇n line) 校正與離線(off-line)校正，其中線上校正直流偏移的機制一般係直 接使用交流耗合(AC Coupling)的方式來即時地消除輸入訊號的直 流偏移，或者使用迴路控制以回授的方式來消除輸入訊號的直流 偏移，然而此種機制由於電阻、電容元件本身會使得時間常數(time constant)過大而導致對於輸入訊號之直流準位改變的反應速度將 會過慢；另一方面，離線校正直流偏移的機制則係在離線時便預 先決疋出用來消除直流偏移的調整量，而在線上運作時便直接使 用該調整量來消除輸入訊號的直流偏移，然而，此種機制因為只 5 1342109 少該輸出訊號與一預定臨界值來決定該偏移校正訊號。 【實施方式】 . 請參照第1圖，第1圖是本發明第一實施例之直流偏移校正裝 . 置100的示意圖。如第1圖所示，直流偏移校正裝置1〇〇包含有 調整電路105與偏移校正電路110,其中調整電路1〇5包含有調整 單元115與放大單元120，並用來依據偏移校正訊號&之電壓準 ^ 位來調低輸入訊號&的電壓準位，調整單元115係以減法器(如第 1圖所示)來加以實現，而放大單元120係為一單端放大器 (single-endedamplifier)並使用增益Al來放大調整單元115的輸出 Sin’以產生輸出訊號S〇ut，因此，調整電路1〇5依據偏移校正訊號 Sc的電壓準位來調整輸入訊號Sin的電壓準位以產生輸出訊號 S0ut;另外’偏移校正電路11〇係依據輸出訊號3邮與預定臨界值(例 如預定臨界電壓準位)Vth、Vth’來決定偏移校正訊號&，其中Vth _的數值大於V*的數值，偏移校正電路11〇包含有電容c與校正 電路125，其中校正電路125包含有比較器c〇MP、c〇MP，與電 晶體Q、Q’ ’並控制電容c進行充電或放電來調整偏移校正 訊號Sc之電壓準位，以間接調整輸人訊號&的電壓準位；電容c 進灯充電或放電的條件係為：若触減s⑽滿足對應賊臨界電 壓準位或是νΑ’的-預定條件時，則偏移校正電路11〇將調整 偏移校正訊號S。，反之’若輸出喊SQUt未滿足該職條件，則 偏移校正電路11G將鋪偏移校正訊號&。 1342109 出訊號sout、偏移校正訊號Sc與預定臨界值Vd、Vd，(本實施例中， 其係為預定臨界電駐)來蚊偏移校正減Se，其巾歉臨界電 壓差vd、vd係分別為二極體D、D’導通時所需要的電壓差，而校 正電路225會分別透過二極體D、D，控制電容c進行放電或充電 來調整偏移校正訊號sc以間接調整輸入訊號Sin的電壓準位；電容 C進行充電或放電的條縣為：若輸出訊號、與偏移校正訊號 sc滿足對應預定臨界電壓差Vd’(或是Vd)：^_預定條件時，則偏移1342109 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a DC offset correction technique, and more particularly to a correction apparatus and method for correcting a signal value and a predetermined threshold. [Prior Art] - Generally speaking, in order to adjust the DC offset (Dc〇ffset) due to the channel effect, due to process, power supply voltage, Lu or temperature change, or other factors, so that it is received The range of signal values can fall within the dynamie range of the latter circuit (for example, analog to digital (4)), (4) the signal is free. The value is saturated due to saturation (saturatoO, at the receiving end of the communication system or other. In this system of requirements, a DC offset settling correction (DCoffsetcalibmtion) mechanism is designed. Currently, the DC offset correction device can be roughly divided into _, which is an online (〇n line) correction and an off-line correction, wherein The mechanism for correcting the DC offset on the line generally uses the AC Coupling method to instantly eliminate the DC offset of the input signal, or uses the loop control to feedback the DC offset of the input signal. This mechanism causes the response speed to change the DC level of the input signal due to the excessive time constant of the resistor and capacitor components. The degree will be too slow; on the other hand, the mechanism for correcting the DC offset offline is to pre-determine the amount of adjustment used to eliminate the DC offset when offline, and use the adjustment directly to eliminate the online operation. The DC offset of the input signal. However, this mechanism determines the offset correction signal because only 5 1342109 has the output signal and a predetermined threshold. [Embodiment] Please refer to FIG. 1 , and FIG. 1 is the present invention. A DC offset correction device of the first embodiment is shown in Fig. 1. As shown in Fig. 1, the DC offset correction device 1A includes an adjustment circuit 105 and an offset correction circuit 110, wherein the adjustment circuit 1〇5 includes There is an adjusting unit 115 and an amplifying unit 120, and is used for lowering the voltage level of the input signal & according to the voltage level of the offset correction signal & the adjusting unit 115 is a subtractor (as shown in FIG. 1). To be implemented, the amplifying unit 120 is a single-ended amplifier and uses the gain A1 to amplify the output Sin' of the adjusting unit 115 to generate an output signal S〇ut. Therefore, the adjusting circuit 1〇5 is offset. Correction The voltage level of the signal Sc is used to adjust the voltage level of the input signal Sin to generate the output signal S0ut; and the 'offset correction circuit 11 is based on the output signal 3 and a predetermined threshold (for example, a predetermined threshold voltage level) Vth, Vth To determine the offset correction signal & wherein the value of Vth_ is greater than the value of V*, the offset correction circuit 11A includes a capacitor c and a correction circuit 125, wherein the correction circuit 125 includes comparators c〇MP, c〇 MP, and the transistor Q, Q' ' and control the capacitor c to charge or discharge to adjust the voltage level of the offset correction signal Sc to indirectly adjust the voltage level of the input signal & the capacitor c into the lamp to charge or discharge The condition is that if the touch minus s(10) satisfies the threshold voltage level of the corresponding thief or the predetermined condition of νΑ', the offset correction circuit 11〇 adjusts the offset correction signal S. On the contrary, if the output call SQUt does not satisfy the job condition, the offset correction circuit 11G will apply the offset correction signal & 1342109 The signal sout, the offset correction signal Sc and the predetermined threshold value Vd, Vd, (in the present embodiment, it is a predetermined critical electric station), the mosquito offset correction minus Se, the apologetic threshold voltage difference vd, vd The voltage difference required for the diodes D and D' to be turned on respectively, and the correction circuit 225 separately adjusts the input signal by adjusting the offset correction signal sc by discharging or charging the diodes D and D respectively. The voltage level of Sin; the county where the capacitor C is charged or discharged is: if the output signal and the offset correction signal sc satisfy the predetermined threshold voltage difference Vd' (or Vd): ^_ predetermined condition, then the offset
•校正電路210會調整偏移校正訊號Sc，反之，若輸出訊號U 偏移权正訊號Se未滿足該預定條件，則偏移校正電路21〇會保持 偏移校正訊號Sc。 -- 在本實施例中’該預定條件為輸出訊號Sout與偏移校正訊號& 的電壓差達到預定臨界電壓差vd或vd’。例如，若輸出訊號s〇ut 的電壓準位大於偏移校正訊號Sc之電壓準位(亦即二極體D，之p 型區的電壓準位大於其N型區的電壓準位)並且其電壓差達到預定 • 臨界電壓差Vd’時，則二極體D’會因為順向偏壓電壓差大於其導 通所需要的預定臨界電壓差Vd，而導通，二極體D則因為處於反 向偏壓的狀態而不導通，因此，輸出訊號s0ut將透過二極體D，對 電容C進行充電，而偏移校正訊號sc的電壓準位因為電容c進行 充電而提升’並間接地降低輸入訊號Sin的電壓準位來達成控制輸 入訊號sin之電壓準位於一振幅範圍内以避免過高的直流準位偏 移；反之’若輸出訊號Sout之電壓準位小於偏移校正訊號8(；的電 壓準位(亦即二極體D之N型區的電壓準位小於其P型區的電壓準 10 1342109 位)並且其電壓差達到預定臨界電壓差Vd，則二極體D會因為順 向偏壓電壓差大於其導通所需要的預定臨界電壓差Vd而導通，二 極體D’則因為處於反向偏壓狀態而不導通，因此，電容c會透過 二極體D來放電，而偏移校正訊號Sc的電壓準位會因為電容c進 行放電而降低，將可間接地提升輸入訊號Sin的電壓準位來達成控 制輸入訊號8^的電壓準位於一振幅範圍内以避免過低的直流準位 偏移。 如上所述可知，當輸出訊號8邮達到預定臨界電壓準位％或 XV時’二極體D及D’二者其中之-會因為輸出訊號^之狀態而 導通，並藉此㈣时進行錢偏移校正之偏移校正減&的電 壓準位，也就是說，此時本實施例之直流偏移校正裝置2⑻乃是 以閉迴路回授的方式來進行直流偏移校正。相反地，當輸出訊號 S〇ut處於預定臨界電壓準位％及％’之間時，二極體D及D，二者 均因輸出訊號5。„,之狀_處於_狀態，因此輸出訊號^並不 會對用來進行直流偏移校正之财校正峨&的電鮮位造成影 響，偏移校正峨\的電鮮蝴會因為電容效絲轉先前的 狀態；也就是說，辦本實施例之直流偏移校正裝置2〇〇乃是以 開迴路回授的方式，藉由所維持的先前狀態來進行直流偏移校正。 此外，於其他實施例中，亦可參考放大單元m放大前的訊 號不參考放大單元120的輸出來校正輸入訊號Sin的直流偏移，亦 即直接將調整單元m的輸出Sin，鎖入比較器c〇Mp、c〇Mp，或 '：£ ) 1342109The correction circuit 210 adjusts the offset correction signal Sc. Conversely, if the output signal U offset right signal Se does not satisfy the predetermined condition, the offset correction circuit 21 maintains the offset correction signal Sc. In the present embodiment, the predetermined condition is that the voltage difference between the output signal Sout and the offset correction signal & reaches a predetermined threshold voltage difference vd or vd'. For example, if the voltage level of the output signal s〇ut is greater than the voltage level of the offset correction signal Sc (ie, the diode D, the voltage level of the p-type region is greater than the voltage level of the N-type region) and When the voltage difference reaches the predetermined threshold voltage difference Vd', the diode D' will be turned on because the forward bias voltage difference is greater than the predetermined threshold voltage difference Vd required for its conduction, and the diode D is in the opposite direction. The state of the bias voltage is not turned on. Therefore, the output signal s0ut will pass through the diode D to charge the capacitor C, and the voltage level of the offset correction signal sc is boosted by the charging of the capacitor c and indirectly reduces the input. The voltage level of the signal Sin is obtained to control the voltage of the input signal sin to be within an amplitude range to avoid an excessive DC level offset; otherwise, if the voltage level of the output signal Sout is smaller than the offset correction signal 8 (; The voltage level (that is, the voltage level of the N-type region of the diode D is smaller than the voltage level of the P-type region 10 1342109 bits) and the voltage difference reaches a predetermined threshold voltage difference Vd, the diode D will be forward The bias voltage difference is greater than that required for its conduction The threshold voltage difference Vd is turned on, and the diode D' is not turned on because it is in a reverse bias state. Therefore, the capacitor c is discharged through the diode D, and the voltage level of the offset correction signal Sc is due to The capacitor c is discharged and lowered, and the voltage level of the input signal Sin can be indirectly raised to achieve that the voltage of the control input signal 8^ is within an amplitude range to avoid an excessively low DC level shift. As described above, When the output signal 8 reaches the predetermined threshold voltage level % or XV, the two of the 'diodes D and D' will be turned on due to the state of the output signal ^, and the offset of the money offset correction will be performed by (4). The shift correction subtracts the voltage level of the &, that is, the DC offset correction device 2 (8) of the present embodiment performs the DC offset correction in a closed loop feedback manner. Conversely, when the output signal S〇 When ut is between the predetermined threshold voltage level % and %', the diodes D and D, both of which are output signals 5, „, the shape _ is in the _ state, so the output signal ^ will not be used for DC offset correction financial correction 峨 & The bit is affected, the offset correction 峨\ is turned on because the capacitive effect wire is turned to the previous state; that is, the DC offset correction device 2 of the present embodiment is in the open loop feedback mode. The DC offset correction is performed by the previous state that is maintained. In other embodiments, the DC signal before the amplification is not referenced to the output of the amplification unit 120 to correct the DC offset of the input signal Sin. That is, directly insert the output Sin of the adjustment unit m into the comparator c〇Mp, c〇Mp, or ':£) 1342109
是二極體D、D’並設定適當的預定臨界電壓準位Vth、Vth’或是預 定臨界電壓差vd或vd，’此種形式的電路組態亦可達到校正輸入 訊號sin之直流偏移的目的(請參閱第3圖以及第4圖，第3圖與第 4圖分別是本發明第三、第四實施例之直流偏移校正裝置3〇〇與 400的示意圖）。再者，請參閱第5圖與第6圖，第5圖與第ό圖 分別是本發明第五、第六實施例之直流偏移校正裝置5〇〇與6〇〇 的示意圖，偏移校正電路11〇、21〇可應用於校正差動輸入訊號Si、 S2之直流偏移以及差動放大電路121中因電晶體製程不匹配所造 成的直流偏移。接著，請參閱第7圖，第7圖為第5圖與第6圖 中之差動放大電路121之一實施例的示意圖。第7圖中所示者係 為一常見之差動放大電路，差動放大電路121係由複數個主動元 件如電阳體來分別作為其增益級（gainstage)及貞載 其實作方式及操作原理係為翻此徽術者所廣泛悉知故不在 此贅述。應注意的是，差動放大電路121另包含有-共模回授路 徑’输於其輸出端及輸入端之間，用以將輸出端之正負端訊號 之共模電壓（即直流準位）控制於—參考共模電壓值I。於本實 施例中’共模回麟㈣由_讀出端之二電阻及-比較器7〇5 所組成’比較器7〇5係依據該二電阻之中點電壓與參考共模電壓 值L來控制二主動負載。藉由上述共模回授路徑之運作'，輸出 =號之正負端訊號Sl，、S2，之直流準位即可趨於—致，此時再加以 =所處理之差動喊具有最錄幅對稱或是固紐封的特性， =正負端峨Sl’、S2’之其中之—因偏移校正電路⑽或21〇之 而進仃了直流偏移之校正時，其另一將亦得以讀保會有同等 12 1342109 的校正效果。 另外’在上述實施例中，若僅考慮校正過高的直流偏移，則 可由校正電路125中移除比較器COMP，與電晶體Q，或是由校正電 路225中移除二極體D，此時校正電路125僅於輸出訊號Sout大於 預定臨界電壓準位νώ時控制電晶體Q導通以使電容c進行充電 來達到調校過高直流偏移的目的，而校正電路225則僅於二極體 φ D’導通時對電容C進行充電來達到調校過高直流偏移的目的；另 一方面，若僅考慮校正過低的直流偏移，則可由校正電路125中 移除比較器COMP與電晶體q或是由校正電路225中移除二極體 D，此時校正電路125僅於輸出訊號S0UJ、於預定臨界電壓準位 -Vth時控制電晶體Q’導通以使電容C進行放電來達到調校過低直 流偏移的目的，而校正電路225則僅於二極體D導通時藉由電容 C進行放電來達到調校過低直流偏移的目的。 鲁 對於-差動輸入訊號對而言，若其具有最大振幅（peak amplitude)對稱或是固定波封（c〇nstantenvel〇p)的特性（例如無 線區域網路（WLAN)中正交分頻多工（0FDM)訊號的前置資 料（preamble))，則只要在設計直流偏移校正機制時，同時控制使 得差動輸入訊號對之正負兩端的直流位準趨於一致，即可達到同 時校正差動訊號之正負兩端之直流偏移的目的。由於對於上述具 有最大振幅對稱或是固定波封特性的差動訊號對而言，其正端訊 號的最大振幅（即其峰值至其直流位準之大小）係與其負端訊號 13 的最大振幅相對稱（即大小相同而方向相反），因此，只要能在進 行直流偏移校正的同時，將校正後之正端訊號與負端訊號的直流 位準調整制-值，即可顧#其+之-的錢偏移校正滿足後 級電路的輸人範圍要树，其另—的錢偏移校正亦滿足之。 "月參閱第8 ®，第8暇本發明第七實施例之直流偏移校正裝 置_的示意圖。如第8圖所示，直流偏移校正裝置_係分別 •校正輸入訊號S】、S2 (在此假設輸入訊號Si、&具有最大振幅對 稱或疋固定波封的特性）以及直流偏移校正裝置_中差動放大 電路805因製程不匹配所造成的直流偏移以產生輸出訊號^，、 V。直流偏移校正裝置_另包含有調整單元81〇、奶（分別利 用減法器835與840來實現）與偏移校正電路825、83〇，其中調 整單元810依據偏移校正訊號sel的電壓準位來調整輸入訊號Si 的電壓準位’其調紐的輸纽驗過放大而產生輸出訊號Si，， 鲁調整單元815則依據偏移校正訊號S(；2的電壓準位來調整輸入訊號 S2的電壓準位’而其調整後的輸出訊號亦經過放大以產生輸出訊 號 S2’。 ° 另外，偏移校正電路825包含有電容(^以及具有電晶體(^與 比較器COIVC^的校正電路845,其用於依據輸出訊號Si’之電壓準 位與預定臨界值νώ來決定偏移校正訊號Scl的電壓準位，若輸出 訊號S〗’滿足對應預定臨界值乂出的一第一預定條件時，則偏移校 正電路825會利用比較器COMPl控制電晶體Ql導通來對電容& 1342109 進行充電以調整偏移校正訊號sel，此時，直流偏移校正裝置800 P會因電晶體Qi之導通而形成一閉迴路（closed loop)直流偏移 校正機制；若輸出訊號sr未滿足該第一預定條件，則偏移校正電 路825會利用比較器c〇MPi控制電晶體q關閉，偏移校正電路 825即會保持偏移校正訊號Sel，此時，直流偏移校正裝置8〇〇即 會因電0曰體Q1之關閉而形成一開迴路（open loop)直流偏移校正 機制，此外，偏移校正電路830包含有電容c2與具有電晶體仏 •與比較11 C0MP2的校正電路，其係用來依據輸出訊號&，之電 壓準位與預定臨界值Vth來決定偏移校正訊號Sc的電壓準位，其 中若輸出赠s2，滿足對應駭臨界值Vthn預定條件時， 則偏移权正電路83〇才會利用比較器c〇Mp2控制電晶體導通 來f電谷C：2進行充電以調整偏移校正訊號h，反之，若輸出訊號 S2未滿足該第二預定條件，則偏移校正電路83〇會保持偏移校正 訊號Sc2。 上所述，預定臨界值Vth係為-預定臨界電鮮位，該第一 預疋條件料輸出峨\’的㈣準位超過預定臨界電壓準位 th而該第一預疋條件則為輸出訊號s 2,的電壓準位超過預定臨 2壓準位Vth。因此，若第—歡條件成立，則比較器C0MP1 i由邏輯準位的控制訊號來導通電晶體Q1 ’電源％將 :電日日體Q1而對電容C1進行充電，偏移校正訊號&的電壓準 立^將隨著電容Cl的充電而提升，而透過減法器835的作用，輪 入几號s〗的電壓準位將被調降而產生輸出訊號I，，因此，輸出訊 15 號sr的電鮮位其最高值將受限於默臨界賴準位％。同樣 地’若第二預定條件成立，則偏移校正電路83()的操作亦相同“ 偏移校正電路825的操作’味器COMP2會輸出具有低邏輯準位 的控制訊號終通電晶體(¾，魏％將經由電晶體⑶而對電容 C2進行充電，偏.移校正訊號s。2的電壓準位亦將隨著電容q的充 電而提升’並透過減法器_的作用，輸人訊號&的電壓準位將 被調降而產生輸出訊號S2’，因此輸出訊號S2,的電壓準位其最高 值亦受歸臨界準位Vth ^如上所述，偏移校正電路2 與830分別將輸出訊ESl’、S2，的最高電壓準位限制於同一預定臨 界電壓準位vth ’而由於輸人峨Si、S2具有最大振騎稱或是固 定波封的躲，則只要關藉續定之㈣機制，使得兩輸入訊 號Si、S2的直流偏移趨於相同數值，即可達到正負訊號&、~同 時元成直流偏移校JL之目;故對於後級電路（如類比數位轉換 器’未顯示於第8圖巾）而言，若預定臨界電壓準位^之值係設 計為較其輸人之㈣範圍為小，輸人端的餘偏移即不會發 生訊號飽合的現象1然，本實施例中之直流偏移校正裝置_ 亦可配合如第7圖所示之包含有共模回授路徑之差動放大電路 121併操作，以確保其正負端訊號均得到適當之校正。因此，對 於後級電路（未齡於第8圖中）來說在峨放大時將不會因為 直流偏移而發生飽和現象。 此外，將兩差動輸出訊號之最低振幅（即另一方向之峰值）限 制於相同預疋臨界電壓準位的方式亦可達成將其校正至相同的直 W偏移準位，請參㈣9圖，第9圖是本發明第八實施例之直流 偏移k正襞置900的示意圖。直流偏移校正裝置8〇〇、9〇〇的主要 - 差異在於直流偏移校正裝置900係依據預定臨界電壓準位Vth，並 分別利用偏移校正電路925、930中的比較器COM&、COMPj 電谷C!、C：2經由電晶體Q〆、Q2’來對地進行放電而非利用電源 Vcc進行充電來達成將差動輸出訊號S!，、S2’校正至相同的直流偏 移準位。若第一預定條件成立，亦即輸出訊號\，的電壓準位低於 參預定臨界電壓準位Vth，，則比較器COMPi會輸出具有高邏輯準位 的控制訊號來導通電晶體。，，電gCi將經由電晶體，對地放 電’偏移校正訊號sel的電壓準位亦將隨著電容Ci的放電而降低， •因此’輸入訊號S1的電壓準位將被提升而產生輸出訊號Si，，故輸 出訊號S!的電塵準位最低只能達到預定臨界電壓準位Vth，；同樣 地，若第二預定條件成立，亦即輸出訊號S2’的電壓準位低於預定 臨界電壓準位W，電容<：2將經由電晶體Q2,對地放電，偏移校 正訊號S。2的電壓準位會隨著電容C2的放電而降低，輸入訊號s2 的電壓準位將被提升而產生輸出訊號1，，故輸出訊號§2,的電壓 準位最低只能達到預定臨界電壓準位Vth’。如上所述，輸出訊號 S!’、S2’的最低電壓準位將被限制於相同的電壓準位乂出，。同樣地， 本實施例中之直流偏移校正裝置900亦會配合如第7圖所示之包 含有共模回授路徑之差動放大電路121 —併操作，以確保其正負 端訊號均得到適當之校正。因此，對於後級電路（未顯示於第9 圖中）來說在訊號放大時將不會因為直流偏移而發生飽和現象。 17 ^42109 凊參閱第10圖，第10圖是本發明第九實施例之直流偏移校正 裝置1000的示意圖，其中直流偏移校正裝置1000係分别利用輸 出訊號Sr與S2’的電壓準位、偏移校正訊號3<；1與sc2以及校正電 路1045與1050所包含的二極體單元(為簡化說明，第1〇圖中僅分 別以二極體D!、Dz來表示之)所對應的預定臨界值vD來決定偏移 校正訊號Scl、Sc的電壓準位’而預定臨界值vD於本實施例中係 為預定臨界電壓差。當輸出訊號\’滿足對應預定臨界電壓差ν〇 鲁的一第一預定條件時(本實施例中，第一預定條件係為輸出訊號Sl， 與偏移校正訊號Scl的電壓差達到預定臨界電壓差Vd)，偏移校正 電路1025才會調整偏移校正訊號\丨，否則偏移校正電路ι〇25會 保持偏移校正訊號Scl ;同樣地，當輸出訊號&’滿足對應預定臨 界電壓差VD的一第二預定條件時(本實施例中，第二預定條件係 為輸出訊號S2’與偏移校正訊號Sc2的電壓差達到預定臨界電壓差 vD)，偏移校正電路1030才會調整偏移校正訊號3。2，否則偏移校 φ正電路1030會保持偏移校正訊號SC1。 預定臨界電壓差VD係指使三極體DrE>2順向導通所需要的最 低偏廢’即開啟電壓（咖-011她哪）（在此假設其偏壓均相同）， 換a之’當輸出訊號S1’之電壓準位高於偏移校正鱗^的電壓 準位並達到預定臨界頓差VD時，二極體D1會導躺輸出訊號 S!會經由二極體Dl對電容C!進行充電以提升偏移校正訊號L 的電壓準位，同樣地，當輸出訊號心，之電壓準位高於偏移校正訊 ’號Sc2的電壓準位並達到預定臨界電壓差VD時，輸出訊號s2，將經 1342109 由被導通的二極體A對電容C2進行充電以提升偏移校正訊號〜 的電鮮位；囉地，本實關巾之直流偏移校正裝置誦亦會 配合如第7圖所示之包含有共模回授路徑之差動放大電路121 一 併操作，以確保其正負端訊號均得到適當之校正，而使得後級電 路不會發生錯誤操作。 請參閱第11圖，第11圖是本發明第十實施例之直流偏移校正 ^ 裝置1100的示意圖。在此實施例中，其係將第10圖所示之二極 體Di、D2的連接關係置換成如第u圖所示之二極體Di、D2，亦 即，將一極體D]、〇2的P型區分別改為連接至偏移校正訊號心丨 . 與S。2,而其N型區則分別改為連接至輸出訊號Si，與&，，因此， •-當輸出訊號sr之電壓準位低於偏移校正訊號Sci之電壓準位而達 到預疋&«界電壓差VD時，電容Q會經由導通的二極體進行放 電來降低偏移校正訊號Scl的電壓準位，並且當輸出訊號&，之電 壓準位低於偏移校正訊號S。2的電壓準位而達到預定臨界電壓差Is the diode D, D' and set the appropriate predetermined threshold voltage level Vth, Vth' or the predetermined threshold voltage difference vd or vd, 'this form of circuit configuration can also achieve the DC offset of the corrected input signal sin The purpose (refer to Fig. 3 and Fig. 4, Figs. 3 and 4 are schematic views of the DC offset correcting devices 3A and 400 of the third and fourth embodiments of the present invention, respectively). Furthermore, please refer to FIG. 5 and FIG. 6 , which are schematic diagrams of the DC offset correction devices 5 〇〇 and 6 第五 of the fifth and sixth embodiments of the present invention, respectively, and offset correction. The circuits 11A, 21A can be applied to correct the DC offset of the differential input signals Si, S2 and the DC offset caused by the transistor process mismatch in the differential amplifier circuit 121. Next, referring to Fig. 7, Fig. 7 is a schematic view showing an embodiment of the differential amplifier circuit 121 in Figs. 5 and 6. The figure shown in FIG. 7 is a common differential amplifying circuit, and the differential amplifying circuit 121 is composed of a plurality of active components such as an electric positive body as its gain stage and the actual operation mode and operation principle. It is not widely described here that it is widely known to those who have turned this emblem. It should be noted that the differential amplifying circuit 121 further includes a - common mode feedback path 'between the output terminal and the input terminal for the common mode voltage of the positive and negative terminals of the output terminal (ie, the DC level). Controlled - reference common mode voltage value I. In the present embodiment, the 'common mode remake (4) is composed of the second resistor of the _ sense terminal and the comparator 7 〇 5 'the comparator 7 〇 5 is based on the midpoint voltage of the two resistors and the reference common mode voltage value L To control the two active loads. By the operation of the above-mentioned common mode feedback path, the DC level of the positive and negative terminal signals S1, S2 of the output = sign can be tended to be the same, and then the differential call processed by the = is the most recorded. Symmetry or the characteristics of the solid seal, = positive and negative terminals 峨Sl', S2' - when the offset correction circuit (10) or 21〇 is corrected for DC offset, the other will be read The guarantee has the same 12 1342109 correction effect. In addition, in the above embodiment, if only the excessive DC offset is corrected, the comparator COMP may be removed from the correction circuit 125, or the diode Q may be removed, or the diode D may be removed by the correction circuit 225. At this time, the correction circuit 125 controls the transistor Q to be turned on to charge the capacitor c to achieve the purpose of adjusting the excessive DC offset only when the output signal Sout is greater than the predetermined threshold voltage level ν , and the correction circuit 225 is only for the diode. When the body φ D' is turned on, the capacitor C is charged to achieve the purpose of adjusting the excessive DC offset; on the other hand, if only the corrected low DC offset is considered, the comparator COMP can be removed from the correction circuit 125. The transistor q or the diode D is removed from the correction circuit 225. At this time, the correction circuit 125 controls the transistor Q' to conduct to discharge the capacitor C only at the output signal S0UJ at a predetermined threshold voltage level -Vth. The purpose of adjusting the low DC offset is achieved, and the correction circuit 225 only adjusts the low DC offset by discharging the capacitor C when the diode D is turned on. For the differential input signal pair, if it has the characteristics of maximum amplitude (peak amplitude) or fixed wave envelope (c〇nstantenvel〇p) (for example, the orthogonal frequency division in the wireless local area network (WLAN) The preamble of the (0FDM) signal, as long as the DC offset correction mechanism is designed, and the control makes the DC input of the differential input signal to be consistent at both ends, the simultaneous correction difference can be achieved. The purpose of the DC offset between the positive and negative ends of the signal. For the differential signal pair having the maximum amplitude symmetry or the fixed wave seal characteristic, the maximum amplitude of the positive terminal signal (ie, the peak value to its DC level) is the maximum amplitude of the negative terminal signal 13 thereof. Symmetrical (that is, the same size and opposite direction), therefore, as long as the DC offset correction can be performed, the corrected DC signal of the positive terminal signal and the negative terminal signal can be adjusted to a value of -, and - The money offset correction satisfies the input range of the latter stage circuit, and the other money offset correction is also satisfied. "Monthly Referring to Fig. 8®, Fig. 8 is a schematic diagram of a DC offset correction device of the seventh embodiment of the present invention. As shown in Fig. 8, the DC offset correction device _ is respectively • corrects the input signal S], S2 (here, assumes that the input signal Si, & has the characteristics of maximum amplitude symmetry or 疋 fixed wave seal) and DC offset correction In the device_the differential amplifying circuit 805, the DC offset caused by the process mismatch is generated to generate the output signals ^, V. The DC offset correction device _ further includes an adjustment unit 81〇, milk (implemented by the subtractors 835 and 840, respectively) and offset correction circuits 825, 83〇, wherein the adjustment unit 810 corrects the voltage level of the signal sel according to the offset To adjust the voltage level of the input signal Si, the output of the switch is amplified and the output signal Si is generated, and the adjustment unit 815 adjusts the input signal S2 according to the voltage level of the offset correction signal S (2). The voltage level 'and its adjusted output signal is also amplified to generate an output signal S2'. ° In addition, the offset correction circuit 825 includes a capacitor (^ and a correction circuit 845 having a transistor (^ and a comparator COIVC^, The method is used for determining the voltage level of the offset correction signal Scl according to the voltage level of the output signal Si′ and the predetermined threshold value νώ. If the output signal S′′′ satisfies a first predetermined condition corresponding to the predetermined threshold value, Then, the offset correction circuit 825 controls the transistor Q1 to be charged by the comparator COMP1 to charge the capacitor & 1342109 to adjust the offset correction signal sel. At this time, the DC offset correction device 800 P is caused by the crystal The conduction of Qi forms a closed loop DC offset correction mechanism; if the output signal sr does not satisfy the first predetermined condition, the offset correction circuit 825 controls the transistor q to be turned off by using the comparator c〇MPi. The offset correction circuit 825 will maintain the offset correction signal Sel. At this time, the DC offset correction device 8 will form an open loop DC offset correction mechanism due to the closing of the electrical body Q1. The offset correction circuit 830 includes a capacitor c2 and a correction circuit having a transistor 与• and a comparison 11 C0MP2, which are used to determine the offset correction signal Sc according to the voltage level of the output signal &, and a predetermined threshold value Vth. The voltage level, wherein if the output s2 is output, and the predetermined condition of the corresponding threshold value Vthn is satisfied, the offset weight positive circuit 83〇 controls the transistor conduction by the comparator c〇Mp2 to charge the battery C:2 To adjust the offset correction signal h, if the output signal S2 does not satisfy the second predetermined condition, the offset correction circuit 83 will maintain the offset correction signal Sc2. As described above, the predetermined threshold Vth is a predetermined threshold. Electricity a fresh bit, the (4) level of the first pre-conditioner output 峨\' exceeds a predetermined threshold voltage level th, and the first pre-condition is an output signal s 2, and the voltage level exceeds a predetermined level 2 Vth. Therefore, if the first condition is satisfied, the comparator C0MP1 i is controlled by the logic level control signal to elect the crystal Q1 'power % will: the electric day body Q1 to charge the capacitor C1, the offset correction signal & The voltage of the voltage will increase with the charging of the capacitor C1, and by the action of the subtractor 835, the voltage level of the wheeled number s will be adjusted to produce the output signal I, therefore, the output signal 15 The highest value of the sr's electric fresh bit will be limited by the default value. Similarly, if the second predetermined condition is satisfied, the operation of the offset correction circuit 83() is also the same. "Operation of the offset correction circuit 825" The scent COMP2 outputs a control signal finalizing crystal having a low logic level (3⁄4, Wei% will charge capacitor C2 via transistor (3), and shift the correction signal s. The voltage level of 2 will also increase with the charging of capacitor q' and pass through the effect of subtractor_, input signal & The voltage level will be adjusted to produce the output signal S2'. Therefore, the highest value of the voltage level of the output signal S2 is also subject to the critical level Vth. As described above, the offset correction circuits 2 and 830 respectively output the signal. The highest voltage level of ESl', S2, is limited to the same predetermined threshold voltage level vth ', and since the input 峨Si, S2 has the maximum vibration riding scale or the fixed wave seal hiding, as long as the continuation (4) mechanism is The DC offset of the two input signals Si and S2 tends to be the same value, so that the positive and negative signals &,~ are simultaneously converted into a DC offset correction JL; therefore, the latter circuit (such as an analog digital converter) is not displayed. In the case of Figure 8, if it is scheduled The value of the boundary voltage level is designed to be smaller than the range of (4) of the input, and the residual offset of the input terminal does not cause the signal to saturate. The DC offset correction device in the embodiment _ The differential amplifying circuit 121 including the common mode feedback path as shown in FIG. 7 can be operated and operated to ensure that the positive and negative signals are properly corrected. Therefore, for the latter circuit (not shown in Fig. 8) In the case of 峨 amplification, saturation will not occur due to DC offset. In addition, the minimum amplitude of the two differential output signals (ie, the peak in the other direction) is limited to the same pre-threshold threshold voltage level. It can also be corrected to the same straight W offset level, please refer to (4) 9 figure, and FIG. 9 is a schematic diagram of the DC offset k positive set 900 according to the eighth embodiment of the present invention. The DC offset correcting device 8〇 The main difference between 〇 and 9〇〇 is that the DC offset correction device 900 is based on the predetermined threshold voltage level Vth and utilizes the comparator COM&, COMPj, and the C:, C, respectively in the offset correction circuits 925, 930: 2 put the ground through the transistors Q〆, Q2' Instead of using the power supply Vcc for charging, the differential output signals S!, S2' are corrected to the same DC offset level. If the first predetermined condition is met, that is, the output signal \, the voltage level is lower than the reference. When the threshold voltage level Vth is predetermined, the comparator COMPi will output a control signal with a high logic level to conduct the crystal. The electric gCi will discharge the ground voltage of the offset correction signal sel via the transistor. It will decrease with the discharge of the capacitor Ci. • Therefore, the voltage level of the input signal S1 will be boosted to produce the output signal Si, so the electric dust level of the output signal S! can only reach the predetermined threshold voltage level Vth. Similarly, if the second predetermined condition is met, that is, the voltage level of the output signal S2' is lower than the predetermined threshold voltage level W, the capacitance <:2 will be discharged to the ground via the transistor Q2, and the offset correction signal S. The voltage level of 2 will decrease with the discharge of capacitor C2, and the voltage level of input signal s2 will be boosted to produce output signal 1, so the output voltage §2, the voltage level can only reach the predetermined threshold voltage. Bit Vth'. As described above, the lowest voltage level of the output signals S!', S2' will be limited to the same voltage level. Similarly, the DC offset correction device 900 in this embodiment also cooperates with the differential amplifier circuit 121 including the common mode feedback path as shown in FIG. 7 to ensure that the positive and negative signals are properly obtained. Correction. Therefore, for the latter stage circuit (not shown in Figure 9), saturation will not occur due to DC offset when the signal is amplified. 17 is a schematic diagram of a DC offset correction device 1000 according to a ninth embodiment of the present invention, wherein the DC offset correction device 1000 utilizes voltage levels of the output signals Sr and S2', respectively. The offset correction signals 3 <;1 and sc2 and the diode units included in the correction circuits 1045 and 1050 (for simplicity of explanation, only the diodes D! and Dz are respectively indicated in the first diagram) The threshold value vD is predetermined to determine the voltage level ' of the offset correction signals Scl, Sc' and the predetermined threshold value vD is a predetermined threshold voltage difference in this embodiment. When the output signal \' satisfies a first predetermined condition corresponding to the predetermined threshold voltage difference ν〇鲁 (in the present embodiment, the first predetermined condition is the output signal S1, and the voltage difference from the offset correction signal Scl reaches a predetermined threshold voltage Difference Vd), the offset correction circuit 1025 will adjust the offset correction signal \丨, otherwise the offset correction circuit ι 25 will maintain the offset correction signal Scl; likewise, when the output signal & 's meets the corresponding predetermined threshold voltage difference In a second predetermined condition of the VD (in the present embodiment, the second predetermined condition is that the voltage difference between the output signal S2' and the offset correction signal Sc2 reaches a predetermined threshold voltage difference vD), and the offset correction circuit 1030 adjusts the bias. The correction signal 3. 2 is shifted, otherwise the offset correction φ positive circuit 1030 maintains the offset correction signal SC1. The predetermined threshold voltage difference VD is the minimum offset required to make the triode DrE>2 forward-passed, that is, the turn-on voltage (the coffee-011 she is) (here, the bias voltage is the same), and the 'output signal S1' When the voltage level is higher than the voltage level of the offset correction scale ^ and reaches the predetermined threshold difference VD, the diode D1 will lie down to output the signal S! The capacitor C! will be charged via the diode D1 to enhance The voltage level of the offset correction signal L is similarly. When the voltage level of the output signal core is higher than the voltage level of the offset correction signal number Sc2 and reaches a predetermined threshold voltage difference VD, the output signal s2 will be 1342109 The capacitor C2 is charged by the turned-on diode A to improve the electric offset position of the offset correction signal~; 啰, the DC offset correction device of the actual wipe is also matched with the figure shown in FIG. The differential amplifying circuit 121 including the common mode feedback path is operated together to ensure that both the positive and negative signals are properly corrected, so that the subsequent circuit does not operate erroneously. Referring to FIG. 11, FIG. 11 is a schematic diagram of a DC offset correction apparatus 1100 according to a tenth embodiment of the present invention. In this embodiment, the connection relationship of the diodes Di and D2 shown in FIG. 10 is replaced by the diodes Di and D2 as shown in FIG. u, that is, the one body D], The P-type areas of 〇2 are respectively connected to the offset correction signal heart 丨. and S. 2, and its N-type area is respectively connected to the output signal Si, and &,, therefore, - when the voltage level of the output signal sr is lower than the voltage level of the offset correction signal Sci, the pre-equivalent & When the voltage difference VD is reached, the capacitor Q is discharged through the turned-on diode to lower the voltage level of the offset correction signal Scl, and when the output signal &, the voltage level is lower than the offset correction signal S. 2 voltage level to reach a predetermined threshold voltage difference
Vd時’電容(：2經由導通的二極體D2進行放電來降低偏移校正訊 號&2的電麗準位。同樣地，本實施例中之直流偏移校正裝置11〇〇 亦會配合如第7圖所示之包含有共模回授路徑之差動放大電路 121 —併操作，以確保其正負端訊號均得到適當之校正，故同樣可 將輸出訊號S1，、&，限制於相同的直流偏移準位而使得後級電路不 會發生錯誤操作。 再者，若不考慮差動放大電路805所提供之電壓增益所帶來的 1342109 好處’亦可直接將調整單元810、815的輸出饋入比較器COMP、 COMP’或是二極體d、D’，並設定適當的預定臨界電壓準位Vth、 νΛ’或是預定臨界電壓差vd或Vd’來達到校正輸入訊號S!、S2之直 流偏移的目的，此亦屬於本發明的範疇。顯然，上述藉由直接將 調整單元810、815的輸出饋入比較器COMP、COMP’或是二極體 D、D’來達到校正輸入訊號&、s2之直流偏移的機制，亦可配合 如第7圖所示之包含有共模回授路徑之差動放大電路12丨一併操 作’以確保其正負端訊號均得到適當之校正，惟此處差動放大電 路121係位於直流偏移校正機制之後級。 總結來說’上述直流偏移校正裝置僅於輸出訊號的電壓準位 (可以是單端放大器處理前或處理後之訊號的電壓準位，或是差 動放大電路處理前或處理後之訊號的電壓準位）滿足上述預定條 件時才經由閉迴路(close loop)控制來進行直流偏移校正，然而，即 使於未滿足預定條件時，由於電容C〗、C2具有暫存電荷的特性而 仍可維持閉迴路控制時之偏移校正訊號的電壓準位，因此，雖然 無法經由閉迴路控制來進行直流偏移校正，卻仍可經由開迴路 (open loop)控制的方式來校正直流偏移；故本發明所揭露的直流偏 移校正裝置同時具有開迴路控制時校正速度較快(亦即收斂時間較 短)以及閉迴路控制時不易造成訊號失真的優點，同時本發明亦可 應用於校正類比數位轉換器(anal〇g_t〇-digital converter)之輸入訊 號的直流偏移，此時預定臨界值可設計為小於該類比數位轉換器 的輸入動態範圍(input dynamic range)以確保該輸入訊號會落入其 20 1342109 輸入動態範圍内。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範 圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖為本發明第一實施例之直流偏移校正裝置的示意圖。 第2圖為本發明第二實施例之直流偏移校正裝置的示意圖。 •第3 ®為本發明第三實施例之直流偏移校正裝置的示意圖。 第4圖為本發明第四實施例之直流偏移校正裝置的示意圖。 第5圖為本發明第五實施例之直流偏移校正裝置的示意圖。 第6圖為本發明第六實施例之直流偏移校正裝置的示意圖。 第7 ®為第5圖與第6贿示之差減大電路的示意圖。 第8圖為本發明第七實施例之直流偏移校正裝置的示意圖。 第9圖為本發明第八實施例之直流偏移校正裝置的示意圖。 •第10圖為本發明第九實施例之直流偏移校正裝置的示意圖。 第11圖為本發明第十實施例直流偏移校正裝置的示意圖。 【主要元件符號說明】 100、300、 直流偏移校正 105、106、 400、500、 裝置 600、800、 900、1000、 206 了調整電路 21 1342109When Vd is 'capacitance (: 2 is discharged through the turned-on diode D2 to reduce the electric resonance level of the offset correction signal & 2. Similarly, the DC offset correction device 11 in this embodiment also cooperates The differential amplifying circuit 121 including the common mode feedback path shown in FIG. 7 is operated to ensure that both the positive and negative signals are properly corrected, so that the output signals S1, , & The same DC offset level makes the subsequent circuit not operate erroneously. Moreover, if the benefit of the 1342109 caused by the voltage gain provided by the differential amplifier circuit 805 is not considered, the adjustment unit 810, 815 can be directly used. The output is fed to the comparator COMP, COMP' or the diodes d, D', and the appropriate predetermined threshold voltage level Vth, ν Λ ' or a predetermined threshold voltage difference vd or Vd ' is set to achieve the corrected input signal S! The purpose of the DC offset of S2 is also within the scope of the present invention. Obviously, the above is achieved by directly feeding the output of the adjusting unit 810, 815 into the comparator COMP, COMP' or the diode D, D'. Correct the input signal &, s2 DC The offset mechanism can also be combined with the differential amplifier circuit 12 including the common mode feedback path as shown in FIG. 7 to ensure that the positive and negative signals are properly corrected, but the difference is here. The amplifying circuit 121 is located after the DC offset correction mechanism. In summary, the DC offset correcting device is only at the voltage level of the output signal (which may be the voltage level of the signal before or after processing by the single-ended amplifier, or The voltage offset of the signal before or after the differential amplifier circuit is processed. The DC offset correction is performed via the closed loop control when the predetermined condition is satisfied. However, even when the predetermined condition is not satisfied, the capacitor is used. C and C2 have the characteristics of temporary charge and can maintain the voltage level of the offset correction signal during closed loop control. Therefore, although DC offset correction cannot be performed via closed loop control, it can still be via the open loop ( Open loop) control method to correct the DC offset; therefore, the DC offset correction device disclosed in the present invention has a fast correction speed (ie, convergence time) Shorter) and the advantage of signal distortion is not easy to be caused by closed loop control. At the same time, the present invention can also be applied to correct the DC offset of an input signal of an analog digital converter (anal〇g_t〇-digital converter). Designed to be smaller than the input dynamic range of the analog to digital converter to ensure that the input signal will fall within its 20 1342109 input dynamic range. The above is only a preferred embodiment of the present invention, The average variation and modification of the scope of the patent application are all covered by the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic diagram of a DC offset correction apparatus according to a first embodiment of the present invention. Fig. 2 is a schematic view showing a DC offset correcting apparatus according to a second embodiment of the present invention. • The third ® is a schematic diagram of the DC offset correction device of the third embodiment of the present invention. Fig. 4 is a schematic view showing a DC offset correcting apparatus according to a fourth embodiment of the present invention. Fig. 5 is a schematic diagram of a DC offset correcting apparatus according to a fifth embodiment of the present invention. Figure 6 is a schematic diagram of a DC offset correction apparatus according to a sixth embodiment of the present invention. The 7th ® is a schematic diagram of the difference between the 5th and 6th bribes. Figure 8 is a schematic diagram of a DC offset correction apparatus according to a seventh embodiment of the present invention. Figure 9 is a schematic diagram of a DC offset correction apparatus according to an eighth embodiment of the present invention. Fig. 10 is a schematic diagram of a DC offset correcting apparatus according to a ninth embodiment of the present invention. Figure 11 is a schematic diagram of a DC offset correction apparatus according to a tenth embodiment of the present invention. [Main component symbol description] 100, 300, DC offset correction 105, 106, 400, 500, device 600, 800, 900, 1000, 206 adjustment circuit 21 1342109
1100 110 、 210 、 825 、 830 、 925 、 930 、 1025 、 1030 、 1125 、 1130 偏移校正電路 115、810、815 調整單元 120 放大單元 121 、 805 差動放大電路 125 、 225 、 845 、 850 、 945 、 950 、 1045、1050、 1145 、 1150 校正電路 230 、 235 二極體單元 705 比較器 835 ' 840 減法器1100 110 , 210 , 825 , 830 , 925 , 930 , 1025 , 1030 , 1125 , 1130 offset correction circuit 115 , 810 , 815 adjustment unit 120 amplification unit 121 , 805 differential amplification circuit 125 , 225 , 845 , 850 , 945 , 950 , 1045 , 1050 , 1145 , 1150 correction circuit 230 , 235 diode unit 705 comparator 835 ' 840 subtractor
22twenty two