TWI339951B - Chip sets and clock generation methods thereof - Google Patents
Chip sets and clock generation methods thereofInfo
- Publication number
- TWI339951B TWI339951B TW096142998A TW96142998A TWI339951B TW I339951 B TWI339951 B TW I339951B TW 096142998 A TW096142998 A TW 096142998A TW 96142998 A TW96142998 A TW 96142998A TW I339951 B TWI339951 B TW I339951B
- Authority
- TW
- Taiwan
- Prior art keywords
- clock generation
- generation methods
- chip sets
- chip
- sets
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW096142998A TWI339951B (en) | 2007-11-14 | 2007-11-14 | Chip sets and clock generation methods thereof |
US12/102,119 US7671645B2 (en) | 2007-11-14 | 2008-04-14 | Chipsets and clock generation methods thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW096142998A TWI339951B (en) | 2007-11-14 | 2007-11-14 | Chip sets and clock generation methods thereof |
Publications (2)
Publication Number | Publication Date |
---|---|
TW200922148A TW200922148A (en) | 2009-05-16 |
TWI339951B true TWI339951B (en) | 2011-04-01 |
Family
ID=40623122
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW096142998A TWI339951B (en) | 2007-11-14 | 2007-11-14 | Chip sets and clock generation methods thereof |
Country Status (2)
Country | Link |
---|---|
US (1) | US7671645B2 (zh) |
TW (1) | TWI339951B (zh) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10716084B2 (en) * | 2016-05-18 | 2020-07-14 | Qualcomm Incorporated | Narrowband positioning signal design and procedures |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5646564A (en) * | 1994-09-02 | 1997-07-08 | Xilinx, Inc. | Phase-locked delay loop for clock correction |
US6249189B1 (en) * | 1998-08-05 | 2001-06-19 | National Science Council Of Republic Of China | Frequency synthesizer accomplished by using multiphase reference signal source |
GB0127537D0 (en) * | 2001-11-16 | 2002-01-09 | Hitachi Ltd | A communication semiconductor integrated circuit device and a wireless communication system |
US7119630B1 (en) * | 2003-09-25 | 2006-10-10 | Cypress Semiconductor Corp. | Frequency synthesizer having a more versatile and efficient fractional-N control circuit and method using vector values |
US7126436B1 (en) * | 2003-09-25 | 2006-10-24 | Cypress Semiconductor Corp. | Frequency synthesizer having a more versatile and efficient fractional-N control circuit and method |
US6924678B2 (en) * | 2003-10-21 | 2005-08-02 | Altera Corporation | Programmable phase-locked loop circuitry for programmable logic device |
TW200701651A (en) * | 2005-06-21 | 2007-01-01 | Via Tech Inc | Reference circuit and signal adjusting circuit |
TWI277858B (en) * | 2005-09-29 | 2007-04-01 | Via Tech Inc | Circuit of dynamically adjusting the basic clock signal for the front-side bus and its method |
US7592846B2 (en) * | 2007-02-16 | 2009-09-22 | Intersil Americas Inc. | Method for using digital PLL in a voltage regulator |
US7532029B1 (en) * | 2007-04-18 | 2009-05-12 | Altera Corporation | Techniques for reconfiguring programmable circuit blocks |
US7602224B2 (en) * | 2007-05-16 | 2009-10-13 | Hynix Semiconductor, Inc. | Semiconductor device having delay locked loop and method for driving the same |
-
2007
- 2007-11-14 TW TW096142998A patent/TWI339951B/zh active
-
2008
- 2008-04-14 US US12/102,119 patent/US7671645B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
TW200922148A (en) | 2009-05-16 |
US7671645B2 (en) | 2010-03-02 |
US20090121758A1 (en) | 2009-05-14 |
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