TWI339367B - Liquid crystal panel and liquid crystal display device having the same - Google Patents

Liquid crystal panel and liquid crystal display device having the same Download PDF

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TWI339367B
TWI339367B TW095112125A TW95112125A TWI339367B TW I339367 B TWI339367 B TW I339367B TW 095112125 A TW095112125 A TW 095112125A TW 95112125 A TW95112125 A TW 95112125A TW I339367 B TWI339367 B TW I339367B
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liquid crystal
pixel
line
crystal cell
voltage
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TW095112125A
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TW200639778A (en
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Jae Kyeong Yun
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Lg Display Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3696—Generation of voltages supplied to electrode drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Theoretical Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal (AREA)

Description

1339367 九、發明說明： 【發明所屬之技術領域】 本發明係有關於一種用於顯示影像之影像平面面板，尤其係有關於一 種液晶面板。而且，本發明有關具有液晶面板之液晶顯示裝置（LCD)，及 其驅動方法。 【先前技術】 習知技術的平面面板例如：液晶面板、電漿顯示面板、發光顯示面板 等’由於重量輕且輪廓薄而為有利。這些平面面板正在取代陰極射線管 (CRT)。在液晶面板中’電場隨著施加至各像素之視頻信號像素資料而變 化。由於所施加之電場，可以調整液晶單元之光線透射，以及然後顯示影 像。 包括在每個液晶面板中的液晶單元共同連接至共同共同電壓線。因 此，各液晶單元以相對於共同電壓而變化之像素電壓信號而充電。換句話 說，此提供給液晶單元之像素電壓信號具有與此共同電壓所不同之差異電 1 壓。因此’習知技術液晶面板耗散大量驅動功率。 而且’習知技術的液晶面板是在一反轉系統中驅動，藉以改善液晶相 對於像素電壓信號之響應特性。該反轉驅動系統包括：一畫面反轉系統， 一線（或行）反轉系統，和一點反轉系統。該畫面反轉系統根據畫面的變 化而蔣像素電壓信號之極性反轉。該線（或行）反轉系統根據線之改變，將 像素電壓信號之極性反轉。該點反轉系統根據像素之改變，將像素電壓信 號的極性反轉。根據此等反轉驅動系統，可以將正像素電壓信號和負像素 電壓信號同時施加於液晶面板。這裏’正像素電壓信號代表相對於共同電 1339367 壓在正極性(+)區域中變化的信號。以及負像素電壓信號代表相對於共同電 堡在負極性(-)區域中變化的信號。因此’加大了施加於液晶面板的像素電 壓信號的振幅寬度。因而，在由反轉驅動系統所驅動之液晶面板之情形中， 產生脈衝式雜訊，且驅動功率消耗增加。 參考第1圖更詳細的說明此問題。第1圖是習知技術LCD的概要圖。 在第1圖中’習知技術的LCD包括：一液晶面板2、連接至一閘極驅動器4 和一資料驅動器6。該液晶面板2在由複數個資料線DLl-DLm和複數個閘極 線GU-GLn相交所界定的區域中具有多數個像素pxl。其中，每個像素包括 一液晶單元CLC和一薄膜電晶體(TFT)。該液晶單元CLC連接到一値從共同 電壓產生器9延伸出的共同電壓線Vcom，及該薄膜電晶體將從相對應信號1339367 IX. Description of the Invention: [Technical Field] The present invention relates to an image plane panel for displaying images, and more particularly to a liquid crystal panel. Moreover, the present invention relates to a liquid crystal display device (LCD) having a liquid crystal panel, and a driving method therefor. [Prior Art] A planar panel of the prior art such as a liquid crystal panel, a plasma display panel, a light-emitting display panel or the like is advantageous in terms of light weight and thin profile. These flat panels are replacing cathode ray tubes (CRTs). In the liquid crystal panel, the electric field varies with the video signal pixel data applied to each pixel. Due to the applied electric field, the light transmission of the liquid crystal cell can be adjusted, and then the image is displayed. The liquid crystal cells included in each of the liquid crystal panels are commonly connected to a common common voltage line. Therefore, each liquid crystal cell is charged with a pixel voltage signal that changes with respect to a common voltage. In other words, the pixel voltage signal supplied to the liquid crystal cell has a differential voltage different from the common voltage. Therefore, the prior art liquid crystal panel dissipates a large amount of driving power. Moreover, the liquid crystal panel of the prior art is driven in an inversion system to improve the response characteristics of the liquid crystal with respect to the pixel voltage signal. The inversion drive system includes: a picture inversion system, a line (or line) inversion system, and a point inversion system. The picture inversion system inverts the polarity of the pixel voltage signal according to the change of the picture. The line (or line) inversion system inverts the polarity of the pixel voltage signal as a function of the line. The dot inversion system inverts the polarity of the pixel voltage signal in accordance with the change in the pixel. According to such an inversion driving system, a positive pixel voltage signal and a negative pixel voltage signal can be simultaneously applied to the liquid crystal panel. Here, the positive pixel voltage signal represents a signal that changes in the positive polarity (+) region with respect to the common electric 1339367. And the negative pixel voltage signal represents a signal that varies in the negative (-) region relative to the common electric castle. Therefore, the amplitude width of the pixel voltage signal applied to the liquid crystal panel is increased. Therefore, in the case of the liquid crystal panel driven by the inversion driving system, pulse type noise is generated, and the driving power consumption is increased. Refer to Figure 1 for a more detailed explanation of this problem. Fig. 1 is a schematic view of a conventional technology LCD. In Fig. 1, the prior art LCD includes a liquid crystal panel 2 connected to a gate driver 4 and a data driver 6. The liquid crystal panel 2 has a plurality of pixels px1 in a region defined by the intersection of a plurality of data lines DL1-DLm and a plurality of gate lines GU-GLn. Each of the pixels includes a liquid crystal cell CLC and a thin film transistor (TFT). The liquid crystal cell CLC is connected to a common voltage line Vcom extending from the common voltage generator 9, and the thin film transistor will receive the corresponding signal

線DL供應至液晶單元CLC之像素電壓信號切換，以響應相對應閘極線GL 之掃福信號。因為，像素的液晶單元CLC連接到共同電壓線Vc〇m，此施加 到液晶單元CLC的像素電虔信號具有不同於共同電壓Vc〇m的電壓。因而， 她加到每個液晶單元的像素電壓 '以及輸出到每—資料線既的像素電壓信 號輸出的振巾自寬度均增大。因此1知技躺液晶硫具有高驅動功率消 耗。 另外’液晶面板2中的像素PXL可由反轉系統進行驅動。例如，如第 2A 圖所不，每-像素能由_像素電壓信號驅動，其中關於各畫面之 極性反轉。並且’將此相對於像素電壓而反轉之極性供應至相鄰像素。其 中第2A SU兄明當奇數（或偶數）畫面的影像顯示時施加給液晶面板2 的每個像素的像素電壓彳§號的極性圖案以及第翻閱明當偶數（或奇數） 1339367 畫面的影像顯科，施加給液晶面板2的每個像素的像素電壓信號的極性 圖案。為了紐性反轉像素健信驗應至每—畫__稍像素，此 資料驅動H 6將來自時序控繼8之像素資料轉換成像素電壓信號， 以及在每-畫面内及水平同步期間，根據資料線將所轉換之像素 電壓信號的極性反轉。因此，若此供應至資料線况卜動的像素電壓信號， 在-個畫面或-水平同步期間具有正電壓，如第3圖所示，則其在下—畫 面或下一水平同步期間具有負電壓。 如上所述，若液晶面板由反轉系統驅動，則此像素電壓信號交替的具 有：相對於該共同電壓的正電壓和負電壓，及振幅寬度亦增大。因此，習 知技術的液晶面板與LCD和具有相同問題:驅動功率消號增加、及脈衝式雜 訊發生之問題。 【發明内容】 因此，本發明涉及一種液晶面板和具有液晶面板的LCD，其在實質上去 避免由於習知技術限制與缺點所產生之一或多個問題。， ® 本發明的目的之一為提供一種適用將驅動功率最小化之液晶面板。 本發明的另一目的為提供一種適用於抑制噪音發生的液晶面板。 本發明的進一步優點為提供一種LCD與驅動方法，其適用於將驅動功 率消耗最小化。 'r 本發明還有一優點為提供一種LCD與驅動方法，其適用於抑制噪音之 發生。 7 1339367 本發明其他之優點與_，其一部份在以下贿中說明，且其一部份 將由以下贿而日_，或可以藉由實施本發明而得知。本發明此等與其他 優點可以藉由在所撰寫之說明、帽專利範圍、以及所關式中所特別指 出之結構而實現與獲得。 為了達成此根據本發明目的之此等與其崎點，如同在此所廣泛說明 並實現的’本發明提供一種液晶面板包括：複數個閘極線：複數個資料線， 其與問極線交點界定像素區域；以及像素，其配置於像倾域巾，且響應 來自相對應閘極線、相對應資料線、以及靠近沿著資料線的切像素之信 號。 根據本發明的另一觀點，提供一種液晶面板，包括··複數個問極線； 複數個#料線’其在㈣極線交點界定像素區域；液晶單元，其配置於像 素區域中’且沿娜魏序連接；以及控制祕元件，其配置於像素區域 中且與問極線、資料線、以及液晶單元連接。 根據本發明的另—觀點，提供一種液晶顯示裝置’包括：閘極驅動器， ”順序的驅動ge_置在液晶面板上之閘極線；以及資料驅動器，其在當下一 個閘極線被驅動時、提供一個第二像素電麼信號給液晶面板的資料線，該 第-像素電壓jg號在當此相賴極線之先前_線以參考電I驅動時、根 據第，一像素電壓信號之第二像素電壓信號。 根據本發明還有另-觀點，提供一種液晶顯示裝置的驅動方法，包括： 依序驅動排列在液晶面板上卿極線，·提供―術目㈣之先前職線的第 -像素電壓信號提供給配置在液晶面板上的資料線；以及當下一個開極線 8 1339367 被驅動時提供一個第二像素電壓信號給資料線，該第二像素電壓根據第一 像素電壓作為參考電壓。 應當作如下的理解：前述之本發明的概括說明及以下詳細的描述均為 舉例及說明之用，其目的在於提供所主張發明的進一步解釋。 此等所附圖式是包括於此說明書中以提供本發明進一步瞭解，其包括 於本說明書中以構成本說明#之—部份，其與此描述—糾說明本發明之 實施例，而用於說明本發明之原理。 【實施方式】 參考附圖所示，現對本發_實施方式作詳細說明。無論為何，相同 的參考號碼是指相同或類似部份。第4圖為根據本發明實施例的lcd概要 圖，以及第5圖說籠據本發明之實施财當液晶面板由點反⑽統驅動 時，施加至液晶面板像素之像素電壓的極性圖案。 在第4圖中，此根據本發明的液晶顯示器，包括一個由閘極驅動器μ 和貧料貧料驅動n 16所驅_液晶面板⑶職晶面板12具有：在由複數 個閘極線GLl-GLn #複數個資料資料線DU_DLm《又所界定的區域之複數 個像素PXL11-PXLnm。此像素pxL) i _pxLnm分別具有薄膜電晶體 TFTl'MTTlni ’其用於切換像素電壓信號以作為對施加至閘極線gl卜⑶打掃 描信號的響應，其中的像素電壓信號由資料線DU_DLm提供給液晶單元 CLC11-CLCnm。像素pXUl_pxUm中的液晶單元acu acim由施加於第— 閘極線GL1的掃描信號驅動，並電性連接—參考電壓線^卜該參考電壓 1339367 線vLerf提供有參考電壓Verf。該參考電壓㈣由一參考電壓產生謂 產生，並雜-雜定的電壓位.麵序控· 18的㈣下該參考電 壓產生H 2G可提供參考電壓Verf給參考電觀vLe小其電壓位準在每— 畫面内變化。參考電壓產生器2ϋ可以選騎換成—個鋼電壓產生器其 類似於習知技術的LCD中的共同電壓產生器9。在這種情況下，由共同電壓 產生器提供的共同電壓VcGm施加給參考電壓線VLerf。糾，可以來自資 料驅動器16之參考電壓Vref供應之參考電壓線vu小這樣情況下，資料 驅動器16可產生參考電壓Verf，在時序控制器18的控制下其電壓位準 在每一畫面内變化。 像素PXL2卜PXUW的液晶單元⑽卜似咖對施加給閘極線似―❿ 的掃描信號㈣，此閘極線GL2-GLn連接在對應於先前閘極線GU至^ 的液晶單元αχιι-αχ (n-1) m和目雜wXL21_PXLnm的薄膜電晶體 TFTll-TFT(n-l)m的汲極端子之間。換句話說，像素pxL21_pxLnra中的液晶 單元ac21-acnm對施加給第2至第n賴極線GL2_GLn的掃難號響應， 其連接在對應於紐祕、線GU-GLn-Ι的在絲較pxL21_pXLnm的薄膜 電晶體TFTU至TFT(rH)_汲極端子和目前像素的目前薄膜電晶體而i 至TFTnm之間。因此，沿資料線DL配置的液晶單元ac串列地的連接到參 考電壓線VLerf，藉以形成一串聯電路。 v 像素PXLU-PXLlm中的液晶單元CLCll-CLClm對第-閘極線GL1的掃 指信號響應，並施加祕參考電觀VLerf的參考麵Verf和對應資料線 DU -DLm的像素電壓信號之間的不同電壓。根據資料線DU _DLm的像素電壓 1339367 信號，像素PXL21 -PXLnm的液晶單元QX21 -CLCnm對第二閘極線到第n閘 極線GL卜GLn的掃描信號響應，並施加具有對應於像素pxL1卜pXL(n_i)m 中的液晶單SCLC1卜CLC(n〜l)m像素電壓信號的一正極性⑴區域電壓位準 或-負極性㈠區域電齡準的像素電壓，其中像素電難號分卿動於在 先則閘極線GLl-GLn-1上的像素PXLli-pxL(n-l)m中的液晶單元 CLCU-CLCl(n-l)m。換句話說，像素PXL2卜PXLnm中的液晶單元 CLC21-CLClnm響應第二至第n閘極線GL1_GLn的掃描信號，所施加的像素 電壓信號高於或低於施加到在先前閘極線GU—GLnd上像素pXLn_p紅 (n-l)m中的液晶單元CLC21-CLClnm的像素電壓信號，其由分別對·應於資 料線DL1-DL上的像素信號的電壓位準驅動。 根據本發明，液晶面板12上的液晶單元CLC21_CLCnmm施加的像素電 壓具有：對應於施加在先前一閘極線的液晶單元CLC11_aci m的電 壓的正極性或負極性。因此，施加到液晶單元⑽卜⑽⑽的像素電壓的 震幅寬度和轉移到資料線DU-DLm的像素電壓信號的振幅寬度被縮小。因 此，液晶面板12的驅動功率消耗被最小化，以及脈衝式雜訊降低。 閘極驅動器14依序使得液晶面板12的閘極線GL卜GLn在每一水平同 步期間響應從時序控制器18發出的閘極時序控制信號。當閘極線GU一GLn 之-被驅麟，㈣驅⑽16提供像錢·號職料線犯他。為此 r' 目的’資料驅動H 16設置成響應從時序控制g 18發出的資料時序控制信 號。並且，資料聪動器16在每個水平同步期間從時序控制器18輸入像素 資料給-個線’以及提供具有像素電壓信號的第一到第m資料線犯勘 1339367 °個線，其具有對應像素> 料邏輯值的電壓位準。該時序控制器ΐ8接收 一視頻資料VD和例如電腦系統圖板的外部源（未示出）發出的同步信號 SYNC。該同步信號sync可包括一垂直同步信號'一水平同步信號和資料 .時脈等。該視頻資料VD包括用於一畫面（或一圖面）的紅、綠或藍色像素資 料。該時序控制器18在同步信號SYNC的基礎上產生閘極控制信號和資料 控制信號。而且，時序控制器18將視頻資料VD的紅、綠或藍色像素資料 一行行的施加到資料驅動器16上。 當液晶面板12由反轉系統驅動時，提供給第一到第m資料線DU DLm 的像素電壓韻可具有：在正極性⑴方向或貞極性㈠方向變動，且對應 於在母1面期間及/或水平同步期間先前一畫面或先前水平期間的像 素電壓信號。而且’像素電壓信號可根據資料線DL1_DLm之改變而極性反 轉。 例如，當液晶面板12由點反轉系統驅動日夺，輪出到資料線犯_勤的 像素電壓紐的電綠料極性與料㈣線上的像素電壓信號之極性相 反’以及在-畫面期間的第一水平期間中對應於參考電壓線νι㈣上的參 考電壓Verf具有正極性或負極性的電壓位準。而且，輸出到資料線阳. 的像素電壓職在每-水平同步_對應於轉—像素賴的電壓位準具 有負，性或正極性的電壓。因此，如第5圖中所示，液晶面板12之上像素 PXUl-PXLrm的液晶單元aa-CLCnm所施加的像素電壓信號的極性與鄰近 像素的液晶單元之極性相反。 參考第5圖，由於第k資料線M上的像素電麼信號膽，接到第』問 1339367 極線GLj和第k資料線DLk的像素pXLjk的液晶單元acjk所施加的像素 電坚（P正像素電壓）QXVjk要高於施加在連接到第（j—1)閘極線GLj_i 和第k資料線DLk的像素pxL (H) k的液晶單元ac (H)让上的像素 電壓CLCV (j~i) k，其由在第k資料線DLK上的像素電壓信號DVk的電壓 位準提供。同樣的，由於在第!^+1 f料線DLk+1上的像素電壓信號㈣【， 連接到第j+1閘極線GLj+1和第k+1資料線DLK+1的像素的液晶單元所施 加的像素電壓（即正像素電壓）aGV (j+1) (k+1)高於：施加在連接到第 j閘極線GLj和第k+l資料線DLk+Ι的像素的液晶單元上的像素電壓，由於 在第k+Ι資料線DLK+1上的像素電壓信號DVk+l的電壓位準提供。相反地， 根據在第k+Ι資料線DLkH上的像素電壓信號DVk+Ι，連接到第j閘極線 GLj和第k+Ι資料線DLK+1的像素的液晶單元CLCj (k+Ι)所施加的像素電 壓（即，負像素電壓）CLCVj (k+Ι)低於：施加在連接到第j-i閘極線乩』·^ 和第k+1資料線DLk+1的像素pxl( j-1)(k+1)的液晶單元CLC( j-l)( k+1) 上的像素電壓’由在第k+1資料線上的像素電壓DVk+l的電廢位準提供β 而且，由於在第k資料線DLk上的像素電壓信號DVk，連接到第j+i閘極線 GLj+Ι和第k資料線DLK的像素PXL( j+Ι)的液晶單元CLC (j+1) k所施加 的像素電壓（即負像素電壓）CLCV (j+1) k低於：施加在連接到第j問極 線GL|和第k資料線DLk的像素CLCVjk的液晶單元CLCjk上的像素電壓， 其由在第1ς資料線DLK上的像素電壓DVk的電壓位準提供。 為了經由第5圖的極性圖案驅動液晶面板丨2，資料驅動器16提供第k 和第k+1像素電壓信號DVk和DVk+1分別給第k和第k+1資料線DLk和 13 1339367 咖。參考第6圖所示’第k像素電壓信號職的電壓位準，參考當第』 水平同步期啊㈣H水平同步躺的««轉，崎應著-個像 素資料的邏輯值（例如灰階值）的電壓增大，即由-個電壓變化差不多與 對應於:個在正極性⑴方向的像素f料的邏輯值的電壓相等並進而所具 有的電祕準，參考當第j+1水平同步期間時的第】水平同步期間的像素 電壓位準通蝴M像偷的繼的瓣低，㈣—個電壓變The pixel voltage signal supplied from the line DL to the liquid crystal cell CLC is switched in response to the buff signal of the corresponding gate line GL. Since the liquid crystal cell CLC of the pixel is connected to the common voltage line Vc 〇 m, the pixel power signal applied to the liquid crystal cell CLC has a voltage different from the common voltage Vc 〇 m. Therefore, the pixel voltage 'to which is applied to each liquid crystal cell and the width of the vibrating towel outputted to the pixel voltage signal of each data line are increased. Therefore, the liquid crystal sulfur has a high driving power consumption. Further, the pixel PXL in the liquid crystal panel 2 can be driven by the inversion system. For example, as shown in Fig. 2A, each pixel can be driven by a _pixel voltage signal in which the polarity of each picture is inverted. And the polarity which is inverted with respect to the pixel voltage is supplied to the adjacent pixel. The image of the pixel voltage 彳§ of each pixel applied to the liquid crystal panel 2 when the image of the odd-numbered (or even) picture is displayed is displayed as the image of the even-numbered (or odd-numbered) 1339367 picture. A polarity pattern of a pixel voltage signal applied to each pixel of the liquid crystal panel 2. In order to reverse the pixel health test to each pixel, the data drive H 6 converts the pixel data from the timing control 8 into a pixel voltage signal, and during each-picture and horizontal synchronization. The polarity of the converted pixel voltage signal is inverted according to the data line. Therefore, if the pixel voltage signal supplied to the data line has a positive voltage during a picture or horizontal synchronization, as shown in FIG. 3, it has a negative voltage during the next-picture or next horizontal synchronization. . As described above, if the liquid crystal panel is driven by the inversion system, the pixel voltage signals alternately have a positive voltage and a negative voltage with respect to the common voltage, and the amplitude width also increases. Therefore, the liquid crystal panel of the prior art and the LCD have the same problems: an increase in driving power cancellation, and a problem in which pulsed noise occurs. SUMMARY OF THE INVENTION Accordingly, the present invention is directed to a liquid crystal panel and an LCD having a liquid crystal panel that substantially obviate one or more problems due to the limitations and disadvantages of the prior art. , ® One of the objects of the present invention is to provide a liquid crystal panel suitable for minimizing driving power. Another object of the present invention is to provide a liquid crystal panel suitable for suppressing noise generation. A further advantage of the present invention is to provide an LCD and driving method that is suitable for minimizing drive power consumption. Still another advantage of the present invention is to provide an LCD and driving method suitable for suppressing the occurrence of noise. 7 1339367 Other advantages and advantages of the present invention, some of which are described in the following bribes, and a part of which will be borne by the following, or may be known by the practice of the invention. These and other advantages of the present invention can be realized and obtained by the structure of the written description, the scope of the invention, and the structure particularly pointed out. In order to achieve this and its advantages in accordance with the purpose of the present invention, as embodied and implemented herein, the present invention provides a liquid crystal panel comprising: a plurality of gate lines: a plurality of data lines, which are defined by intersections with the interrogation lines a pixel region; and a pixel disposed in the image-like towel and responsive to signals from the corresponding gate line, the corresponding data line, and the tangential pixel along the data line. According to another aspect of the present invention, there is provided a liquid crystal panel comprising: a plurality of interrogation lines; a plurality of #feed lines' defining a pixel region at a (four) pole line intersection; a liquid crystal cell disposed in the pixel region 'and along And a control element, which is disposed in the pixel area and connected to the interrogation line, the data line, and the liquid crystal unit. According to another aspect of the present invention, there is provided a liquid crystal display device 'including: a gate driver," a sequential driving ge_ a gate line disposed on the liquid crystal panel; and a data driver that is driven when the next gate line is driven Providing a second pixel electric signal to the data line of the liquid crystal panel, wherein the first pixel voltage jg is when the previous _ line of the associated polar line is driven by the reference electric I, according to the first pixel voltage signal According to still another aspect of the present invention, there is provided a method for driving a liquid crystal display device, comprising: sequentially driving a clear line arranged on a liquid crystal panel, and providing a first line of the previous line of the head (4) The pixel voltage signal is supplied to the data line disposed on the liquid crystal panel; and when the next open line 8 1339367 is driven, a second pixel voltage signal is supplied to the data line, and the second pixel voltage is used as a reference voltage according to the first pixel voltage. It is to be understood that the following general description of the invention and the following detailed description The accompanying drawings are included to provide a further understanding of the invention, and are in The embodiments are described in detail with reference to the accompanying drawings. The same reference numerals refer to the same or similar parts. The lcd schematic diagram according to the embodiment of the present invention, and the fifth diagram illustrates the polarity pattern of the pixel voltage applied to the pixels of the liquid crystal panel when the liquid crystal panel is driven by the dot-reverse (10) system according to the implementation of the present invention. In FIG. 4, The liquid crystal display according to the present invention comprises a gate driver 12 driven by a gate driver μ and a lean material. The liquid crystal panel (3) has a plurality of data sheets in a plurality of gate lines GL1-GLn # Line DU_DLm "a plurality of pixels PXL11-PXLnm of the defined region. This pixel pxL) i _pxLnm respectively has a thin film transistor TFT1'MTTlni' for switching the pixel voltage signal as a pair The response to the scan signal to the gate line gl (3), wherein the pixel voltage signal is supplied from the data line DU_DLm to the liquid crystal cell CLC11-CLCnm. The liquid crystal cell acu acim in the pixel pXU1_pxUm is scanned by the scan signal applied to the first gate line GL1 Drive, and electrical connection - reference voltage line ^ The reference voltage 1339367 line vLerf is provided with a reference voltage Verf. The reference voltage (four) is generated by a reference voltage, and the hetero-acoustic voltage level. Surface sequence control · 18 (4) The reference voltage is generated by H 2G to provide a reference voltage Verf to the reference electrical view vLe small and its voltage level varies within each picture. The reference voltage generator 2ϋ can be switched to a steel voltage generator similar to A common voltage generator 9 in a conventional LCD. In this case, the common voltage VcGm supplied from the common voltage generator is applied to the reference voltage line VLerf. In the case where the reference voltage line vu supplied from the reference voltage Vref of the data driver 16 is small, the data driver 16 can generate the reference voltage Verf, and its voltage level changes within each picture under the control of the timing controller 18. The liquid crystal cell (10) of the pixel PXL2b PXUW is similar to the scan signal (4) applied to the gate line, and the gate line GL2-GLn is connected to the liquid crystal cell αχιι-αχ corresponding to the previous gate line GU to ^ ( N-1) m and between the 汲 terminal of the thin film transistor TFT11-TFT(nl)m of wXL21_PXLnm. In other words, the liquid crystal cell ac21-acnm in the pixel pxL21_pxLnra responds to the Sweeping Number applied to the 2nd to nth-thila-polar line GL2_GLn, which is connected to the in-line corresponding to the secret, line GU-GLn-Ι, pjL21_pXLnm The thin film transistor TFTU to TFT (rH)_汲 terminal and current pixel of the current thin film transistor and i to TFTnm. Therefore, the liquid crystal cells ac arranged along the data line DL are connected in series to the reference voltage line VLerf, thereby forming a series circuit. v The liquid crystal cell CLC11-CLClm in the pixel PXLU-PXLlm responds to the swept signal of the first gate line GL1, and applies between the reference surface Verf of the reference VLerf and the pixel voltage signal of the corresponding data line DU-DLm. Different voltages. According to the pixel voltage 1339367 signal of the data line DU_DLm, the liquid crystal cell QX21-CLCnm of the pixel PXL21-PXLnm responds to the scan signal of the second gate line to the nth gate line GLbGLn, and is applied with the corresponding pixel pxL1bpXL (n_i)m liquid crystal single SCLC1 b CLC (n ~ l) m pixel voltage signal of a positive (1) regional voltage level or - negative polarity (a) regional electrical age quasi-pixel voltage, where the pixel electric hard number is divided The liquid crystal cell CLCU-CLCl(nl)m in the pixel PXLli-pxL(nl)m on the preceding gate line GL1-GLn-1. In other words, the liquid crystal cells CLC21-CLClnm in the pixel PXL2b PXLnm are responsive to the scan signals of the second to nth gate lines GL1_GLn, and the applied pixel voltage signal is higher or lower than the applied to the previous gate line GU_GLnd. The pixel voltage signals of the liquid crystal cells CLC21-CLClnm in the upper pixel pXLn_p red (nl)m are driven by the voltage levels of the pixel signals on the data lines DL1-DL, respectively. According to the present invention, the pixel voltage applied to the liquid crystal cell CLC21_CLCnmm on the liquid crystal panel 12 has a positive polarity or a negative polarity corresponding to the voltage applied to the liquid crystal cell CLC11_acim of the previous gate line. Therefore, the amplitude width of the pixel voltage applied to the liquid crystal cell (10) (10) (10) and the amplitude width of the pixel voltage signal transferred to the data line DU-DLm are reduced. Therefore, the driving power consumption of the liquid crystal panel 12 is minimized, and the pulse type noise is lowered. The gate driver 14 sequentially causes the gate line GLb GLn of the liquid crystal panel 12 to respond to the gate timing control signal issued from the timing controller 18 during each horizontal synchronization. When the gate line GU-GLn is driven by the Lin, the (4) drive (10) 16 provides him with a money line. For this purpose, the r' destination' data drive H 16 is set to respond to the data timing control signal sent from the timing control g 18 . And, the data encryptor 16 inputs the pixel data from the timing controller 18 to the - line ' during each horizontal synchronization and provides the first to mth data lines having the pixel voltage signal to map 1339367 ° lines, which have corresponding Pixel> The voltage level of the logic value. The timing controller 8 receives a video material VD and a synchronization signal SYNC from an external source (not shown) such as a computer system board. The sync signal sync may include a vertical sync signal 'a horizontal sync signal and data, a clock, and the like. The video material VD includes red, green or blue pixel data for a picture (or a picture). The timing controller 18 generates a gate control signal and a data control signal based on the synchronization signal SYNC. Moreover, the timing controller 18 applies the red, green or blue pixel data of the video material VD to the data driver 16 line by line. When the liquid crystal panel 12 is driven by the inversion system, the pixel voltages supplied to the first to mth data lines DU DLm may have a variation in the positive polarity (1) direction or the 贞 polarity (1) direction, and correspond to during the mother 1 plane and / or pixel voltage signal during the previous picture or previous horizontal period during horizontal synchronization. Moreover, the pixel voltage signal can be reversed in polarity according to the change of the data line DL1_DLm. For example, when the liquid crystal panel 12 is driven by the dot inversion system, the polarity of the pixel of the pixel voltage of the data line that is turned to the data line is opposite to the polarity of the pixel voltage signal of the material (four) line and during the period of the picture. The reference voltage Verf corresponding to the reference voltage line νι (4) in the first horizontal period has a voltage level of positive polarity or negative polarity. Moreover, the pixel voltage output to the data line yang. The voltage level corresponding to the turn-to-pixel sync has a negative, positive or positive voltage. Therefore, as shown in Fig. 5, the polarity of the pixel voltage signal applied to the liquid crystal cells aa-CLCnm of the pixels PXU1-PXLrm above the liquid crystal panel 12 is opposite to the polarity of the liquid crystal cells of the adjacent pixels. Referring to FIG. 5, since the pixel on the kth data line M is electrically signaled, the pixel is applied to the liquid crystal cell acjk of the pixel pXLjk of the 1339367 polar line GLj and the kth data line DLk (P positive) The pixel voltage) QXVjk is higher than the pixel voltage CLCV (j~) of the liquid crystal cell ac (H) applied to the pixel pxL (H) k connected to the (j-1)th gate line GLj_i and the kth data line DLk. i) k, which is provided by the voltage level of the pixel voltage signal DVk on the kth data line DLK. Similarly, due to the pixel voltage signal (4) on the ^^+1 f-feed line DLk+1, the liquid crystal connected to the pixels of the j+1th gate line GLj+1 and the k+1th data line DLK+1 The pixel voltage (ie, positive pixel voltage) aGV (j+1) (k+1) applied by the cell is higher than: liquid crystal applied to pixels connected to the jth gate line GLj and the k+1th data line DLk+Ι The pixel voltage on the cell is provided due to the voltage level of the pixel voltage signal DVk+1 on the k+th data line DLK+1. Conversely, according to the pixel voltage signal DVk+Ι on the k+th data line DLkH, the liquid crystal cell CLCj (k+Ι) connected to the pixel of the jth gate line GLj and the k+th data line DLK+1 The applied pixel voltage (ie, negative pixel voltage) CLCVj (k+Ι) is lower than: pixel pxl (j- applied to the jith gate line ···^ and the k+1th data line DLk+1) 1) The pixel voltage ' on the liquid crystal cell CLC(jl)(k+1) of (k+1) is supplied by the electric waste level of the pixel voltage DVk+1 on the k+1th data line, and The pixel voltage signal DVk on the k data line DLk is applied to the liquid crystal cell CLC(j+1) k connected to the j+i gate line GLj+Ι and the pixel PXL(j+Ι) of the kth data line DLK The pixel voltage (ie, the negative pixel voltage) CLCV (j+1) k is lower than: the pixel voltage applied to the liquid crystal cell CLCjk of the pixel CLCVjk connected to the j-th problem line GL| and the k-th data line DLk, which is The voltage level of the pixel voltage DVk on the first data line DLK is supplied. In order to drive the liquid crystal panel 丨2 via the polarity pattern of FIG. 5, the data driver 16 supplies the kth and k+1th pixel voltage signals DVk and DVk+1 to the kth and k+1th data lines DLk and 13 1339367, respectively. Refer to Figure 6 for the voltage level of the 'kth pixel voltage signal, refer to the first horizontal synchronization period. (4) H level synchronously lying ««转,崎应一-pixel data logical value (such as grayscale value The voltage increases, that is, the voltage change is almost equal to the voltage corresponding to the logical value of the pixel f material in the positive polarity (1) direction and thus has the electrical secret, and the reference is synchronized at the j+1th level. During the period of the period], the pixel voltage level during the horizontal synchronization is the same as that of the stolen butterfly. (4) A voltage change

不^。對應於個在負極性㈠方向的像素資料的邏輯值的電壓相 等。類似的’第㈣像«號賺+1所具錢電驗準，參考當第】 水平同細時的第Η水平同爛的像素電壓位準，其變化的程度與 對狀-個在負極性㈠方向的像賴料的邏輯值的電麵近，並進而具有 的電齡準’參考當請水平同步躺時的第卜_步_的像素電 壓其支化的;k度與對應於一個在正極性⑴方向的像素資料的邏輯值的電 壓相近。 在第」閘極線GLj上的第k像素pXLjk的薄膜電晶體TFTjk的導通基 於對在第〕閉極線GLj上的高電壓的掃描信號_的響應，所以在第^資 料線耻上的像素電壓信號斷提供到相應的液晶單元CLCjk。目此，第j 問極線GLj的第k液晶單元似认上施加從第k資料線脱來的像素電屋 信號Dvk。從而’第j間極線GLj的第k液晶單元所施加的像素電麼 (即正極像素觸CLCjk高於：像素龍ac (H) k，其施加在對應的 先^閘極線GLH的液晶單元CLC (⑷让上，由在第k資料線上的像素 她言號DVk的電·準提供。類似的，在第」閉極線阳上的第⑹傈 14 1339367 素的薄膜電晶體TFTjk+l的導通，響應於對在第j閘極線GLj上的高位準 的掃描信號GLS] ’所以在$ k+1資料線DLk+1上的像素電壓信號提 供到相應的液晶單元CLCj (k+l)〇因此，在第j閘極線GLj·上的第叫液 晶單元CLCj (k+Ι)施加有從第k+i資料線DLkH的像素電壓信號。 所以’在第j閘極線GLj上的第k+Ι液晶單元CLCj (k+1)所施加的像素電 壓（即負像素電壓）CLCVj (k+Ι)要低於像素電壓〇£乂（卜丨）（k+1)，其 施加在對應的先前閘極線GLj-1的液晶單元CLC (j-l) (k+l)上，由在第 k+丨資料線上的像素電壓信號ovk+i的電壓位準提供。 同樣，在帛j+l _線α j+1上的第k像素pXL⑽）k的薄膜電晶體 TFWk的導通’基於對在第川閉極線GL川上的高位準的掃描信號 GLS』>1的響應，所以在第k資料線DLk上的像素電壓信號况妝提供到相應 的液晶單元CLC( j+1 )k。因此，第川閘極線GLj+1的第k液晶單元acj+lk 上施加從第k資料線DLk來的像素電壓信號DLVk。因此，第jH 線GLj+1 的第k液晶單兀CLCj+lk所施加的像素電摩（即負像素電壓）acj+lk低於 像素電壓CLCjk，其施加在對應的前閘極線GLj的液晶單元CLCjk上由在 第k資料線上的像素電壓域腿的電廢位準提供。類似的在第川閘 極線GLj+Ι上的第k+1像素pxL(⑽⑽）的薄膜電晶體tft (川）⑽） 的導，通，響應於對在第j+1閉極線GLj+1上的高位準的掃描信號gls川， 所以在第k+Ι資料線DLk+Ι上的像素電壓信號DVk+1提供到相應的液晶單 兀acj+i(k+i)。因此，在第川問極線GL川上的第㈣液晶單元川 (kH) %加有從第k+i資料線DLk+1的像素電壓信號。從而，在第 15 j+1閘極線GLj+1上的第k+1液晶單元cLCjH(k+l)所施加的像素電壓（即 負像素電壓）CLCVj+1 (k+Ι)要低於像素電壓CLCVj (k+1)，其施加在對應 的先刖閘極線GLj的液晶單元CLCj (k+l)上，由在第k+Ι資料線DLk+1上 的像素電壓信號DVk+Ι的電壓位準提供。 以此方式，包括在液晶面板12的像素中每個液晶單元施加的像素電壓 尚於或低於這樣的像素電壓，其施加在先前線的液晶單元中，通過在對應 的貧料線上的像素電壓信號的電壓位準。因此，液晶單元的像素電壓的振 幅寬度和提供到每個資鱗DL的像素電壓信號賴幅寬度得以縮減。從 而，液晶面板12和具有同樣液晶面板的lCD根據本發明能夠減少驅動功率 消耗及抑制脈衝型的雜訊的發生。 第7圖為根據本發明的實施例的如第4圖所示的液晶面板丨2的結構。 由於連接到三個資料線DLk-Ι到DLk+Ι的像素如所示，連接到出個資料線 DL1到DLm的nxm數量的像素pxlu- pxLnm根據本發明的實施例，可包括 在液晶面板12中，這對於熟悉本領域的技術人員明顯可知。從而，n%數 量的像素PXL11- PXLnm將在第7圖中得以說明。 參考第7圖，液晶面板12在由複數閘極線GL卜GLn和複數資料線DU_ DLm所界定的區域中包括複數個像素pXLn_pxLnm。像素腿卜 PXLnm 具 有薄y電晶體TFTU- TFTnm，其分別連接到閘極線GL1_ GLn和 資料線DL1- DLm。這些連接到第二至第n閘極線GL2_GLn的像素pxi^_pxL⑽進一步的 包括液明單元(XCll- CLClm ’其連接在薄膜電晶體TFT2卜TFTnm和這些分 別連接到先則閘極，線GL1_ GLn」的薄膜電晶體而卜滿七的沒極之 问。這些連接到第一閘極線GL1的像素PXU1-PxLnm進一步的分別包括連 接在參考電壓線Viref和連接到第一閘極線GU的薄膜電晶體吓了丨卜吓丁化 的汲極（即液晶單元CLC21- CLC2m)之間的液晶單元CLCU_ CLClm。 液晶單tcCLCII- CLCnm分別包括；電性連接到相應的薄膜電晶體的汲 極和下一線液晶單元的第一像素電極圖案FPEP1 hFpEPnm，以及電性連接到 參考電壓線verf或者㈣-線的薄膜電晶體的沒極和相應液晶單元的第二 像素電極圖案SPEP11 -SPEPnm。此第一與第二像素電極圖案FPEp與spEp形 成冠形。而且，此冠形第一與第二電極圖案吓卯與$即交替配置於像素 區令。 例如，由第j閘極線GLj和第k資料線DLk驅動的像素PXLjk的液晶 單^CLCjk連接在：第j-i閘極線GLj_i上的第k像素pxLk的液晶單元ac (j-l)k、和第jH閘極線GLj+1上的第k像素PXLk的液晶單元CLC( j+1) k之間。換s之，由第j閘極線GLj•和第k資料線DLk驅動的像素pXLjk的 液晶單兀CLCjk連接在：與第j—丨閘極線乩卜丨連接的第k薄膜電晶體TFT (j-l)k的汲極和與第j閘極線GLj連接的薄膜電晶體TFTjk的汲極之間。 同時，第一線上的液晶單元的第一像素電極圖案FpEpu_FpEpim電性 連接到第1閘極線GL1上的薄膜電晶體TFT11_ TFTlm的汲極，並電性連接 下一綿上的液晶單元CLC21-CLC2m的第二像素電極圖案SPEP2卜FPEP2m。相 v 反地，第一線上的液晶單元(1(：11_(1(：1111的第二像素電極圖案 SPEPll-SPEPlm連接到參考電壓線Vlerf。該冠形的第一和第二像素電極圖 案FPEP和SPEP交替的配置在像素區域中。 1 1339367 因此與第—到第n-l閘極線GLl-GLn-l連接的薄膜電晶體τρπι-TFT(n-l)m的汲極分別電性連接到形成在像素區域中，並由閘極線乩卜 GL(n-l)驅動的第一像素電極圖案FpEpu_FpEp(n i)旧和形成在像素區域 並由下一個閘極線GL2_ GLn驅動的第二像素電極圖案spEpi卜兕即（η—。 m。由第一閘極線GL1驅動的液晶單元acn_CLClm的第二像素電極圖案 SPEP1卜SPEP1 m電性連接到參考電壓線線卜由第〇問極線驅動的薄 膜電晶體TFTnl- TFTmn的祕·連翻：形成在減像魏域的第一像 素電極圖案fPEPn卜FPEPrnn。 在本發明的液晶6板12巾，液晶單元的兩種像素電極難電性連接 到：先前線和下-線的液晶單元的像素電極圖案，其沿資料線况鄰近配置， 以及液晶單元㈣至參考電壓線Vlerfe當串聯液晶單元施加參考先前線的 液晶皁το的像素電壓的正或負的像素電壓時，所施加的像素電壓的振幅寬 度降低。因此，液晶面板12 #驅動功率消耗$低，並且脈衝型雜訊得以抑 制。 如上所述，像素的液晶單元所施加的像素電壓（即正或負像素電壓） 高於或低於：參考所施加的像素電壓的相應的資料線的像素電壓信號。因 此’液晶單元上的齡電_触寬度、提供給資騎DL的像素電壓的振 幅寬^、提供給資料線的像素電磨信號的振幅宽度都得以縮小。因此液 晶面板和昇有該部件的LCD的驅動功率消耗能夠減少，並且脈衝型的雜訊 得以抑制。 對於熟習此技術人士而為明顯，可以在本發明中作各種修正與變化， !$ 1339367 而不會偏離本發明之精神與範圍。因此，其用意為本發明包括：在所附申 請專例範圍及其等同物範圍中之本發明之修正與變化。No ^. The voltages corresponding to the logical values of the pixel data in the negative polarity (1) direction are equal. A similar 'fourth (like) « earned +1 has the money to check the electricity, refer to the first level. The level of the same level is the same as the level of the pixel voltage, the degree of change and the opposite - one in the negative polarity (1) The direction of the electrical value of the logical value of the material is close, and then has the electrical age of the reference 'refer to the pixel voltage of the first step when the horizontal synchronization is lying; the k degree corresponds to one The voltage of the logical value of the pixel data in the positive polarity (1) direction is similar. The conduction of the thin film transistor TFTjk of the kth pixel pXLjk on the "th gate line GLj" is based on the response to the high voltage scan signal_ on the ">thright line GLj, so the pixel on the second line of shame The voltage signal is supplied to the corresponding liquid crystal cell CLCjk. Therefore, the kth liquid crystal cell of the jth question mark line GLj seems to recognize that the pixel house signal Dvk taken from the kth data line is applied. Thus, the pixel applied by the kth liquid crystal cell of the jth epipolar line GLj (ie, the positive pixel touch CLCjk is higher than: the pixel dragon ac (H) k, which is applied to the liquid crystal cell of the corresponding first gate line GLH CLC ((4) Let, by the pixel on the kth data line, the number of the DVk is provided by the battery. Similarly, the (6) 傈 14 1339367 element of the thin film transistor TFTjk+l on the "closed line" Turned on, the pixel voltage signal on the $k+1 data line DLk+1 is supplied to the corresponding liquid crystal cell CLCj (k+l) in response to the high level scan signal GLS]' on the jth gate line GLj Therefore, the first liquid crystal cell CLCj (k+Ι) on the jth gate line GLj· is applied with the pixel voltage signal from the k+i data line DLkH. Therefore, 'on the jth gate line GLj The pixel voltage (ie, negative pixel voltage) CLCVj (k+Ι) applied by the k+Ι liquid crystal cell CLCj (k+1) is lower than the pixel voltage 丨(乂)(k+1), which is applied to the corresponding The liquid crystal cell CLC (jl) (k+1) of the previous gate line GLj-1 is supplied by the voltage level of the pixel voltage signal ovk+i on the k+th data line. Similarly, at 帛j+l _ Line α The conduction of the thin film transistor TFWk of the kth pixel pXL(10))k on the j+1 is based on the response to the high-level scan signal GLS on the 川川关线线 GL川>1, so the kth data line DLk The upper pixel voltage signal condition is supplied to the corresponding liquid crystal cell CLC(j+1)k. Therefore, the pixel from the kth data line DLk is applied to the kth liquid crystal cell acj+lk of the second gate line GLj+1. The voltage signal DLVk. Therefore, the pixel electric motor (ie, the negative pixel voltage) acj+lk applied by the kth liquid crystal unit CLCj+lk of the jHth line GLj+1 is lower than the pixel voltage CLCjk, which is applied to the corresponding front gate. The liquid crystal cell CLCjk of the line GLj is provided by the electric waste level of the pixel voltage domain leg on the kth data line. A similar thin film of the k+1th pixel pxL ((10)(10)) on the second gate line GLj+Ι The conduction of the crystal tft (chuan) (10)), in response to the high level of the scanning signal glschuan on the j+1th closed line GLj+1, so the pixel on the k+th data line DLk+Ι The voltage signal DVk+1 is supplied to the corresponding liquid crystal cell 兀acj+i(k+i). Therefore, the (fourth) liquid crystal cell (kH) % on the 川川线线 GL川 is added with the pixel voltage signal from the k+i data line DLk+1. Therefore, the pixel voltage (ie, the negative pixel voltage) CLCVj+1 (k+Ι) applied to the k+1th liquid crystal cell cLCjH(k+1) on the 15th j+1th gate line GLj+1 is lower than The pixel voltage CLCVj (k+1) is applied to the liquid crystal cell CLCj (k+1) of the corresponding pre-gated gate line GLj, and the pixel voltage signal DVk+Ι on the k+th data line DLk+1 The voltage level is provided. In this way, the pixel voltage applied to each of the liquid crystal cells included in the pixels of the liquid crystal panel 12 is still below or lower than the pixel voltage applied to the liquid crystal cell of the previous line by the pixel voltage on the corresponding lean line. The voltage level of the signal. Therefore, the amplitude of the pixel voltage of the liquid crystal cell and the width of the pixel voltage signal supplied to each of the scales DL are reduced. Therefore, the liquid crystal panel 12 and the lCD having the same liquid crystal panel can reduce the driving power consumption and suppress the occurrence of pulse type noise according to the present invention. Fig. 7 is a view showing the structure of a liquid crystal panel unit 2 as shown in Fig. 4 according to an embodiment of the present invention. Since the pixels connected to the three data lines DLk-Ι to DLk+Ι are as shown, the nxm number of pixels pxlu-pxLnm connected to the one of the data lines DL1 to DLm may be included in the liquid crystal panel 12 according to an embodiment of the present invention. This will be apparent to those skilled in the art. Thus, n% of the number of pixels PXL11-PXLnm will be explained in Fig. 7. Referring to Fig. 7, the liquid crystal panel 12 includes a plurality of pixels pXLn_pxLnm in a region defined by the complex gate line GLb GLn and the complex data line DU_DLm. The pixel leg PXLnm has a thin y transistor TFTU-TFTnm which is connected to the gate line GL1_ GLn and the data lines DL1- DLm, respectively. The pixels pxi^_pxL(10) connected to the second to nth gate lines GL2_GLn further include a liquid crystal cell (XC11-CLClm' which is connected to the thin film transistor TFT2b TFTnm and these are respectively connected to the first gate, the line GL1_GLn The thin film transistor is not well-known. The pixels PXU1-PxLnm connected to the first gate line GL1 further include a film connected to the reference voltage line Viref and the first gate line GU, respectively. The transistor scares the liquid crystal cell CLCU_CLClm between the bungee (ie, liquid crystal cell CLC21-CLC2m). The liquid crystal single tcCLCII-CLCnm respectively includes; electrically connected to the corresponding thin film transistor of the drain and the lower a first pixel electrode pattern FPEP1 hFpEPnm of the one-line liquid crystal cell, and a second electrode pattern SPEP11 - SPEPnm of the thin film transistor electrically connected to the reference voltage line verf or the (four)-line and the second pixel electrode pattern SPEP11 - SPEPnm of the corresponding liquid crystal cell. The second pixel electrode patterns FPEp and spEp form a crown shape, and the crown first and second electrode patterns are scared and alternately arranged in the pixel region. For example, the jth gate line GLj and the kth data are The liquid crystal cell CLCLjk of the pixel DLkk driven by the DLk is connected to the liquid crystal cell ac (jl)k of the kth pixel pxLk on the jith gate line GLj_i, and the kth pixel PXLk of the jth gate line GLj+1 Between the liquid crystal cells CLC(j+1)k, the liquid crystal cell CLCjk of the pixel pXLjk driven by the jth gate line GLj• and the kth data line DLk is connected to: the jth gate line Between the drain of the kth thin film transistor TFT (jl) k connected to the drain and the drain of the thin film transistor TFTjk connected to the jth gate line GLj. Meanwhile, the first pixel of the liquid crystal cell on the first line The electrode pattern FpEpu_FpEpim is electrically connected to the drain of the thin film transistor TFT11_TFTlm on the first gate line GL1, and is electrically connected to the second pixel electrode pattern SPEP2 FPEP2m of the liquid crystal cell CLC21-CLC2m on the next wafer. Conversely, the liquid crystal cell on the first line (1(:11_(1111) second pixel electrode pattern SPEP11-SPEPlm is connected to the reference voltage line Vlerf. The first and second pixel electrode patterns FPEP and SPEP of the crown shape Alternately arranged in the pixel area. 1 1339367 Therefore, the thin film connected to the first to nl gate lines GLl-GLn-1 The drains of the crystal τρπι-TFT(nl)m are electrically connected to the first pixel electrode pattern FpEpu_FpEp(ni) formed in the pixel region and driven by the gate line GL(nl) and formed in the pixel region. And the second pixel electrode pattern spEpi, which is driven by the next gate line GL2_ GLn, is (η-. m. The second pixel electrode pattern SPEP1 SPEP1m of the liquid crystal cell acn_CLClm driven by the first gate line GL1 is electrically connected to the reference voltage line, and the thin film transistor TFTnl-TFTmn driven by the second line is connected. : forming a first pixel electrode pattern fPEPn FPEPrnn in the subtraction domain. In the liquid crystal 6 panel 12 of the present invention, the two pixel electrodes of the liquid crystal cell are electrically connected to the pixel electrode pattern of the liquid crystal cell of the front line and the lower line, which are disposed adjacent to the data line condition, and the liquid crystal cell (4) to The reference voltage line Vlerfe when the series liquid crystal cell applies a positive or negative pixel voltage of the pixel voltage of the liquid crystal soap τ ο of the previous line, the amplitude width of the applied pixel voltage is lowered. Therefore, the liquid crystal panel 12 # drive power consumption is low, and pulse type noise is suppressed. As described above, the pixel voltage (ie, the positive or negative pixel voltage) applied by the liquid crystal cells of the pixel is higher or lower than: the pixel voltage signal of the corresponding data line with reference to the applied pixel voltage. Therefore, the aging width on the liquid crystal cell, the amplitude of the pixel voltage supplied to the DL, and the amplitude width of the pixel honing signal supplied to the data line are reduced. Therefore, the driving power consumption of the liquid crystal panel and the LCD in which the component is lifted can be reduced, and the pulse type noise can be suppressed. It is obvious to those skilled in the art that various modifications and changes can be made in the present invention, without departing from the spirit and scope of the invention. Therefore, it is intended that the present invention include the modifications and variations of the invention in the scope of the appended claims.

19 1339367 【圖式簡單說明】 第1圖為習知技術LCD之概要圖； 第2A與2B圖說明習知技術的LCD的反轉驅動系統： 第3圖為波形圖，其說明施加到由反轉系統驅動的液晶面板之像素的 電壓變化； 第4圖為根據本發明實施例的LCD概要圖； 第5圖說明根據本發明之實施例當液晶面板由點反轉系統驅動時，施 加至液晶面板的像素之像素電壓的極性圖案； 第6圖為根據本發明之實施例當液晶面板由點反轉系統驅動時；在LCD 的各部分的信號之波形圖；以及 第7圖為根據本發明實施例第4圖之液晶面板之佈局。 【主要元件符號說明】 2 液晶面板 4 閘極驅動器 6 資料驅動器 8 時序控制器 9 共同電壓產生器 12 液晶面板 14 閘極驅動器 16 資料驅動器 18 時序控制器 20 參考電壓產生器 2019 1339367 [Simple description of the drawings] Fig. 1 is a schematic diagram of a conventional LCD; FIGS. 2A and 2B are diagrams showing a reverse driving system of a conventional LCD: FIG. 3 is a waveform diagram illustrating the application to the inverse A voltage change of a pixel of a liquid crystal panel driven by a system; FIG. 4 is a schematic view of an LCD according to an embodiment of the present invention; and FIG. 5 illustrates a liquid crystal panel applied to a liquid crystal when driven by a dot inversion system according to an embodiment of the present invention a polarity pattern of pixel voltages of pixels of the panel; FIG. 6 is a waveform diagram of signals in various portions of the LCD when the liquid crystal panel is driven by the dot inversion system according to an embodiment of the present invention; and FIG. 7 is a diagram according to the present invention The layout of the liquid crystal panel of Fig. 4 of the embodiment. [Main component symbol description] 2 LCD panel 4 Gate driver 6 Data driver 8 Timing controller 9 Common voltage generator 12 LCD panel 14 Gate driver 16 Data driver 18 Timing controller 20 Reference voltage generator 20

Claims (1)

、申讀專利範圍： η日!(更)正替， l 一種液晶面板，包括·· 複數個閘極線； 複數個資料線’其與閘極線相交處界定像素區域；以及 複數個像素，其配置於像素區域中，且響應來自相對應的間極線、 相對應的龍線之信號，其巾複數個像素包括第—像素，由複數 個難線的-第-閘極線與複數個資料線之相妓所界定、以及 第二像素，由複數個間極線的其餘間極線與複數個資料線之相交 處所界定， 其中第-像素包括液晶單元’連接在參考電壓線與連接至第—閘極 線之薄膜電晶體的沒極電極之間， 其中第二像素包括液晶單元，連接在連接至其餘閘極線的薄膜電晶 體和連接至先前間極線之薄膜電晶體的錄電極之間， 其中沿資料線配置之第-像素的液晶單元倾參考電壓線串聯， ，、中…貝料線配置之第二像素的液晶單元係串級連接至參考電壓 線，從而形成一串聯電路。 2·如申請專利範圍第Ί項之液晶面板，其中 麟二像素的液晶單元交替的施加：具有相對於施加在先前一液晶 單元的電塵的正極性或負極性的像素電壓。 1339367 3. 如申凊專利範圍1項之液晶面板，其中 第一像素的每一液晶單元包括： 一連接到先前液晶單元的第一像素電極圖案；以及 一連接到下一個液晶單元的第二像素電極圖案。 4. 如申請專利範圍第3項之液晶面板，其中 此第一和第二像素電極圖案具有冠狀形狀。 5·如申請專利範圍第4項之液晶面板，其中 交替配置冠形的第一和第二像素電極圖案。 6. —種液晶面板包括： 複數個閘極線； 複數個資料線，其與閘極線相交處界定像素區域；The scope of application for patents: η日! (more), l a liquid crystal panel, including · a plurality of gate lines; a plurality of data lines 'which define a pixel area at the intersection with the gate line; and a plurality of pixels, The signal is disposed in the pixel region, and in response to the signal from the corresponding interpolar line and the corresponding dragon line, the plurality of pixels of the towel include the first pixel, and the plurality of hard-wired-first-gate lines and the plurality of pixels The second pixel is defined by the phase of the data line, and is defined by the intersection of the remaining interpole lines of the plurality of interpolar lines and the plurality of data lines, wherein the first pixel includes a liquid crystal cell 'connected to the reference voltage line and connected to a second gate comprising a liquid crystal cell connected to a thin film transistor connected to the remaining gate line Between the liquid crystal cell of the first pixel disposed along the data line, the liquid crystal cell of the second pixel is connected in series to the reference voltage line, and the liquid crystal cell of the second pixel is connected in series. Forming a series circuit. 2. The liquid crystal panel of claim 2, wherein the liquid crystal cells of the lining are alternately applied: having a pixel voltage of a positive polarity or a negative polarity with respect to the electric dust applied to the previous liquid crystal cell. 1. The liquid crystal panel of claim 1, wherein each liquid crystal cell of the first pixel comprises: a first pixel electrode pattern connected to the previous liquid crystal cell; and a second pixel connected to the next liquid crystal cell Electrode pattern. 4. The liquid crystal panel of claim 3, wherein the first and second pixel electrode patterns have a crown shape. 5. The liquid crystal panel of claim 4, wherein the crown-shaped first and second pixel electrode patterns are alternately arranged. 6. A liquid crystal panel comprising: a plurality of gate lines; a plurality of data lines defining a pixel area at a intersection with the gate lines; 配置在像素區域中且沿資料線串聯的液晶單元；以及 配置在像《域巾並沿閘極線、㈣線和液晶單元連接的控綱 關元件， 其中每一個液晶單元包括：一連接到先前液晶單 乐像素電 極圖案；以及一連接到下一個液晶單元的第二 …牟电極圖案， 其中第一和第二像素電極圖案具有冠狀形狀。 2 7.如申請專利範圍第q項之液晶面板，其中 液晶單元交替的施加此相對於施加在先前液晶單元上電壓具有正與 負極性之一的像素電壓。 8·如申請專利範圍第6項之液晶面板，其中 冠形的第一和第二像素電極圖案交替的配置。 9. 一種液晶顯示裝置，包括： 一液晶面板，包括複數個閘極線、複數個資料線，在閘極線和複 數個像素之被處_域界定像素區域，概轉麵在複數侧 極線和複數個資料線之相交處所界定的區域； -閘極驅動器，其依序的驅動配置在該液晶面板上的問極線； -資料驅動器，當驅動下_個閘極線時，提供_第二像素電壓信 號到液晶面板的資料線，當驅動鄰近閘極線的先前閉極線時，該 第二像素電壓信號以第-像素電壓信號為基礎作為參考電壓；以 及 一參考電壓產生器，供應一參考電壓至一參考電壓線， 其中複數個像素包括第一像素，係由複數個閘極線的一第一閘極 線和複數個龍線之相域所界定、以及第二像素，由複數個閉 極線的其餘閘極線和複數個資料線之相交處所界定， 其中第-像素包括液晶單元，連接在參考電壓線和—連接至第一 1339367 閘極線的薄膜；晶體之汲極電極之間， 其中第-像素包括液晶單元’連接在—連接至其餘閘極線的薄膜 電晶體和-連接至先前閘極線之舰電晶體敝極電極之間， 其中沿貢料線配置之第-像素的液晶單元健參考賴線串聯。 10.如申請專利範圍第9項之液晶顯示裝置，其中 第二像素電壓信號具有：對應於像素龍的邏輯值的不同於第一 像素電壓信號的電壓。 11_如申請專利範圍第9項之液晶顯示裝置，其中 第-像素電壓彳§號交替的高於或低於該第—像素電壓信號。 12. —種液晶顯示裝置之驅動方法，包括： 依序的驅動配置在液晶面板上的閘極線； 提供-鄰近資料線攸極_第—像素電壓信號給配置在液 晶面板上的資料線；以及 當-下-個閘極線被驅動時，提供_第二像素電壓信號給資料 線’該第二像素電壓以第一像素電壓為基礎並作為參考電壓， 其中就錢包括概_極線、概個資雜，在酿線和複 數個像素之相交處的區域界定像素區域，複數個像素係在複 數個閘極線和複數师料線之被處所界定的區域， 4 1339367 其巾魏轉素包鄉―像素，係轉賴麟騎—第一閉極 線和複數個資料線之相交處所界定、以及第二像素，由複數 個閘極線的其餘間極線和複數個資料線之相交處所界定， 其令第-像素包括液晶較，連接在參考緣線和_連接至第一 閘極線的薄膜電晶體之汲極電極之間， 其令第一像素包括液晶單元，連接在—連接至其餘線的薄膜 電晶體和—連接至先前閑極線之薄膜電晶體的汲極電極之 間， 貝料線配置之第__像素的液晶單元係與參考電壓線串聯。 13. 如申請專利範圍第I2項之驅動方法，其中 第二像錢號具有對應於像邏咐同於第一像 素電壓彳§欢的電壓。 14. 如申印專利範圍第12項之驅動方法，其中 第二像素電壓信號交替的高於或低於該第—像素電壓信號。 5a liquid crystal cell disposed in the pixel region and connected in series along the data line; and a control element disposed in a field like a field line along the gate line, the (four) line, and the liquid crystal cell, wherein each liquid crystal unit includes: a connection to the previous a liquid crystal single-tone pixel electrode pattern; and a second ...-electrode pattern connected to the next liquid crystal cell, wherein the first and second pixel electrode patterns have a crown shape. 2. The liquid crystal panel of claim q, wherein the liquid crystal cell alternately applies the pixel voltage having one of positive and negative polarities with respect to a voltage applied to the previous liquid crystal cell. 8. The liquid crystal panel of claim 6, wherein the first and second pixel electrode patterns of the crown are alternately arranged. 9. A liquid crystal display device comprising: a liquid crystal panel comprising a plurality of gate lines and a plurality of data lines, wherein the gate lines and the plurality of pixels are defined by a pixel region, and the generalized surface is at a plurality of side lines The area defined by the intersection of the plurality of data lines; - the gate driver, which is sequentially driven to be arranged on the liquid crystal panel; - the data driver, when driving the lower gate line, provides _ a two-pixel voltage signal to a data line of the liquid crystal panel, when driving a previous closed line adjacent to the gate line, the second pixel voltage signal is used as a reference voltage based on the first pixel voltage signal; and a reference voltage generator is supplied a reference voltage to a reference voltage line, wherein the plurality of pixels comprise a first pixel, defined by a first gate line of the plurality of gate lines and a phase domain of the plurality of dragon lines, and the second pixel, the plurality of pixels The intersection of the remaining gate lines of the closed line and the plurality of data lines, wherein the first pixel includes a liquid crystal cell connected to the reference voltage line and connected to the first 1339367 gate a thin film; between the drain electrodes of the crystal, wherein the first pixel includes a liquid crystal cell 'connected to a thin film transistor connected to the remaining gate lines and - connected to the front gate electrode of the ship's transistor, The liquid crystal cell of the first pixel disposed along the tributary line is connected in series with the reference line. 10. The liquid crystal display device of claim 9, wherein the second pixel voltage signal has a voltage different from a first pixel voltage signal corresponding to a logic value of the pixel dragon. The liquid crystal display device of claim 9, wherein the first-pixel voltage 交替§ is alternately higher or lower than the first-pixel voltage signal. 12. A driving method for a liquid crystal display device, comprising: sequentially driving a gate line disposed on a liquid crystal panel; providing a neighboring data line drain _ a first pixel voltage signal to a data line disposed on the liquid crystal panel; And when the lower-lower gate line is driven, providing a second pixel voltage signal to the data line 'the second pixel voltage is based on the first pixel voltage and serves as a reference voltage, wherein the money includes a _ pole line, An area is defined by a region where the intersection of the brewing line and the plurality of pixels defines a pixel region, and the plurality of pixels are in a region defined by a plurality of gate lines and a plurality of material lines, 4 1339367 Baoxiang-Pixel, which is converted to Lai Linqi, is defined by the intersection of the first closed-circuit line and the plurality of data lines, and the second pixel, the intersection of the remaining interpolar lines and the plurality of data lines of the plurality of gate lines Defining, wherein the first pixel comprises a liquid crystal, connected between the reference edge line and the drain electrode of the thin film transistor connected to the first gate line, wherein the first pixel comprises a liquid crystal cell, and the connection is connected to The thin film transistor of the remaining line and the drain electrode connected to the thin film transistor of the previous idle line, the liquid crystal cell of the __ pixel of the bead line configuration is connected in series with the reference voltage line. 13. The method of claim 1, wherein the second image currency has a voltage corresponding to a voltage similar to the first pixel voltage. 14. The driving method of claim 12, wherein the second pixel voltage signal is alternately higher or lower than the first pixel voltage signal. 5
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