TWI339354B - Microcontroller instruction set - Google Patents
Microcontroller instruction set Download PDFInfo
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- TWI339354B TWI339354B TW093132265A TW93132265A TWI339354B TW I339354 B TWI339354 B TW I339354B TW 093132265 A TW093132265 A TW 093132265A TW 93132265 A TW93132265 A TW 93132265A TW I339354 B TWI339354 B TW I339354B
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- Prior art keywords
- instruction
- bit
- register
- microcontroller
- present
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
Description
1339354 九、發明說明: 【發明所屬之技術領域】 本發明係關於微控器,更明確言之,本發明係關於集合 在一指令集中並用於操控該微控器之行為的操作碼指令。 【先前技術】 微控器單元(MCU)用於製造與電子產業已有許多年。圖1 顯示用於中型MCU裝置之一典型核心記憶體匯流排組態。 在許多情形下,微控器利用精簡指令集計算(RISC)微處理 器。部分此等裝置之高性能可歸因於RISC微處理器中常見 的若干架構性特徵。此等特徵包括:1339354 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to a microcontroller, and more specifically to the present invention, to an opcode instruction that is assembled in an instruction set and used to manipulate the behavior of the microcontroller. [Prior Art] A microcontroller unit (MCU) has been used in the manufacturing and electronics industries for many years. Figure 1 shows a typical core memory bus configuration for a medium MCU device. In many cases, the microcontroller utilizes a reduced instruction set computing (RISC) microprocessor. The high performance of some of these devices is attributable to several architectural features that are common in RISC microprocessors. These features include:
Harvard 架構 長字指令 單字指令 單週期指令 指令管線操作 精簡指令集 暫存器檔案架構 正交(對稱)指令 Harvard架構: 如圖2所示,Harvard架構具有程式記憶體26與資料記憶 體22,此等記憶體係分開的記憶體,並且可藉由CPU 24從 分開的匯流排予以存取。此使得頻寬相對於傳統的von Neumann架構(如圖3所示)有所改善,在von Neumann架構 中,CPU 34使用相同的匯流排從相同的記憶體36擷取程式 96779.doc 1339354 ”凝料為了執行一指令,v〇n Neumann機器必須穿過8位 元匯机排進行一或多次(_般為多次)存取,以榻取該指令。 接著,可能需要擷取、操作及可能寫入資料。從此說明中 可看出,匯流排可變得極其擁擠。 與von Neumann機器相反,在Harvard架構之下,在單個 才曰令週期中擷取該指令的所有14個位元。因此在Hamrd 架構下,正在存取程式記憶體時,資料記憶體係在一獨立 的匯流排上,並且可進行讀取與寫入。此等分開的匯流排 能夠在執行一指令的同時擷取下一指令。 長字指令: 長字指令的指令匯流排寬於8位元資料記憶體匯流排(前 者的位元更多)^因為兩個匯流排是分開的,故可實現此特 徵。此進一步使得指令的尺寸不同於8位元寬資料字,從而 可更有效地使用程式記憶體,因為程式記憶體的寬度係針 對架構要求加以最佳化。 單字指令: 單字指令操作碼係14位元寬,從而可具有所有的單字指 令。一 14位元寬的程式記憶體存取匯流排可在單個週期中 擷取一 14位元指令。若使用單字指令,則程式記憶體位置 的字數目等於裝置的指令數目。此表示所有的位置皆係有 效指令。典型地,在von Neumann架構(如圖3所示)中,大 多數指令為多位元組。然而’一般而言,具有4K位元組程 式記憶體之裝置將允許大約2K的指令。此2:丨的比率係一般 化的’並且取決於應用碼。因為每個指令要採用多個位元 96779.doc 1339354 組’故不能保證每個位置均係一有效的指令。 指令管線: 該指令管線係-使指令之掏取與執行重疊的二級管線。 指令的榻取耗用-機器週期(「TCY」),而指令的執行則 耗用另TCY。然而,由於目前指令的榻取與先前指令的 執行係重叠的’故在每個單—的TCY期間,榻取一指令, 並且執行另一指令。 單週期指令: 如果程式記憶體匯流排係14位元寬,故可在單個TCY中 操取整個指令。該指令包令 α 7匕3所有所需要的資訊,並且係在Harvard architecture long word instruction single word instruction single cycle instruction instruction pipeline operation streamlined instruction set register file archive architecture orthogonal (symmetric) instruction Harvard architecture: As shown in Figure 2, the Harvard architecture has program memory 26 and data memory 22, The memory of the memory system is separated and can be accessed by the CPU 24 from a separate bus. This results in an improvement in bandwidth over the traditional von Neumann architecture (shown in Figure 3). In the von Neumann architecture, the CPU 34 uses the same bus to fetch the program from the same memory 36. 96790.doc 1339354 In order to execute an instruction, the v〇n Neumann machine must go through the 8-bit bus machine for one or more (_ many times) accesses to take the command. Then, it may be necessary to capture, operate and It is possible to write data. As can be seen from this description, the busbar can become extremely crowded. Contrary to the von Neumann machine, under the Harvard architecture, all 14 bits of the instruction are fetched in a single command cycle. Therefore, under the Hamrd architecture, when the program memory is being accessed, the data memory system is on a separate bus and can be read and written. These separate buss can be read while executing an instruction. One instruction. Long word instruction: The instruction bus of the long word instruction is wider than the 8-bit data memory bus (more bits of the former) ^ This feature can be realized because the two bus lines are separate. Make The size of the command is different from the 8-bit wide data word, so that the program memory can be used more effectively because the width of the program memory is optimized for the architectural requirements. Single word instruction: The single word instruction operation code is 14 bits wide. Thus, all single word instructions can be used. A 14-bit wide program memory access bus can capture a 14-bit instruction in a single cycle. If a single word instruction is used, the number of words in the program memory location is equal to the device's The number of instructions. This means that all locations are valid instructions. Typically, in the von Neumann architecture (shown in Figure 3), most of the instructions are multi-bytes. However, in general, there are 4K byte programs. The memory device will allow approximately 2K instructions. This 2: 丨 ratio is generalized 'and depends on the application code. Because each instruction uses multiple bits 96790.doc 1339354 group', each location cannot be guaranteed Both are valid instructions. Command pipeline: This command pipeline is the secondary pipeline that makes the acquisition and execution of the command overlap. The sleep of the command - the machine cycle ("TCY"), and The execution of the instruction consumes another TCY. However, since the current instruction's couch is overlapped with the execution of the previous instruction, the instruction is taken during the TCY of each order, and another instruction is executed. Single-cycle instructions: If the program memory bus is 14 bits wide, the entire instruction can be fetched in a single TCY. This instruction package gives α 7匕3 all the information needed and is tied to
單個週期中加以執行。b I 如果扣令的結果修改了程式計數器 的内容’則執行中可能會狃沪 b會延遲一週期。此要求清除管線, 並且擷取一新的指令。 精簡指令集: =指令錢經過精心設計並幻系高度正交( :需較少的指令即可執行全部必要的任務。如果指令較 y則可更快地學習整個指令集。 暫存器擋案架構: 可直接或間接地定址該暫存 ^ 钿系/貝枓-己隐體。將所有 的特殊功此暫存器’包括程式 有 中。 双态映射於貝料記憶體 正交(對稱)指令: 正交指令使得可能使用任何定 行任何操作。此對 ^ 可存器上執 貝力口之不存在「特殊的指令」, 96779.doc 1339354 孝式°又汁既簡單又高效。此外,可大幅簡化學習曲線。 °亥中型指令集僅使用兩個非暫存器導向的指令,其係用於 兩個核心特徵。其卜個係SLEEP指《,其將裝置置於最 低功率使用模式。另—個係CLRWDT指令,其藉由防止晶 片上監視計時器(WDT)上溢並重設裝置來保證晶片正確操 作。 時脈方案/指令週期: 在内口戸將日^·脈輸入(自〇scl) 一分為四,以產生非重叠的 重時脈,即Ql、Q2、QWQ4。在内部,於每個…遞增 式梢a (PC),且於Q4 t從程式記憶體擷取指令並將盆 鎖存於指令暫存器I在後續物糾4期間解碼並執行指 7。圖4與5說明時脈與指令執行流。 指令流/管線操作: 一「指令週期」纟圖4所示之四個Q週期(q1、q2、q^ Q4)所組成’該等q週期包含如圖續5所示的γ。岸注音, 在圖5中,除任何程式分支之外,在單個週期中執行所㈣ 令。程式分支耗用兩個週期,因為從管線「清除」擷取指 令,同時擷取新的指令然後加以執行。 掏取耗用一指令週期,而 週’月而解碼與執行則耗用另一指令週 期。f而’由於管線操作,每個指令在可在-週期中有效 也執订纟I才日令使程式計數器發生變化(例如, 則需要-額外的週期來完成該指令(圖5)。該 於程式計數器在Q1中遞婵。.批 遞增在執行週期中,於週_中將 所擷取的指令鎖存入r指八赵 ' 才曰7暫存器(IR)」中。然後在Q2、 96779.doc 1339354 Q’、Q4週期期間解碼亚執行此指令。在期間讀取(運算 元讀取)以及在Q4期間寫入(目的地寫入)資料記憶體。圖5 顯示用於所示指令序列之二級管線之操作。在時間tcy〇, 從程式記憶體擷取第-指令。在丁⑺期間,執行第一指令 同時操取第二指令。在TCY2_,執行第二指令同時操取 第三指令。在TCY3_,操取第四指令同時執行第三指令 (CALL SUB_ip當第二指令完成執行時,cpu強制指令四 的位址進人㈣’然後將程式計數器(pc)變為請【的位 址。此表示需要從管線「清除」在TCY3期間所榻取的指令。 在TCY4期間,清除指令四(作為一 N〇p來執行)並且擷取位 址SUBJ的指令。最後在TCY5„,執行指令五並掘取位 址SUB_1 + 1的指令。 雖然先前技術之微控器係有用的,但無法模擬各種模 組。而且,如圖!所示的微控器類型無法線性化位址空間。 最後,先前技術之微控器易受編譯器錯誤問題之影響。所 需要者係-種用於微控器之設備、方法與系統,其能夠線 性化位址空間以便實現模組化模擬。本技術令亦存在減少 編譯器錯誤之需要。 【發明内容】 本發明藉由提供-微控器指令集而克服了上述問題以及 現有技術的其他缺陷與不足,該微控器指令集可消除先前 技術中所碰到的許多編譯器錯誤。而Α,提供__設備與系 統用來實現一線性化位址空間,其使模組化模擬成為可能。 本發明可直接 < 間接地定址#冑存㈣帛《資料記憶 96779.doc 1339354 體。將所有特殊功能暫存器, 暫存恶Mx,、 匕括程式计數器(pc)與工作 暫存,映射於該資料記憶體 稱)指令集,其使得可使用任何定址具有—正交(對 行任何操作。此對稱的”,加之何暫存器上執 , '加之不存在「特殊的最佳情 ,」使本發明的程式設計既簡單又高效。此外,可大 化用於寫入軟體應用程式的學習曲線。本發明相對於二 技術的其中一處改進係’使兩個樓案暫存器可用於某此二 運算元指令中。此使得資料可在兩個暫存器之間直接移 動’而不必經過W暫存器’ 0而可提高性能,並降低程式 記憶體之使用。 本發明之較佳具體實施例包括一 ALU/W暫存器、一 PLA、一 8位元乘法器、一具有堆疊之程式計數器㈣、一 表格鎖存器/表格指標、一 ROM鎖存器/IR鎖存器、FSR、中 斷定向電路以及最常見的狀態暫存器。與先前技術不同, 本發明之設計不需要一單獨模組令的計時器、所有的重設 產生電路(WDT、POR、BOR等)、中斷旗標、致動旗標、 INTCON暫存器、RCON暫存器、組態位元、裝置ID字元、 ID位置與時脈驅動器。 熟習此項技術者參考詳細說明與附圖之後將會明白額外 的具體實施例。 【實施方式】 本發明係一種用於在數項具體實施例中提供一微控器指 令集與微控器架構的設備、方法與系統,該微控器架構包 括一線性化的位址空間,其可實現模組化模擬。 96779.doc 12 1339354 本發明之較佳具體實施例之設備架構以四相内部時脈方 案修改先前技術的Harvard架構,使資料路徑為8位元,而 指令長度為16位元《而且,該較佳具體實施例具有一線性 化的記憶體定址方案,其消除對分頁與分庫的需要❶本發 明之記憶體定址方案允許程式記憶體定址能力高達而立 元組。本發明亦支援模組的模擬。 本發明藉由提供-微控器指令集而克服了上述問題以及 現有技術的其他缺陷與不足,該微控器指令集可消除先前 技術中所碰到的許多編譯器錯誤。而且,提供一設備與系 統用來實現一線性化位址空間,其使模組化模擬成為可能。 本發明可直接或間接地定址其暫存器檔案或資料記憶 體。將所有特殊功能暫存器,包括程式計數器(pc)與工作 暫存器(W)映射於該資料記憶冑中。轉明具有一正交(對 稱)指令集,其使得可使用任何定址模式在任何暫存器上執 行任何操作》此對稱的性質,加之不存在「特殊的最佳情 況使本發明的程式設計既簡單又高效。此外,可大幅簡 化學習曲線。本發明相對於先前技術的一系列架構改進之 一係,使兩個檔案暫存器可用於某些二運算元指令中。此 使得資料可在兩個暫存器之間直接移動,而不必經過…暫 存器,因而可提高性能,並降低程式記憶體之使用。圖6 顯示本發明之微控器核心之方塊圖。 圖6中說明本發明之微控器核心按照習慣做法,圖6 令的連接信號線可包含一斜線’該斜線旁邊的數字指示信 號線的頻寬(以位元為單位)。參考圖6的右上角,有—資料 96779.doc 1 己憶體1G4’其係用於儲存資料以及傳輸資料至-t央處理 單70 (下述)亚k 4中央處理單S傳輸資料。該資料記憶體 係由複數個位址位置組成。在本發明之較佳具體實施例 令,該資料記憶體m係一線性化4K記憶體,其係被分成複 數個4刀’其中每個部分有十六個頁面或儲存庫。典型地, 每個儲存庫具有256位址位置。在該較佳具體實施例中複 數個儲存庫中的其中—個儲存庫係專門用於通用與專用暫 存器,在此情形中係最高的儲存庫,即儲存庫0。 經由一位址鎖存器102將一選擇電路108耗合至資料記憶 體104。該選擇電路⑽係用於選擇複數個供應儲存庫位址 本發明之較佳具體實施例包括一 ALU140與工作暫存 器136; — PLA; — 8位元乘法器;一程式計數器(pc)i68與 堆疊170; —表格鎖存器124;表格指標148 :一 r〇m鎖存器 152與IR鎖存器126 ; FSR120、121、122;中斷定向電路以 及最常見的狀態暫存器。與先前技術不同,本發明之設計 不需要一單獨模組中的計時器、所有的重設產生電路 (WDT、POR、BOR等)、令斷旗標、致動旗標、INTC〇N暫 存器、RCON暫存器、組態位元、裝置m字元、①位置與時 脈驅動器。 I/O列表: 使用本發明可獲得一大張輸入/輸出(1/0)命令列表,表i 中顯示該I/O列表。 96779.doc 14 1339354 表1 I/O列表 名 稱 計數 I/O 正常操作 操作測試 模組 程式 模組 模擬 模組 addr<21:0> 22/0 程式記憶體位址 nqbank<3:0> 4/0 活動低RAM儲存庫 選擇 d<15:0> 16/1 程式記憶體資料 db<7:0> 8/1/0 資料匯流排 forcext 1/1 強制外部指 令測試模式 irp<7:0> 8/0 周邊位址 irp9 1/0 指令暫存器位元9 ncodeprt 1/1 活動低碼保護 neprtim 1/1 活動低EPROM寫入 結束 nhalt 1/1 活動低 暫停 nintake 1/1 活動低中斷確認提前 以及從睡眠中醒來 np<7:0> 8/0 表格鎖存資料 npcmux 1/0 活動低PC多工 npchold 1/0 活動低PC保持 nprtchg 1/1 活動低埠改變中斷 nq4clrwdt 1/0 活動低清除wdt nq4sleep 1/0 活動低睡眠 nqrd 1/0 活動低讀取檔案 nreset 1/1 活動低重設 nwrf 1/0 活動低寫入檔案 ql:q4 4/1 4相Q時脈 qi3 1/1 Q時脈之組合 q23 1/1 Q時脈之組合 q41 1/1 Q時脈之組合 testO 1/1 測試模式0 tsthvdet 1/1 高電壓偵測 wreprom 1/0 寫入eprom writem 1/0 寫入記憶體 wrtbl 1/0 表格寫入指令 nintakd 1/1 中斷確認延遲 intak 1/1 中斷確認 96779.doc •15- 1339354 時脈方案/指令週期 如圖7所示,在内部將時脈輸入(自〇scl)—分為四,以產 生非重疊的四重時脈,即Q1、Q2、QmQ4。在内部,於每 ^Qi遞增程式計數器(PC),且使用Q4從程式記憶體梅取指 :並將其鎖存於指令暫存11中。在後續的Q1與Q4期間解碼 並執行指令。在Q1„完成PLA解碼。在的師週期期 間,從記憶體或周邊元件讀取運算元並且ALu執行計算。 在Q4期間,將結果寫人目的地位置。圖8說明時脈 行流。 、曰7钒 Q週期活動 如圖7所示,每個指令週期(TCY)係由四則週期⑼至 成。亥Q週期係與裝置振盪器週期(TOSC)相同。0调 個指令週期解碼、讀取、處理資料、寫入等的時 :曰疋T圖(圖7)顯示Q週期與指令週期的關係。可將 且二行指令週期(TCY)的四個Q週期一般化為:Execute in a single cycle. b I If the result of the deduction modifies the contents of the program counter, then there may be a delay in the execution of the program. This requires clearing the pipeline and taking a new instruction. Reduced instruction set: = instruction money is carefully designed and the phantom is highly orthogonal (: requires fewer instructions to perform all necessary tasks. If the instruction is y, the entire instruction set can be learned faster. Architecture: The temporary storage system can be directly or indirectly addressed. The special function of this register is included in the program. The two-state mapping is in the quadrilateral memory orthogonal (symmetric) Instruction: Orthogonal instructions make it possible to use any operation of any line. There is no "special instruction" in the memory port of this register, 96779.doc 1339354 孝式° is easy and efficient. The learning curve can be greatly simplified. The medium-sized instruction set uses only two non-scratch-oriented instructions for two core features. The SLEEP refers to ", which places the device in the lowest power usage mode. Another one is the CLRWDT instruction, which prevents the wafer from operating properly by preventing the watchdog timer (WDT) from overflowing and resetting the device. Clock scheme/instruction cycle: Input the pulse in the internal port (self-〇scl) ) divided into four In order to generate non-overlapping heavy clocks, namely Ql, Q2, QWQ4. Internally, in each ... incremental tip a (PC), and in Q4 t capture instructions from the program memory and latch the pot in the instruction The buffer I decodes and executes the finger 7 during the subsequent object correction 4. The clock and instruction execution flow are illustrated in Figures 4 and 5. Instruction flow/pipeline operation: One "instruction cycle" 四个 four Q cycles (q1) as shown in Figure 4. , q2, q^ Q4) The 'q cycles include γ as shown in Figure 5. In Fig. 5, except for any program branch, execute the (4) command in a single cycle. It takes two cycles because the instruction is fetched from the pipeline and the new instruction is fetched and executed. The instruction takes one instruction cycle, while the decoding and execution of the week consumes another instruction cycle. f and 'Because of the pipeline operation, each instruction is valid in the - cycle and also the program counter is changed (for example, it takes - an extra cycle to complete the instruction (Figure 5). The program counter is repeated in Q1. The batch increment is in the execution cycle and will be captured in the week_ The instruction is latched into r, which means that the instruction is executed in the Q2, 96779.doc 1339354 Q', Q4 cycle. The read is performed during the period. And write (destination write) data memory during Q4. Figure 5 shows the operation of the secondary pipeline for the sequence of instructions shown. At time tcy, the first instruction is fetched from the program memory. (7) During the execution of the first instruction, the second instruction is executed at the same time. In TCY2_, the second instruction is executed while the third instruction is being executed. In TCY3_, the fourth instruction is executed while the third instruction is executed (CALL SUB_ip when the second instruction is completed) At the time, the cpu forces the address of the instruction four to enter (4)' and then changes the program counter (pc) to the address of []. This means that you need to "clear" the instructions that were taken during TCY3 from the pipeline. During TCY4, instruction four is cleared (executed as a N〇p) and the instruction of address SUBJ is fetched. Finally, at TCY5, execute instruction five and dig the instruction of address SUB_1 + 1. Although the prior art microcontroller is useful, it cannot simulate various modules. Moreover, the type of microcontroller shown in Figure ! cannot Linearizing the address space. Finally, prior art microcontrollers are susceptible to compiler error problems. Those in need are devices, methods and systems for microcontrollers that can linearize address space for implementation. Modular simulation. The present invention also has the need to reduce compiler errors. SUMMARY OF THE INVENTION The present invention overcomes the above problems and other deficiencies and deficiencies of the prior art by providing a set of microcontroller control instructions. The instruction set eliminates many of the compiler errors encountered in the prior art. Furthermore, the __device and system are used to implement a linearized address space, which makes modular simulation possible. The present invention can be directly < Inter-ground addressing #胄存(四)帛"Data Memory 96779.doc 1339354. All special function registers, temporary memory Mx, and program counter (pc) and work temporary storage, mapped to this data The memory set is called the instruction set, which makes it possible to use any address--orthogonal (any operation on the line. This symmetry), plus the register on the register, 'plus the absence of "special best," The programming of the invention is simple and efficient. In addition, the learning curve for writing to the software application can be enlarged. One of the improvements of the present invention relative to the second technology is that the two building registers can be used for some. In the two operand instructions, this allows the data to be moved directly between the two registers without having to go through the W register '0' to improve performance and reduce the use of program memory. Examples include an ALU/W register, a PLA, an 8-bit multiplier, a stacked program counter (4), a table latch/table index, a ROM latch/IR latch, FSR, Interrupt directional circuits and the most common state registers. Unlike the prior art, the design of the present invention does not require a separate module timer, all reset generation circuits (WDT, POR, BOR, etc.), interrupt flags. , actuating the flag, INTC The ON register, the RCON register, the configuration bit, the device ID character, the ID location, and the clock driver. Those skilled in the art will appreciate additional embodiments after reference to the detailed description and the drawings. The present invention is an apparatus, method and system for providing a microcontroller instruction set and a microcontroller architecture in a plurality of specific embodiments, the microcontroller architecture comprising a linearized address space, which Implementing a modular simulation. 96779.doc 12 1339354 The device architecture of the preferred embodiment of the present invention modifies the prior art Harvard architecture with a four-phase internal clock scheme such that the data path is 8 bits and the instruction length is 16 bits. Moreover, the preferred embodiment has a linearized memory addressing scheme that eliminates the need for paging and partitioning. The memory addressing scheme of the present invention allows program memory addressing capabilities to be as high as the stereol. The invention also supports simulation of modules. The present invention overcomes the above problems and other deficiencies and deficiencies of the prior art by providing a set of microcontroller instructions that eliminates many of the compiler errors encountered in the prior art. Moreover, a device and system are provided for implementing a linearized address space that enables modular simulation. The present invention can address its scratchpad file or data memory directly or indirectly. All special function registers, including the program counter (pc) and the work register (W), are mapped in the data memory. It turns out that there is an orthogonal (symmetric) instruction set that allows any operation to be performed on any register using any addressing mode. The nature of this symmetry, combined with the absence of "special best cases, makes the programming of the present invention both Simple and efficient. In addition, the learning curve can be greatly simplified. One of the series of architectural improvements of the present invention relative to the prior art is that two file registers can be used in some of the two operand instructions. The scratchpads move directly between the registers without having to go through the ... register, thereby improving performance and reducing the use of program memory. Figure 6 shows a block diagram of the core of the microcontroller of the present invention. According to the customary practice, the connecting signal line of Figure 6 may include a diagonal line. The number next to the diagonal line indicates the bandwidth of the signal line (in bits). Referring to the upper right corner of Figure 6, there is - data 96779.doc 1 Recollection 1G4' is used to store data and transmit data to the -t central processing unit 70 (described below) sub-k 4 central processing single S transmission data. The data memory system consists of multiple The address location is composed. In a preferred embodiment of the present invention, the data memory m is a linearized 4K memory, which is divided into a plurality of 4 knives, each of which has sixteen pages or a repository. Typically, each repository has 256 address locations. In the preferred embodiment, one of the plurality of repositories is dedicated to general purpose and dedicated registers, in this case the highest The repository, i.e., repository 0. A selection circuit 108 is consuming a data memory 104 via an address latch 102. The selection circuit (10) is used to select a plurality of supply repository addresses. The specific embodiment includes an ALU 140 and a work register 136; - PLA; - 8-bit multiplier; a program counter (pc) i68 and stack 170; - table latch 124; table indicator 148: a r〇m lock 152 and IR latches 126; FSRs 120, 121, 122; interrupt directional circuits and the most common state registers. Unlike the prior art, the design of the present invention does not require a timer in a single module, all Reset generation circuit (WDT, POR, BOR, etc. , break flag, actuated flag, INTC〇N register, RCON register, configuration bit, device m-character, 1-position and clock driver. I/O list: Available with the present invention A large list of input/output (1/0) commands, the I/O list is shown in table i. 96779.doc 14 1339354 Table 1 I/O List Name Counting I/O Normal Operation Operation Test Module Program Module Simulation Module addr<21:0> 22/0 program memory address nqbank<3:0> 4/0 active low RAM repository select d<15:0> 16/1 program memory data db<7:0> 8 /1/0 Data bus forcext 1/1 Force external command test mode irp<7:0> 8/0 Peripheral address irp9 1/0 Instruction register bit 9 ncodeprt 1/1 Active low code protection neprtim 1/ 1 active low EPROM write end nhalt 1/1 activity low pause nintake 1/1 activity low interrupt acknowledge early and wake up from sleep np<7:0> 8/0 table latch data npcmux 1/0 active low PC Npchold 1/0 activity low PC keep nprtchg 1/1 activity low 埠 change interrupt Nq4clrwdt 1/0 active low clear wdt nq4sleep 1/0 active low sleep nqrd 1/0 active low read file nreset 1/1 active low reset nwrf 1/0 active low write file ql:q4 4/1 4 phase Q Clock qi3 1/1 Q clock combination q23 1/1 Q clock combination q41 1/1 Q clock combination testO 1/1 test mode 0 tsthvdet 1/1 high voltage detection wreprom 1/0 write Eprom writem 1/0 write memory wrtbl 1/0 table write instruction nintakd 1/1 interrupt acknowledge delay intak 1/1 interrupt acknowledge 96790.doc •15- 1339354 clock scheme/instruction cycle as shown in Figure 7, in Internally, the clock input (self-〇scl) is divided into four to generate non-overlapping quadruple clocks, namely Q1, Q2, and QmQ4. Internally, the program counter (PC) is incremented every ^Qi, and the pointer is fetched from the program memory using Q4: and latched in the instruction temporary memory 11. The instructions are decoded and executed during subsequent Q1 and Q4. The PLA decoding is completed at Q1. During the teacher cycle, the operands are read from the memory or peripheral components and ALU performs the calculation. During Q4, the results are written to the destination location. Figure 8 illustrates the clock flow. 7 Vanadium Q cycle activity is shown in Figure 7. Each instruction cycle (TCY) is from four cycles (9) to completion. The HQ cycle is the same as the device oscillator period (TOSC). 0 is decoded and read, When processing data, writing, etc.: 曰疋T diagram (Figure 7) shows the relationship between Q cycle and instruction cycle. The four Q cycles of two-line instruction cycle (TCY) can be generalized as:
Q 1 .指令解碼週期或強制NOP Q2 .指令讀取週期或NOP Q3 :處理資料Q 1. Instruction decoding cycle or forced NOP Q2. Instruction read cycle or NOP Q3: Processing data
Q4 ·心令寫入週期或NOP 母個指令將顯示該指令的詳細Q週期操作。 指令流/管線操作 成^_ q_ (φ'Q2'㈣⑽所組 而解碼與執行耗用另,取制“令週期, 曰々k,。然而,由於管線操作, 96779.doc 16 1339354 每個指令在一週期中有效地執行。有四類指令流。第一類 係一正常的1字元1週期管線指令。如圖9所示,此等指令將 耗"效週期來執行。第二類係1字元2週期管線清除指 '此等私令包括相對的分支,相對的呼叫、跳過與返回。 田S 7改^ PC時,捨棄管線擁取。如圖1 〇所示,此使得 該指令耗用兩個有效週期來執行。第三類係、表格操作指 令。此等指令將暫停掏取以***以及讀取或寫入週期至程 式記憶體。執行表格操作時㈣取的指令係保㈤週期,並 在表格操作之後的下-週期執行,如圖11所示。第四類係 新的二字指令。此等指令包括MOVFF與M0VLF。在此等指 令中’指令之後的操取包含該等位址的剩餘部分。對於執 行第一字元期間的MOVFF,該機器將執行該源暫存器的讀 取。在執行第二字元期間’獲得源位址,然後該指令將完 成該移動’如圖12所示。M0VLF與此類似,不過其在⑽ 週期中移動2個文字值進入,如圖13所示。 第五’係CALL與GOTO的二字指令。在此等指令中指令 之後的擷取包含跳轉或呼叫目的地位址的剩餘部分。正^ 情況下,此等指令將需要3個週期來執行,其令2個用於擷 取該等2指令字元,另外1個用於隨後的管線清除。然而, 藉由在第二次擷取時提供一高速路徑,可在指令執行的第 一週期中以完整的值來更新PC ’從而得到一2週期指令,如 .圖14所示。第六,係中斷辨識執行。在下面的中斷部分中 論述中斷期間的指令週期。 96779.docQ4 • The heartbeat write cycle or NOP master instruction will display the detailed Q cycle operation of the instruction. The instruction stream/pipeline operation is set to ^_q_ (φ'Q2'(4)(10) and the decoding and execution consumes another, and the "order cycle, 曰々k, is taken. However, due to pipeline operation, 96779.doc 16 1339354 each instruction Executed effectively in a cycle. There are four types of instruction streams. The first class is a normal 1-character 1-cycle pipeline instruction. As shown in Figure 9, these instructions will consume the "expiration cycle". A 1-character 2-cycle pipeline clearing means that these private orders include relative branches, relative calls, skips, and returns. When the field S 7 is changed to PC, the pipeline is discarded. As shown in Figure 1, this makes The instruction is executed in two valid cycles. The third type is a table operation instruction. These instructions will suspend the capture to insert and read or write cycles to the program memory. When executing the table operation (4) The (five) cycle, and the next-cycle execution after the table operation, as shown in Figure 11. The fourth class is the new two-word instruction. These instructions include MOVFF and M0VLF. In these instructions, the operation after the instruction Contains the remainder of the addresses. For the M during the first character period OVFF, the machine will perform a read of the source register. During the execution of the second character 'get the source address, then the instruction will complete the move' as shown in Figure 12. M0VLF is similar, but it is (10) Move 2 literal values into the cycle, as shown in Figure 13. The fifth 'system' is a two-word instruction for CALL and GOTO. The instruction after the instruction in these instructions contains the remainder of the jump or call destination address. ^ In the case, these instructions will take 3 cycles to execute, which causes 2 to fetch the 2 instruction characters and 1 for subsequent pipeline clearing. However, by the second capture A high-speed path is provided to update the PC 'with a complete value in the first cycle of instruction execution to obtain a 2-cycle instruction, as shown in Figure 14. Sixth, interrupt recognition execution. In the interrupt section below The instruction cycle during the interrupt is discussed. 96779.doc
ALU 本發明包含一 8位元算術與邏輯單元(alu)M2與工作暫 存器136 ’如圖6所示。ALU 142係一通用算術單元。其執行 工作暫存器中之資料與任何暫存器擋案之間的算術與布爾 函數。ALU U2係8位元寬,並能夠執行加法、減法、移位 1!邏輯運异。除非另外提及,否則算術運算係二的補數性 f。工作(w)暫存器136係一用於ALUl4〇操作之8位元工作 暫存窃》w暫存器136係可定址的,並且可直接寫入或讀 取:AUJUO能夠對兩個運算元或單個運算元執行算術或邏 輯運^。所有的單運算元指令在…暫存器136或既定檔案暫 存器上操作。對於兩個運算元的指令,其t-個運算元係 W暫存器136 ’而另-個係-檔案暫存器或-8位元立即常 數,或一等效的儲存媒體。 根據所執行的指令,ALU 14〇可影響STATUS暫存器(下 述)一中進位(C)、數位進位(DC)、零(z)、上溢(〇v)與負⑻ {儿之值C與DC位元係在減法中分別用作一借位與數位 借出位元。 本發月之&佳具體實施例包括—8 X8硬體乘法器1 34,其 係包括於如圖6‘七a* m 斤不之裳置的ALU 142中。藉由使乘法成為 _ /认,;4操作可在單個指令週期中完成。此硬體運 #系-出16位疋結果之無符號的乘法。將該結果儲存進 16位凡乘積暫存器(PRQDH:PR〇DL卜乘法器不會影響 ST娜暫存器中的任何旗標。 狀態暫存器 96779.doc -18- 。圖15中顯示狀 位元7-5未予實 ▲ ST御S暫存器包含ALui4〇之狀態位元 〜暫存器°在本發明之較佳具體實施例中 施’並且係作為|0,讀取。 ,系’ N」,即負位疋。此位元係用於有符號的算術(2 的補數)°其指示該結果是否為負,(ALUMSb=1),1=結果 為負,〇=結果為正。 位兀3係「0V」上溢位元。此位元係用於有符號的算術 (2的補數)。其指示7位元大小之上溢使符號位元(位元乃 改支狀態。對於此位元’ 1 =有符號算術發生上溢,(在此算 術運算中),並且〇=無上溢發生。 元係 z」令位元。對於此位元,丨=算術或邏輯運算 的紇果為令,亚且〇=算術或邏輯運算的結果非零。 4元1係DC」數位進位/借位位元。對於此位元,1 =該 果的第4低序位元發生進位輸出,並且〇=該結果的第4低 序位元不發生進位輸出。應注意對於借位,可使極性反 轉。 位凡0係「C」進位/借位位元。對於此位元,1=該結果的 取兩有效位το發生進位輸出,並且〇=該結果的最高有效位 元不發生進位輸出。與位元1一樣’對於借位,可使極性反 轉。 c與DC位元係減法中分別用作一借位與數位借位位元。 進位係ALU位元7進位輸出。數位進位係aLu位元3進位輸 出。如果ALU結果位元<7:〇>為1〇,,則零位元為真。^^係ALU 結果位元7。如果2的補數結果超過+ 127或小於_128,則將 96779.doc -19- 1339354 設定上溢位元。上溢係ALU位元6進位輸出與ALU位元7進 位輸出之XOR運算。與所有其他暫存器一樣,STATUS暫存 器可為任何指令的目的地。如果STATUS暫存器係影響任一 狀態位元之指令的寫入目的地,則停用對狀態位元的寫 入。根據ALU結果與指令規格來設定或清除該等位元。因 此,將STATUS暫存器作為目的地之指令的結果可能與預期 不符。ALU The present invention includes an 8-bit arithmetic and logic unit (alu) M2 and a work register 136' as shown in FIG. The ALU 142 is a general purpose arithmetic unit. It performs arithmetic and Boolean functions between the data in the scratchpad and any scratchpad file. The ALU U2 is octet wide and is capable of performing addition, subtraction, and shifting. Unless otherwise mentioned, the arithmetic operation is the complement of f. The work (w) register 136 is an 8-bit work temporary storage for the ALUl4 operation. The w register 136 is addressable and can be directly written or read: AUJUO can operate on two operands. Or a single operand performs arithmetic or logic operations. All single operand instructions operate on the ... scratchpad 136 or the intended file register. For two operand instructions, the t-operating elements are the W register 136' and the other-system-file register or -8-bit immediate constant, or an equivalent storage medium. Depending on the instruction being executed, ALU 14〇 can affect the STATUS register (described below) one carry (C), digital carry (DC), zero (z), overflow (〇v) and negative (8) The C and DC bits are used as a borrow and a digital lending bit, respectively, in subtraction. The preferred embodiment of the present month includes an -8 X8 hardware multiplier 1 34, which is included in the ALU 142 as shown in Fig. 6 'seven a* m kg. By making the multiplication _ / acknowledgment, the 4 operations can be completed in a single instruction cycle. This hardware transports the unsigned multiplication of the 16-bit result. The result is stored in the 16-bit product register (PRQDH: PR〇DL multiplier does not affect any flags in the ST Na register. Status register 96779.doc -18-. Figure 15 shows The bit 7-5 is not implemented. The ST-S register contains the status bit of the ALui4~ register. In the preferred embodiment of the present invention, 'is taken as |0, read. Line 'N', which is the negative bit 疋. This bit is used for signed arithmetic (2's complement) ° which indicates whether the result is negative, (ALUMSb=1), 1=the result is negative, 〇=result Positive. Positioned as 3 "0V" overflow bit. This bit is used for signed arithmetic (2's complement). It indicates that the 7-bit size overflows the sign bit (the bit is changed) Branch state. For this bit '1 = signed arithmetic overflow, (in this arithmetic operation), and 〇 = no overflow occurs. The element z" is the bit. For this bit, 丨 = arithmetic or The result of the logical operation is that the result of the arithmetic and logical operation is non-zero. 4 yuan 1 series DC" digital carry / borrow bit. For this bit, 1 = the fourth low order of the fruit yuan The raw bit is output, and 〇 = the fourth low-order bit of the result does not have a carry output. It should be noted that for the borrow, the polarity can be reversed. The bit 0 is the "C" carry/borrow bit. Yuan, 1 = the result of the two significant bits τ ο a carry output, and 〇 = the most significant bit of the result does not carry a carry output. Like bit 1 'for borrowing, the polarity can be reversed. c and DC The bit system subtraction method is used as a borrowing and a digit borrowing bit respectively. The carry system ALU bit 7 carries the carry output. The digital carry system aLu bit 3 carries the carry output. If the ALU result bit <7:〇> 1〇,, then the zero is true. ^^ is the ALU result bit 7. If the complement result of 2 exceeds + 127 or is less than _128, then 96796.doc -19- 1339354 is set to the overflow bit. Overflow ALU bit 6 carry output and ALU bit 7 carry output XOR operation. Like all other registers, the STATUS register can be the destination of any instruction. If the STATUS register affects any status bit The write of the instruction of the meta-instruction disables the writing of the status bit. According to the ALU result and the instruction specification To set or clear the bits. Therefore, the result of the instruction to use the STATUS register as a destination may not match expectations.
例如,CLRF REG指令一般將該暫存器寫入至〇,並設定Z 位元。CLRF STATUS指令將停用對N、OV、DC與C位元的 寫入,並設定Z位元。此使得STATUS暫存器變為〇〇〇u uluu。因此,推薦僅使用BCF、BSF、SWAPF與MOVWF指 令來改變STATUS暫存器,因為此等指令不會影響任何狀態 位元。若要瞭解其他指令如何影響該等狀態位元,請參閱 「指令集概述」。 程式計數器模组For example, the CLRF REG instruction typically writes the scratchpad to 〇 and sets the Z bit. The CLRF STATUS instruction will disable writing to N, OV, DC, and C bits and set the Z bit. This causes the STATUS register to become 〇〇〇u uluu. Therefore, it is recommended to use only the BCF, BSF, SWAPF, and MOVWF instructions to change the STATUS register because these instructions do not affect any status bits. To find out how other instructions affect these status bits, see "Instruction Set Overview." Program counter module
修改該程式計數器(PC)168(參閱圖6),以允許擴展至最大 21位元。此係藉由添加一 5位元寬PCLATU暫存器而完成, 該暫存器之操作係類似於PCLATH暫存器。亦修改PC 168 來定址程式記憶體中之位元組而非字。若要實施此舉,PC 168之LSb處需有一位元組定址位元始終為〇。Pcl的LSb位 元係可讀取的’但不可寫入,如果使用者試圖將·丨I寫入 LSb ’則結果將為'〇’。若要允許隱藏測試EPr〇m,則pc 168 需有一隱藏的第22位元(位元21)(參閱圖16)。此PC位元在正 常情況下為0。當進入測試模式或程式設計模式時,設定此 96779.doc -20- 1339354 位元,並且將從測試區域擷取該等指令。一旦設定此位元’ 則其無法藉由執行程式而清除,必須重設裝置。 程式計數器(PC) 168最大達如圖16所示的一 21位元暫存 器。將PCL 184,即PC 168的低位元組,映射進資料記憶體 104中(參閱圖6)。PCL 184係可讀取以及可寫入的,正如任 何其他暫存器一樣。PCH 182與PCU 180係PC的高位元組, 並且不可直接定址。因為未將PCH 182與PCU 184映射進資 料或程式記憶體160中,故將暫存器PCLATH 178 (PC高鎖 存器)及PCLATU 176 (PC上部鎖存器)用作PC 168之高位元 組之保持鎖存器。 將PCLATH 178與PCLATU 176映射進資料記憶體104。使 用者可經由PCLATH 178讀取及寫入PCH 182,並經由 PCLATU 176讀取及寫入PCU 180 〇每次於Q1期間擷取指令 之後,將PC 168的字遞增2,除非: •藉由一 GOTO、CALL、RETURN、RETLW、RETFIE或 Branch指令修改0 •藉由中斷回應修改。 •由於一指令對PCL 168的目的地寫入。 「跳過」等效於被跳過位址處之一強制NOP週期。圖16 與17顯示各種情況之程式計數器之操作。 參考圖16,不同指令之PC 168、PCLATH 178與PCLATU 1 7 6的操作如下: a.關於PCL的讀取指令: 對於讀取PCL 184的任何指令。d=0的所有位元組指令; 96779.doc -21 · 1339354 MOVFF PCL, X ; CPFSEQ ; CPFSGT ; CPFSLT ; MULWF ; TSTFSZ然後PCL至資料匯流排然後至ALU或至目的地。最 後,PCH至 PCLATH與 PCU至 PCLATU。 b.關於PCL的寫入指令: 寫入PCL 184的任何指令。例如,MOVWF; CLRF; SETF, 然後寫入8位元資料至資料匯流排1 74,然後至PCL 1 84。還 有,PCLATH至 PCH與 PCLATU至 PCU。 c.關於PCL的讀取-修改-寫入指令:Modify the program counter (PC) 168 (see Figure 6) to allow expansion to a maximum of 21 bits. This is done by adding a 5-bit wide PCLATU register, which operates similar to the PCLATH register. The PC 168 is also modified to address the bytes in the program memory rather than the words. To implement this, a tuple addressing bit at the LSb of the PC 168 is always 〇. The LSb bit of Pcl is readable but not writable. If the user attempts to write 丨I to LSb, the result will be '〇'. To allow the hidden test EPr〇m, pc 168 needs to have a hidden 22nd bit (bit 21) (see Figure 16). This PC bit is 0 in normal case. When entering test mode or programming mode, set this 96779.doc -20- 1339354 bit and retrieve the instructions from the test area. Once this bit is set, it cannot be cleared by executing the program, and the device must be reset. The program counter (PC) 168 is up to a 21-bit scratchpad as shown in FIG. PCL 184, the lower byte of PC 168, is mapped into data memory 104 (see Figure 6). The PCL 184 is readable and writable, just like any other scratchpad. PCH 182 and PCU 180 are high-order tuples of PC and are not directly addressable. Since the PCH 182 and PCU 184 are not mapped into the data or program memory 160, the scratchpads PCLATH 178 (PC high latch) and PCLATU 176 (PC upper latch) are used as the high byte of the PC 168. Hold the latch. PCLATH 178 and PCLATU 176 are mapped into data memory 104. The user can read and write to the PCH 182 via the PCLATH 178 and read and write to the PCU 180 via the PCLATU 176. Each time the instruction is fetched during Q1, the word of the PC 168 is incremented by 2 unless: • by one GOTO, CALL, RETURN, RETLW, RETFIE, or Branch instruction modification 0 • Modification by interrupt response. • Due to an instruction write to the destination of PCL 168. "Skip" is equivalent to one of the skipped addresses to force a NOP period. Figures 16 and 17 show the operation of the program counter for various situations. Referring to Figure 16, the operation of PC 168, PCLATH 178 and PCLATU 176 for different instructions is as follows: a. Read command for PCL: Any instruction to read PCL 184. All byte instructions for d=0; 96779.doc -21 · 1339354 MOVFF PCL, X ; CPFSEQ ; CPFSGT ; CPFSLT ; MULWF ; TSTFSZ then PCL to data bus and then to ALU or to destination. Finally, PCH to PCLATH and PCU to PCLATU. b. Write instruction for PCL: Any instruction written to PCL 184. For example, MOVWF; CLRF; SETF, then write 8-bit data to data bus 1 74, then to PCL 1 84. Also, PCLATH to PCH and PCLATU to PCU. c. Read-modify-write instructions for PCL:
對PCL進行讀取-寫入-修改操作的任何指令。d=l的所有 位元組指令;位元指令;NEGF。讀取:PCL至資料匯流排 至ALU。寫入:將8位元結果寫入至資料匯流排以及至PCL, 然後 PCLATH至 PCH;最後 PCLATU至 PCU。Any instruction that performs a read-write-modify operation on the PCL. All byte instructions of d=l; bit instructions; NEGF. Read: PCL to data bus to ALU. Write: Write 8-bit results to the data bus and to PCL, then PCLATH to PCH; finally PCLATU to PCU.
讀取-修改-寫入僅以結果影響PCL 184。分別將PCLATH 178與PCLATU 176中的值載入PCH 182與PCU 180。例如, 對於指令「ADDWF」,PCL 1 84將導致以下跳轉。如果在指Read-modify-write only affects PCL 184 with the result. The values in PCLATH 178 and PCLATU 176 are loaded into PCH 182 and PCU 180, respectively. For example, for the instruction "ADDWF", PCL 1 84 will cause the following jump. If you are pointing
令之前,PC = 0003F0h、W = 30h、PCLATH = 〇5h及 PCLATU =lh ’則在指令之後PC = 01052〇h »為了完成一真實的20 位元計算跳轉,使用者需要計算20位元目的地位址,寫入 PCLATH 178與PCLATU 176,然後將低值寫入PCL 168 〇 d. RETURN指令: 使用圖1 7將<MRU>堆疊至PC<20:0>,GOTO與CALL指令 之 PC 168、PCLATH 178與 PCLATU 176之操作如下: e. CALL、GOTO指令: 在2字指令(操作碼)中提供一目的地位址。第一字操作碼 96779.doc -22- 1339354 <6:0>至PCL<7:1>。第一字操作碼<7>至PCLATH<0>以及至 PCH<0>。第二字操作碼 <6:〇> 至 PCLATH<7:1> 以及 PCH <7:1>。第二字操作碼 <ιι:7> 至 PCLATU<4:0> 以及 PCU <4:0> ° 應注意,以下與PC 168有關的操作不會改變PCLATH 178 與PCLATU 176 : a. RETLW、RETURN與 RETFIE指令》 b. 將中斷向量強制到PC上。Before the command, PC = 0003F0h, W = 30h, PCLATH = 〇5h and PCLATU = lh ' then PC = 01052〇h after the instruction » In order to complete a real 20-bit calculation jump, the user needs to calculate the 20-bit destination bit. Address, write PCLATH 178 and PCLATU 176, then write the low value to PCL 168 〇d. RETURN command: Use <MRU> to stack PC to PC <20:0>, GOTO and CALL instruction PC 168, The operation of PCLATH 178 and PCLATU 176 is as follows: e. CALL, GOTO instructions: Provide a destination address in a 2-word instruction (opcode). The first word opcode 96779.doc -22- 1339354 <6:0> to PCL<7:1>. The first word operation code <7> to PCLATH<0> and to PCH<0>. The second word operation code <6:〇> to PCLATH<7:1> and PCH <7:1>. The second word opcode <ιι:7> to PCLATU<4:0> and PCU <4:0> ° It should be noted that the following operations related to PC 168 do not change PCLATH 178 and PCLATU 176: a. RETLW, RETURN and RETFIE instructions b. Force the interrupt vector to the PC.
c. 關於PCL的讀取-修改-寫入指令(例如BSF PCL,2)。 返回堆疊操作 本發明具有一 31層深的返回(或硬體)堆疊。堆疊的深度 相對於先前技術有所增加,以便允許更複雜的程式。該堆 疊非為程式或資料記憶體空間的一部分。c. Read-modify-write instructions for PCL (eg BSF PCL, 2). Back to Stack Operation The present invention has a 31 layer deep return (or hard) stack. The depth of the stack has increased relative to the prior art to allow for more complex programs. This stack is not part of the program or data memory space.
當執行一 CALL或RC ALL指令或確認一中斷時’將PC 168 推到堆疊上。當執行RETURN、RETLW或RETFIE指令時, 從該堆疊拉出PC 168值。PCLATU 176與PCLATH 178不受 任何返回指令的影響。 該堆疊用作一 31字元x21位元RAM與一 5位元堆疊指標, 並且在所有重設之後將堆疊指標初始化為OOOOOb0不存在 與堆疊指標OOOh相關聯的RAM字。此僅係一重設值。一 CALL·型指令引起向該堆疊推入期間,首先使堆疊指標遞 增,並且在該堆疊指標所指向的RAM位置寫入PC的内容。 一 RETURN型指令引起從該堆疊取出期間,將STKPTR所指 向的RAM位置的内容轉移至PC,然後使堆疊指標遞減。 96779.doc -23· 1339354 堆疊頂部存取Push the PC 168 onto the stack when executing a CALL or RC ALL command or confirming an interrupt. When the RETURN, RETLW, or RETFIE instruction is executed, the PC 168 value is pulled from the stack. PCLATU 176 and PCLATH 178 are not affected by any return commands. The stack is used as a 31-character x 21-bit RAM with a 5-bit stacking indicator, and the stacking indicator is initialized to OOOOOb0 after all resets. There is no RAM word associated with the stacked indicator OOOh. This is only a reset value. A CALL-type instruction causes a stack indicator to be incremented during the push-in to the stack, and the contents of the PC are written at the RAM location pointed to by the stack indicator. A RETURN type command causes the contents of the RAM location pointed to by the STKPTR to be transferred to the PC during fetching from the stack, and then the stacking index is decremented. 96779.doc -23· 1339354 Stack top access
堆疊的頂部係可讀取及可寫入的。三個暫存器位置 TOSU、TOSH與TOSL定址STKPTR所指向的堆疊RAM位 置。此允許使用者在必要時實施一軟體堆疊。在一CALL或 RC ALL指令或一中斷之後,該軟體可藉由讀取TOSU、TOSH 與TOSL暫存器而讀取被推入的值。可將此等值放置於一使 用者定義的軟體堆疊上。在返回時,軟體可替換TOSU、 TOSH與TOSL並進行一返回。應注意,在此時間期間,使 用者必須停用全域中斷致動位元,以防止無意中執行堆疊 操作。 PUSH與POP指令The top of the stack is readable and writable. Three register locations TOSU, TOSH, and TOSL address the stack RAM location pointed to by STKPTR. This allows the user to implement a software stack when necessary. After a CALL or RC ALL instruction or an interrupt, the software can read the pushed value by reading the TOSU, TOSH, and TOSL registers. This value can be placed on a user-defined software stack. On return, the software can replace TOSU, TOSH and TOSL and make a return. It should be noted that during this time, the user must disable the global interrupt actuation bit to prevent inadvertent stacking operations. PUSH and POP instructions
因為堆疊頂部(TOS)係可讀取及可寫入的,故在不干擾正 常程式執行的情況下將值推到堆疊上以及從堆疊上拉出值 的能力係一理想的選擇。為了將目前的PC值推到堆疊上, 可執行一 PUSH指令。此舉將目前的PC值推到該堆疊上;設 定TOS = PC與PC = PC + 2。在不干擾正常執行的情況下, 從該堆疊拉出TOS值並使用先前被推到該堆疊上的值將其 替換的能力,係藉由使用POP指令來達成。POP指令從該堆 疊拉出TOS值,但此值未寫入PC ;推到該堆疊上的先前值 則變為TOS值。 返回堆疊指標(STKPTR) STKPTR暫存器包含返回堆臺指標值與上溢及下溢位 元。堆疊上溢位元(STKOVF)與下溢位元(STKUNF)允許使 用軟體驗證堆疊條件。僅在重設POR之後清除STKOVF與 96779.doc -24· 1339354 STKUNF位元。 在將PC推到該堆疊上3 1次之後(未從該堆疊上拉出任何 值),第32次推入覆寫來自第3 1次推入的值,並設定 STK-OVF位元,而STKPTR則保持於11111b。第33次推入覆 寫第32次推入(依此類推),而STKPTR保持於11111b。 在對堆疊進行足夠多次取出以卸載該堆疊之後,下一次 取出將向PC返回零值,並且設定STKUNF位元,同時使 STKPTR保持於00000b。下一次取出再次返回零(依此類推) 同時使STKPTR保持於00000b »應注意,在下溢的情況下將 一零返回至PC具有使該程式定向於重設向量的效果,其中 可驗證堆疊條件並採取適當的動作。 可經由STKPTR暫存器來存取堆疊指標。使用者可讀取與 寫入堆疊指標值。RTOS可使用此值進行返回堆疊維護。圖 18顯示STKPTR暫存器。堆疊指標的值將為〇至31。重設時’ 該堆疊指標值將為〇。推入時,該堆疊指標將遞增’而取出 時則遞減。 堆疊上溢/下溢重設 按照使用者的選擇,上溢與下溢可使一裝置重設中斷程 式碼。使用一組態位元STVRE來致動該重設。當停用STVRE 位元時,上溢或下溢將設定適當的STKOVF或STKUNF位元 而不引起重設。當致動STVRE位元時,上溢或下溢將設定 適當的STKOVF或STKUNF位元,然後使一裝置重設的性質 非常類似於WDT重設。在任一情況下,不清除STK0VF或 STKUNF位元,除非使用者軟體或P〇R重設將其清除。圖18 96779.doc -25- 1339354 至21說明堆疊暫存器。圖22至29說明堆疊操作。 程式記憶體 本發明之較佳具體實施例具有最高達2百萬位元組 (2Μ)χ8使用者程式記憶體空間。該程式記憶體空間主要係 要包含用於執行的指令’然而’可使用表格讀取與寫入指 令來儲存與存取資料表格。有另—心8測試程式記憶體空 間用於測試R0M、組態位元與識別字元。 該裝置具有最高達21位元之程式計數器,其能夠定址 2MX8程式記憶體空間。還有一第22 %位元,在正常操作參 期間,其係,隱藏的,並且當其被設㈣,可存取組態位元、 裝置ID與測試R 〇 Μ。可在測試模式或程式設計模式中設定 此位7L ’亚且必須重設該裝置才能清除此位元。使用此位 元•又定無法存取使用者程式記憶體空間。因為PC必須存取 矛王式°己隐體中一偶數位元組邊界上的指令,故PC的LSb係 一默示的,〇,,並且對於每—指令,PC遞增二。 «亥重叹向量係000000h,並且該高優先權中斷向量係 0 0 0 0 0 8 h,並日 吒/基 it 44* 低優先權中斷向量係〇〇〇〇18h(參閱圖3〇)。 ▼ 程式記憶體組織 矛弋》己It體中的每個位置具有—位元組位址。此外,每2 個鄰近位元纟且且右一 ^ — 、八男一子位址。圖3 1顯示具有所示位元組與 :位址之&式s己憶體之映射。在程式記憶體内,必須使該 等^ 7的子對齊。圖32顯示具有數個範例性指令之程式記 " 、射以及置於該映射中針對該等指令之十六進制 表釔操作將與位元組實體—起工作◊表格區塊不必字 96779.doc •26· 1339354 對齊,故表格區塊可在任何位元組位址開始與結束。此點 的例外係,使用表格寫入來程式化内部程式記憶體或外部 字元寬快閃記憶體的情況。當程式化時,可能需要將寫入 資料與程式化方法所用的字元寬度對齊。 程式記憶體模式 本發明可以五種可能的程式記憶體組態之一來操作。藉 由組態位元來選擇該組態。可能的模式為: • MP-微處理器 • EMC-擴充微控器 0 • PEMC-受保護擴充微控器 • MC-微控器 • PMC-受保護微控器 微控器與受保護微控器模式僅允許内部執行。在該程式 記憶體之外的任何存取均讀取所有的零。受保護的微控器 模式亦致動碼保護特徵。微控器係一未程式化裝置的預設 模式。 擴充微控器模式存取内部程式記憶體與外部程式記憶· 體。執行在内部與外部記憶體之間自動地切換。該2丨位元 :位址允許2M位元組的程式記憶體範圍。受保護擴充微控 器模式將藉由防止對内部記憶體的表格讀取/寫入同時仍 允許執行與表格讀取/寫入外部程式 記憶體進行碼保護。 ΙΜ呈式 該微處理器模式僅存取外部程式記憶體。忽略該晶片上 程式記憶體。該2!位元之位址允許2河位元組的程=憶體 96779.doc •27· 1339354 範圍。 在裝置的正常操作期間’藉由使用TBLRD指令,可讀取 測試記憶體與組態位元。如果RC0N暫存器中的LWRT位元 被設定或者裝置處於測S式與程式設計模式’則僅可使用 TBLWT指令來修改此等區域°Because the top of stack (TOS) is readable and writable, the ability to push values onto the stack and pull values from the stack without disturbing normal program execution is an ideal choice. In order to push the current PC value onto the stack, a PUSH instruction can be executed. This pushes the current PC value onto the stack; set TOS = PC and PC = PC + 2. The ability to pull a TOS value from the stack and replace it with a value previously pushed onto the stack without disturbing normal execution is achieved by using a POP instruction. The POP instruction pulls the TOS value from the stack, but this value is not written to the PC; the previous value pushed onto the stack becomes the TOS value. Return Stacking Indicator (STKPTR) The STKPTR register contains the return stack indicator value and the overflow and underflow bits. Stack Overflow Bits (STKOVF) and Underflow Bits (STKUNF) allow software to verify stacking conditions. The STKOVF and 96779.doc -24·1339354 STKUNF bits are cleared only after the POR is reset. After pushing the PC onto the stack 31 times (no value is pulled from the stack), the 32nd push overwrites the value from the 31st push and sets the STK-OVF bit, and STKPTR remains at 11111b. The 33rd push overrides the 32nd push (and so on) while the STKPTR remains at 11111b. After the stack is removed multiple times to unload the stack, the next take-out will return a zero value to the PC and set the STKUNF bit while keeping the STKPTR at 00000b. The next time it is taken back to zero again (and so on) while keeping STKPTR at 00000b » It should be noted that returning a zero to the PC in the case of underflow has the effect of orienting the program to the reset vector, where the stacking condition can be verified and Take the appropriate action. Stacking metrics can be accessed via the STKPTR register. The user can read and write the stack indicator values. The RTOS can use this value to return to stack maintenance. Figure 18 shows the STKPTR register. The value of the stacked indicator will be 〇 to 31. When resetting, the stack indicator value will be 〇. When pushed in, the stack indicator will increment 'and decrease when it is fetched. Stack Overflow/Underflow Reset The overflow and underflow can cause a device to reset the interrupt code according to the user's choice. The reset is actuated using a configuration bit STVRE. When the STVRE bit is deactivated, an overflow or underflow will set the appropriate STKOVF or STKUNF bit without causing a reset. When the STVRE bit is actuated, an overflow or underflow will set the appropriate STKOVF or STKUNF bit, and then the nature of a device reset is very similar to the WDT reset. In either case, the STK0VF or STKUNF bit is not cleared unless the user software or P〇R reset clears it. Figure 18 96779.doc -25-1339354 through 21 illustrate the stack register. 22 to 29 illustrate the stacking operation. Program Memory A preferred embodiment of the present invention has up to 2 million bytes (2 Μ) χ 8 user program memory space. The program memory space is primarily intended to contain instructions for execution 'however' table read and write instructions can be used to store and access data tables. There is another - heart 8 test program memory space for testing R0M, configuration bits and identification characters. The device has a program counter of up to 21 bits that can address 2MX8 program memory space. There is also a 22nd bit, which is hidden during the normal operation, and when it is set (4), the configuration bit, device ID and test R 〇 are accessible. This bit can be set in test mode or programming mode and must be reset to clear this bit. Use this bit • You will not be able to access the user program memory space. Since the PC must access the instructions on the boundary of an even number of bits in the Spear-Type Hidden Object, the LSb of the PC is implied, 〇, and for each instruction, the PC is incremented by two. «Hai sigh vector 000000h, and the high priority interrupt vector is 0 0 0 0 0 8 h, and the day 基 / base it 44 * low priority interrupt vector system 〇〇〇〇 18h (see Figure 3 〇). ▼ Program Memory Organization Each location in the body has a 1-bit address. In addition, every 2 adjacent bits and the right one ^ - , eight male and one sub-address. Figure 31 shows a mapping of the <forms' memory of the indicated byte and the address. In the program memory, the sub-items must be aligned. Figure 32 shows a program with several exemplary instructions ", and the hexadecimal table placed in the map for those instructions will work with the byte entity. The table block does not have to be word 96797 .doc •26· 1339354 Alignment, so the table block can start and end at any byte address. The exception to this is the use of table writes to program internal program memory or external character wide flash memory. When stylized, you may need to align the write data with the character width used by the stylization method. Program Memory Mode The present invention can operate in one of five possible program memory configurations. This configuration is selected by configuring the bit. The possible modes are: • MP-Microprocessor • EMC-Expanded Microcontroller 0 • PEMC-Protected Expansion Microcontroller • MC-Microcontroller • PMC-Protected Microcontroller Microcontroller and Protected Microcontroller The mode is only allowed to be executed internally. All accesses outside of the program's memory read all zeros. The protected microcontroller mode also activates the code protection feature. The microcontroller is a preset mode for an unprogrammed device. Expand the microcontroller mode to access internal program memory and external program memory. Execution automatically switches between internal and external memory. The 2 bits: The address allows the program memory range of 2M bytes. The protected extended microcontroller mode will protect the table from reading/writing external program memory by preventing read/write to the internal memory table. ΙΜ Presentation This microprocessor mode only accesses external program memory. The program memory on the wafer is ignored. The 2!bit address allows for 2 rivers of the tuple = memory 96779.doc • 27· 1339354 range. Test memory and configuration bits can be read by using the TBLRD instruction during normal operation of the device. If the LWRT bit in the RC0N register is set or the device is in S-mode and programming mode, then only the TBLWT instruction can be used to modify these areas.
在測試與程式設計模式中才能從此等區域執行9 僅在具有被定義為1/0接針之部分的外部記憶體匯流排 之裝置上才能使用擴充微控器模式與微處理器模式。表2 列出了哪些模式玎存取内部與外部記憶體。圖33說明不同 程式模式中的裝置記憶體映射。 圖2裝置模式記憶體存取 操作模式 内部程式記憶體 外部程式記憶體 微處理器 無存取 執行/TBLRD/TBLWT 擴充微控器 執行/TBLRD/TBLWT 執行/TBLRD/TBLWT 受保護擴充微控器 執行 執行/TBLRD/TBLWT 微控器 執行/TBLRD/TBLWT 無存取 受保護微控器 %f/TBLRD 無存取 外部程式記憶體介面 當選擇微處理器或擴充微控器模式時,最多將四個埠組 怨為系統匯流排。兩個埠及第三個埠的一部分係多工位址/ 資料El 排而另外~個埠的一部分係用於控制信號。需 要外°卩組件來解多工位址與資料。外部記憶體介面可在8 位7G貝料&式或16位元資料模式令運行。外部記憶體介面 上的位址總係值元組位址。 圖36與37分別說明16位元與8位元資料的外部記憶體連 96779.doc • 28· 1339354 接°外部程式記憶體匯流排共享接針上的1/〇埠功能。圖μ 列出了 I/O接針功能上外部匯流排功能之典型映射。在擴充 微控器模式中,當該裝置係在内部記憶體之外執行時,該 等控制信號將不活動。其將進入一狀態,其中5力〉、 八<19:0>係三態;0E、WRH、WRL、1^與[]8信號係「i」; UBAO與 ALE係「0」》 16位元外部介面 如果外部介面係16位元,則將作為16位元字元榻取該等 私·?。该OE輸出致動信號將一次致動兩種類型的程式記憶 體以輸出一 16位元字元》無需將該位址的最低有效位元 ΒΑ0連接至記憶體裝置。 一外部表格讀取邏輯上係一次執行一位元組,儘管該記 憶體將從外部讀取一 16位元字元。該位置的最低有效位元 將在内部於高與低位元組(LSb=0至較低位元組,LSb=l至較 尚位元組)之間進行選擇。微處理器與擴充微控器模式中的 外部位址係21位元寬;此允許定址最高達2M位元組b 一 16位元匯流排上的一外部表格寫入邏輯上係一次執行 位元組。貫際的寫入將取決於所連接之外部裝置的類型 與MEMCON暫存器中的WM<1:〇>位元,如圖34所示。表 格操作部分詳細說明實際的寫入週期& 8位元外部介面 如果外部介面係8位元,則將作為2個8位元之位元組擷取 -玄等h v。在—指令週期内掏取兩個位元組。無需將該位 址的最低有效位元連接至記憶體裝置。崎出致動信號與 96779.doc •29- 將在4週期之Q3部分致動從程式記憶體讀取該指令 的最π有效位疋組,然後在該週期之部分,ba〇將變為 〇並將靖取最低有效位元組,以形成16位元指令字元。 外邛表格讀取亦係一次執行一位元組。一外部表格寫 入係_人執行—位元組。在每次外部寫入時,WRL係活動 的0 田選擇8位元介面時,不使用WRH、線路,並且 接針返回到I/O埠功能。一組態位元選擇外部介面的8位元 模式。 外部等待週期 X外。卩。己憶體介面支援等待週期。該外部記憶體等待週 期僅適用於透過該外部匯流排之表格讀取與表格寫入操 作因為裝置之執行係與指令擷取聯繫在一起,故執行速 率比擷取速率快係沒有意義的。因此,如果需要使程式擷 取放丨又,則必須使該處理器速度以一不同的TCY時間放慢。 MEMCON暫存器中的WAIT <丨:〇>位元將在每個記憶體 擷取週期選擇〇、1、2或3個額外的TCY週期。對於一 16位 疋"面上的表格讀取與寫入,該等等待週期將係有效的。 在8位元介面上,對於表格讀取與寫入,該等待僅將發生 於Q4上。 上電時等待之預設設定係要確定最大3個TcY週期的等 待。此可確保慢速的記憶體可在重設之後立即在微處理器 楔式中工作。一組態位元,稱為WAIT,將致動或停用等待 狀態。圖39說明16位元介面,而圖4〇說明8位元,在兩種情 96779.doc -30- 1339354 形下皆顯示不具有等待之程式記憶體指令擷取以及具有等 待狀態之表格讀取。 外部匯流排信號停用 為了靈活地利用提交給外部匯流排的接針,在組態位元 中提供數個停用。為了停用整個外部匯流排,正如在擴充 微控器模式中時可能進行的那樣,以及允許一 Dma功能, 如圖35所示在MEM-CON暫存器中組態EBDIS位元。此停用 將允許對整個外部匯流排介面進行三態處理。此將允許 DMA操作以及透過1/0接針功能藉由程式控制來直接控制 外部裝置。 在模擬器系統中,-ME裝置必須具有用於表示匯流排停 用組態位元的輸入,以使1/0埠功能可偵測到作為外部介面 之接針的狀態。_ME裝置亦具有一特殊輸入接針,其指示 該模擬器系統是否係處於微處理器或擴充微控器模式。 資料記憶體 在本發明中,可將資料記憶體與通用RAM尺寸擴充至 4096位元組。資料記憶體位址係12位元寬。將該資料記憶 體分割成16個儲存庫,每個儲存庫有256位元組,該等儲存 庫包含通用暫存器(GPR)與特殊功能暫存器(SFR卜 將GPR機械化為一位元組寬RAM陣歹,尺寸相當於組合 的G P R暫存器。通常在s F R控制其功能的周邊元件之間分配 SFR 〇 藉由儲存庫選擇暫存器(BSR<3:G>)來選擇儲存庫。㈣ 暫存器可能存取16個以上的儲存庫,然而直接長定址模式 96779.doc 31 1339354 係限於12位元位址或16個儲存庫》bsR受到相應限制> 裝置指令可在一指令週期中讀取、修改並寫入一特定位 置。每個週期僅產生一位址,故不可能在單個週期中讀取 一位置並修改/寫入另一位置。圖42說明一範例性資料記憶 體映射。 通用暫存器 在所有PIC裝置中,所有的資料RAM皆被所有指令用作暫 存器。大多數資料記憶體儲存庫僅包含GPR記憶體,所有 裝置的儲存庫〇上必須包括有G p R記憶體。 儲存庫0中的GPR數目之絕對最小值係128。此GPR區域, 稱為存取RAM,係必要的,以使程式師可具有不論BSR設 定如何皆可存取的資料結構。 特殊功能暫存器 SFR係特殊暫存η,通常用於裝置與周邊控制及狀態功 能。所有指令皆可存取此等暫存器。如有可能,儲存㈣ 之上部128位元組中應包含所有的咖。如果㈣不使用一 特定裝置上所有可用的位置,則不實施未❹的位置,並 ^將其讀取裝置,例如lcd控制器可在除儲存 庫15之外的其他儲存庫中具有sir區域。 ^庫15中SFR之邊界可因裝置不同而進行修改。存取 中必須包括至少16個咖。圖43顯示—可能的 功能暫存器映射。圖44盘45 + #、# 述。 〃45顯™m力能暫存器之概 定址模式 96779.doc •32- 1339354 本發明支援7個資料定址模式: •固有 •文字 •直接短 •直接強制 •直接長 •間接 •索引間接偏移 其中三個模式,即直接強制、直接長與間接索引係PIC 架構的新模式。 固有 對於某些指令,例如DAW,除操作碼中所明確定義的定 址之外,不需要其他定址。 文字 文字指令包含一文字常數欄位,通常用於一數學運算, 例如ADDLW。文字定址亦用於GOTO、CALL與分支操作碼。 直接短 大多數數學與移動指令在直接短定址模式中操作。在此 定址模式中,該指令包含該資料之最低有效位址之八個位 元。位址的其餘四個位元係來自儲存庫選擇暫存器或 BSR。BSR係用於在資料記憶體區域中的各儲存庫之間切換 (參見圖47)。 對大容量通用記憶體空間的需要指示了 一通用RAM分庫 方案。BSR的下半位元組選擇目前活動的通用RAM儲存 96779.doc -33 -Execution from these areas is only possible in test and programming modes. 9 Expanded microcontroller mode and microprocessor mode are only available on devices with external memory busses that are defined as part of the 1/0 pin. Table 2 lists which modes access internal and external memory. Figure 33 illustrates device memory mapping in different program modes. Figure 2 Device Mode Memory Access Operation Mode Internal Program Memory External Program Memory Microprocessor No Access Execution / TBLRD/TBLWT Extended Microcontroller Execution / TBLRD / TBLWT Execution / TBLRD / TBLWT Protected Extended Microcontroller Execution Execute /TBLRD/TBLWT Microcontroller Execution /TBLRD/TBLWT No Access Protected Microcontroller %f/TBLRD No Access External Program Memory Interface When selecting microprocessor or expansion microcontroller mode, up to four The blame is the system bus. Part of the two 埠 and the third 系 are multiplexed addresses/data El platoons and a part of the other 埠 系 is used for control signals. An external component is required to solve the multiplex address and data. The external memory interface can be run in 8-bit 7G Beacon & or 16-bit data mode. The address on the external memory interface is the total tuple address. Figures 36 and 37 illustrate the external memory connection of 16-bit and 8-bit data, respectively. 96779.doc • 28· 1339354 Connect to the external program memory bus to share the 1/〇埠 function on the pin. Figure μ shows a typical mapping of the external bus function on the I/O pin function. In the extended microcontroller mode, when the device is executed outside of the internal memory, the control signals will be inactive. It will enter a state in which 5 forces >, eight <19:0> are tri-state; 0E, WRH, WRL, 1^ and []8 signal systems "i"; UBAO and ALE are "0"" 16 bits If the external interface is 16 bits, then the external interface will be taken as a 16-bit character. . The OE output actuation signal will actuate both types of program memory at a time to output a 16-bit character. There is no need to connect the least significant bit ΒΑ0 of the address to the memory device. An external table read logically executes a tuple at a time, although the memory will read a 16-bit character from the outside. The least significant bit of the location will be selected internally between the high and low bytes (LSb = 0 to the lower byte, LSb = 1 to the higher byte). The external address in the microprocessor and extended microcontroller mode is 21 bits wide; this allows addressing up to 2M bytes b. An external table write on a 16-bit bus is logically executed once. group. The contiguous write will depend on the type of external device connected and the WM<1:〇> bit in the MEMCON register, as shown in Figure 34. The table operation section details the actual write cycle & 8-bit external interface. If the external interface is 8 bits, it will be retrieved as two 8-bit bytes - Xuan et al. Two bytes are fetched during the - instruction cycle. There is no need to connect the least significant bit of the address to the memory device. Sakiy actuation signal and 96679.doc • 29- will be activated in the Q3 part of the 4 cycles to read the most π-valid group of the instruction from the program memory, and then in the part of the cycle, the 〇 will become 〇 The least significant byte will be taken to form a 16-bit instruction character. The reading of the foreign form is also performed by one tuple at a time. An external form is written into the system _ human execution - a byte. In each external write, the WRL system's active 0 field selects the 8-bit interface, does not use WRH, line, and the pin returns to the I/O埠 function. A configuration bit selects the 8-bit mode of the external interface. The external wait period is X. Hey. The memory interface supports the waiting period. The external memory wait cycle is only applicable to table read and table write operations through the external bus because the execution of the device is associated with instruction fetching, so the execution rate is less meaningful than the fetch rate. Therefore, if you need to make the program unloaded, you must slow the processor speed by a different TCY time. The WAIT <丨:〇> bit in the MEMCON register will select 〇, 1, 2 or 3 additional TCY cycles in each memory capture cycle. For a 16-bit 疋" table read and write, these wait cycles will be valid. On the 8-bit interface, for table reads and writes, this wait will only occur on Q4. The default setting waiting for power-on is to determine the wait for a maximum of 3 TcY cycles. This ensures that slow memory can work in the microprocessor wedge immediately after reset. A configuration bit, called WAIT, will activate or deactivate the wait state. Figure 39 illustrates the 16-bit interface, while Figure 4 illustrates the 8-bit. In both cases, 96796.doc -30- 1339354 shows the program memory instruction capture without wait and the table read with wait state. . External bus signal deactivation In order to flexibly utilize the pins submitted to the external bus, several deactivations are provided in the configuration bits. To deactivate the entire external bus, as may be done while expanding the microcontroller mode, and to allow a Dma function, configure the EBDIS bit in the MEM-CON register as shown in Figure 35. This deactivation will allow tristate processing of the entire external bus interface. This will allow DMA operations and direct control of external devices via program control via the 1/0 pin function. In the simulator system, the -ME device must have an input to indicate the bus stop configuration bit so that the 1/0 function can detect the state of the pin as the external interface. The _ME device also has a special input pin that indicates whether the simulator system is in the microprocessor or expansion microcontroller mode. Data Memory In the present invention, the data memory and general RAM size can be expanded to 4096 bytes. The data memory address is 12 bits wide. The data memory is divided into 16 repositories, each of which has 256 bytes, and the repositories include a general purpose register (GPR) and a special function register (SFR mechanizes GPR into a single element) The group wide RAM array is equivalent in size to the combined GPR register. Usually the SFR is allocated between the peripheral components whose s FR controls its function. The storage select register (BSR<3:G>) is used to select the storage. (4) The scratchpad may access more than 16 repositories, however the direct long addressing mode 96779.doc 31 1339354 is limited to 12-bit addresses or 16 repositories. bsR is subject to corresponding restrictions. Read, modify, and write to a specific location during the instruction cycle. Only one address is generated per cycle, so it is not possible to read a location and modify/write another location in a single cycle. Figure 42 illustrates an example data. Memory Map. General Purpose Register In all PIC devices, all data RAM is used as a scratchpad by all instructions. Most data memory banks contain only GPR memory, and all devices must be included in the repository. G p R memory The absolute minimum number of GPRs in repository 0 is 128. This GPR region, called access RAM, is necessary so that the programmer can have a data structure that can be accessed regardless of the BSR settings. The SFR is a special temporary storage η, which is usually used for device and peripheral control and status functions. All instructions can access these registers. If possible, the upper 128 bytes of the storage (4) should contain all the coffee. If (iv) not using all available locations on a particular device, the unfinished location is not implemented and its reading device, such as the lcd controller, may have a sir region in a repository other than the repository 15. The boundary of the SFR in the library 15 can be modified by the device. At least 16 coffees must be included in the access. Figure 43 shows the possible function register map. Figure 44 disk 45 + #, # 。 45 display TMm Force Registers Addressing Mode 96797.doc • 32- 1339354 The present invention supports 7 data addressing modes: • Inherent • Text • Direct Short • Direct Mandatory • Direct Long • Indirect • Index Indirect Offset Three Mode, that is, straight Mandatory, Direct Long and Indirect Indexing are new modes of the PIC architecture. Inherently for some instructions, such as DAW, no addressing is required other than the addressing defined in the opcode. Text literals contain a literal constant field, usually Used for a mathematical operation, such as ADDLW. Text addressing is also used for GOTO, CALL and branch opcodes. Directly short Most math and move instructions operate in direct short addressing mode. In this addressing mode, the instruction contains the lowest data. The eight bits of the valid address. The remaining four bits of the address are from the repository select register or BSR. The BSR is used to switch between repositories in the data memory area (see Figure 47). The need for a large-capacity general-purpose memory space indicates a general-purpose RAM partition scheme. The lower half of the BSR selects the currently active general purpose RAM storage. 96779.doc -33 -
I3393M 庫。為協助此操作, 指令。 在指令集令已提供了—M0VLB儲存庫 如果不實施目前選定从 、疋的儲存庫(例如儲存庫丨3),任何 取將讀取所有,0,。完赤料 成對位疋桶的任何寫入,並且根據情 況來設定/清除STATUS暫存器位元。 直接強制 將所有的特殊功能暫存器(SFR)映射進資料記憶體空間 令。為了方便地存取SFR,—般將其全部映射進儲存庫15。 為了簡化存取’指令中有一 1位元欄位,其將位址指向通用 讀之儲存庫〇之下半部分以及SFR之儲存庫15之上半部 分,而不論BSR的内容為何。將BSR設定為BsR=n,於是, 可以任何指令定址3個儲存庫,即直接強制模式中的儲存庫 〇與15以及直接短模式中的儲存庫「打」。 直接長 直接長定址將資料位址的全部十二個位元編碼進該指 令。唯有MOVFF指令才使用此模式。 間接定址 間接定址係定址資料記憶體的-種模式,其,藉由另— 暫存Is來決定該指令中的資料記憶體位址。這對於資料記 憶體中的資料表格或堆叠可能係有用的。圖53顯示間接定 址之操作。FSR暫存器的值係用作資料記憶體位址。 間接定址暫存器 本發明具有三個I 2位元暫存器用於間接定址。此等暫存 B · 益疋· 96779.doc -34- 1339354I3393M library. To assist with this operation, the instructions. The M0VLB repository has been provided in the instruction set. If you do not implement the repository currently selected from , (for example, repository 丨 3), any fetch will read all, 0,. Complete any writes of the paired bins and set/clear the STATUS register bit as appropriate. Direct Force Directs all Special Function Registers (SFRs) into the Data Memory Space Order. In order to conveniently access the SFR, all of them are mapped into the repository 15 as usual. To simplify access, there is a 1-bit field in the instruction that points to the lower half of the general-purpose read repository and the upper half of the SFR's repository 15, regardless of the content of the BSR. The BSR is set to BsR=n, so that three banks can be addressed by any command, that is, the banks 直接 and 15 in the direct forcing mode and the bank in the direct short mode. Direct Long Direct Long Address encodes all twelve bits of the data address into the instruction. This mode is only used by the MOVFF instruction. Indirect Addressing Indirect addressing is a mode of addressing data memory. The data memory address in the instruction is determined by another temporary storage Is. This may be useful for data tables or stacking in data memory. Figure 53 shows the operation of indirect addressing. The value of the FSR register is used as the data memory address. Indirect Addressing Register The present invention has three I 2 bit registers for indirect addressing. Such temporary storage B · Yi Yi · 96779.doc -34- 1339354
• FSROH與FSROL• FSROH and FSROL
• FSR1H與FSR1L• FSR1H and FSR1L
• FSR2H與FSR2L FSR係12位元暫存器,並允許定址4096位元組資料記憶 體位址範圍中的任何位置。• FSR2H and FSR2L FSR are 12-bit registers and allow any location in the 4096-bit data memory address range to be addressed.
除此之外,存在實體上不予實施的暫存器INDF0、INDF1 與INDF2。讀取或寫入至此等暫存器可啟動間接定址,其 中對應FSR暫存器中的值係資料的位址。如果經由FSR間接 地讀取檔案INDF0(或INDF1,2)本身,則讀取全部'0’(設定零 位元)。同樣,如果間接地寫入INDF0(或INDF1,2),則該操 作將等同於NOP,並且STATUS位元不受影響。 間接定址操作 每個INDF暫存器具有四個與其關聯的位址。當完成對四 個INDF位置之一的資料存取時,所選定的位址將FSR暫存 器組態為:In addition to this, there are scratchpads INDF0, INDF1, and INDF2 that are not physically implemented. Reading or writing to these registers initiates indirect addressing, where the value of the data in the FSR register corresponds to the address of the data. If the file INDF0 (or INDF1, 2) itself is indirectly read via the FSR, all '0's (set zero bits) are read. Similarly, if INDF0 (or INDF1, 2) is written indirectly, then the operation will be equivalent to NOP and the STATUS bit will not be affected. Indirect Addressing Operation Each INDF register has four addresses associated with it. When data access to one of the four INDF locations is completed, the selected address configures the FSR scratchpad as:
•在間接存取之後自動遞減FSR中的值(位址)(後遞減)。 •在間接存取之後自動遞增FSR中的值(位址)(後遞增)。 •在間接存取之前自動遞增FSR中的值(位址)(預遞增)。 •在間接存取之後不改變FSR中的值(位址)(無變化)。 當使用自動遞增或自動遞減特徵時,對FSR的影響不會 被反映到STATUS暫存器中。例如,如果間接定址使FSR等 於'0',則將不設定Z位元。添加此等特徵使FSR在用於資料 表格操作之外還可用於堆疊指標。 索引間接定址 96779.doc -35- 1339354 每個INDF具有一與其關聯的位址,其執行一索引的間接 存取。當發生對此INDF位置的資料存取時,將FSR組態為: •在間接存取之前,添加W暫存器中有符號的值以及FSR 中的值以形成該位址。 •不改變FSR值。 間接定址(INDF)暫存器之間接寫入 如果FSR暫存器包含一值,該值指向間接暫存器 (FEFh-FEBh、FE7h-FE3h、FDFh-FDBh)之一,貝丨J 一 間接讀 取將讀取OOh(設定零位元),而一間接的寫入將等效於一 NOP(STATUS位元不受影響)。 指標(FSR)暫存器之間接寫入 如果完成一間接定址操作,其中該目標位址係一 FSRnH 或FSRnL暫存器,則寫入操作將主導預遞增/遞減或後遞增/ 遞減功能。舉例來說: FSR0=FE8h (比 FSR0L位置少一) W=50h MOVWF *(++FSR0) ; (PREINCO) 將FSR0遞增一至FE9h,指向FSR0L。然後,將W寫入 FSR0L可將FSR0L改變為50h。然而, FSR0=FE9h (FSR0L的位置) W=50h MOVWF *FSR0++ ; (POSTINCO) 在要發生FSR0遞增的同時,將試圖寫入W至FSR0L。W 的寫入將勝過後遞增,並且FSR0L將為50h。 96779.doc -36- 1339354 指令集概述 本發明之指令集由77個指令組成。由於先前技術架構中 過量的頁面與儲存庫切換,需要線性化程式與資料記憶體 映射,並且修改δ玄心令集,以促進此線性化。本法明之較 佳具體實施例之資料記憶體空間具有最多達4Κ位元組,其 係由1 6個儲存庫組成,每個儲存庫有256個位元組。在本發 明的較佳具體實施例中,所有的特殊功能暫存器都位於一 儲存庫中,較佳係指定所有執行檔案操控(其可強制一虛擬 儲存庫)之指令之操作碼中的一位元。因此,不必切換儲存 0 庫來存取特殊功能暫存器。 在較佳具體實施例中,於先前技術系統的基礎上將程式 S己憶體空間修改成最多達2Μ位元組。將pc&丨3位元增加到 最多21位元,並將引起跳轉的某些指令(CALL·、GOTO)改 變為二字指令,以載入用於PC的21位元值。相對於先前技 術的另一改進係包括模組化模擬器。此需要在兩個用於模 擬之曰曰片之間進行通信,並且為了達成所需的速度,不可 能在相同的指令週期内具有不同的來源與目的地暫存器。· 因此’消除先前技術中的MOVPF與MOVFP指令。為了保持 此功忐性,添加一二字指令MOVFF。 可將本發明的指令集分組成三類: •位元組導向 •位元導向 •文字與控制操作。 圖56顯示此望& 寺格式。圖54顯示操作碼的欄位說明。此等 96779.doc -37- 1339354 說明有助於瞭解圖57至59中以及附錄A中所找到的每個特 定指令說明中的操作碼。圖Π4說明指令解碼映射。 對於位元組導向的指令,,f表示一檔案暫存器指定符, 並且·(!·表示一目的地指定符。該檔案暫存器指定符指定該 指令係要使用哪個檔案暫存器。該目的地指定符指定該操 作的結果係要放到何處。如果,d,=,〇,,則將該結果放到%暫 存器中。如果’d’=,l,,則將該結果放到該指令所指定的檔案 暫存器中。 同樣,對於位元組導向的指令,,a·表示虛擬儲存庫選擇 位元。如果’a’=’〇’,則覆蓋BSR,並選擇虛擬儲存庫。如果 = ,則不覆蓋儲存庫選擇暫存器(BSR)。 對於位元導向的指令,,b,表示一位元欄位指定符其選 擇文連操作影響的位元的數目,而’ f表示該位元所在的棺 案位址。 對於文字與控制操作,,k,表示一8、12、16或20位元常數 或文字值。而且,V表示快速呼叫/返回選擇位元。如果 s-〇,陰影暫存器(sha(jow register)係未使用。如果,s,=,1 ·, 則經一 RETURN或HETFIE指令從陰影暫存器更新w、BSR 與STATUS暫存器,或經一 CALL指令從對應的暫存器載入 陰影暫存器。最後,,n,係2的補數,其決定相對分支指令之 跳轉的方向與幅度。 该指令集係高度正交的並且係被分組成: •位元組導向操作 •位元導向操作 96779.doc -38- 1339354 •文字與控制操作 在單個指令週期内執行所有指令,除非: •一條件測試為真 •因一指令而改變該程式計數器 •執行一檔案至檔案轉移 •執行一表格讀區或一表格寫入指令 在上列情況下,該執行耗用兩個指令週期,其中第二週 期作為一 NOP執行。• Automatically decrement the value (address) in the FSR after indirect access (post-decreasing). • Automatically increments the value (address) in the FSR after indirect access (post-increment). • Automatically increment the value (address) in the FSR (pre-increment) before indirect access. • The value (address) in the FSR is not changed after indirect access (no change). When using the auto-increment or auto-decrement feature, the effect on the FSR is not reflected in the STATUS register. For example, if the indirect addressing causes the FSR to be equal to '0', then the Z bit will not be set. Adding these features allows the FSR to be used to stack metrics in addition to data table operations. Index Indirect Addressing 96779.doc -35- 1339354 Each INDF has an address associated with it that performs an indirect access to an index. When a data access to this INDF location occurs, the FSR is configured to: • Add a signed value in the W scratchpad and the value in the FSR to form the address prior to indirect access. • Do not change the FSR value. Indirect Addressing (INDF) Register Interconnect Write If the FSR register contains a value, the value points to one of the indirect registers (FEFh-FEBh, FE7h-FE3h, FDFh-FDBh), and the indirect read The fetch will read OOh (set zero bit), and an indirect write will be equivalent to a NOP (the STATUS bit is unaffected). Index (FSR) Register Interconnect Write If an indirect addressing operation is completed where the target address is an FSRnH or FSRnL register, the write operation will dominate the pre-increment/decrement or post-increment/decrement function. For example: FSR0=FE8h (one less than the FSR0L position) W=50h MOVWF *(++FSR0) ; (PREINCO) Increase FSR0 by one to FE9h, pointing to FSR0L. Then, writing W to FSR0L changes FSR0L to 50h. However, FSR0=FE9h (the position of FSR0L) W=50h MOVWF *FSR0++ ; (POSTINCO) At the same time as FSR0 is incremented, an attempt is made to write W to FSR0L. W writes will be faster than post-increment and FSR0L will be 50h. 96779.doc -36- 1339354 Instruction Set Overview The instruction set of the present invention consists of 77 instructions. Due to excessive page and repository switching in prior art architectures, linearization of program and data memory mapping is required, and the δ mystery set is modified to facilitate this linearization. The data memory space of the preferred embodiment of the present invention has up to 4 bytes, which consists of 16 banks, each of which has 256 bytes. In a preferred embodiment of the present invention, all of the special function registers are located in a repository, preferably one of the opcodes of all instructions that execute file manipulation (which can force a virtual repository) Bit. Therefore, it is not necessary to switch to the storage 0 library to access the special function register. In a preferred embodiment, the program's memory space is modified to a maximum of 2 bytes on the basis of prior art systems. Increase the pc&3 bits to a maximum of 21 bits, and change some of the instructions (CALL·, GOTO) that caused the jump to a two-word instruction to load the 21-bit value for the PC. Another improvement over the prior art includes a modular simulator. This requires communication between the two slices used for the simulation, and in order to achieve the required speed, it is not possible to have different source and destination registers in the same instruction cycle. · Therefore 'eliminate the MOVPF and MOVFP instructions in the prior art. In order to maintain this power, add a two-word instruction MOVFF. The instruction set of the present invention can be grouped into three categories: • Bit tuple oriented • Bit oriented • Text and control operations. Figure 56 shows this look & temple format. Figure 54 shows the field description of the opcode. These 96779.doc -37- 1339354 instructions help to understand the opcodes in each of the specific instruction descriptions found in Figures 57 through 59 and in Appendix A. Figure 4 illustrates the instruction decode map. For a byte-oriented instruction, f denotes a file register specifier, and (!) denotes a destination specifier. The file register specifier specifies which file register to use for the instruction. The destination specifier specifies where the result of the operation is to be placed. If, d, =, 〇, then the result is placed in the % scratchpad. If 'd' =, l, then the The result is placed in the file register specified by the instruction. Similarly, for byte-oriented instructions, a· represents the virtual repository selection bit. If 'a'='〇', the BSR is overwritten and selected Virtual repository. If =, the repository select register (BSR) is not overwritten. For bit-oriented instructions, b, indicates the number of bits in a single field designator that affects the selected file operation. And 'f denotes the file address where the bit is located. For text and control operations, k means an 8-, 12, 16 or 20-bit constant or literal value. Moreover, V means fast call/return selection bit. If s-〇, the shadow register (sha (jow register) is not used. If s, =, 1 ·, the w, BSR and STATUS registers are updated from the shadow register via a RETURN or HETFIE instruction, or the shadow register is loaded from the corresponding register via a CALL instruction. ,, n, the complement of the system 2, which determines the direction and magnitude of the jump relative to the branch instruction. The instruction set is highly orthogonal and is grouped into: • a byte-oriented operation • a bit-oriented operation 96779.doc -38- 1339354 • Text and control operations execute all instructions in a single instruction cycle unless: • a conditional test is true • the program counter is changed by an instruction • a file is transferred to a file transfer • a table read area is executed or The table write instruction takes two instruction cycles in the above case, and the second cycle is executed as a NOP.
作為來源/目的地之特殊功能暫存器 本發明之正交指令集允許讀取與寫入所有的檔案暫存 器,包括特殊功能暫存器。有部分特殊情況係使用者應該 意識到的:Special Function Scratchpad as Source/Destinity The orthogonal instruction set of the present invention allows reading and writing of all file registers, including special function registers. There are some special cases that users should be aware of:
作為目的地之STATUSSTATUS as destination
如果一指令寫入至STATUS暫存器,則可作為該指令的結 果而設定或清除Z、C、DC、0V與N位元並且覆寫所寫入的 原始資料位元。If an instruction is written to the STATUS register, the Z, C, DC, 0V, and N bits can be set or cleared as a result of the instruction and the written original data bit can be overwritten.
作為來源或目的地之PCL PCL上的讀取、寫入或讀取-修改-寫入可具有下列結果: •對於一讀取PCL,首先PCU至PCLATU ;然後PCH至 PCLATH ;然後PCL至目的地。 •對於一寫入PCL,首先PCLATU至PCU ;然後PCLATH 至PCH;然後8位元結果值至PCL。 •對於一讀取-修改-寫入:首先PCL至ALU運算元,然後 PCLATH至PCH,然後PCLATU至PCU,然後8位元結果至 96779.doc 09- 1339354 PCL° 其中: PCL=程式計數器低位元組 PCH=程式計數器高位元組 PCLATH=程式計數器高保持鎖存器 PCU=程式計數器上部位元組 PCLATU=程式計數器上部保持鎖存器 dest=目的地,W或f。Read, write or read-modify-write on PCL PCL as source or destination can have the following results: • For a read PCL, first PCU to PCLATU; then PCH to PCLATH; then PCL to destination . • For a write to PCL, first PCLATU to PCU; then PCLATH to PCH; then 8-bit result value to PCL. • For a read-modify-write: first PCL to ALU operand, then PCLATH to PCH, then PCLATU to PCU, then 8-bit result to 96790.doc 09- 1339354 PCL° where: PCL=program counter low bit Group PCH=Program Counter High Bit PCLATH=Program Counter High Hold Latch PCU=Program Counter Upper Part Tuple PCLATU=Program Counter Upper Hold Latch dest=destination, W or f.
位元操控 所有的位元操控指令皆係藉由首先讀取整個暫存器、在 所選定的位元上操作以及寫回結果而完成(讀取-修改-寫入 (R-M-W))。當在某些特殊功能暫存器(例如埠)上操作時, 使用者應記住此點。應注意,係在Q1週期中設定或清除藉 由該裝置所操控的狀態位元(包括中斷旗標位元)。因此,在 包含此等位元的暫存器上執行R-M-W指令時不會有問題。Bit manipulation All bit manipulation instructions are completed by first reading the entire scratchpad, operating on the selected bit, and writing back the result (read-modify-write (R-M-W)). The user should remember this point when operating on some special function registers (such as 埠). It should be noted that status bits (including interrupt flag bits) manipulated by the device are set or cleared during the Q1 cycle. Therefore, there is no problem when executing the R-M-W instruction on the scratchpad containing these bits.
圖60至113包含本發明之指令集内各指令之一般操作之 流程圖。各圖顯示用於擷取與執行本發明之指令集内之指 令的一般化與特定步驟。例如,圖60顯示用於擷取位元組 導向檔案暫存器操作之步驟,其包含指令ADDWF、 ADDWFC、ANDWF、COMF、DECF、INCF、IORWF、MOVF、 RLCF、RLNCF、RRCF、RRNCF、SUBFWB、SUBWF、 SUBWFB、SWAPF、XORWF、MOVWF與 NOP。同樣,圖 61顯示用於執行位元組導向檔案暫存器操作之步驟,其包 含指令 ADD WF、ADD WFC、AND WF、COME、DECF、INCF、 96779.doc -40- 1339354 IORWF、MOVF、RLCF、RLNCF、RRCF、RRNCF、SUBFWB、 SUBWF、SUBWFB、SWAPF與 XORWF(但 MOVWF只進行一 虛設讀取,並且NOP進行一虛設讀取與一虛設寫入)<» 圖77顯示文字操作之擷取步驟,其包括指令ADDLW、 ANDLW、IORLW、MOVLW、SUBLW與 XORLW。如前,圖 78顯示文字操作之執行步驟,其包括指令ADDLW、 ANDLW、IORLW、MOVLW、SUBLW與 XORLW。Figures 60 through 113 contain a flow chart of the general operation of the instructions within the instruction set of the present invention. The figures show the generalization and specific steps of the instructions in the instruction set for capturing and executing the invention. For example, FIG. 60 shows the steps for extracting a byte-oriented archive register operation, including instructions ADDWF, ADDWFC, ANDWF, COMF, DECF, INCF, IORWF, MOVF, RLCF, RLNCF, RRCF, RRNCF, SUBFWB, SUBWF, SUBWFB, SWAPF, XORWF, MOVWF and NOP. Similarly, Figure 61 shows the steps for performing a byte-oriented archive register operation, including the instructions ADD WF, ADD WFC, AND WF, COME, DECF, INCF, 96779.doc -40-1339354 IORWF, MOVF, RLCF , RNLCF, RRCF, RRNCF, SUBFWB, SUBWF, SUBWFB, SWAPF and XORWF (but MOVWF only performs a dummy read, and the NOP performs a dummy read and a dummy write) <» Figure 77 shows the capture of the text operation The steps include instructions ADDLW, ANDLW, IORLW, MOVLW, SUBLW, and XORLW. As before, Figure 78 shows the execution steps of the text operation, including the instructions ADDLW, ANDLW, IORLW, MOVLW, SUBLW, and XORLW.
圖90顯示擷取分支操作之流程圖,其包括指令BC、BN、 BNC、BNN、BNV、BNZ、BV與BZ。同樣,圖90顯示執行 分支操作之流程圖,其包括指令BC、BN、BNC、BNN、BNV、 BNZ、BV與BZ。其餘圖式顯示擷取與執行指令集中其他指 令的步驟。Figure 90 shows a flow chart of the branching operation including instructions BC, BN, BNC, BNN, BNV, BNZ, BV and BZ. Similarly, Figure 90 shows a flow chart for performing a branch operation including instructions BC, BN, BNC, BNN, BNV, BNZ, BV, and BZ. The remaining diagrams show the steps to retrieve and execute other instructions in the instruction set.
對於需要兩次擷取來獲得完整指令的多字指令而言,使 用三個流程圊來說明整個擷取與執行程序。例如,圖70至 72說明MOVFF指令。圖70顯示一相對較標準的擷取操作》 然而,圖7 1顯示操作框左側MOVFF第一部分的執行,而操 作框右邊部分則顯示指令之第二字元的擷取。因此,圖72 僅顯示MOVFF指令之第二字元之執行步驟。針對其他多字 指令提供類似的流程圖:LFSR (圖79至81) ; GOTO(圖102 至 104); CALL(圖 105至 107); TBLRD*、TBLRD* +、TBLRD*-與 TBLRD + *(圖 108 至 110) ; TBLWT*、TBLWT*+、TBLWT*-與 TBLWT+*(圖 111 至 113)。 附錄A包含本發明之指令集之操作碼與指令之詳細列 表&基於所有目的以引用方式併入附錄A中之材料。 96779.doc 1339354 内容。 將IR中所包含的資料視為一無符號整數,並且不將結果 儲存於FSR2中。有四種定址模式: •間接(INDF); •具有增量/減量(FSR2 + )、(+FSR2)與(FSR2-)之間接模 式; •具有偏移之間接模式(FSR2 + W,其中W的内容係用於 偏移);以及For multi-word instructions that require two captures to get a complete instruction, three flow blocks are used to illustrate the entire capture and execution process. For example, Figures 70 through 72 illustrate the MOVFF instruction. Figure 70 shows a relatively standard capture operation. However, Figure 71 shows the execution of the first part of the MOVFF on the left side of the operation box, while the right part of the operation block shows the capture of the second character of the instruction. Thus, Figure 72 shows only the execution steps of the second character of the MOVFF instruction. A similar flow chart is provided for other multi-word instructions: LFSR (Figures 79 to 81); GOTO (Figures 102 to 104); CALL (Figures 105 to 107); TBLRD*, TBLRD* +, TBLRD*- and TBLRD + *( Figures 108 to 110); TBLWT*, TBLWT*+, TBLWT*- and TBLWT+* (Figures 111 to 113). Appendix A contains a detailed list of opcodes and instructions for the instruction set of the present invention & the material incorporated in Appendix A by reference for all purposes. 96779.doc 1339354 Content. The data contained in the IR is treated as an unsigned integer and the result is not stored in FSR2. There are four addressing modes: • Indirect (INDF); • Incremental/Decrement (FSR2 + ), (+FSR2) and (FSR2-) Interconnect modes; • Offset Interconnect mode (FSR2 + W, where W Content is used for offset);
•具有文字偏移之間接模式(FSR2+文字)。 本發明包括一指令集,當調用該指令集時,其在微控器 上執行一或多個任務。以下說明數個指令。在特殊的情況 下,可藉由,例如,一開關或其他等效的措施來調用此等 指令。• Has a text offset connection mode (FSR2+ text). The present invention includes an instruction set that, when invoked, executes one or more tasks on the microcontroller. The following describes several instructions. In special cases, such instructions may be invoked by, for example, a switch or other equivalent measure.
「PUSHL」指令將一 8位元文字值推入至該堆疊上。 PUSHL指令的實際語法係「PUSHL k」,其中0 <= k <= 225。 該命令的調用不會影響微控器的狀態。PUSHL指令的編碼 係「1110 1010 kkkk kkkk」,其中8位元文字係藉由該指令 的kkkk kkkk部分來指定。此處,將該8位元文字複製至第 二檔案選擇暫存器(「FSR2」)正在定址的位置,並使FSR2 遞減。 「SUBFSR」指令從一檔案選擇暫存器(「FSR」)減去一 5 位元文字。該命令的語法係「SUBFSR f, k」,其中0 <= f <= 2與0 <= k < = 63。該命令的調用不會影響微控器的狀態。該 命令的編碼係「111 0 1 001 ffkk kkkk」,當被調用時,其從 96779.doc -43 - 1339354 FSRf減去6位元(無符號)文字,並將結果儲存回FSRf,其中 該指令的「ff」部分指定特定的檔案選擇暫存器,並且該指 令的「kk kkkk」部分指定文字。 「SUBULNK」指令從第二檔案選擇暫存器(「FSR2」) 減去一 5位元文字,並將所得到的值返回。該命令的語法係 「SUBULNK k」,其中0<=k<= 63。該命令的調用不會影 響微控器的狀態。該命令的編碼係「1110 1001 llkk kkkk」, 當被調用時,其從FSR2減去6位元(無符號)文字,將結果儲 存回FSR2,並將該結果與該執行返回到呼叫器。 「ADDFSR」指令將一 5位元文字添加至一 FSR。該指令 的語法係「ADDFSR f,k」,其中 0 <= f <= 2與 0 <= k <= 63。 微控器的狀態不受此指令的影響。該指令的編碼係「1110 1000 ffkk kkkk」,當被調用時,其將6位元(無符號)文字添 加至從FSRf,並將所得到的值儲存回FSRf,其中該指令的 「ff」部分指定特定的檔案選擇暫存器,並且該指令的「kk kkkk」部分指定文字。 「ADDULNK」指令將一 5位元文字添加至FSR2,並且將 該結果與該執行返回呼叫常式。該指令的語法係 「ADDULNK k」,其中0 <= k <= 63。該指令的調用不會影 響微控器的狀態。該指令的編碼係「111 〇 1 〇〇〇 11 kk kkkk」, 其中當調用時,將一 6位元(無符號)文字(其係由該指令的 「kk kkkk」部分指定)添加至FSR2,並將該結果儲存回 FSR2,並將執行返回至呼叫器。 「MOVSF」指令將一堆疊位置儲存至通用暫存器 96779.doc 1339354 (「GPR」)。該指令的語法係「MOVSF s,d」,其中〇 <= s <= 127與0 <= d <== 4095。該指令的調用不會影響微控5|的狀 態。該指令的編碼係在二字中,其中Word 1係「111 〇丨〇丄iThe "PUSHL" command pushes an 8-bit literal value onto the stack. The actual grammar of the PUSHL instruction is "PUSHL k", where 0 <= k <= 225. The call to this command does not affect the state of the microcontroller. The code of the PUSHL instruction is "1110 1010 kkkk kkkk", in which the 8-bit text is specified by the kkkk kkkk part of the instruction. Here, the 8-bit text is copied to the location where the second file selection register ("FSR2") is being addressed, and FSR2 is decremented. The "SUBFSR" command subtracts a 5-digit literal from a file selection register ("FSR"). The syntax of this command is "SUBFSR f, k", where 0 <= f <= 2 and 0 <= k < = 63. The call to this command does not affect the state of the microcontroller. The code of the command is "111 0 1 001 ffkk kkkk". When called, it subtracts 6-bit (unsigned) text from 96790.doc -43 - 1339354 FSRf and stores the result back to FSRf, where the command The "ff" part specifies a specific file selection register, and the "kk kkkk" part of the instruction specifies the text. The "SUBULNK" command subtracts a 5-digit literal from the second file selection register ("FSR2") and returns the resulting value. The syntax of this command is "SUBULNK k", where 0 <=k<= 63. The call to this command does not affect the state of the microcontroller. The command is encoded as "1110 1001 llkk kkkk", when called, it subtracts 6-bit (unsigned) text from FSR2, stores the result back into FSR2, and returns the result to the caller with the execution. The "ADDFSR" instruction adds a 5-digit literal to an FSR. The syntax of this instruction is "ADDFSR f,k", where 0 <= f <= 2 and 0 <= k <= 63. The state of the microcontroller is not affected by this instruction. The code of the instruction is "1110 1000 ffkk kkkk". When called, it adds 6-bit (unsigned) text to the slave FSRf and stores the resulting value back into FSRf, where the "ff" part of the instruction Specify a specific file selection register, and the "kk kkkk" part of the instruction specifies the text. The "ADDULNK" instruction adds a 5-digit literal to FSR2 and returns the result to the call return routine. The syntax of this instruction is "ADDULNK k", where 0 <= k <= 63. The call to this instruction does not affect the state of the microcontroller. The code of the instruction is "111 〇1 〇〇〇11 kk kkkk", where when invoked, a 6-bit (unsigned) text (which is specified by the "kk kkkk" portion of the instruction) is added to FSR2. The result is stored back to FSR2 and execution is returned to the pager. The "MOVSF" instruction stores a stack location to the general purpose register 96779.doc 1339354 ("GPR"). The syntax of this instruction is "MOVSF s,d", where 〇 <= s <= 127 and 0 <= d <== 4095. The call of this instruction does not affect the state of the microcontroller 5|. The code of the instruction is in the two words, where Word 1 is "111 〇丨〇丄i
Osss ssss」’並且 Word 2係「1111 dddd dddd dddd」,並且其 中該指令之第一字元的「sss ssss」部分指定一來源,而該 第二字元的「dddd dddd dddd」部分指定目的地。調用該指 令時’將7位元文字值添加至FSR2中的值,得到一 8位元值 之源位址’隨後會將該源位址複製至由12位元值d所指定的 一位置》FSR2值不受MOVSF指令的影響,微控器的狀態也 不受影響。 「MOVSS」指令將一堆疊位置複製至另一堆疊位置β該 指令的語法係「MOVSS s,d」,其中0 <= s <= 127與〇 <= d <= 127。該指令的調用不會影響微控器的狀態。該指令的編碼 係在二字中’其中Word 1係「1110 l〇n lsss ssss」,並且 Word 2係「1111 χχχχ xddd dddd」,並且其中該指令之第一 字元的「sss ssss」部分指定一來源,而該第二字元的「ddd dddd」部分指定目的地。調用該指令時,將7位元文字值添 加至FSR2中的值,得到一 8位元值之源位址’隨後會將該源 位址複製至由一位址(該位址係藉由將該7位元值添加至 FSR2中的值而決定)所指定的一位置。fs‘R2值不受M〇vss 指令的影響,微控器的狀態也不受影響。 「CALLW」指令係一間接的呼叫。該指令的語法係 「CALLW」。該指令的調用不會影響微控器的狀態。該命 令的编碼係「〇〇〇〇 〇〇〇〇 〇〇〇 1 〇 1 〇〇」,當調用該指令時’將 96779.doc -45- 1339354 下—指令的位址推到該硬體堆疊上。明確言之,將來自第 一暫存器(例如PCLATU:PCLATH)的值複製至程式計數器 「pc」)較高的16位元令,並將第二暫存器(例如w暫存器 「WREGj ))中的值複製至PC較低的8位元。Osss ssss"' and Word 2 is "1111 dddd dddd dddd", and the "sss ssss" part of the first character of the instruction specifies a source, and the "dddd dddd dddd" part of the second character specifies the destination . When the instruction is called, 'add the 7-bit literal value to the value in FSR2 to get the source address of an 8-bit value' and then copy the source address to a position specified by the 12-bit value d. The FSR2 value is not affected by the MOVSF instruction and the state of the microcontroller is not affected. The "MOVSS" instruction copies a stack position to another stack position. The syntax of the instruction is "MOVSS s,d", where 0 <= s <= 127 and 〇 <= d <= 127. The call to this instruction does not affect the state of the microcontroller. The encoding of the instruction is in the two words 'where Word 1 is "1110 l〇n lsss ssss", and Word 2 is "1111 χχχχ xddd dddd", and the "sss ssss" part of the first character of the instruction is specified A source, and the "ddd dddd" portion of the second character specifies the destination. When the instruction is invoked, a 7-bit literal value is added to the value in FSR2 to obtain a source address of an 8-bit value. The source address is then copied to the address by the address (the address is The 7-bit value is added to the value in FSR2 to determine the location specified. The fs‘R2 value is not affected by the M〇vss instruction and the state of the microcontroller is not affected. The "CALLW" command is an indirect call. The syntax of this command is "CALLW". The call to this instruction does not affect the state of the microcontroller. The code of this command is "〇〇〇〇〇〇〇〇〇〇〇1 〇1 〇〇", when the instruction is called, 'push the address of the instruction 96796.doc -45-1339354 to the hardware On the stack. Specifically, copy the value from the first scratchpad (eg PCLATU: PCLATH) to the higher 16-bit command of the program counter "pc" and the second register (eg w register "WREGj" The value in )) is copied to the lower 8-bit of the PC.
本發明因而充分地適於實行該目的,並獲得上述之目的 與優點,以及其他在此所固有者。雖然已參照本發明示範 性具體實施例來說明與定義本發明,但此類參照並不代表 本發明的限制,也不可推論此類限制。誠如熟悉—般相關 技術者所知,本發明可以修正、變更與貝有相當的型式及 功能。本發明所描述並說明的具體實施例僅用於示範說 明,而非詳盡說明本發明範圍。因此,本發明僅藉由附加 之申請專利範圍的精神與範圍而予以限制,並在各方面給 予同等物完全的認可。 【圖式簡單說明】 圖1係先前技術之中型微控器單元之示意方塊圖 圖2係先前技術Harvard架構之示意方塊圖; 圖3係先蚋技術v〇n Neumann架構之示意方塊圖 圖4係先前技術之時脈/指令週期之時序圖; 圖5係執行多重指令之示意圖; 圖6係本發明之微控器核心之示意方塊圖; 圖7為本發明q週期活動的時序圖; 圖8為本發明之時脈/指令週期的時序圖; 圖9係本發明之指令管線流程圖; 圖10係本發明之指令管線流程圖; 96779.doc -46 - 1339354 圖11係本發明之指令管線流程圖; 圖12係本發明之指令管線流程圖; 圖13係本發明之指令管線流程圖; 圖14係本發明之指令管線流程圖; 圖15係本發明之狀態暫存器之方塊圖; 圖16係本發明之程式計數器之方塊圖; 之方 圖Π係使用CALl^G〇T〇指令之本發明程式計數言 塊圖; 圖18係本發明之堆疊指標暫存器之方塊圖; 圖19係本發明之堆疊頂部上部暫存器之方塊圖; 圖20係本發明之堆疊頂部高暫存器之方塊圖; 圖21係本發明之堆疊頂部低暫存器之方塊圖; 圖2 2 s兒明本發明之堆疊重設操作; 圖23說明本發明之初始化堆疊上的第一 call ; 圖24說明本發明之堆疊上的第二連續call ; 圖25說明本發明之堆疊上第31與第32連續CALL ; 圖26說明本發明之堆疊上的一返回p〇p操作; 回取 圖2 7 5兒明一在本發明内引起堆疊下溢狀況的堆疊返 出; 圖28忒明本發明之堆疊上的一 pusf^_令,· 圖29說明本發明之堆疊上的一 ρ〇ρ指令; 圖30係本發明之程式記憶體映射與堆疊之方塊圖; 圖3 1係本發明之記憶體映射之方塊圖; 圖32係本發明之記憶體映射之方塊圖; 96779.doc -47· 1339354 圖3 3係一在不同程式模式中本發明之裝置記憶體映射之 方塊圖; 圖34係一說明本發明之MEMCON暫存器之方塊圖; 圖35係一說明本發明之C0NFIG7組態位元組之方塊圖; 圖36係本發明之16位元外部記憶體連接組態之示意方塊 圖; 圖37係本發明之8位元外部記憶體連接組態之方塊圖; 圖3 8係本發明之典型埠功能之列表; 圖39係本發明之16位元模式中外部程式記憶體匯流排之 時序圖; 圖40係本發明之8位元模式中外部程式記憶體匯流排之 時序圖; 圖41係本發明之外部匯流排週期類型之列表; 圖42係本發明之資料記憶體映射與指令「&」位元之示意 方塊圖; 圖43係本發明之特殊功能暫存器之映射; 圖44係本發明之核心特殊功能暫存器之示意圖; 圖45係圖44之核心特殊功能暫存器之延續; 圖46係本發明之直接短定址模式之示意方塊圖; 圖47係本發明之BSR操作之示意方塊圖; 圖48係本發明之獄操作在模擬/測試模式期間之示意方 塊圖; 圖49係本發明之直接強制定址模式 不思方塊圖; 圖50係本發明之直接強制定址模式之示意方塊圖; 96779.doc • 48 · 1339354 圖5 1係本發明之直接長定址模式之示意方塊圖; 圖52係本發明之間接定址模式之示意方塊圖; 圖53係本發明之間接定址模式之示意方塊圖; 圖54係本發明之說明性列表操作碼欄位; 圖55係本發明之間接定址符號之列表; 圖56說明本發明之指令之通用格式; 圖57係本發明之指令集之部分列表; 圖58係本發明之指令集之部分列表; 圖59係本發明之指令集之部分列表; 圖60係本發明之位元組導向檔案暫存器操作之流程圖; 圖61係本發明之位元組導向檔案暫存器操作(執行)之流 程圖, 圖62係本發明之CLRF、NEGF、SETF(擷取)指令的流程 圖; 圖63係本發明之CLRF、NEGF、SETF(執行)指令的流程 圖, 圖 64係,本發明之DECFSZ、DCFSNZ、INCFSZ、ICFSNZ(擷 取)指令的流程圖; 圖 65係、本 明之 DECFSZ、DCFSNZ、INCFSZ、ICFSNZ(擷 取)指令的流程圖’ 圖 66係本發明之 CPFSEQ、CPFSQT、CPFSLT與 TSTFSZ(擷 取)指令的流程圖; 圖 67係本發明之 CPFSEQ、CPFSQT、CPFSLT與 TSTFSZ(執 行)指令的流程圖; 96779.doc -49- 1339354 圖68係本發明之MULWF(擷取)指令的流程圖; 圖69係本發明之MULWF(執行)指令的流程圖; 圖70係本發明之MULFF(擷取)指令的流程圖; 圖71係本發明之MULFF(執行1)指令的流程圖; 圖72係本發明之MULFF(執行2)指令的流程圖;The invention is thus fully adapted to carry out the objects and advantages and advantages of the invention described herein. While the invention has been illustrated and described with reference to the exemplary embodiments of the present invention As is known to those skilled in the art, the present invention can be modified and modified to have a similar type and function. The specific embodiments of the invention have been described and illustrated by way of illustration Therefore, the invention is limited only by the spirit and scope of the appended claims, and the equivalents are fully recognized in all respects. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic block diagram of a prior art mid-level microcontroller unit. FIG. 2 is a schematic block diagram of a prior art Harvard architecture. FIG. 3 is a schematic block diagram of a prior art v〇n Neumann architecture. Figure 7 is a schematic diagram of the execution of multiple instructions; Figure 6 is a schematic block diagram of the core of the microcontroller of the present invention; Figure 7 is a timing diagram of the q-cycle activity of the present invention; 8 is a timing diagram of a clock/instruction cycle of the present invention; FIG. 9 is a flowchart of a command pipeline of the present invention; FIG. 10 is a flowchart of a command pipeline of the present invention; 96779.doc -46 - 1339354 FIG. 11 is an instruction of the present invention Figure 12 is a flow chart of a command pipeline of the present invention; Figure 13 is a flow chart of a command pipeline of the present invention; Figure 14 is a flow chart of a command pipeline of the present invention; Figure 15 is a block diagram of a state register of the present invention Figure 16 is a block diagram of the program counter of the present invention; the block diagram is a block diagram of the program of the present invention using the CALL^G〇T〇 instruction; Figure 18 is a block diagram of the stacked index register of the present invention; Figure 19 is the present invention Figure 20 is a block diagram of a stacked top high register of the present invention; Figure 21 is a block diagram of a stacked top low register of the present invention; Figure 23 illustrates the first call on the initialization stack of the present invention; Figure 24 illustrates the second consecutive call on the stack of the present invention; Figure 25 illustrates the 31st and 32nd consecutive CALLs on the stack of the present invention; Figure 26 illustrates a return p 〇 p operation on the stack of the present invention; the retrace Figure 275 shows the stack return of the stack underflow condition in the present invention; Figure 28 illustrates a stack on the stack of the present invention FIG. 29 illustrates a ρ〇ρ command on the stack of the present invention; FIG. 30 is a block diagram of the program memory map and stack of the present invention; FIG. 3 is a block diagram of the memory map of the present invention. Figure 32 is a block diagram of the memory map of the present invention; 96779.doc -47· 1339354 Figure 3 is a block diagram of the device memory map of the present invention in different program modes; Figure 34 is a block diagram illustrating the present invention Block diagram of MEMCON register; Figure 35 is a diagram illustrating the present invention Figure 36 is a block diagram of a 16-bit external memory connection configuration of the present invention; Figure 37 is a block diagram of an 8-bit external memory connection configuration of the present invention; 3 is a list of typical 埠 functions of the present invention; FIG. 39 is a timing diagram of an external program memory bus in the 16-bit mode of the present invention; FIG. 40 is an external program memory bus in the octet mode of the present invention. Figure 41 is a list of external bus cycle types of the present invention; Figure 42 is a schematic block diagram of the data memory mapping and instruction "&" bits of the present invention; Figure 43 is a special function of the present invention. Figure 44 is a schematic diagram of the core special function register of the present invention; Figure 45 is a continuation of the core special function register of Figure 44; Figure 46 is a schematic block diagram of the direct short addressing mode of the present invention; Figure 47 is a schematic block diagram of the BSR operation of the present invention; Figure 48 is a schematic block diagram of the prison operation of the present invention during the simulation/test mode; Figure 49 is a block diagram of the direct strong addressing mode of the present invention; This hair Schematic block diagram of the direct strong addressing mode; 96779.doc • 48 · 1339354 Figure 5 1 is a schematic block diagram of the direct long addressing mode of the present invention; Figure 52 is a schematic block diagram of the interfacing mode of the present invention; Figure 45 is a schematic block diagram of the present invention; Figure 55 is a list of addressable symbols in the present invention; Figure 56 is a general format of the instructions of the present invention; Figure 58 is a partial list of the instruction set of the present invention; Figure 59 is a partial list of the instruction set of the present invention; Figure 60 is a bit group oriented file register operation of the present invention. Figure 61 is a flow chart of the operation (execution) of the byte-oriented file register of the present invention, and Figure 62 is a flow chart of the CLRF, NEGF, SETF (read) instructions of the present invention; Figure 63 is the present invention Flowchart of CLRF, NEGF, SETF (execution) instructions, Fig. 64 is a flow chart of DECFSZ, DCFSNZ, INCFSZ, ICFSNZ (draw) instructions of the present invention; Fig. 65 is a DECFSZ, DCFSNZ, INCFSZ, I of the present invention. <Desc/Clms Page number> Flowchart; 96779.doc -49- 1339354 Figure 68 is a flow chart of the MULWF (Draw) instruction of the present invention; Figure 69 is a flow chart of the MULWF (Execution) instruction of the present invention; Figure 70 is a MULFF of the present invention (撷Figure 71 is a flow chart of the MULFF (Execution 1) instruction of the present invention; Figure 72 is a flow chart of the MULFF (Execution 2) instruction of the present invention;
圖73係本發明之BCF、BSF、BTG(擷取)指令的流程圖; 圖74係本發明之BCF、BSF、BTG(擷取)指令的流程圖; 圖75係本發明之BTFSC與BTFSS(擷取)指令的流程圖; 圖76係本發明之BTFSC與BTFSS(執行)指令的流程圖; 圖77係本發明之文字操作(擷取)的流程圖; 圖78係本發明之文字操作(執行)的流程圖; 圖79係本發明之LFSR(擷取)指令的流程圖; 圖80係本發明之LFSR(執行1)指令的流程圖; 圖81係本發明之LFSR(執行2)指令的流程圖; 圖82係本發明之DAW(擷取)指令的流程圖;Figure 73 is a flow chart of the BCF, BSF, BTG (draw) instructions of the present invention; Figure 74 is a flow chart of the BCF, BSF, BTG (draw) instructions of the present invention; Figure 75 is a BTFSC and BTFSS of the present invention (Fig. Figure 76 is a flow chart of the BTFSC and BTFSS (execution) instructions of the present invention; Figure 77 is a flow chart of the text operation (capture) of the present invention; Figure 78 is a text operation of the present invention ( Figure 79 is a flow chart of the LFSR (Extraction) instruction of the present invention; Figure 80 is a flow chart of the LFSR (Execution 1) instruction of the present invention; and Figure 81 is an LFSR (Execution 2) instruction of the present invention. Figure 82 is a flow chart of the DAW (draw) instruction of the present invention;
圖83係本發明之DAW(執行)指令的流程圖; 圖84係本發明之MULLW(擷取)指令的流程圖; 圖85係本發明之MULLW(執行)指令的流程圖; 圖86係本發明之CLRWDT、HALT' RESET與SLEEP(擷取) 指令的流程圖; 圖 87係、本 |务明之 CLRWDT、HALT、RESET與 SLEEP(執 ^亍) 指令的流程圖; 圖88係本發明之MOVELB(擷取)指令的流程圖; 圖89係本發明之MOVLB(執行)指令的流程圖; 96779.doc -50- 1339354 圖90係本發明之分支操作(擷取)的流程圖; 圖91係本發明之分支操作(執行)的流程圖; 圖92係本發明之BRA與RCALL(擷取)指令的流程圖; 圖93係本發明之BRA與RCALL(執行)指令的流程圖; 圖94係本發明之PUSH(擷取)指令的流程圖; 圖95係本發明之PUSH(執行)指令的流程圖; 圖96係本發明之POP(擷取)指令的流程圖; 圖97係本發明之POP(執行)指令的流程圖; 圖98係本發明之RETURN與RETFIE(擷取)指令的流程 圖; 圖99係本發明之RETURN與RETFIE(執行)指令的流程 圖; 圖100係本發明之RETLW(擷取)指令的流程圖; 圖101係本發明之RETLW(執行)指令的流程圖; 圖102係本發明之GOTO(擷取)指令的流程圖; 圖103係本發明之GOTO(執行1)指令的流程圖; 圖104係本發明之GOTO(執行2)指令的流程圖; 圖105係本發明之CALL(擷取)指令的流程圖; 圖106係本發明之CALL(執行1)指令的流程圖; 圖107係本發明之CALL(執行2)指令的流程圖; 圖 108 係,本發明之 TBLRD*、TBLRD*+、TBLRD*·與 TBLRD + *(擷取)指令的流程圖; 圖 109 係本發明之 TBLRD*、TBLRD*+、TBLRD*-與 TBLRD + *(執行1)指令的流程圖; 96779.doc -51 · 1339354 圖 110 係本發明之 TBLRD*、TBLRD*+、TBLRD*-與 TBLRD + *(執行2)指令的流程圖; 圖 111 係本發明之 TBLWT*、TBLWT*+、TBLWT*-與 TBLWT+*(擷取)指令的流程圖; 圖 112 係本明之 TBLWT*、TBLWT*+、TBLWT*-與 TBLWT+*(執行)指令的流程圖; 圖 113 係、本發明之 TBLWT*、TBLWT*+、TBLWT*-與 TBLWT+*(執行2)指令的流程圖; 圖Π 4係本發明之指令解碼映射; 圖115係根據本發明原理之交替分頁方案之方塊圖。 圖11 6係根據本發明原理之交替分頁方案之方塊圖。 【主要元件符號說明】 22 資料記憶體Figure 83 is a flow chart of the DAW (execution) instruction of the present invention; Figure 84 is a flow chart of the MULLW (execution) instruction of the present invention; Figure 85 is a flow chart of the MULLW (execution) instruction of the present invention; Flowchart of the CLRWDT, HALT' RESET and SLEEP (intake) instructions of the invention; Figure 87 is a flow chart of the CLRWDT, HALT, RESET and SLEEP (execution) instructions; Figure 88 is the MOVELB of the present invention. Figure 30 is a flow chart of the MOVLB (execution) instruction of the present invention; 96779.doc -50-1339354 Figure 90 is a flow chart of the branch operation (taken) of the present invention; Flowchart of the branch operation (execution) of the present invention; Fig. 92 is a flowchart of the BRA and RCALL instructions of the present invention; Fig. 93 is a flowchart of the BRA and RCALL (execution) instructions of the present invention; FIG. 95 is a flowchart of a PUSH (execution) instruction of the present invention; FIG. 96 is a flowchart of a POP (Capture) instruction of the present invention; FIG. 97 is a flowchart of the present invention. Flowchart of POP (execution) instruction; Figure 98 is a RETURN and RETFIE (read) instruction of the present invention Figure 99 is a flow chart of the RETURN and RETFIE (execute) instructions of the present invention; Figure 100 is a flow chart of the RETLW (execution) instruction of the present invention; and Figure 101 is a flow chart of the RETLW (execution) instruction of the present invention. Figure 102 is a flow chart of a GOTO (Extract) instruction of the present invention; Figure 103 is a flow chart of a GOTO (Execution 1) instruction of the present invention; Figure 104 is a flow chart of a GOTO (Execution 2) instruction of the present invention; 105 is a flowchart of a CALL instruction of the present invention; FIG. 106 is a flowchart of a CALL (execution 1) instruction of the present invention; FIG. 107 is a flowchart of a CALL (execution 2) instruction of the present invention; Flowchart of the TBLRD*, TBLRD*+, TBLRD*· and TBLRD + * (take) instructions of the present invention; FIG. 109 is a TBLRD*, TBLRD*+, TBLRD*- and TBLRD+* of the present invention (execution 1 Flowchart of the instruction; 96779.doc -51 · 1339354 Figure 110 is a flow chart of the TBLRD*, TBLRD*+, TBLRD*- and TBLRD + * (execution 2) instructions of the present invention; Figure 111 is a TBLWT* of the present invention , TBLWT*+, TBLWT*- and TBLWT+* (draw) instructions flow chart; Figure 112 is the TBLWT*, TBLWT*+, TBLWT*- and TBLWT+ Flowchart of the (execution) instruction; Figure 113 is a flow chart of the TBLWT*, TBLWT*+, TBLWT*- and TBLWT+* (execution 2) instructions of the present invention; Figure 4 is an instruction decoding map of the present invention; 115 is a block diagram of an alternate paging scheme in accordance with the principles of the present invention. Figure 11 is a block diagram of an alternate paging scheme in accordance with the principles of the present invention. [Main component symbol description] 22 Data memory
24 CPU 26 程式記憶體24 CPU 26 program memory
34 CPU 36 資料與程式記憶體 100 微控器核心 102 位址鎖存器 104 資料記憶體 106 資料鎖存益 108 選擇電路 110 儲存庫 112 解碼器 96779.doc -52- 133935434 CPU 36 Data and Program Memory 100 Microcontroller Core 102 Address Latches 104 Data Memory 106 Data Latching Benefits 108 Select Circuitry 110 Repository 112 Decoder 96779.doc -52- 1339354
118 儲存庫選擇暫存器 120 FSR 121 FSR 122 FSR 124 表格鎖存器 126 IR鎖存器 128 乘積暫存器 134 硬體乘法器 136 工作(W)暫存器 140 算術與邏輯單元(ALU) 142 算術與邏輯單元(ALU) 144 指令解碼器 148 表格指標 152 ROM鎖存器 154 系統匯:流排 158 資料鎖存器 160 資料或程式記憶體 162 位址鎖存器 168 程式計數器(PC) 170 堆疊 172 堆疊指標 174 資料匯流排 176 PCLATU 178 PCLATH 96779.doc -53- 1339354118 Repository Select Scratchpad 120 FSR 121 FSR 122 FSR 124 Table Latch 126 IR Latch 128 Product Scratchpad 134 Hardware Multiplier 136 Operation (W) Scratchpad 140 Arithmetic and Logic Unit (ALU) 142 Arithmetic and Logic Unit (ALU) 144 Instruction Decoder 148 Table Indicator 152 ROM Latch 154 System Spool: Bank 158 Data Latch 160 Data or Program Memory 162 Address Latch 168 Program Counter (PC) 170 Stack 172 Stacking Indicators 174 Data Bus 176 PCLATU 178 PCLATH 96779.doc -53- 1339354
180 PCU 182 PCH 184 PCL180 PCU 182 PCH 184 PCL
96779.doc •54·96779.doc •54·
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US51391003P | 2003-10-23 | 2003-10-23 | |
US10/796,771 US7203818B2 (en) | 1999-03-26 | 2004-03-09 | Microcontroller instruction set |
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US8327379B2 (en) * | 2006-08-24 | 2012-12-04 | Kernelon Silicon Inc. | Method for switching a selected task to be executed according with an output from task selecting circuit |
US7996651B2 (en) * | 2007-11-30 | 2011-08-09 | Microchip Technology Incorporated | Enhanced microprocessor or microcontroller |
US8793426B2 (en) * | 2009-02-11 | 2014-07-29 | Microchip Technology Incorporated | Microcontroller with linear memory access in a banked memory |
US9747105B2 (en) | 2009-12-17 | 2017-08-29 | Intel Corporation | Method and apparatus for performing a shift and exclusive or operation in a single instruction |
KR102514717B1 (en) * | 2016-10-24 | 2023-03-27 | 삼성전자주식회사 | Memory controller and memory system including the same |
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