1338788 九、發明說明： 【發明所屬之技術領域】 一種SAS通道之測試裝置及其測試方法，尤指一種使用 PCI-E通道測试SAS通道之橋接裝置及其測試方法。 【先前技術】 SAS(Se「ial Attached SCSI)介面是新一代的 scs丨(Sma丨丨 Computer Small Interface，SCSI)介面。SAS 是由並行 scs丨介面 • (Para丨丨scsi)之後所開發出的全新介面。因此SAS介面可以提 供多點介接、並且資料可以6Gb/s速度雙向傳輸。此外，SAS介 面透過縮小連接線的設計，而有減少系統内部空間的優點，而且 SAS介面還可向下相容，例如SATA(Se「ja| ATA)硬碟。 SAS通道是利用低電壓差分信號(L〇w D咐沉的從1338788 IX. Description of the invention: [Technical field of invention] A test device for SAS channel and a test method thereof, in particular, a bridge device for testing a SAS channel using a PCI-E channel and a test method thereof. [Prior Art] The SAS (Se "ial Attached SCSI" interface is a new generation of scs丨 (Sma丨丨Computer Small Interface, SCSI) interface. SAS was developed by the parallel scs丨 interface (Para丨丨scsi). The new interface, so the SAS interface can provide multi-point interface, and the data can be transmitted bidirectionally at 6Gb/s speed. In addition, the SAS interface has the advantage of reducing the internal space of the system by reducing the design of the connection line, and the SAS interface can also be down. Compatible, such as SATA (Se "ja| ATA" hard disk. SAS channel is using low voltage differential signal (L〇w D sinking from
Si_’ LVDS)進行資料傳輸’根據SAS的規範每對差分線路分別 _具有TX +、TX ·、RX +與RX -。在每對差分線路上可以採用 1.5GbPS和3.0GbpS的資料傳輸速率。其中，SAS通道所使用的 傳接收電壓分別TX為8〇〇〜16〇〇mV、Rx為〜伽。 月 > 考第1a圖」所示，其係為習知之飼服器與硬碟 連。示，。圖S知的SASif道測試方法是將控制端11〇透過SAS 貪板120與SAS硬碟130相連結，檢測程式對SAS硬碟13〇存 取操作if過對SAS硬碟130的讀寫，藉以測試SAS通道是否 口年存取其中，SAS背板120上分別具有複數對SAS接 7 Γ338788 口 121 ’分別將SAS硬碟13〇連結至SAS接口⑵。請參考厂第 化圖」所示’其係為習知撕通道之檢測流程圖。首月先，剌 ，試用SAS硬碟安裝至SAS雜_ sm)。接下來，啟動系 統的測試程式（步驟S12G)。測試程式對SAS硬碟進行存取操作 (步驟S13G)待观統接收SAS硬碟的存取測試報告 S140)〇 彳由於SAS貪板120中可以具有8〜16個SAS接口 121， 其中步驟S110需要用人工作業的方式來更換SAS背板12〇和 SAS硬碟130，所以在拆/裝等量的SAS硬碟130就得耗費許多 時間此外，系統重新啟動的話也需要額外的時間，如此一來整 體的測試咖就會隨之拉長，使得測試效率低落。 【發明内容】 鑒於以上的問題，本發明的主要目的在於提供一種sas通道 _ 之2°式裝置’應用於SAS背板所包括的複數對SAS接口，債測 斤k擇的該對SAS通道於傳輸資料較否發送及接收到的信號是 否一致。 為達上述目的，本發明所揭露之SAS通道之測試裝置，其包 ，t有$控制端、PCI七微處理器、PCI-E對SAS轉接板、信號回 理L且控制端用以選擇SAS通道及發送控制命令。PC丨-E微處 押Γ電11連捿於控制端與pci-E通道，ρα·Ε微處理n用以接收 1端之控制命令’ Ρα_Ε微處理n根據控制命令發出測試信號 1338788 PCI E通道。PCI’E對SAS轉接板電性連結於pC卜E通道與 #板PCI-E對SAS轉接板用以轉換pci_E通道與SAS通 道之間的傳輸信號。SAS背板中更包括複數對的SAS接口，每對 的SAS接口各分別電性連接一個信號回送模組。 ，將SAS背板中的第_SAS接口與第二撕接口透過信號回 达模組電性連結，使得第—^接口將接__試信號輸出至 第一 SAS接口 ’第一 SAS接口將所接收到的測試信號在回傳至 # PCLE微處理器。 從本發明的另一觀點，本發明提出-種SAS通道之測試方 法’其包括下列步驟：提供Ρα-E對SAS轉接板，用以連接PC|-E 通道與SAS背板。提供信號回送模組，係電性連接於SAS背板， 信號回送模組用以連結SAS背板中之第一 SAS接口與第二撕 接口。PCI_E微處理器發送測試信號，測試信號分別經由ρα·Ε 通道、PCI-E對SAS轉接板傳送至第一 SAS接口。第一 SAS接 #⑽測試信號輸出至第二SAS接口，第二SAS接口將測試信號 經在由Ρα，Ε對SAS轉接板、PCI七通道回傳至PC|_E微處理 器。Pd-Ε微處理器比對發送至第一 SAS通道的測試信號與接收 自第二SAS接口的測試信號是否一致。 本發明除了利用PCI-E作為橋接SAS通道外，另外也透過信 號回送模組將經過第- SAS接口的測試信號傳送至第二SAS接 口。接著，第二SAS接口將測試信號回傳至孤㈣處理器。由 1338788 .Ρα_Ε微處理器比對發送至第-SAS通道的測試信號與接收自第 γ二SAS接口_試信號是否-致。使縣發日种無須採用SAS 硬碟，可以節省拆裝SAS硬碟的時間，而且可以依序檢測不同 SAS通道。此外，Ρα_Ε的通道頻寬最高可以為i()gb，可以完全 支援SAS通道頻寬。 有關本發明的佩與實作，_合圖树最佳實施例詳細說 明如下。 ®【實施方式】 本發明將 PCI-E(Peripheral Component 丨nterconnect Express卩下簡稱pq_e)通道橋接至SAS通道，控制端利用收 發資料至PCI-E裝置用以測試SAS通道是否正常。pc卜e的連接 是建立在一個雙向序列的(1-bit)點對點連接基礎之上，此稱之為傳 輸通道(Lane)。PCI_E在傳送及接收數據會使用不同的傳輸通道， • 兩個PCI-E設備之f摘連接成為賴(Unk)，這形成了彳組或更多 的傳輪通道。各個設備最少支援1個傳輸通道的連結，ρα_Ε也 可以有2，4，8，16，32個通道的連結。 舉例來說，PCI-E係為16通道，換句話說就是有16個低電 壓差分偽號組，在每一組中皆有τχ +/_與RX +/_傳輸資料線， 所以故共有64條雙向傳輸資料線。就以16通道的ρα-Ε通道可 以提供16組SAS接口用以連接SAS硬碟。PCI-E若使用32各 通道時最大可以提供10GB的頻寬，而SAS通道支援的頻寬最大 1338788 可支援6GB。如此一來f>q_E可以更好的提供雙向相容性。 請參考「第2圖」所示’其係為本發明之SAS通道之檢測裝 置示意圖。本發明的SAS通道之測試裝置，其包括有：控制端 210、PCI-E 微處理器 210、PCI-E 通道 230、PCI-E 對 SAS 轉接 板240、信號回送模組260。 控制端210用以選擇SAS通道及發送控制命令。控制端21〇 可以根據不同場合應用於不同的計算機設備。例如，控制端21〇 可以是但不限於是個人電腦(PC)或伺服器(Serve「)。ρα_Ε微處理 器210電性連接於控制端21〇與pc丨·Ε通道23〇，ρ〇μΕ微處理 器210用以接收控制端210之控制命令，ρα·Ε微處理器210根 據控制命令發出測試信號至pC|_E通道230。Si_’ LVDS) performs data transmission. Depending on the SAS specification, each pair of differential lines has _TX +, TX ·, RX + and RX - respectively. Data transfer rates of 1.5 GbPS and 3.0 GbpS can be used on each pair of differential lines. Among them, the transmission receiving voltage used by the SAS channel is 8 〇〇 16 16 mV, and R x is ～ gamma. Month > Test 1a, which is a conventional feeding device and a hard disk. Show,. The SASif test method of FIG. S is to connect the control terminal 11 to the SAS hard disk 130 through the SAS board 120, and the detection program reads and writes the SAS hard disk 130 to the SAS hard disk. The SAS channel is tested for access to the SAS backplane 120. The SAS backplane 120 has a plurality of pairs of SAS connected to the Γ 338 788 port 121 ' respectively, and the SAS hard disk 13 〇 is connected to the SAS interface (2). Please refer to the factory diagram "shown" as the flow chart for the detection of the conventional tear channel. First month, first, try SAS hard disk installation to SAS _ sm). Next, the test program of the system is started (step S12G). The test program accesses the SAS hard disk (step S13G) to receive the SAS hard disk access test report S140). Since the SAS board 120 can have 8 to 16 SAS interfaces 121, step S110 needs to be performed. The SAS backplane 12A and the SAS hard disk 130 are replaced by manual operation, so it takes a lot of time to disassemble/install the same amount of SAS hard disk 130. In addition, the system needs additional time to restart, so that The overall test coffee will be lengthened, making the test inefficient. SUMMARY OF THE INVENTION In view of the above problems, the main object of the present invention is to provide a sas channel _ 2° device ' applied to a plurality of pairs of SAS interfaces included in a SAS backplane, and the pair of SAS channels selected by the UE Whether the transmitted data is consistent with whether the transmitted and received signals are consistent. In order to achieve the above object, the test device for the SAS channel disclosed by the present invention has a control terminal, a PCI seven microprocessor, a PCI-E pair SAS adapter board, a signal processing L, and a control terminal for selecting SAS channel and send control commands. The PC丨-E micro-portion 11 is connected to the control terminal and the pci-E channel, and the ρα·Ε micro-processing n is used to receive the 1-terminal control command 'Ρα_Εmicro-processing n. The test signal is issued according to the control command 1338788 PCI E channel . The PCI'E pair SAS interposer is electrically connected to the pC E channel and the # board PCI-E pair SAS interposer to convert the transmission signal between the pci_E channel and the SAS channel. The SAS backplane further includes a plurality of pairs of SAS interfaces, and each pair of SAS interfaces are electrically connected to a signal loopback module. The first _SAS interface and the second tearing interface in the SAS backplane are electrically connected through the signal returning module, so that the first-th interface outputs the __ test signal to the first SAS interface, the first SAS interface The received test signal is passed back to the #PCLE microprocessor. From another aspect of the present invention, the present invention proposes a test method for a SAS channel which includes the steps of providing a Ρα-E pair SAS interposer for connecting a PC|-E channel to a SAS backplane. The signal returning module is electrically connected to the SAS backplane, and the signal loopback module is used to connect the first SAS interface and the second tearing interface in the SAS backplane. The PCI_E microprocessor sends a test signal, and the test signal is transmitted to the first SAS interface via the ρα·Ε channel and the PCI-E to the SAS adapter board. The first SAS connects the #(10) test signal to the second SAS interface, and the second SAS interface passes the test signal to the PC|_E microprocessor via the Ρα, SSAS adapter board, and the PCI 7 channel. The Pd-Ε microprocessor compares the test signal sent to the first SAS channel with the test signal received from the second SAS interface. In addition to using the PCI-E as a bridge SAS channel, the present invention also transmits a test signal passing through the first SAS interface to the second SAS interface through the signal loopback module. The second SAS interface then passes the test signal back to the orphan processor. The test signal sent to the first-SAS channel by the 1338788 .Ρα_Ε microprocessor is compared with the received signal received from the γ nd SAS interface _ test signal. It is not necessary to use SAS hard disk for the county to send the sun, which can save the time of disassembling the SAS hard disk, and can detect different SAS channels in sequence. In addition, the channel bandwidth of Ρα_Ε can be up to i()gb, which fully supports the SAS channel bandwidth. Regarding the present invention, the preferred embodiment of the compositing tree is explained in detail below. ® [Embodiment] The present invention bridges a PCI-E (Peripheral Component 丨nterconnect Express 卩 abbreviated as pq_e) channel to a SAS channel, and the control terminal uses the transmission and reception data to the PCI-E device to test whether the SAS channel is normal. The connection of the pc is based on a two-way (1-bit) point-to-point connection, which is called a lane. PCI_E uses different transmission channels for transmitting and receiving data. • Two PCI-E devices are connected as Unk, which forms a group or more of the transmission channels. Each device supports a minimum of one transmission channel connection, and ρα_Ε can also have 2, 4, 8, 16, and 32 channels. For example, the PCI-E system is 16 channels. In other words, there are 16 low-voltage differential pseudo-number groups. In each group, there are τχ +/_ and RX +/_ transmission data lines, so there are 64 in total. A two-way transmission of data lines. The 16-channel ρα-Ε channel provides 16 sets of SAS interfaces for connecting SAS hard disks. PCI-E can provide up to 10GB of bandwidth when using 32 channels, while SAS channels support a maximum bandwidth of 1338788 to support 6GB. In this way, f>q_E can better provide bidirectional compatibility. Please refer to "Figure 2" for a description of the SAS channel detection device of the present invention. The test device for the SAS channel of the present invention comprises: a control terminal 210, a PCI-E microprocessor 210, a PCI-E channel 230, a PCI-E pair SAS transfer board 240, and a signal loopback module 260. The control terminal 210 is used to select a SAS channel and send a control command. The control terminal 21〇 can be applied to different computer devices depending on the occasion. For example, the control terminal 21〇 may be, but not limited to, a personal computer (PC) or a server (Serve “). The ρα_Ε microprocessor 210 is electrically connected to the control terminal 21〇 and the pc丨·Ε channel 23〇, ρ〇μΕ The microprocessor 210 is configured to receive a control command from the control terminal 210, and the microprocessor 210 sends a test signal to the pC|_E channel 230 according to the control command.
PCI-E對SAS轉接板240電性連結於通道230與SAS 背板250，Ρα_Ε對SAS轉接板24〇用以轉換pc| E通道23〇 與SAS通道之_傳輸信號。SAS背板25Q中更包括複數對的 SAS接口’每對的SAS接口各分別電性連接一信號回送模組 挪。信號回送模組26Q可以是但不限於卿積體減電路或跳線 線路所組成。此外’在本實施例中僅列舉SAS背板中的第一The PCI-E pair SAS adapter board 240 is electrically connected to the channel 230 and the SAS backplane 250, and the Ρα_Ε to the SAS adapter board 24 is used to convert the transmission signal of the pc|E channel 23〇 and the SAS channel. The SAS backplane 25Q further includes a plurality of pairs of SAS interfaces. Each pair of SAS interfaces are electrically connected to a signal loopback module. The signal loopback module 26Q can be, but is not limited to, a composite body subtraction circuit or a jumper line. In addition, only the first in the SAS backplane is listed in this embodiment.
SAS接口 251與第二SAS接口 252為例，並非僅只有一對SAS 接〇 〇 將信號回送模組260將SAS背板25〇中的第一SAS接口 251 與第二sAS接σ 252相互電性連接。使得第一 sas接口 251將 1338788 接收到的測試信號可以輸出至第二SAS接口 252。第二sas接 口 252再將測試信號經由pc|_E對SAS轉接板24〇、％丨七通道 ' 230回傳至PCkE微處理器210。 請參考「第3圖」所示’其係為本發明之SAS通道之檢測流 程圖。SAS通道之檢測方法，包括下列步驟：提供pc丨·e對撕 轉接板240，用以連接Pc丨.E通道23〇與撕背板25〇(步驟 S310)。提供仏號回送模組260，係電性連接於SAS背板25〇， • 信號回送模組260用以連結SAS背板25〇中之第一 SAS接口 ％1 與第-SAS接口 252(步驟S320)〇PCI-E微處理器21〇發送測試 信號’測試信號分別經由PC丨·Ε通道23〇、ρα-Ε對SAS轉接板 240傳送至第- SAS接口 251 (步驟S33〇)。第一 sas接口 251 將測試信號輸出至第二SAS接口 252，第二SAS接口脱將測 試信號經在由Ρα·Ε對SAS轉接板240、PCUE通道23()回傳至 PCI-E微處理器21〇(步驟S34Q)。ρα_Ε微處理器21()比對發送 至第- SAS if道的測試信號與接收自第二SAS接口 252的測試 信號是否一致(步驟S350)。 為能清楚制本㈣之檢測裝置讀財法，在此試以本發 明之測試裝置的詳細操作流程說明之。請參考「第4圖」所示， 其係為本發明之SAS通道之檢測裝置運作流程圖。首先，控制端 210發送控制命令至pCI_E微處理器(步驟S41〇)。pc|_E _理 器根據控齡令發制試信號至Ρα_Ε對SAS難板24〇 (步驟 12 1338788For example, the SAS interface 251 and the second SAS interface 252 are not only a pair of SAS interfaces, and the signal returning module 260 electrically connects the first SAS interface 251 and the second sAS interface 252 in the SAS backplane 25A. connection. The first sas interface 251 causes the test signal received by 1338788 to be output to the second SAS interface 252. The second sas interface 252 then passes the test signal back to the PCkE microprocessor 210 via the pc|_E pair SAS interposer board 24, % 丨 seven channels '230. Please refer to "Figure 3" for the detection flow of the SAS channel of the present invention. The method for detecting the SAS channel includes the following steps: providing a pc 丨·e pair tearing adapter plate 240 for connecting the Pc丨.E channel 23〇 and the tearing back plate 25〇 (step S310). The nickname loopback module 260 is electrically connected to the SAS backplane 25A. The signal loopback module 260 is configured to connect the first SAS interface %1 and the first-SAS interface 252 of the SAS backplane 25A (step S320). The PCI-E microprocessor 21 transmits a test signal 'test signal to the SAS interface board 251 via the PC 丨·Ε channel 23 〇, ρα-Ε, respectively (step S33 〇). The first sas interface 251 outputs a test signal to the second SAS interface 252, and the second SAS interface removes the test signal from the SAS interposer 240 and the PCUE channel 23 () to the PCI-E microprocessing by Ρα·Ε. The device 21 is (step S34Q). The ρα_Ε microprocessor 21() compares whether the test signal transmitted to the -SAS if track coincides with the test signal received from the second SAS interface 252 (step S350). In order to be able to clearly understand the reading method of the test device (4), the detailed operation flow of the test device of the present invention is explained here. Please refer to "Figure 4", which is a flow chart of the operation of the detection device of the SAS channel of the present invention. First, the control terminal 210 sends a control command to the pCI_E microprocessor (step S41). Pc|_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _
S420)。PCI-Ε對SAS轉接板240將測試信號轉換並傳送至SAS 背板250的第一 SAS接口 251 (步驟S430，步驟S410〜S430分 別對應至步驟S330)。 第一 SAS接口 251接收PCI-E對SAS轉接板240的測試信 號’並傳送至第二SAS接口 252(步驟S440)。第二SAS接口 252 接收來自於第一 SAS接口 251的測試信號，第二SAS接口 252 回傳測試信號至PCI-E對SAS轉接板240(步驟S450)。PCI-E對 $ SAS轉接板240轉換信號至PCI-E微處理器(步驟S460，步驟 S440〜S460分別對應步驟S34〇hPC|_E微處理器比對傳送前的 測試信後與接收回傳的測試信號(步驟S470 ’對應步驟S350)。控 制端210接收比對結果並生成紀錄報告(步驟S48〇)。接下來，控 制端210選擇下一對測試的SAS接口，並重複步驟S4i〇至步驟 S480直至所有SAS背板240上的每一對的SAS接口都被測試完 為止。 本發明除了利用PCI-E作為橋接SAS通道外，另外也透過信 號回送模組260將經過第一 SAS接口 251的測試信號傳送至第二 SA接口。接著，第二SAS接口 252將測試信號回傳至PCI-E微 處理器210。由PCI-E微處理器210比對發送至第一 SAS通道的 測試信號與接收自第二SAS接口 252的測試信號是否一致。使得 本發明中無須採用SAS硬碟，可以節省拆裝SAS硬碟的時間， 而且可以依序檢測不同SAS通道。因為PCI-E的通道頻寬最高可 13 1338788 以為10GB ’所以可以完全核SAS通道頻寬。 雖然本發_祕之較佳實施鋪露如上，财並非用以限 疋本發明’任何熟習相像技藝者，在賴縣發明之精神和範圍 内田可作些許之更動與潤飾，因此本發明之專利保護範圍須視 本說明書_之申請翻範_界定者為準。 【圖式簡單說明】 第1a圖係為習知之伺服器與SAS硬碟連結示意圖。 第1 b圖係為習知sas通道之檢測流程圖。 第2圖係為本發明之SAS通道之檢測裝置示意圖。 第3圖係為本發明之SAS通道之檢測流程圖。 第4圖係為本發明之SAS通道之檢測裝置運作流程圖。 【主要元件符號說明】 110 伺服器 120 SAS背板 121 SAS 接口 130 SAS硬碟 200 SAS通道之測試裝置 210 控制端 220 PCI-E微處理器 230 PCI-E通道 240 PCI-E對SAS轉接板 1338788 250 SAS背板 251 第一 SAS接口 252 第二SAS接口 260 信號回送模組S420). The PCI-Ε pair SAS interposer 240 converts and transmits the test signal to the first SAS interface 251 of the SAS backplane 250 (step S430, steps S410 to S430 correspond to step S330, respectively). The first SAS interface 251 receives the test signal ' of the PCI-E to the SAS interposer 240' and transmits it to the second SAS interface 252 (step S440). The second SAS interface 252 receives the test signal from the first SAS interface 251, and the second SAS interface 252 returns the test signal to the PCI-E pair SAS interposer 240 (step S450). The PCI-E converts the signal to the PCI-E microprocessor to the SAS adapter board 240 (step S460, and steps S440 to S460 correspond to the test signal before the transmission of the step S34〇hPC|_E, respectively). The test signal (step S470' corresponds to step S350). The control terminal 210 receives the comparison result and generates a record report (step S48A). Next, the control terminal 210 selects the next pair of tested SAS interfaces, and repeats step S4i to Step S480 until each pair of SAS interfaces on all SAS backplanes 240 are tested. In addition to using PCI-E as the bridge SAS channel, the present invention also passes through the first SAS interface 251 through the signal loopback module 260. The test signal is transmitted to the second SA interface. Next, the second SAS interface 252 transmits the test signal back to the PCI-E microprocessor 210. The test signal sent to the first SAS channel is compared by the PCI-E microprocessor 210. Whether the test signal received from the second SAS interface 252 is consistent, so that the SAS hard disk is not required in the present invention, the time for disassembling the SAS hard disk can be saved, and different SAS channels can be detected in sequence. Because of the channel frequency of the PCI-E Width up to 1 3 1338788 I thought 10GB' so I can completely verify the SAS channel bandwidth. Although the better implementation of this issue is the same as above, the money is not limited to the invention. Anyone who is familiar with the artist, the spirit and scope of the invention in Lai County Uchida can make some changes and retouching, so the scope of patent protection of this invention shall be subject to the definition of this specification. [Simplified description of the drawing] Figure 1a is a conventional server and SAS hard disk. Figure 1 b is a flow chart of the detection of the conventional SAS channel. Figure 2 is a schematic diagram of the detection device of the SAS channel of the present invention. Figure 3 is a flow chart of the detection of the SAS channel of the present invention. The figure is a flow chart of the operation of the detecting device of the SAS channel of the present invention. [Main component symbol description] 110 Server 120 SAS backplane 121 SAS interface 130 SAS hard disk 200 SAS channel test device 210 Control terminal 220 PCI-E micro processing 230 PCI-E channel 240 PCI-E pair SAS adapter board 1338788 250 SAS backplane 251 first SAS interface 252 second SAS interface 260 signal loopback module