TWI336930B - Methods for forming a bit line contact - Google Patents

Description

1336930 九、發明說明： 【發明所屬之技術領域】 本發明係㈣於—種半導體製程，且㈣有關於 避免位元線UitHne)與位元線短路（sh()n)之自方法。 【先前技術】1336930 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention is a method in which (4) a semiconductor process is performed, and (4) a method of avoiding short-circuit (sh()n) between a bit line UitHne) and a bit line. [Prior Art]

積體電路的發展技術曰新月異，其發展趨勢往功能強 大’尺寸縮小與速度純的方向前進，而動㈣機存 憶體（DRAM)的製造技術亦是如此，然 來越小’例如下降至次110·則容易因層間介電二越) 填溝能力不佳，而在ILD中產生孔洞，進而發生位元線盘 位元線短路的問題。 /、 以:將配合第〗圖說明習知之形成記憶裝置之位元線 接觸插塞（bit line contact)的中間製程剖面圖，以說明 位兀線與位元線短路之問題發生。在矽基底1〇〇中形成有 δ己憶裝置所需的半導體元件，例如電容等，不過此處為了 簡化圖式’僅以平整的基底1 〇〇表示之。基底i 〇〇具有記 憶陣列區（memory array region)及周邊電路區（pedpherai circuit region)，為了簡化說明，此處僅以記憶陣列區ι〇 作說明。 記憶陣列區10上方設置有複數個閘極結構1〇8，以供 衣作子元線之用，此處，閘極結構1 〇 8包含閘極導電芦 150以及閘極上蓋層160，其中閘極導電層15〇包括多晶 矽層130，以及用以降低電阻值之金屬矽化物層ι4〇。閘 極結構108係形成於閘極介電層12〇上，閘極結構1〇8之 側壁上形成閘極間隙壁170,在相鄰之閘極結^ ι〇8之間The development technology of integrated circuits is changing with each passing day, and its development trend is moving toward the powerful 'size reduction and speed pure direction, and the manufacturing technology of the dynamic (four) machine memory (DRAM) is the same, but the smaller the 'for example Dropping to the next 110. is easy due to the interlayer dielectric Diffusion). The filling ability is poor, and holes are generated in the ILD, and the bit line of the bit line is short-circuited. /, to: The intermediate process profile of the bit line contact forming the memory device will be described in conjunction with the figure to illustrate the occurrence of a short circuit between the bit line and the bit line. A semiconductor element such as a capacitor or the like required for the δ-resonation device is formed in the 矽 substrate 1 ,, but here, for the sake of simplicity, the figure is shown only by the flat substrate 1 。. The substrate i 〇〇 has a memory array region and a pedpherai circuit region. For the sake of simplicity of explanation, only the memory array region will be described here. A plurality of gate structures 1〇8 are disposed above the memory array region 10 for use as a sub-line. Here, the gate structure 1 〇8 includes a gate conductive reed 150 and a gate cap layer 160. The pole conductive layer 15A includes a polysilicon layer 130, and a metal telluride layer ι4〇 for reducing the resistance value. The gate structure 108 is formed on the gate dielectric layer 12, and the gate spacer 170 is formed on the sidewall of the gate structure 1〇8, between adjacent gate junctions 〇8

Client’s Docket N〇.:93079 TT^s Docket No:0548-A50821-TW/final/Ciaire 5 1336930 係二】中則具有源極/汲極區]〇5。閘極介電層】20 極卜笔Γ乳化法所形成之氧化矽層；閘極間隙壁170及閉 極上盍層】60係由氮化矽所構成。 形志閉極結構108上方及相鄰之閘極結構108之間 glass，^PSr^】】〇 ’例如硼磷矽破璃（一一咖山瞻 極έ士構⑽二曰"電層。然而，隨著線寬越小，相鄰之閘 溝妒力不Γ見比約到達4〜5 ’如此將導致介電層n〇填 r^致於介電層m中產生孔洞6〇。後續 =(圖中未緣示），並接著於位元線接觸二3 入之導線接觸插塞（圖中未緣示）°然而，填 塞產生電錯：孔洞60與其他鄰近之位元線接觸插 法。因此’目前蛋需-種改善上述缺點之半導體製造方 【發明内容】 有鑑於此，本發明之目的在盖 力不佳’而導致之位元線與位元線短二的二電：：填溝 避免位元線與位⑽短路的方法，可確保㈣=斤 根據上述，本發明提供一種 法’包括:提供-基底，依序形的製造方 閘極Client’s Docket N〇.:93079 TT^s Docket No:0548-A50821-TW/final/Ciaire 5 1336930 Series 2 has source/bungee area]〇5. Gate dielectric layer] The ruthenium oxide layer formed by the 20-electrode emulsification method; the gate spacer 170 and the closed-layer upper layer] 60 series consists of tantalum nitride. Between the shape of the closed-pole structure 108 and the adjacent gate structure 108 between the glass, ^PSr^] 〇 〇 'such as borophosphorus 矽 ( ( 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一 一However, as the line width is smaller, the adjacent sluice force does not reach a ratio of about 4 to 5 '. This will cause the dielectric layer n 〇 to form a hole 6 介 in the dielectric layer m. = (not shown in the figure), and then contact the two-input wire contact plug on the bit line (not shown). However, the plug produces an electrical error: the hole 60 is in contact with other adjacent bit lines. Therefore, 'the current egg needs to be a semiconductor manufacturer that improves the above disadvantages. [Invention] In view of the above, the object of the present invention is that the bit line and the bit line are two short: : Filling the trench to avoid the short circuit between the bit line and the bit (10), to ensure (4) = kg According to the above, the present invention provides a method comprising: providing a substrate, in order to manufacture a square gate

Client's Docket N〇.；93079 ττ s Docket No:0548-A50821-TW/fmal/Claire 6 V電層、一閘極上蓋層、一 圖案化光阻層於嗲罩慕屏 曰；土氐上；形成一 口；利用該圖索Λ 該圖案化光阻層具有-開 幕層及部二閘為遮罩，經由該開口關該罩 丨刀之泫閘極上盍層；移除該圖案 幕層及該閑極上蓋層之側壁-該罩= 形成==去除該閉極蓋上層及閉極導電層，以 么士構層，去除該間隙壁，以形成複數個閘極 隙;形成一介電層於該基底上，並填入 之間隙中，圖案化該介電層，以形成—位元線接 元成—導電層於該位元線接觸窗中，以形成位 疋線接觸插塞。 乂饥 【實施方式】 以下貫施例將伴隨著圖式說明本發明之概念，在 ^明中一’相似或相同之部分係使用相同之標號，並且^ :、中元件之形狀或厚度可擴大或縮*。需特別注意的 疋’圖中未緣示或描述之元件，可以是熟習此技藝之人士 所去:之形式’此外’當敘述一層係位於一基板或是另—層 τ此層可直接位於基板或是另一層上，或是其間 有中介層。 以下配合第2a至2h圖說明本發明實施例之位元線接 觸插塞之製造方法，其可避免位元線與位元線短路之問題 么生適用於5己憶裝置，如動態隨機存取記憶體 (dram)。首先，請參照第2a圖，提供一基底2〇〇，例 如矽晶圓，基底200包括記憶陣列區以及周邊電路區，為Client's Docket N〇.;93079 ττ s Docket No:0548-A50821-TW/fmal/Claire 6 V electric layer, a gate upper cap layer, a patterned photoresist layer on the 慕 慕 曰 曰; Using the figure, the patterned photoresist layer has a - opening layer and a second gate as a mask through which the upper gate layer of the mask is closed; the patterned layer and the idle layer are removed Side wall of the cover layer - the cover = formation = = removing the upper layer of the closed cap and the conductive layer of the closed pole, the layer is removed by a sorcerer, the spacer is removed to form a plurality of gate gaps; and a dielectric layer is formed on the substrate And filling the gap, patterning the dielectric layer to form a bit line-forming element-conducting layer in the bit line contact window to form a bit line contact plug.乂 【 【 实施 实施 实施 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下 以下Or shrink*. Components that are not specifically shown or described in the drawings may be those skilled in the art: the form 'further' when the layer is located on a substrate or another layer τ, this layer may be directly on the substrate Or on another layer, or with an intermediation layer in between. The following is a description of the manufacturing method of the bit line contact plug according to the embodiment of the present invention, which can avoid the problem that the bit line and the bit line are short-circuited, which is suitable for the 5 memory device, such as dynamic random access. Memory (dram). First, please refer to FIG. 2a to provide a substrate 2, such as a germanium wafer. The substrate 200 includes a memory array region and a peripheral circuit region.

Clienfs Docket N〇.:93079 TT's Docket No:0548-A50821.TW/fina]/Claire 7 1336930 了簡化說明，此處僅以記憶陣列區20作說明。 接著，於記憶陣列區20之基底200上依序形成閘極 介電層220、閘極導電層250、閘極上蓋層260、及罩幕 層280。在一實施例中，閘極介電層220可以是利用熱氧 化法所形成之氧化矽層；閘極導電層250可包括如多晶矽 層230、以及用以降低電阻之金屬矽化層240等導電材 料，其可利用低壓化學氣相沈積法（LPCVD )依序沈積 於閘極介電層220上；閘極上蓋層260可為藉由低壓化學 φ 氣相沈積法形成之氮化矽，其作為保護閘極及絕緣之用 途；罩幕層280可包括氧化物，其可藉由化學氣相沈積法 (CVD)形成，舉例而言，罩幕層280可為利用含有四乙 基矽酸鹽（TEOS)為反應氣體所形成之氧化矽，罩幕層 280與閘極上蓋層260兩者具高蝕刻選擇比為較佳。在其 他實施例中，可在閘極上蓋層260及罩幕層280之間另形 成抗反射層，例如氮氧化矽層，以增加黃光製程之製程寬 裕度(process window ) 〇 請參照第2b圖，利用習知之微影技術於罩幕層280 ® 上形成第一圖案化光阻層290，且第一圖案化光阻層290 至少具有一開口（圖中未繪示）。接著，以此第一圖案化 光阻層290為罩幕，經由此開口蝕刻罩幕層280以及部分 之閘極上蓋層260,如此，於罩幕層280與閘極上蓋層260 中形成開口部190，較佳者閘極上蓋層260約去除三分之 一的厚度，而留下約三分之二的厚度。在一實施例中，可 利用如反應性離子餘刻（reactive ion etching，RIE)或高 密度電漿蝕刻之乾蝕刻法去除未被第一圖案化光阻層290 覆蓋之罩幕層280以及部分之閘極上蓋層260。Clienfs Docket N〇.:93079 TT's Docket No:0548-A50821.TW/fina]/Claire 7 1336930 is a simplified description, only the memory array area 20 is illustrated here. Next, a gate dielectric layer 220, a gate conductive layer 250, a gate cap layer 260, and a mask layer 280 are sequentially formed on the substrate 200 of the memory array region 20. In an embodiment, the gate dielectric layer 220 may be a ruthenium oxide layer formed by thermal oxidation; the gate conductive layer 250 may include a conductive material such as a polysilicon layer 230 and a metal rumination layer 240 for reducing resistance. It can be deposited on the gate dielectric layer 220 by low pressure chemical vapor deposition (LPCVD). The gate cap layer 260 can be a tantalum nitride formed by a low pressure chemical φ vapor deposition method. The use of the gate and the insulating layer; the mask layer 280 may include an oxide which may be formed by chemical vapor deposition (CVD). For example, the mask layer 280 may be made of tetraethyl niobate (TEOS). It is preferred that both the mask layer 280 and the gate cap layer 260 have a high etching selectivity for the yttrium oxide formed by the reactive gas. In other embodiments, an anti-reflective layer, such as a ruthenium oxynitride layer, may be formed between the gate cap layer 260 and the mask layer 280 to increase the process window of the yellow light process. Please refer to section 2b. The first patterned photoresist layer 290 is formed on the mask layer 280® by a conventional lithography technique, and the first patterned photoresist layer 290 has at least one opening (not shown). Then, the first patterned photoresist layer 290 is used as a mask, and the mask layer 280 and a portion of the gate cap layer 260 are etched through the opening, so that an opening is formed in the mask layer 280 and the gate cap layer 260. Preferably, the gate cap layer 260 is about one-third the thickness removed, leaving about two-thirds the thickness. In one embodiment, the mask layer 280 and portions not covered by the first patterned photoresist layer 290 may be removed by dry etching such as reactive ion etching (RIE) or high density plasma etching. The gate upper cap layer 260.

Client's Docket No.:93079 TT's Docket No:0548-A50821-TW/final/Claire 8 1336930 請參照第2c圖，利用電漿灰化法（plasma ashing )或 濕式剝除法（wet stripping)去除第一圖案化光阻層290 之後，於閘極上蓋層260及罩幕層280之側壁上形成間隙 壁310。在一實施例中，間隙壁310材料層可包括氧化物， 例如氧化矽，其形成方法可包括先順應性的沈積氧化矽層 (圖中未繪示）以覆蓋閘極上蓋層260及罩幕層280，接 著利用如乾姓刻之非等向性姓刻法（anisotropic etching ) 回蝕刻氧化矽層，而於開口部190中的閘極上蓋層290及 φ 罩幕層280之側壁留下間隙壁310，如第2c圖所示。 接著，請參照第2d圖，以罩幕層280及間隙壁310 為罩幕，藉由如電漿餘刻（plasma etching)或反應性離 子蝕刻之乾蝕刻法去除閘極上蓋層260及閘極導電層 250，並暴露閘極介電層220，以形成由閘極導電層250、 閘極上蓋層260、罩幕層280及間隙壁310構成之閘極疊 層 302。 請參照第2e圖，藉由濕蝕刻法去除間隙壁310，以形 成閘極結構320，並且在相鄰之閘極結構320之間形成一 ® 上部具有擴大部之間隙320a。舉例而言，可利用稀釋之 氫氟酸（dilute HF，DHF )溶液去除由氧化石夕所構成之間 隙壁310，以形成由閘極導電層250、閘極上蓋層260及 罩幕層280所構成之閘極結構320。由於在閘極結構320 中的罩幕層280及部分之閘極上蓋層260之寬度小於閘極 導電層250之寬度，因此，相鄰之閘極結構320之間可形 成上部具有擴大部之間隙320a。 請參照第2f圖，形成閘極間隙壁340於閘極結構320 之側壁，以覆蓋閘極導電層250之侧壁。在一實施例中，Client's Docket No.:93079 TT's Docket No:0548-A50821-TW/final/Claire 8 1336930 Please refer to Figure 2c to remove the first pattern by plasma ashing or wet stripping. After the photoresist layer 290 is formed, a spacer 310 is formed on the sidewalls of the gate upper cap layer 260 and the mask layer 280. In an embodiment, the material layer of the spacers 310 may include an oxide, such as ruthenium oxide, and the method for forming the method may include first conforming deposition of a ruthenium oxide layer (not shown) to cover the gate cap layer 260 and the mask. Layer 280, followed by etchback of the hafnium oxide layer by anisotropic etching, such as a dry surname, leaving a gap in the sidewalls of the gate cap layer 290 and the φ mask layer 280 in the opening 190. Wall 310 is shown in Figure 2c. Next, referring to FIG. 2d, the mask layer 280 and the spacers 310 are used as masks, and the gate cap layer 260 and the gate are removed by dry etching such as plasma etching or reactive ion etching. The conductive layer 250 exposes the gate dielectric layer 220 to form a gate stack 302 composed of a gate conductive layer 250, a gate cap layer 260, a mask layer 280, and a spacer 310. Referring to Figure 2e, the spacers 310 are removed by wet etching to form the gate structure 320, and a gap 320a having an enlarged portion at the upper portion is formed between the adjacent gate structures 320. For example, the spacers 310 formed of the oxidized stone can be removed by using a dilute HF (DHF) solution to form the gate conductive layer 250, the gate cap layer 260, and the mask layer 280. A gate structure 320 is formed. Since the width of the mask layer 280 and the portion of the gate cap layer 260 in the gate structure 320 is smaller than the width of the gate conductive layer 250, a gap between the adjacent gate structures 320 having an enlarged portion may be formed between the adjacent gate structures 320. 320a. Referring to FIG. 2f, a gate spacer 340 is formed on the sidewall of the gate structure 320 to cover the sidewall of the gate conductive layer 250. In an embodiment,

Client's Docket No.:93079 TT's Docket No:0548-A50821-TW/final/Claire 1336930 閘極間隙壁340可包括氮化矽，其形成方法包括先以化學 氣相沈積法順應性的沈積氮化矽層於閘極結構320及閘 極介電層220上，接著再實施非等向性蝕刻法，回蝕刻氮 化矽層，以於閘極結構320之側壁留下氮化矽層，作為閘 極間隙壁340。在形成閘極間隙壁340之後，可利用閘極 結構320及閘極間隙壁340為離子佈植罩幕，實施離子植 . 入製程，以在基底200中形成源/汲極區350。 請參照第2g圖，在閘極結構320上方形成介電層 φ 400，並填入相鄰之閘極結構320之間之上部具有擴大部 的間隙320a。介電層400可包括藉由次常壓化學氣相沈 積法（SACVD)形成之硼磷矽玻璃（BPSG)，並且在沈 積BPSG之後，可實施一回火製程，以促進BPSG之流動 性。較佳者，在形成介電層400之後更實施平坦化步驟， 如藉由化學機械研磨法（CMP )，以平坦化介電層400。 值得注意的是，由於閘極結構320之間的間隙320a之上 部具有一擴大部，其深寬比（aspect ratio )因此降低，也 因此可增加介電層400之填溝力（gap-fill capability)。 ® 在第2g圖中，間隙320a之深寬比即D2/W2，其中D2/W2 以小於3為較佳。由於間隙320a的深寬比（aspect ratio ) 降低，當介電層400填入閘極結構320之間的間隙320a 時，可降低於介電層400中產生孔洞的機率。 請參照2h圖，形成第二圖案化光阻層380於介電層 400上，以定義位元線（bit line)接觸窗，之後利用第二 圖案化光阻層380為罩幕，蝕刻介電層400及其下之閘極 介電層220，以於相鄰之閘極結構320之間形成位元線接 觸窗420。最後，利用電漿灰化法（plasma ashing)或濕Client's Docket No.: 93079 TT's Docket No: 0548-A50821-TW/final/Claire 1336930 The gate spacer 340 may include tantalum nitride, which is formed by a chemical vapor deposition method followed by deposition of a tantalum nitride layer. On the gate structure 320 and the gate dielectric layer 220, an anisotropic etching method is further performed to etch back the tantalum nitride layer to leave a tantalum nitride layer on the sidewall of the gate structure 320 as a gate gap. Wall 340. After the gate spacers 340 are formed, the gate structures 320 and the gate spacers 340 can be used as ion implantation masks to perform ion implantation processes to form source/drain regions 350 in the substrate 200. Referring to Fig. 2g, a dielectric layer φ 400 is formed over the gate structure 320, and a gap 320a having an enlarged portion between the adjacent gate structures 320 is filled. The dielectric layer 400 may include borophosphorus bismuth glass (BPSG) formed by sub-atmospheric chemical vapor deposition (SACVD), and after the BPSG is deposited, a tempering process may be performed to promote the mobility of the BPSG. Preferably, a planarization step is performed after forming the dielectric layer 400, such as by chemical mechanical polishing (CMP), to planarize the dielectric layer 400. It is to be noted that since the upper portion of the gap 320a between the gate structures 320 has an enlarged portion, the aspect ratio thereof is thus reduced, and thus the gap filling force of the dielectric layer 400 can be increased (gap-fill capability). ). ® In the 2g diagram, the aspect ratio of the gap 320a is D2/W2, where D2/W2 is preferably less than 3. Since the aspect ratio of the gap 320a is lowered, when the dielectric layer 400 is filled in the gap 320a between the gate structures 320, the probability of generating holes in the dielectric layer 400 can be reduced. Referring to FIG. 2h, a second patterned photoresist layer 380 is formed on the dielectric layer 400 to define a bit line contact window, and then the second patterned photoresist layer 380 is used as a mask to etch dielectric. Layer 400 and its underlying gate dielectric layer 220 form a bit line contact window 420 between adjacent gate structures 320. Finally, using plasma ashing or wet

Client’s Docket No.:93079 TT's Docket N〇:0548-A50821 -TW/final/Claire 10 1336930 式剝除法（wet stripping )去除第二圖案化光阻層390。 接著，於接觸窗420中填入導電層，以形成位元線接 觸插塞440，如第2i圖所示。在一實施例中，可藉由化學 氣相沈積法在介電層400上形成例如鎢金屬之導電層材 料，並填入位元線接觸窗420中，較佳者，形成於位元線 接觸窗420中之導電層材料更可包括金屬阻障層，例如 . 鈦、钽、氮化鈦或氮化钽及其組合，其順應性的沈積於位 元線接觸窗420之側壁及底部。最後，可藉由化學機械研 φ 磨法（CMP )去除介電層400上之多餘的導電層材料，而 餘留在位元線接觸窗420中之導電層材料係構成位元線 接觸插塞440。 在上述實施例中，由於本發明改善習知之閘極結構 108之間的間隙之深寬比過大的問題，其導致填入其中之 介電層H0產生孔洞。藉由本發明之概念，在完成位元線 接觸插塞440製作之後，位元線接觸插塞440與其他鄰近 之位元線接觸插塞（圖中未繪示）不會因彼此之電性連 接，而導致位元線與位元線短路的情形發生，如此，可提 *升元件之可靠度。 另外，需注意的是，上述實施例雖以dram之位元 線接觸插塞作為範例作說明，然而位於記憶裝置之周邊電 路區或其他半導體裝置具有填溝能力不佳而造成元件可 靠度降低之問題，同樣可應用本發明之概念解決之。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此項技藝者，在不脫離本發明之精 神和範圍内，當可作更動與潤飾，因此本發明之保護範圍 當視後附之申請專利範圍所界定者為準。Client's Docket No.: 93079 TT's Docket N: 0548-A50821 - TW/final/Claire 10 1336930 Wet stripping removes the second patterned photoresist layer 390. Next, a conductive layer is filled in the contact window 420 to form a bit line contact plug 440, as shown in Fig. 2i. In one embodiment, a conductive layer material such as tungsten metal may be formed on the dielectric layer 400 by chemical vapor deposition and filled in the bit line contact window 420, preferably formed in a bit line contact. The conductive layer material in the window 420 may further include a metal barrier layer, such as titanium, tantalum, titanium nitride or tantalum nitride, and combinations thereof, which are deposited in the sidewalls and bottom of the bit line contact window 420. Finally, the excess conductive layer material on the dielectric layer 400 can be removed by chemical mechanical grinding (CMP), and the conductive layer material remaining in the bit line contact window 420 constitutes a bit line contact plug. 440. In the above embodiment, since the present invention improves the problem of the excessive aspect ratio of the gap between the conventional gate structures 108, it causes the dielectric layer H0 filled therein to generate holes. With the concept of the present invention, after the completion of the bit line contact plug 440, the bit line contact plug 440 and other adjacent bit line contact plugs (not shown) are not electrically connected to each other. And the situation that the bit line and the bit line are short-circuited occurs, so that the reliability of the component can be improved. In addition, it should be noted that although the above embodiment uses the bit line contact plug of the dram as an example, the peripheral circuit area or other semiconductor device located in the memory device has poor filling ability and the component reliability is lowered. The problem can also be solved by applying the concept of the present invention. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the invention may be modified and retouched without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application attached.

Client's Docket No.:93079 TT's Docket N〇:0548-A50821-TW/final/Claire 1] 1336930 【圖式簡單說明】 第1圖係繪示習知之形成記憶裝置之位元線接觸插塞 的中間製程剖面圖； 第2 a至2 i圖說明本發明實施例之位元線接觸插塞之製 造方法。Client's Docket No.:93079 TT's Docket N〇:0548-A50821-TW/final/Claire 1] 1336930 [Simplified Schematic] Figure 1 shows the intermediate process of forming a bit line contact plug for a memory device. Cross-sectional view; Figures 2a through 2i illustrate a method of fabricating a bit line contact plug in accordance with an embodiment of the present invention.

【主要元件符號說明】 先前技術 10〜記憶陣列區； 100〜基底； 108〜閘極結構； 120〜閘極介電層； 140〜金屬石夕化物層； 160〜閘極上蓋層； 實施方式 20〜記憶陣列區； 220〜閘極介電層； 240〜金屬石夕化層； 260〜閘極上蓋層； 290〜第一圖案化光阻層； 310〜間隙壁； 320〜閘極結構； 340〜閘極間隙壁； 400〜介電層； 420〜位元線接觸窗； 60〜孔洞； 105〜源/汲極區； 110〜介電層； 130〜多晶碎層； 150〜閘極導電層； 170〜閘極間隙壁。 200〜基底； 230〜多晶碎層； 250〜閘極導電層； 280〜罩幕層； 190〜開口部； 302〜閘極疊層； 320a〜間隙； 350〜源/沒極區； 380〜第二圖案化光阻層； 440〜位元線接觸插塞。[Description of main component symbols] Prior art 10 to memory array region; 100 to substrate; 108 to gate structure; 120 to gate dielectric layer; 140 to metal-lithium layer; 160 to gate upper cap layer; ~ memory array area; 220 ~ gate dielectric layer; 240 ~ metal shihua layer; 260 ~ gate upper cap layer; 290 ~ first patterned photoresist layer; 310 ~ spacer; 320 ~ gate structure; ~ gate spacer; 400 ~ dielectric layer; 420 ~ bit line contact window; 60 ~ hole; 105 ~ source / drain region; 110 ~ dielectric layer; 130 ~ polycrystalline layer; 150 ~ gate conduction Layer; 170~ gate spacer. 200~ substrate; 230~ polycrystalline layer; 250~ gate conductive layer; 280~ mask layer; 190~ opening; 302~ gate stack; 320a~ gap; 350~ source/no-polar area; a second patterned photoresist layer; a 440-bit line contact plug.

Clienfs Docket No.:93079 12 TT's Docket No:0548-A50821-TW/final/ClaireClienfs Docket No.:93079 12 TT's Docket No:0548-A50821-TW/final/Claire

Claims (1)

U36930 年月日修(乾)正本 修正日 _ 99 年 11 Ψ 第96118〇39號申請專利範圍修正本 十、申請專利範圍： 1.一種位元線接觸插塞的製造方法，包括： &供一基底，依序形成一閘極介電層、一閘極導電 層、一閘極上蓋層、及一罩幕層於該基底上； 形成一圖案化光阻層於該罩幕層上，該圖案化光阻層 具有一開口； 曰 利用該圖案化光阻層做為遮罩，經由該開口蝕刻該罩 幕層及部分之該閘極上蓋層； 移除該圖案化光阻層； 形成一間隙壁於該罩幕層及該閘極上蓋層之側壁； 罩幕層及該間隙壁為遮罩，去除該閘極上蓋層及 閘極導電層，以形成複數個閘極疊層； 之該間隙壁’以形成複數個閘極結構，並且於相鄰 結構之間形成一上方具有擴大部之間隙； 之間隙^介電層於該基底上，並填入該上方具有擴大部 固莱化該介電層 %日从％取一彳立兀線接觸窗；以及 觸插塞。層於該位元線接觸窗中，以形成位元線接 造方法，其中該罩=位几線接觸插塞的製 氣體的氧化矽。a已括利用3有四乙基矽酸鹽為反應 造方項所述之位元線朗插塞的製 4、中相極上蓋層包括氮化％。 造方法:所述之位元線接觸插塞的製 r Θ間隙壁包括氧化矽。 13 1^6930 第96丨聊號申請專利範圍修正本 ί:修正日期：99年丨丨月8日 & 2 u利&圍第1項所述之位元線接觸插塞的製 &方法，其中在利用該圖案化光阻層做 ==幕層及部分之該職上蓋層之步驟中，該閉』 層、力去除三分之一的厚度，而留下約三分之二的厚 造方^ H 利犯圍第】項所述之位元線接觸插塞的製 壁，包括··幕層及該閘極上蓋層之側壁形成該間隙 上蓋成—間隙壁材料層於該罩幕層及該閘極 非‘：向性蝕刻該間隙壁材料層，以於該罩幕声 "上盍層之側壁上形成該間隙壁。 s / 造方項所述之位元線接觸插塞的製 上蓋層及閘極導隙壁為遮罩，去除該閘極 U由·^ 步驟係利用—乾钱刻完成。 造方法:===以=接觸插綱 造方法，其中去除該間隙壁二線接^插塞的製 〗〇.如申請專利範圍第9 :餘刻完成。 製造方法，其中該濕蝕 稀位，線接觸插塞的 刻。 4係以稀釋之氩氤酸溶液進行钱 】1.如申請專利範圍第 _ 製造方法，更包括： 、以之位凡線接觸插塞的 形成-間極間隙壁於該閑 12.如申請專利範圍 年电層之惻壁。 項所述之位元線接觸插塞的 IJ36930 第96118039號申請專利麵修正本 丨修正日期：99年η月8日 製造方法，該閘極導電層包括多晶石夕層或金屬石夕化物層。 制、=申範圍第1項所述之位元線接觸插塞的 衣k方法，其中遠介電層包括硼磷矽玻璃。 f造！專鄉㈣1項所述之位元賴觸插塞的 ‘相、…二形成該介電層於該基底上之步驟係以化學 氧相沈積法完成。 于 ㈣圍第1項所述之位元線接觸插塞的 在形成該介電層於該基底上之後，更包括 、 化予機械研磨步驟。 製造申Λ專範圍第1項所述之位元線接觸插塞的 以化學氣相；4;:完:導電層於該位元線接觸窗之步驟係 製造1項所述m線接觸插塞的 18如二中该導電層包括一金屬阻障層。 製造方法申：ί利乾圍第11項所述之位元線接觸插塞的 其_該閘極間隙壁包括氮化矽。U36930 Yearly Repair (Dry) Original Revision Date _ 99 Year 11 Ψ No. 96118〇39 Application Patent Revision Amendment 10, Patent Application Scope: 1. A method for manufacturing a bit line contact plug, including: & a substrate, sequentially forming a gate dielectric layer, a gate conductive layer, a gate cap layer, and a mask layer on the substrate; forming a patterned photoresist layer on the mask layer, the The patterned photoresist layer has an opening; the patterned photoresist layer is used as a mask, the mask layer and a portion of the gate cap layer are etched through the opening; the patterned photoresist layer is removed; a spacer is disposed on the mask layer and a sidewall of the gate cap layer; the mask layer and the spacer are masks, and the gate cap layer and the gate conductive layer are removed to form a plurality of gate stacks; The spacers are formed to form a plurality of gate structures, and a gap having an enlarged portion is formed between the adjacent structures; a gap is formed on the substrate, and the upper portion is filled with the enlarged portion to fix the Dielectric layer % day takes a 彳 兀 line contact window from % And a contact plug. A layer is in the bit line contact window to form a bit line bonding method, wherein the mask = bit lines contact the yttria of the gas of the plug. a has been prepared by using 3 tetraethyl decanoate as the bit line plug described in the reaction formula. 4. The middle phase cap layer includes nitriding %. Manufacturing method: the bit line contact plug of the bit line Θ spacer includes yttrium oxide. 13 1^6930 The 96th 丨 号 申请 申请 申请 申请 申请 申请 ί ί : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : The method wherein, in the step of using the patterned photoresist layer as the == curtain layer and a portion of the upper cap layer, the closed layer and the force are removed by a third of the thickness, leaving about two-thirds of the The wall of the bit line contact plug described in the item of the above-mentioned item, including the curtain layer and the side wall of the upper layer of the gate layer, the cover is formed as a layer of the spacer material in the cover The curtain layer and the gate are not ': a layer of the spacer material is etched to form the spacer on the sidewall of the mask layer. The upper cover layer and the gate gap wall of the bit line contact plug described in the s / 造方 clause are masks, and the removal of the gate U is performed by using the dry-money. Manufacturing method: === in the form of contact plugging, wherein the method of removing the second-line connector of the spacer is 〇. If the patent application scope is 9: the remaining time is completed. A manufacturing method in which the wet etching is thin, and the line is in contact with the plug. 4 series of diluted argonic acid solution for money] 1. As claimed in the scope of the _ manufacturing method, including:, in place of the line contact plug formation - the inter-electrode gap in the idle 12. If you apply for a patent The wall of the annual electric layer. IJ36930 No. 96113039, the bit line contact plug described in the above-mentioned application, is amended. The date of revision is: the manufacturing method of the ninth month, the gate conductive layer includes a polycrystalline layer or a metal lithium layer. . The method of fabricating a bit line contact plug according to item 1, wherein the far dielectric layer comprises borophosphon glass. f made! The step of forming the dielectric layer on the substrate by the one-of-a-kind (1) bit-contacting plug is completed by chemical oxygen phase deposition. After the formation of the dielectric layer on the substrate, the bit line contact plug of the first item is further included in the mechanical polishing step. Manufacturing the bit line contact plug according to item 1 of the application scope to the chemical vapor phase; 4;: finishing: the step of the conductive layer contacting the window in the bit line to manufacture one of the m line contact plugs In the 18th, the conductive layer comprises a metal barrier layer. The method of manufacturing the method of: the bit line contact plug of the eleventh item described in the eleventh item, the gate spacer comprises tantalum nitride.