1334207 九、發明說明： 【發明所屬之技術領域】 一種導電凸塊之製法，尤指一種在電路板之電性連接 墊上利用電鍍與化學置換方式形成合金導電凸塊之製作方 法0 【先前技術】 在現行覆晶（Flip Chip)技術中，係在半導體積體電路 (1C)晶片的表面上配置有電極墊，且在一有機電路板上形 成有相對叙電性連接墊，俾藉由在該晶片以及電路板之 間設置例如為合金導電凸塊之導電結構，以提供該晶片以 ^生接觸面朝下的方式設置於該電路板上，其中，該合金 V電凸塊提供該晶片以及電路板間的電性輪人 以及機械性的連接。 V ；1334207 IX. Description of the invention: [Technical field of invention] A method for manufacturing a conductive bump, in particular, a method for forming an alloy conductive bump by electroplating and chemical replacement on an electrical connection pad of a circuit board 0 [Prior] In the current Flip Chip technology, an electrode pad is disposed on a surface of a semiconductor integrated circuit (1C) wafer, and a relatively electrically conductive connection pad is formed on an organic circuit board, An electrically conductive structure, such as an alloy conductive bump, is disposed between the wafer and the circuit board to provide the wafer on the circuit board with the contact surface facing downward, wherein the alloy V electrical bump provides the wafer and the circuit Electrical wheels between the boards and mechanical connections. V ;
目前業界通常係藉由電鍵兩層金屬再重溶的方式以 fA該至電^板之雜連純上形成合金導電凸塊。請參閱第 電凸塊^顯示f知之電路板電性連接墊之合金導 接墊結步驟。首先係提供—具有至少—電性連 3⑽之電路板1G，並在料路板 護層U，該絕緣保護層^且 开乂成、，巴緣保 該電性連接塾1〇〇(八、广歼孔110以暴露出 10上形成-導電層12且==;接著在該電路板 13,且該阻層η形成有至广門導孔^ 接墊100 (如第1B R _開孔以裸露出該電性連 鍍方式在該開孔13(^所不）；然後藉由該導電層12以電 中之電性連接墊100上形成一第一金 19431(修正版） 5 1J34207 • j層如第re圖所示）；再以電鑛方式於該第一金屬 .θ⑷上形成一第二金屬層142 (如第⑺圖所示）；接著 ‘移除該阻層13及該阻層13所覆蓋之導電層】2 (如第u -圖所示）；最後在足以使該第一及第二金屬層⑷⑷之 金屬材料熔融之迴銲溫度條件下，進行迴焊 ， .(RefWS0ldering)製程，使該第一及第二金屬層⑷⑷ •在該電路板H)之電性連接墊！⑼场電 14 (如第if圖所示）。 等私凸塊 然而，對於前述電錢兩層金屬之製法而言，由於受到 制，該第二金屬層142係僅電鍍形成 上表面，且該第二金屬層142的電鑛厚度亦不 =匕Γ後續進行迴焊製程時因兩層金屬接觸面積 ==重炼溫度的影響，而造成導電凸塊内合金成份 —句勻及結合力強度欠佳的問題 凸塊的導電特性。 P曰U i導电 此外’或有使用合金雷奶液 電性連接塾上形成合金』在該電路板之 量—金材電=上形成足夠分 (電鐘厚度）較單&金％㈣的電鑛條件 的複雜性。 ”电鍍液更難控制’因而會增加製程 凸塊内之均勻性及結 重要課題。 因此，如何增加合金成份於導電 合力強度’已成為目前半導體業界之 【發明内容】 19431(修正版） 6 丄仔zu/ 丄仔zu/ 本發明之主要目的係在提 導電凸塊之製法，得增加 ，俾以提高結合強度及導 鑑於前述習知技術之缺失， 供一種電路板電性連接墊之合金 合金成份均勻分佈於導電凸塊中 電特性。 本毛明之又一目的，係在一 之合全導在权併種電路板電性連接塾 金W凸塊之製法，得利於控制導電凸塊之厚戶。 之人Si月之另一目的，係在提供-種電路板電性：接墊 電凸塊之製法’得利於控制導電凸塊内 伤，進而降低製程之複雜性。 '卢成 3上述及其他相關目#’.本發明即提供—種電路板 =連接塾之合金導電凸塊之製法，係包括：提供—表面 有複數電性連接墊之電路板，該電路板表面形成有一絕 緣保護層，且該絕緣保護層具有複數開孔以外露該些電性 連接塾；於該電路板之絕緣保護層表面形成一阻層，且於 該阻層上形成有複數開孔以顯露出該電性連接塾；於該阻 層之開孔中電鑛-金屬層，且該金屬層形成於該電^接 墊上;移除該阻層；以及於該金屬層表面化鍍一金屬銀層， 且使該金屬銀層完全包覆該金屬層表面。 曰 經由前述製程後，復可進行一迴焊製程使該金屬層及 金屬銀層熔合成一合金導電凸塊。 該電路板及該阻層之間復設有一導電層，該導電層覆 蓋該絕緣保護層表面及外露於該絕緣保護層開孔之電性連 接墊表面，藉由該導電層以電鍍形成該金屬層；前述之移 除該阻層復包括移除該阻層所覆蓋之導電層；另該電性連 19431(修正版） 7 1334207 .接墊表面及金屬層間復包括形成一導電柱；前述之使該金 •屬銀層完全包覆該金屬層表面復包括使該金屬銀層完全包 ’覆該導電柱表面；該金屬銀層係以無電電鍍及化學沉積之 其中一者形成於該金屬層表面。 經由前述製程後，復可將形成於導電柱上之金屬層， 及包覆V電柱及金屬層之金屬銀層進行一迴焊製程使該及 •金屬銀層熔合成一合金導電凸塊。 於-較佳實施態樣中’該金屬層之金屬材料係為錫。 響相較於習知技術，本發明係藉由電鍍與化學置換方式 (無電電鍍或化學沉積）在電路板之電性連接墊上沉積^ 屬層以增加金屬層間之接觸面積，再經迴焊製程使金屬層 及金屬銀層均勻溶合成一合金導電凸塊，藉以改善習知^ 用兩層電鍍金屬方式因兩層金屬接觸面積不充足而造成首 電凸塊内合金成份混合不充份及導致結合強度降低=問钕 題，同時亦可解決使用合金電鍵液方式因電鐘厚度㈣控 籲制而造成合金成份難控制且製程複雜的問題。 二 【實施方式】 以下係藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 暸解本發明之其他優點與功效。 第一實施例 s青參閱苐2A至2F圖’其係顯示本發明笼— 矛—声、施例之 電路板=性連接墊之合金導電凸塊之製法之流程步驟，以 下結合第2A至2F圖詳細説明本發明之製作方法 19431(修正版) 8 1334207 首先，請參閱第2A圖，提供一表面具有複數電性連 • 接墊200之電路板20，該電路板20表面形成有一絕緣保 • 護層21，且該絕緣保護層21具有複數開孔210以外露該 秦 些電性連接墊200。該電路板20可以為具有單層或多層導 電線路之基板，有關於基板形成電性連接墊、導電線路及 •絕緣保護層之製程技術繁多，惟乃業界所熟知之製程技 •術，其非本案之技術特徵，故未再予贅述。 其次，請參閱第2B圖，於該電路板20之絕緣保護層 籲 21表面及外露於該絕緣保護層21開孔210之電性連接墊 200表面形成一導電層22,該導電層22主要作為後述電鍍 金屬材料所需之電流傳導路徑，其可由金屬、合金或沉積 數層金屬層所構成，如選自銅、錫、鎳、鉻、鈦、銅-鉻合 金或錫-鉛合金所構成之群組之其中一者。且該導電層22 可藉由物理氣相沈積（P VD)、化學氣相沈積（C VD)、無電鍍 或化學沈積等方式形成。 φ 再者，如第2B圖所示，於該導電層22表面形成一阻 層23，且於該阻層23上形成有複數開孔230以露出該些 電性連接塾200上表面之導電層22。其中，該阻層23可 例如為乾膜或液態光阻等之光阻層（Photoresist)，其可利用 印刷、旋塗或貼合等方式覆蓋於該導電層22上，並可藉由 曝光（Exposure)及顯影（Development)等圖案化製程使該阻 層23形成該開孔230,亦或藉由雷射技術形成該開孔230, 藉以顯露出覆蓋於該電性連接墊200上之部分導電層22。 然後，請參閲第2C圖，於該阻層23之開孔230中形 9 19431(修正版） 1334207 成一金屬層241，且該金屬層241覆蓋於該電性連接墊200 上。於本實施例中，該金屬層241之金屬材料係為錫（Sn)， • 其可透過電鑛（Electroplating)製程並藉由該導電層22與該 * .電性連接墊200等電流傳導路徑，俾在該電性連接墊200 上直接形成電鍍金屬層（金屬層241)。 • 接著，請參閱第2D圖，藉由例如化學藥液剝除製程 - 移除該阻層23及其所覆蓋之導電層22。 再請參閱第2E圖，於該金屬層241表面化鑛一金屬 • 銀層242，且使該金屬銀層242完全包覆該金屬層241表 面。於本實施例中，該金屬銀層242可透過無電電鍍或化 學沉積等化學金屬置換製程沉積一薄膜金屬層（金屬銀層 242)於該金屬層241上，且該薄膜金屬層（金屬銀層242) 完全包覆該金屬層241表面，使該金屬層241及金屬銀層 242之間具有充分的接觸面積。 最後，請參閱第2F圖，在足以使該電鍍之金屬層241 $與化學置換沉積之金屬銀層242熔融之溫度條件下，經迴 焊製程使該金屬層241及金屬銀層242熔合成一合金導電 凸塊24。由於該金屬層241及金屬銀層242間具有充分的 接觸面積，因此，該金屬層241及金屬銀層242之金屬材 料可充分混合以形成均勻的合金導電凸塊24 (錫銀導電凸 塊）。 第二實施例 請參閱第3A至3G圖，其係顯示本發明第二實施例之 電路板電性連接墊之合金導電凸塊製法之流程步驟，以下 10 19431(修正版） 1334207 結合第3A至3G圖詳細説明本發明之製作方法 之技術及㈣係相同於第—實施例之部份 重斤= 明，以簡化說明書之内容。 料再重覆5兄 請參閱f 3A圖，提供一.表.面具有複數電性連接塾· 之電路板20^，該電路板2G表面形成有—絕緣保護層^， 且該絕緣保護層2 1且古AT. BB -71 〇 ·, Λ 整·。 數開孔2心外露該些電性連接 請參閲第3B圖，於該絕緣保護層21表面及外露出該 絕緣保護層2!複數開孔21〇之電性連接塾：㈣面形成一 導電層22’該導電層22主要作為後述電鐘金屬材料所需 之電流傳導路徑。再於該導電層22表面形成—阻層^， 且於該阻層23上形成有複數開孔23()以露出該些電性連接 墊200上表面之導電層22。 請參閲第3C圖’於該阻層23之開孔23〇中電鍵形成 -導電柱201，且該導電柱2G1覆蓋於該電性連接塾鳩 上。其中，該導電柱2〇1係為金屬導電柱，且其金屬㈣ 之炼點溫度應高於後續迴焊製程之重熔溫度，因此其不會 在後續迴焊製程中重炫而影響合金導電凸塊中之合金成θ 份0 請參閲f 3D圖’於該阻詹23之開孔23〇及該導電柱 2〇1上電鍍形成金屬層241 (電鍍金屬層），其中，該金屬 層24!之金屬材料係為錫（Sn)。由於該電性連接墊2〇〇及 金屬層241間已形成有導電桂2〇1，由此可節省沉積於該 開孔230中之金屬層241之電鍍金屬材料。 19431 (修正版） 11 1334207 請參閱第3E圖，藉由例如化學藥液剝除製程移除該 ’阻層23及其所覆蓋之導電層22。 請麥閱第3F圖，藉由無電電鍍或化學沉積等化學金 •屬置換製程以於該金屬層241表面化鍍一金屬銀層242(薄 膜金屬層）’且使該金屬銀層242完全包覆該金屬層241 表面及該導電柱2〇1表面。最後，請參閱第3G圖在足 '以使該電鍍沉積之金屬層241與化學置換沉積之金屬銀層 242重炫之溫度條件下’經迴焊製程使該金屬層241及金 藝屬銀層242熔合成一合金導電凸塊24 (錫銀導電凸塊）。 表τ、剛所述’本發明係首先透過電鍍製程在外露於阻層. 之電性連接墊上形成金屬層（電鍍金屬層），再於移除該 阻層後透過無電電鍍或化學沉積之化學金屬置換製程將金 j銀層（薄膜金屬層）完全包覆該金屬層，最後利用迴焊 製程使該金屬層及金屬銀層溶合成一合金導電凸塊。由於 該金屬銀層之厚度薄且易於控制，同時亦不受該阻層之限 鲁制而可完全覆蓋該金屬層之外表面（上表面及側表面）， 在足X使該電鑛沉積之金屬層與化學置換沉積之金屬 銀層溶融之溫度條件下，該金屬層及金屬銀層間因具有充 分的接觸面積而易於混合，由此即可形成合金成份均句且 力強度較佳之合金導電凸塊。因此，本發明之電 勻性及結合力強Ϊ 以增加合金成份之均 又’進而提昇合金導電凸塊之導電特性。 带卜、本發明係藉由電鍍與化學置換方式以在該電路 私味連接塾上沉積金屬層’而無需使料鍍條件（電 】9431(修正版） ⑶4207 链厚度）較難控制之合金電鐘液進行電鍍，因此，本發明 ^電路板電性連接墊之合金導電凸塊之製法可以利於控制 V电凸塊内之合金成份，進而降低製程之複雜性。 上述實施·例僅例示性說明本發明之原理及其功效， 非用於限制本發明。任何熟悉此項技藝之人士均可 =本發明之精神及範訂，對上述實施例進行修飾與改延 交。因此’本發明之權利保護範圍， 範圍所列。 、心甲叫專利 _【圖式簡單說明】 接墊為剖㈣，係顯示習知之電路板電性連 接墊之合金導電凸塊製法之流程步驟； 第2A至2F圖為剖視圖，係顯示本發明第一奋 電路板電性i車技執·>人a、旨 Μ施例之 第5 t 凸塊製法之流程步驟；以及 至3G圖為剖視圖，係顯示杳 電路板電性連接墊之合全導t 弟一例之 金凸塊製法之流程步驟。 【主要元件符號說明】 10、20 電路板 100、200電性連接墊 11、21 絕緣保護層 110 ' 130、210、23 開孔 12 ' 22 導電層 13、23 阻層 14、24 合金導電凸塊 141、241金屬層 19431(修正版) 13 1334207 142 第二金屬層 242 金屬銀層 201 導電柱At present, in the industry, the alloy conductive bumps are formed by fA to the hybrid of the electrodes by means of re-dissolving the two layers of metal. Please refer to the electric bumps to show the alloy lead-bonding step of the electrical connection pads of the circuit board. Firstly, a circuit board 1G having at least - electrical connection 3 (10) is provided, and in the material layer protection layer U, the insulation protection layer is opened and closed, and the edge of the edge is protected by the electrical connection 八1〇〇 (8. The wide hole 110 is formed to expose a conductive layer 12 on the surface 10 and ==; then on the circuit board 13, and the resist layer η is formed with a via hole to the gate 100 (such as the 1B R _ opening to Excluding the electrical plating method in the opening 13 (^); then forming a first gold 19431 (corrected version) by electrically connecting the conductive layer 12 to the electrical connection pad 100. 5 1J34207 • j a layer is as shown in the re diagram); a second metal layer 142 is formed on the first metal .θ(4) by electro-mineralization (as shown in the figure (7)); then the resist layer 13 and the resist layer are removed 13 covered conductive layer] 2 (as shown in Figure u-); finally reflowed under reflow temperature conditions sufficient to melt the metal material of the first and second metal layers (4) (4). (RefWS0ldering) The process is such that the first and second metal layers (4) (4) • the electrical connection pads on the circuit board H)! (9) Field power 14 (as shown in the figure of if). Isocratic bumps However, for the above-mentioned method of manufacturing two-layer metal of electricity, the second metal layer 142 is only plated to form the upper surface, and the thickness of the second metal layer 142 is not = 匕ΓIn the subsequent reflow process, due to the influence of two layers of metal contact area == refining temperature, the conductive composition of the alloy in the conductive bumps - the uniformity of the sentence and the strength of the bonding force is poor. P曰U i Conductive In addition, or use alloy ferrite to electrically connect the alloy to form an alloy. In the amount of the board - gold material = form a sufficient amount (electric clock thickness) compared to single & gold% (four) The complexity of the electro-mineral conditions. "The plating solution is more difficult to control", thus increasing the uniformity and important problems in the process bumps. Therefore, how to increase the strength of the alloy composition in the conductive force has become the current semiconductor industry [invention content] 19431 (revision) 6 丄仔zu/丄仔zu/ The main purpose of the present invention is to increase the bonding strength and improve the bonding strength and to provide an alloy alloy for the electrical connection pads of the circuit board in view of the lack of the prior art. The composition is evenly distributed in the electrical characteristics of the conductive bumps. Another purpose of the present invention is to control the thickness of the conductive bumps in a method of electrically connecting the gold-plated W bumps. Another purpose of the person Si Moon is to provide a kind of circuit board electrical: the method of forming the electric bumps is beneficial to control the internal resistance of the conductive bumps, thereby reducing the complexity of the process. Other related items #'. The present invention provides a circuit board = a method for manufacturing an alloy conductive bump of a tantalum, comprising: providing a circuit board having a plurality of electrical connection pads on the surface, the surface of the circuit board is formed An insulating protective layer, wherein the insulating protective layer has a plurality of openings to expose the electrical connecting ports; a resist layer is formed on the surface of the insulating protective layer of the circuit board, and a plurality of openings are formed on the resist layer to expose The electrical connection is formed; an electric ore-metal layer is formed in the opening of the resist layer, and the metal layer is formed on the electrical pad; the resist layer is removed; and a metallic silver layer is plated on the surface of the metal layer And the metal silver layer completely covers the surface of the metal layer. After the foregoing process, a reflow process is performed to melt the metal layer and the metal silver layer into an alloy conductive bump. The circuit board and the resistor A conductive layer is disposed between the layers, and the conductive layer covers the surface of the insulating protective layer and the surface of the electrical connection pad exposed on the opening of the insulating protective layer, and the conductive layer is used to form the metal layer by electroplating; The resist layer includes a conductive layer covered by the resist layer; and the electrical connection 19431 (revision) 7 1334207. The surface of the pad and the metal layer further comprise a conductive pillar; the foregoing makes the gold silver The layer completely covers the metal layer The surface layer includes completely coating the metal silver layer to cover the surface of the conductive pillar; the metal silver layer is formed on the surface of the metal layer by electroless plating and chemical deposition. After the foregoing process, the complex is formed on the conductive layer. The metal layer on the pillar, and the metal silver layer covering the V-pillar and the metal layer are subjected to a reflow process to melt the metal silver layer into an alloy conductive bump. In the preferred embodiment, the metal layer The metal material is tin. Compared with the prior art, the present invention deposits a metal layer on the electrical connection pads of the circuit board by electroplating and chemical replacement (electroless plating or chemical deposition) to increase the contact between the metal layers. The area and the reflow process enable the metal layer and the metallic silver layer to be uniformly dissolved into an alloy conductive bump, thereby improving the conventional alloying method by using two layers of plating metal due to insufficient contact area of the two layers of metal. Insufficient mixing of ingredients and reduced bonding strength = question, but also solve the problem of using alloy key liquid method due to the thickness of the electric clock (four) control system, which makes the alloy composition difficult to control and the process is complicated. . [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand other advantages and effects of the present invention from the disclosure of the present disclosure. The first embodiment s 苐 A 2A to 2F diagram 'which shows the process steps of the cage of the present invention - the spear-sound, the circuit board of the embodiment = the alloy conductive bump of the sexual connection pad, the following combines the 2A to 2F DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 1931 (Revised Edition) 8 1334207 First, please refer to FIG. 2A to provide a circuit board 20 having a plurality of electrical pads 200 on the surface, and an insulating layer is formed on the surface of the circuit board 20 The protective layer 21 has a plurality of openings 210 for exposing the electrical connection pads 200. The circuit board 20 can be a substrate having a single layer or a plurality of conductive lines, and has various manufacturing processes for forming electrical connection pads, conductive lines, and an insulating protective layer on the substrate, but is well known in the industry as a process technology. The technical features of this case are not repeated here. Next, referring to FIG. 2B, a conductive layer 22 is formed on the surface of the insulating protective layer 21 of the circuit board 20 and the surface of the electrical connection pad 200 exposed on the opening 210 of the insulating protective layer 21. The conductive layer 22 is mainly used as a conductive layer 22 The current conduction path required for electroplating a metal material, which may be composed of a metal, an alloy or a deposition of several metal layers, such as selected from the group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy or tin-lead alloy. One of the groups. And the conductive layer 22 can be formed by physical vapor deposition (P VD), chemical vapor deposition (C VD), electroless plating or chemical deposition. Further, as shown in FIG. 2B, a resist layer 23 is formed on the surface of the conductive layer 22, and a plurality of openings 230 are formed on the resist layer 23 to expose the conductive layer on the upper surface of the electrical connection layer 200. twenty two. The resist layer 23 can be, for example, a photoresist layer of a dry film or a liquid photoresist, which can be covered on the conductive layer 22 by printing, spin coating or lamination, and can be exposed by exposure ( The patterning process such as Exposure and development forms the barrier layer 23 to form the opening 230, or the opening 230 is formed by laser technology, thereby exposing a portion of the conductive layer covering the electrical connection pad 200. Layer 22. Then, referring to FIG. 2C, a metal layer 241 is formed in the opening 230 of the resist layer 23, and the metal layer 241 is overlaid on the electrical connection pad 200. In this embodiment, the metal material of the metal layer 241 is tin (Sn), which is permeable to an electroplating process and has a current conduction path by the conductive layer 22 and the electrical connection pad 200. , a plating metal layer (metal layer 241) is directly formed on the electrical connection pad 200. • Next, refer to FIG. 2D, by removing the resist layer 23 and the conductive layer 22 it covers by, for example, a chemical liquid stripping process. Referring again to FIG. 2E, a metal-silver layer 242 is surfaced on the metal layer 241, and the metal silver layer 242 is completely coated on the surface of the metal layer 241. In this embodiment, the metal silver layer 242 can deposit a thin film metal layer (metal silver layer 242) on the metal layer 241 through a chemical metal replacement process such as electroless plating or chemical deposition, and the thin metal layer (metal silver layer) 242) The surface of the metal layer 241 is completely covered to have a sufficient contact area between the metal layer 241 and the metallic silver layer 242. Finally, referring to FIG. 2F, the metal layer 241 and the metallic silver layer 242 are melted by a reflow process under a temperature condition sufficient to melt the plated metal layer 241 $ and the chemically deposited metal silver layer 242. Alloy conductive bumps 24. Since the metal layer 241 and the metal silver layer 242 have a sufficient contact area, the metal material of the metal layer 241 and the metal silver layer 242 can be sufficiently mixed to form a uniform alloy conductive bump 24 (tin-silver conductive bump). . For the second embodiment, please refer to FIGS. 3A to 3G, which are flowcharts showing the method for manufacturing the alloy conductive bump of the electrical connection pad of the circuit board according to the second embodiment of the present invention. The following 10 19431 (revision) 1334207 is combined with the third embodiment. 3G is a detailed description of the technique of the present invention and (4) is the same as that of the first embodiment to simplify the description. Re-repeating 5 brothers, please refer to the f 3A diagram, providing a circuit board 20^ having a plurality of electrical connections ,, the surface of the circuit board 2G is formed with an insulating protective layer ^, and the insulating protective layer 2 1 and ancient AT. BB -71 〇·, Λ whole. The number of openings 2 is exposed to the electrical connections. Referring to FIG. 3B, the insulating protective layer 2 is exposed on the surface of the insulating protective layer 21; the electrical connection of the plurality of openings 21〇: (4) the surface forms a conductive The layer 22' of the conductive layer 22 is mainly used as a current conduction path required for the metal material of the electric clock to be described later. A resist layer is formed on the surface of the conductive layer 22, and a plurality of openings 23 () are formed on the resist layer 23 to expose the conductive layer 22 on the upper surface of the electrical connection pads 200. Referring to FIG. 3C, in the opening 23 of the resist layer 23, a conductive pillar 201 is formed by a key, and the conductive pillar 2G1 covers the electrical connection port. Wherein, the conductive column 2〇1 is a metal conductive column, and the metal (4) refining point temperature should be higher than the remelting temperature of the subsequent reflow process, so it will not reproduce in the subsequent reflow process and affect the alloy conduction. The alloy in the bump is θ 份 0. Please refer to the f 3D diagram of the opening 23 of the resistor 23 and the conductive pillar 2 〇 1 to form a metal layer 241 (electroplated metal layer), wherein the metal layer The metal material of 24! is tin (Sn). Since the conductive connecting layer 2 and the metal layer 241 are formed with the conductive layer 2, the metal plating material of the metal layer 241 deposited in the opening 230 can be saved. 19431 (Revised) 11 1334207 Referring to Figure 3E, the resist layer 23 and the conductive layer 22 it covers are removed by, for example, a chemical liquid stripping process. Please refer to FIG. 3F for surface-coating a metal silver layer 242 (thin film metal layer) on the metal layer 241 by a chemical gold substitution process such as electroless plating or chemical deposition, and completely coating the metal silver layer 242. The surface of the metal layer 241 and the surface of the conductive pillar 2〇1. Finally, please refer to FIG. 3G to make the metal layer 241 and the gold-colored silver layer by the reflow process under the temperature condition of the metal layer 241 of the electroplated deposition and the metal silver layer 242 of the chemically-deposited deposition. 242 is fused to form an alloy conductive bump 24 (tin-silver conductive bump). Table τ, just described, 'the invention firstly forms a metal layer (electroplated metal layer) on an electrical connection pad exposed on the resist layer through an electroplating process, and then passes the electroless plating or chemical deposition chemistry after removing the resist layer. The metal replacement process completely coats the gold layer (the thin film metal layer) with the metal layer, and finally dissolves the metal layer and the metallic silver layer into an alloy conductive bump by a reflow process. Since the metal silver layer is thin and easy to control, and is not restricted by the resist layer, the outer surface (upper surface and side surface) of the metal layer can be completely covered, and the electric deposit is deposited in the foot X. Under the temperature condition that the metal layer and the chemically deposited metal silver layer are melted, the metal layer and the metal silver layer are easily mixed due to having a sufficient contact area, thereby forming an alloy conductive convex having a uniform alloy composition and a good strength. Piece. Therefore, the electrical uniformity and bonding strength of the present invention are strong to increase the alloy composition and thereby improve the electrical conductivity of the alloy conductive bumps. With the invention, the present invention is to deposit a metal layer on the circuit of the circuit by means of electroplating and chemical replacement without the need for material plating conditions (Electricity) 9431 (Revision) (3) 4207 chain thickness) The clock liquid is electroplated. Therefore, the method for manufacturing the alloy conductive bump of the electrical connection pad of the present invention can facilitate controlling the alloy composition in the V-electrode bump, thereby reducing the complexity of the process. The above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Any person skilled in the art can modify and modify the above embodiments with the spirit and scope of the present invention. Therefore, the scope of the invention is set forth in the scope of the claims. , the nail is called a patent _ [Simple diagram of the diagram] The pad is a section (4), which is a flow chart showing the method of manufacturing an alloy conductive bump of a conventional circuit board electrical connection pad; FIGS. 2A to 2F are cross-sectional views showing the invention The first step of the circuit board electrical i-car technology ·> a, the fifth step of the method of the method of the bumps; and the 3G figure is a cross-sectional view, showing the electrical connection pads of the circuit board The process steps of the golden bump manufacturing method of the whole guide. [Major component symbol description] 10, 20 circuit board 100, 200 electrical connection pads 11, 21 insulation protection layer 110 ' 130, 210, 23 opening 12 ' 22 conductive layer 13, 23 resistance layer 14, 24 alloy conductive bump 141, 241 metal layer 19431 (revision) 13 1334207 142 second metal layer 242 metal silver layer 201 conductive column
14 19431(修正版）14 19431 (revision)