TWI331393B - Memory device and method of fabricating the same - Google Patents
Memory device and method of fabricating the same Download PDFInfo
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1331393 修正日期:99年5月25曰 第96105263號專利說明書修正本 九、發明說明: 【發明所屬之技術領域】 本發明係關於一種記憶體裝置,特別是有關於一種具 有記憶體裝置之導線結構及其製造方法。 【先前技術】 積體電路的發展技術日新月異,其發展趨勢往功能強 大,尺寸縮小與速度加快的方向前進,而動態隨機存取記 憶體(DRAM)的製造技術亦是如此,尤其是其記憶容量的 增加更是最重要的關鍵。 現今大多數的DRAM單元是由一個電晶體與一個電容 器所構成,目前的設計係搭配一種深溝渠電容器(deep trench capaci tor ),將三維的電容器結構製作於半導體 矽基底内的深溝渠中,可以縮小記憶單元的尺寸與電力消 耗,進而加快其操作速度。由於目前DRAM之記憶容量已 達到256百萬位甚至512百萬位元以上,在元件積集度要 求越來越高的情況下,記憶單元與電晶體的尺寸需要大幅 縮小,才可能製造出記憶容量更高,處理速度更快的DRAM。 請參閱第1圖,係繪出傳統記憶體裝置10之剖面示 意圖。一半導體矽基底12内製作有一深溝渠電容器20, 包含一埋入式下電極板(buried plate) 14、一節點介電 層(node dielectric) 16以及一上電極板18。深溝渠電 容器20之形成,首先係利用反應性離子蝕刻(RIE),於 P型半導體矽基底12内形成深溝渠,然後,藉由一重度 摻雜氧化物(例如:砷玻璃(ASG))以及高溫短時間的退1331393 Revision Date: Patent Specification No. 96105263, May 25, 1999, the present invention is related to the invention. And its manufacturing method. [Prior Art] The development technology of integrated circuits is changing with each passing day, and its development trend is moving toward powerful functions, size reduction and speed acceleration, and the manufacturing technology of dynamic random access memory (DRAM) is also the case, especially its memory capacity. The increase is the most important key. Most of today's DRAM cells are made up of a transistor and a capacitor. The current design is paired with a deep trench capaci tor, which is fabricated in a deep trench in the semiconductor germanium substrate. Reduce the size and power consumption of the memory unit, thus speeding up its operation. Since the memory capacity of DRAM has reached 256 million bits or even 512 million bits or more, the memory cell and the size of the transistor need to be greatly reduced in order to create a memory in the case where the component accumulation requirement is higher and higher. Higher capacity, faster processing DRAM. Referring to Figure 1, a cross-sectional view of a conventional memory device 10 is depicted. A deep trench capacitor 20 is fabricated in a semiconductor germanium substrate 12, including a buried lower plate 14, a node dielectric 16 and an upper electrode plate 18. The deep trench capacitor 20 is formed by first forming a deep trench in the P-type semiconductor germanium substrate 12 by reactive ion etching (RIE), and then by heavily doping an oxide (for example, arsenic glass (ASG)) and High temperature for a short time
0548-A50285-TW 第96105263號專利說明書修正本 ,修正曰期·· 99年5月:κ 口 火製程’可使n+型離子 月。日 域,而形成- ΓΗ型擴散區J S 渠下方區 的埋入式下電極板;於深溝竿下:才;:::溝,電容器20 成-氮切層,料料=與底部形 I),並喊(吻s)第-多層叫 以形成深溝渠電容器20的上電極板18。 〜則可 接^先於深溝渠上方區域的側壁上製作—領型 a“lel:ctric) 22,再於深溝渠上方區域内: 作曰雜之第二多晶矽層Π) 24 ’再繼續製 一夕日日矽層(Bs p〇iy) 26。後續則可進行一淺意 :隔離區⑽)32、字元線WL1、WL2、源 r; ,、位元接觸插塞BC以及位元、線BL等製程,#中淺“; :::二2是用來區分兩相鄰之DRAM胞或定義記憶體裝▲ 此外,為了連接深溝渠電容器20以及表面 f,深溝渠之頂部開口周圍的矽基底12内形成有—埋= 贡外擴政區域(buried strap outdif fusion) 28,亦稱 =為;節點接合介面(n〇de junc1:i〇n),其形成方式是使 第二多晶矽層24内之n+型離子經由第三多晶矽層別而 向外擴散至鄰近的發基底12中。因此,第三多晶石夕層26 也稱為一埋入帶多晶矽層(BS poly) 26。領型介電層22 之目的是使隔絕埋入帶外擴散區域28與埋入電極板14 之間達到有效的隔絕,以防止此處的漏電流問題 (vertical leakage)增加 DRAM 胞之保留時間(retenti〇n time) °0548-A50285-TW Amendment No. 96105263 Patent Specification, Amendment Period · May, 1999: κ mouth fire process ' can make n+ type ions month. The Japanese domain forms a buried lower electrode plate in the lower part of the JS channel in the ΓΗ-type diffusion zone; in the deep trench: only:::: trench, capacitor 20 into a nitrogen-cut layer, material = and bottom shape I) And shouting (kiss s) the first-multilayer is called to form the upper electrode plate 18 of the deep trench capacitor 20. ~ can be made before the side wall of the area above the deep trench - collar type "lel:ctric" 22, and then in the upper area of the deep trench: as the second polycrystalline layer of noisy) 24 'Continue Bs p〇iy 26. Afterwards, a shallow meaning can be made: isolation area (10) 32, word line WL1, WL2, source r; , bit contact plug BC and bit, Line BL and other processes, #中浅"; ::: 2 2 is used to distinguish two adjacent DRAM cells or define memory ▲ In addition, in order to connect the deep trench capacitor 20 and the surface f, around the top opening of the deep trench A buried strap outdif fusion 28 is also formed in the base 12, and is also referred to as a node bonding interface (n〇de junc1: i〇n), which is formed by making the second polycrystal The n+ type ions in the germanium layer 24 diffuse outward into the adjacent hair substrate 12 via the third polysilicon layer. Therefore, the third polycrystalline layer 26 is also referred to as a buried polycrystalline layer (BS poly) 26. The purpose of the collar dielectric layer 22 is to achieve effective isolation between the buried buried out-of-band diffusion region 28 and the buried electrode plate 14 to prevent the vertical leakage here from increasing the retention time of the DRAM cell ( Retenti〇n time) °
0548-A50285-TW 1331393 ‘ 第96】05263號專利說明書修正本 修正曰期:99年5月25曰 然而,傳統之領型介電層22、第二多晶矽層(Poly 11 ) 24、第三多晶矽層26之導線結構,影響埋入帶外擴散區 域28的分佈,以及電晶體與深溝渠之重疊容忍度,在記 憶體裝置尺寸繼續縮小時,導致埋入帶外擴散區域28處 發生嚴重的漏電流,並產生次臨界電壓(sub-Vt)的問題。 此外,隨著更先進製程而繼續微縮記憶體裝置之尺寸 時,導線結構之第二多晶矽層(Poly II) 24的阻值影響 變的更為嚴重,高阻值及其電阻電容延遲效應(RC delay),將影響記憶體裝置之運作。 胃 因此,需要一種新的記憶體裝置導線結構,以解決埋 入帶外擴散區域28的分佈所產生的問題,改善次臨界電 壓(sub-Vt)的問題,以及改善導線結構之阻值及電阻電 容延遲效應(RC delay)。 【發明内容】 本發明提供一種記憶體裝置,包含:一基底,具有一 深溝渠及一上表面;一深溝渠電容器,位於該深溝渠下 • 部;一導線結構,位於該深溝渠内之該深溝渠電容器上 方,其中該導線結構包含:一導電層連接該深溝渠電容 器、一領型介電層位於深溝渠側壁以包圍該導電層、及一 埋入帶層位於該領型介電層上方並鄰接該導電層;以及一 埋入帶阻擋層,位於該領型介電層上方之深溝渠側壁鄰接 該基底及該埋入帶層。 本發明提供一種記憶體裝置的製造方法,包含:提供 一基底;形成一深溝渠於該基底中;形成一深溝渠電容器 於該深溝渠下部;形成一頜型介電層於該深溝渠電容器上0548-A50285-TW 1331393 'No. 96】05263 Patent Specification Revision This revision period: May 25, 1999 However, the traditional collar dielectric layer 22, the second polysilicon layer (Poly 11) 24, The wire structure of the tripoly germanium layer 26 affects the distribution of the buried out-of-band diffusion region 28 and the overlap tolerance of the transistor and the deep trench, and causes the buried out-of-band diffusion region 28 to be buried as the size of the memory device continues to shrink. A serious leakage current occurs and a sub-voltage (sub-Vt) problem occurs. In addition, as the size of the memory device continues to be reduced with more advanced processes, the resistance of the second polysilicon layer (Poly II) 24 of the wire structure becomes more severe, the high resistance value and the delay effect of the resistor and capacitor. (RC delay), which will affect the operation of the memory device. The stomach therefore requires a new memory device wire structure to solve the problems caused by the distribution of the buried out-of-band diffusion region 28, improve the sub-critical voltage (sub-Vt) problem, and improve the resistance and resistance of the wire structure. RC delay. SUMMARY OF THE INVENTION The present invention provides a memory device comprising: a substrate having a deep trench and an upper surface; a deep trench capacitor located under the deep trench; a wire structure located in the deep trench Above the deep trench capacitor, wherein the wire structure comprises: a conductive layer connecting the deep trench capacitor, a collar dielectric layer on the sidewall of the deep trench to surround the conductive layer, and a buried strap layer above the collar dielectric layer Adjacent to the conductive layer; and a buried barrier layer, the deep trench sidewalls above the collar dielectric layer abut the substrate and the buried strap layer. The present invention provides a method of fabricating a memory device, comprising: providing a substrate; forming a deep trench in the substrate; forming a deep trench capacitor in the lower portion of the deep trench; forming a jaw dielectric layer on the deep trench capacitor
0548-A50285-TW 弟96105263號專利說明書修正本 方之該深溝渠側壁;形成 =正日期:"年5月25日 ^ vrn Φ ^ 、, V电層於該洙溝渠内鄰接該深 領型介電層所包m形成一埋入 結介電層上方並鄰接該導電層,以形成導線 【實施方式】 性,::例:實施方式之描述係關連至所屬圖示之易讀 關部實施方式之一部份,在實施方式中,相 ,名稱用詞例如「較低、較上、水平、垂直、上、下 :此^部等」及其衍生詞彙皆須參考圖示中所繪之方向: 關名稱用詞僅便於實施方式描述之便利性,而不需 ^方向上建構或操作儀器設備。名稱用詞 如「連接、互連、耦合等」係有關於其中之^ 、過中間結構與另一物體緊連或黏合,φ包含可動 式或剛性連接,除非有另外描述。 考第2圖,提供—基底112,該基底112例如是由 m;’: 1成之基底,其次,於基底112表面形成一墊層, 二一 I先沉積—氧切墊層114覆蓋該基底112,然後沉 鼠化石夕墊層116覆蓋該氧化石夕墊層114。以塾層作為 幕藉由使用微影製程及反應性離子姓刻(RIE )势、, 於基底112内形成深溝渠118。 、 ^士第3圖,接著進行深溝渠電容器13Θ的製作,深 溝渠電容器一般包括埋入式下電極板、節點介電層及上電 ,板’而以下實施例則僅為方便說明起見,其不應用以限 ^本發明。首先可藉由一重度摻雜氧化物,例如砷玻璃 ASG ) ’以及高溫短時間的退火製程(RTp ),使型離0548-A50285-TW The patent specification of 96105263 modifies the side wall of the deep trench of the party; formation = positive date: " May 25th ^ vrn Φ ^ , , V electric layer adjacent to the deep collar type in the trench The dielectric layer comprises a dielectric layer formed over the buried dielectric layer and adjacent to the conductive layer to form a conductive line. [Example]: The description of the embodiment is related to the implementation of the easy-to-read part of the figure. Part of the method, in the embodiment, the name, the wording of the name such as "lower, upper, horizontal, vertical, upper and lower: this part, etc." and its derivative words must refer to the figure Direction: The term name is used only to facilitate the convenience of the description of the implementation, without the need to construct or operate the equipment. Names such as "join, interconnect, couple, etc." are related to ^, the intermediate structure is closely attached or bonded to another object, and φ contains a movable or rigid connection unless otherwise described. Referring to FIG. 2, a substrate 112 is provided. The substrate 112 is, for example, a substrate formed of m; ':1, and secondly, a pad layer is formed on the surface of the substrate 112. The II-I deposit-oxygen pad layer 114 covers the substrate. 112, then a ratification fossil mat 116 covers the oxidized stone mat 114. The deep trenches 118 are formed in the substrate 112 by using the lithography layer as a screen by using a lithography process and a reactive ion surname (RIE) potential. ^, Figure 3, followed by the fabrication of deep trench capacitors 13Θ, deep trench capacitors generally include buried lower electrode plates, node dielectric layers and power-on, board' and the following examples are for convenience only. It is not intended to limit the invention. First, the type can be separated by a heavily doped oxide, such as arsenic glass ASG) and a short-time annealing process (RTp).
0548-A50285-TW 1331393 “ 第96105263號專利說明書修正本 修正日期:99年5月25日 子,例如As—,擴散至深溝渠118下方區域,形成一 n+型 擴散區,用來作為深溝渠電容器130的埋入式下電極板 ' 124。其次形成一介電層於深溝渠118下方區域之内側壁 ' 與底部,其材料可包含氮化矽或氧化矽,用來作為深溝渠 電容器130的節點介電層126;以及於深溝渠内沉積一 n+ 型摻雜之第一多晶石夕層(Poly I ),並回姓(recess )第一 多晶矽層至一預定深度,用來作為深溝渠電容器130的上 電極板128。 完成上述之深溝渠電容器130之後,於深溝渠電容器 胃 130上方區域的深溝渠118側壁上形成一領型介電層 (collar dielectric) 122。舉例而言,領型介電層可選擇採 用下列製程步驟完成,例如可先藉由低壓化學氣相沉積法 (LPCVD),於晶圓表面沉積一氧化矽層,其覆蓋第一多 晶矽層128、深溝渠118、氧化矽墊層114及氮化矽墊層 116,具有一厚度約305±3〇A ;再藉由一快速熱製程 (RTP),緻密化該氧化矽層,厚度變為130±13A ;然後 蝕刻該氧化矽層,使之露出第一多晶矽層128及氮化矽墊 • 層116之上表面,形成一領型氧化矽層,該領型氧化矽層 覆蓋深溝渠118之側壁及氧化矽墊層114之側壁,此作用 亦在保護氧化矽墊層114不受後續製程所侵害。0548-A50285-TW 1331393 "Patent Specification No. 96105263 Amendment Revision Date: May 25, 1999, for example, As-, diffuses into the area below the deep trench 118 to form an n+ type diffusion region for use as a deep trench capacitor 130 The buried lower electrode plate '124. Secondly, a dielectric layer is formed on the inner sidewall 'and the bottom of the region below the deep trench 118, and the material thereof may include tantalum nitride or tantalum oxide for use as a node of the deep trench capacitor 130. An electric layer 126; and depositing an n+-type doped first polycrystalline layer (Poly I) in the deep trench, and returning the first polycrystalline germanium layer to a predetermined depth for use as a deep trench The upper electrode plate 128 of the capacitor 130. After completing the deep trench capacitor 130 described above, a collar dielectric 122 is formed on the sidewall of the deep trench 118 in the region above the deep trench capacitor stomach 130. For example, the collar type The dielectric layer can be selected by the following process steps. For example, a ruthenium oxide layer can be deposited on the surface of the wafer by low pressure chemical vapor deposition (LPCVD), which covers the first polysilicon layer 128, the deep trench 118, oxygen The ruthenium pad layer 114 and the ruthenium nitride pad layer 116 have a thickness of about 305±3 〇A; and the yttrium oxide layer is densified by a rapid thermal process (RTP) to a thickness of 130±13 A; The ruthenium oxide layer is exposed to the upper surface of the first polysilicon layer 128 and the tantalum nitride pad layer 116 to form a collar type ruthenium oxide layer covering the sidewall of the deep trench 118 and the ruthenium oxide layer. The sidewall of the pad layer 114 also serves to protect the yttrium oxide pad layer 114 from subsequent processes.
參考第4圖,接著需形成導線結構140之導電層132, 其位於深溝渠118内,鄰接該深溝渠電容器130,主要是 上電極板128,且該導電層132由領型介電層]22所包圍。 本實施例則以具導電性之金屬化合物來取代多晶矽材 料,以下則以氮化鈦(TiN)為例,其中,於形成氮化鈦 之前,可進行一預先清洗步驟,如藉由使用氨水NH40H 0548-A50285-TW 9 1331393 f ___正本 赃_: 99年5月?5日 (DHF)以清除晶圓上的雜質;於深溝渠 積法&方法係包含化學氣相沉 去彳卜&勒,^可進仃一化學機械研磨製程(CMP), =除鼠 =墊層116上不必要之氮化鈦,露出氮化石夕 =二接?Γ氮化鈦,例如可使用含硫酸及過氧 &表面之既疋冰度,以形成導線結構導 祕狀方式_領型氧切層mi 'θ 之/木度,以控制記憶體裝置此處之導電路 控制電流大小及深溝渠電容ϋ 130之有效儲 存電何蚪間。本發明之實施例中,導 巧等金屬化合物取代多晶侧曰(亦即、= 可避免多晶石夕材料中之摻雜物離子, 於後續製程中擴散至基底112 申離子(Α〇, 处.☆〜底 *影響記憶體裝置之效 月匕,因此貫鈿例優點之一,可有效控制埋入 外擴散區域的分佈,提高電 ( ,容忍度’在記憶體裝置尺寸繼續縮小時,可 流的產生,以改盖次臨《雷厭 咸y漏电 P箬争參、隹制$。 ,電1 (Sub-Vt)的問題;此外, f二 繼續微縮記憶體裝置之尺寸時,包含 〇.lMm以下製程,本發明實 才匕各 之電阻0㈣㈣sii吻),可具有較低 delay)。接著進行一預先清电應, 液(歷ι·υ,以清除晶圓上雜/使—鼠酸溶 在本發明之實施例中,可形成—埋 例如由薄氮化物或氧化物材料所構成層1j4, 或氮化石夕層。埋入帶阻稽層134—般係二該領二介Referring to FIG. 4, a conductive layer 132 of the wire structure 140 is formed, which is located in the deep trench 118 adjacent to the deep trench capacitor 130, mainly the upper electrode plate 128, and the conductive layer 132 is formed by a collar dielectric layer] Surrounded by. In this embodiment, the polycrystalline germanium material is replaced by a conductive metal compound. Hereinafter, titanium nitride (TiN) is taken as an example. Before the titanium nitride is formed, a pre-cleaning step can be performed, for example, by using ammonia water NH40H. 0548-A50285-TW 9 1331393 f ___正本赃_: May 99? 5th (DHF) to remove impurities on the wafer; in the deep trench method & method includes chemical vapor deposition, and can be used in a chemical mechanical polishing process (CMP), = deratization = unnecessary titanium nitride on the pad layer 116, exposing the nitriding of the nitrite to the second layer of titanium nitride, for example, the surface of the sulphuric acid and the peroxygen-containing surface can be used to form a wire structure. _ Collar oxygen cut layer mi 'θ / wood degree, to control the memory device here control circuit current and deep trench capacitance ϋ 130 effective storage power. In the embodiment of the present invention, a metal compound such as a derivative replaces the polycrystalline side enthalpy (ie, = can avoid dopant ions in the polycrystalline material, and diffuses to the substrate 112 in a subsequent process (Α〇, ☆~底* affects the effect of the memory device. Therefore, one of the advantages of the 钿 , 可 可 可 可 可 可 可 可 可 可 可 可 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋 埋The flow can be generated to replace the problem of "Thunder", "Throat", and "Sub-Vt"; in addition, f2 continues to reduce the size of the memory device, including 〇.lMm the following process, the present invention is the actual resistance of each of the 0 (four) (four) sii kiss), can have a lower delay. Then carry out a pre-clearing electricity, liquid (recorded to remove the miscellaneous / make - mouse The acid is dissolved in the embodiment of the present invention, and a layer 1j4 composed of a thin nitride or an oxide material, or a layer of nitride nitride can be formed, for example, buried in the barrier layer 134.
0548-A50285-TW 10 ^96105263 赃圓:99年5月25日 112 术側壁’覆蓋露出之基底]】2,鄰接基底 ]34且右二程所形成之埋入帶層136 ;此埋入帶阻撞層 ’、有 尽度約5至7Α,可用lv、态木k丘丨祕7 _la 度及控制電流。 A 了用以適當控制離子擴散程 麥考第5圖,接著進行埋入帶層(BS) 136的製作, ,於5玄領型介電層122上方並鄰接導電層132,以形成導 、、-口構f,例中該埋入帶層材質係以非晶石夕(咖啡〇如 I:: A例,形成埋入帶層136,填入之前蝕刻領型氧 =2=細縫中,覆蓋導電層132及基底ιΐ2; 工可在500 c環境中,沉積約3〇〇a (AMORPHOUS Silicon)。 〈非日日石夕 •辟2第6f,之後可藉由使用濕飯刻製程,钱刻埋入 :;11“ 出導電層132、氮化矽墊層116、氧化矽 制! H分基底112,完成埋入帶層⑽)136的 ,,形成導線結構U0。在本發明之實施例中,因為以 ίΓ鈦等金屬化合物取代多晶矽材料(亦即 10 ’摻雜物之來源僅可能來自埋入帶層136,因此所妒 廣二區域138 ’具有較低之分佈,可改善‘ k界电壓(sub-Vt)的問題。 山:考第7圖,接著需形成一淺溝槽絕緣層(STI) 142, =’、線、、。構140之部分上方區域,本實施例可利用傳統 丁’進行一微影製程以定義出淺溝槽絕: 後沉疒氧切層,對晶圓進行一平坦化製程,以二^ 化石夕層116及氧化石夕墊層114,形成記憶體裝置刚之0548-A50285-TW 10 ^96105263 Round: May 25, 1999 112 The sidewall of the surgical 'covers the exposed base】] 2, adjacent to the base] 34 and the right second pass formed by the buried layer 136; this buried zone The barrier layer 'has a degree of about 5 to 7 Α, and can use lv, state wood k 丨 secret 7 _ la degree and control current. A is used to properly control the ion diffusion process, and the fabrication of the buried layer (BS) 136 is performed on the 5th dielectric layer 122 and adjacent to the conductive layer 132 to form a conductive layer. - the mouth structure f, in the example, the material of the buried layer is made of amorphous stone (coffee such as I:: A, forming a buried layer 136, and etching the collar oxygen before filling = 2 = slit) Covering the conductive layer 132 and the substrate ιΐ2; it is possible to deposit about 3 〇〇a (AMORPHOUS Silicon) in a 500 c environment. <Non-day shi shi shi 2, 6f, then by using a wet rice engraving process, money The conductive structure 132, the tantalum nitride layer 116, the yttrium oxide layer, the H-substrate 112, and the buried layer (10) 136 are formed to form the wire structure U0. In the embodiment of the present invention In the middle, since the polycrystalline germanium material is replaced by a metal compound such as titanium, (that is, the source of the 10' dopant is only likely to come from the buried layer 136, the wide area 138' has a lower distribution, which can improve the 'k boundary The problem of voltage (sub-Vt). Mountain: Test Figure 7, then form a shallow trench insulation layer (STI) 142, = ', line, ,. In the upper portion of the portion 40, this embodiment can perform a lithography process to define a shallow trench by using a conventional Ding: a post-deposited oxygen layer, and a planarization process is performed on the wafer to form a planarization layer 116. And the oxidized stone mat layer 114, forming a memory device just
0548-A50285-TW 1331393 第96105263號專利說明書修正本 修正日期:99年5月25曰 淺溝槽絕緣層(STI) 142,同時定義出記憶體裝置100之 主動區域(Active Area )(圖中未示)。 雖然本發明已以較佳實施例揭露如上5然其並非用以 限定本發明,任何熟悉此項技藝者,在不脫離本發明之精 神和範圍内,當可做些許更動與潤飾,因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 0548-A50285-TW 12 1331393 ‘ 第96105263號專利說明書修正本 修正日期:99年5月25曰 【圖式簡單說明】 _ 為了更完整闡述本發明内容及其中之益處,特對於圖 • 示内容作一說明: 第1圖係繪出傳統記憶體裝置之剖面示意圖。 第2至7圖係依據本發明之實施例,記憶體裝置製造 過程不同階段之剖面示意圖。 【主要元件符號說明】 基底〜12、112 ; 節點介電層〜16、126 ; 深溝渠電容器〜20、130 ; 第二多晶矽層〜24 ; 導電層〜132 ; 埋入帶層〜136 ; •,導線結構〜30、140 ; 氧化石夕墊層〜114 ; 記憶體裝置〜10、100 ;0548-A50285-TW 1331393 Patent Specification No. 96105263 Revision of this revision date: May 25, 1999, shallow trench insulation (STI) 142, and defining the active area of the memory device 100 (Active Area) Show). The present invention has been disclosed in the preferred embodiments of the present invention, and is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. 0548-A50285-TW 12 1331393 'Patent No. 96105263 Amendment Revision Date: May 25, 1999 [Simple Description of the Drawings] _ In order to more fully illustrate the contents of the present invention and its benefits, One explanation: The first figure is a schematic cross-sectional view of a conventional memory device. 2 through 7 are schematic cross-sectional views showing different stages of the manufacturing process of the memory device in accordance with an embodiment of the present invention. [Main component symbol description] substrate ~12,112; node dielectric layer ~16,126; deep trench capacitor ~20,130; second polysilicon layer ~24; conductive layer ~132; buried layer ~136; •, wire structure ~ 30, 140; oxidized stone mat layer ~ 114; memory device ~ 10, 100;
埋入式下電極板〜14、124 ; 上電極板〜18、128 ; 領型介電層〜22、122 ; 第三多晶碎層〜26 ; 埋入帶阻擋層〜134 ; 埋入帶外擴散區域〜28、138 淺溝槽絕緣層〜32、142 ; 氮化矽墊層〜116。Buried lower electrode plate ~14,124; upper electrode plate ~18,128; collar dielectric layer ~22,122; third polycrystalline layer ~26; buried with barrier layer ~134; buried outside the band Diffusion region ~ 28, 138 shallow trench insulation ~ 32, 142; tantalum nitride pad ~ 116.
0548-A50285-TW 130548-A50285-TW 13
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