TWI328343B

TWI328343B - Variable gain amplifier with gain adjusting circuit

Info

Publication number: TWI328343B
Application number: TW95149586A
Authority: TW
Inventors: Wen Chang Lee; Ying Che Tseng
Original assignee: Via Tech Inc
Priority date: 2006-05-11
Filing date: 2006-12-28
Publication date: 2010-08-01
Also published as: TW200743300A; CN101009479A; CN100578926C

Description

九、發明說明：【發明所屬之技術領域】本發明係關於一種具增益調整裝置之可調式增益放大器’特別是關於一種應用互補式金氧半導體之具增益調整裝置之可調式增益放大器。【先前技術】由於通訊科技的進步，無線通訊已被廣泛的使用於各種電子產品，現今通訊系統已進入第三代行動通訊（寛頻分碼多工接取 ’ Wideband Code Division Multiple Access， WCDMA)時代’故對於通訊品質的要求更加提高。另外，於WCDMA通訊系統中，因内部電路皆需使用放大器，故放大器的好壞直接影響通訊品質。對可調式增益放大器（Variable Gain Amplifier，VGA) 而言（以下簡稱為放大器），增益值係為放大器要項之一，如圖1所示，習知之放大器1包含一指數電流轉換電路 11、一電壓緩衝電路12以及一放大電路13,其中，電壓緩衝電路12係分別與指數電流轉換電路11與放大電路13 電性連接。另外’放大器1之作動方式如下：指數電流轉換電路11係自外部接收一電流控制訊號Icl，經由指數電流轉換電路11將電流控制訊號Icl轉換為一電流輸出訊號 1〇以送至電壓緩衝電路12，而電壓缓衝電路12係依據電流輸出訊號1〇以輸出電壓控制訊號Vcl至放大電路13 ’ 當放大電路13自外部接收一輸入訊號Input後，放大電路 1328343IX. INSTRUCTIONS OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to an adjustable gain amplifier with a gain adjustment device, particularly to an adjustable gain amplifier with a gain adjustment device using a complementary MOS. [Prior Art] Due to advances in communication technology, wireless communication has been widely used in various electronic products. Today's communication systems have entered the third generation of mobile communication (Wandaband Code Division Multiple Access, WCDMA) The era's requirements for communication quality are even higher. In addition, in the WCDMA communication system, since the internal circuit needs to use an amplifier, the quality of the amplifier directly affects the communication quality. For a Variable Gain Amplifier (VGA) (hereinafter referred to as an amplifier), the gain value is one of the main requirements of the amplifier. As shown in FIG. 1, the conventional amplifier 1 includes an exponential current conversion circuit 11 and a voltage. The buffer circuit 12 and the amplifying circuit 13 are electrically connected to the exponential current converting circuit 11 and the amplifying circuit 13, respectively. In addition, the operation mode of the amplifier 1 is as follows: the index current conversion circuit 11 receives a current control signal Icl from the outside, and converts the current control signal Icl into a current output signal 1〇 via the exponential current conversion circuit 11 to be sent to the voltage buffer circuit 12 The voltage buffer circuit 12 is based on the current output signal 1〇 to output the voltage control signal Vcl to the amplifying circuit 13'. When the amplifying circuit 13 receives an input signal Input from the outside, the amplifying circuit 1338343

G =G =

/ exp V 13係依據電壓控制訊號Vcl之調整而得到用以放大輸入訊號Input的較佳增益值’並以輸出訊號〇utput輸出。通常放大器1之放大電路13皆是使用BjT電晶體來達成該電路，但是因為使用BJT電晶體之製程較昂貴，且不易與互補式金氧半導體（complementary metal-oxide semiconductor，CMOS)製程相容，故近來則以M〇s電晶體取代。如圖2所示，以MOS電晶體達成之放大器2係包含一指數電流轉換電路21、一電壓緩衝電路22以及一放大電路23 ’其作動方式與上述放大器ι(如圖1所示）相同’而當指數電流轉換電路21之MOS電晶體工作於次臨界（sub-threshold)區時’則可達到與使用BJT電晶體之放大電路13時相同之功效。此時，電壓缓衝電路22之電晶體 Ql、Q2則工作於飽和（saturation)區，而電流增益〇則為：/ exp V 13 is based on the adjustment of the voltage control signal Vcl to obtain a better gain value for amplifying the input signal Input' and outputted as an output signal 〇utput. Generally, the amplifier circuit 13 of the amplifier 1 uses a BjT transistor to achieve the circuit, but since the process using the BJT transistor is expensive and difficult to be compatible with a complementary metal-oxide semiconductor (CMOS) process, Therefore, it has recently been replaced by an M〇s transistor. As shown in FIG. 2, the amplifier 2 realized by the MOS transistor includes an exponential current conversion circuit 21, a voltage buffer circuit 22, and an amplifying circuit 23' which are operated in the same manner as the above amplifier ι (shown in FIG. 1). When the MOS transistor of the exponential current conversion circuit 21 operates in the sub-threshold region, the same effect as when the amplifier circuit 13 of the BJT transistor is used can be achieved. At this time, the transistors Q1 and Q2 of the voltage buffer circuit 22 operate in a saturation region, and the current gain 〇 is:

GG

2 1 (-Rl*Icl^ 1 + 2顾 • * exp 、2nVr > IB J 若電晶體Q1工作於次^界區，且電晶體Q2工作於飽和區，則電流增益G為： nVr , 其中’ G為電、"il增益’ IB為偏壓電流(bias current)， II與12為分別流經電晶體Q1與Q2之電流，Ri為電阻， Icl為電流控制訊號，VT為臨界電壓。由於WCDMA通訊系統規格上的需求，使用m〇S電 7 1328343 晶體之放大器時，電流增益G需具有指數線性之特性，但是在實際應用時，不論電晶體Ql、Q2工作於那個區域，所得到的電流增益G皆具有指數非線性之特性。舉例來說，如圖3所示，其係為當使用MOS電晶體之放大器時電流增益G與電流控制訊號Icl之關係，其中斜率A的曲線係為電晶體Ql、Q2工作於飽和區的理想電流增益G，而斜率B的曲線係為電晶體Q1工作於次臨界區，且電晶體Q2工作於飽和區的理想電流增益G。但在實際應用時，當電流增益G為高增益時，電流增益G會跟斜率A的曲線相差至3dB左右的差距（如實線所示）。為了補償這3dB 左右的差距，通常會另外設計一增益補償電路來補償電流增益，而習知之增益補償電路體積龐大且複雜，這也會使得系統設計的難度大幅提升。承上所述，如何提供一種能夠解決上述問題之具增益調整裝置之可調式增益放大器，實屬當前重要課題之一。【發明内容】有鑑於上述課題，本發明提供一種可得到電流增益為指數線性之增益調整裝置及相關之可調式增益放大器。本發明提供一種應用於可調式增益放大器之增益調整裝置，包含一線性指數轉換迴路、一電壓緩衝迴路以及一冪次轉換迴路。線性指數轉換迴路係接收一線性控制訊號，並轉換線性控制訊號以輸出一指數控制訊號，而電壓緩衝迴路，係與線性指數轉換迴路電性連接以接收指數控 g 制訊號，並依據指數控制訊號與一偏壓電流以輸出一回授訊號至冪次轉換迴路，同時電壓緩衝迴路亦輸出—電壓^ 制訊號以控制可調式增益放大器的電流增益，冪次轉換ς 路係與線性指數轉換迴路與電壓緩衝迴路電性連接以接收指數控制訊號與回授職，並將指數控制訊號與回授訊號之乘積開方後乘2再加上偏壓電流以輸出一冪次訊號至線性指數轉換迴路。本發明又提供一種具增益調整裝置之可調式增益放 ^器’包含-增益調整裝置以及—放大電路，其中增益調整裝置包含一線性指數轉換迴路、一電壓緩衝迴路以及一冪次轉換迴路。線性減_迴路係接收—線性控制訊號並轉換線性控制訊號以輸出一指數控制訊號，電壓緩衝迴路係與線性指數轉換迴路電性連接以接收指數控制，號，並依據指數控制訊號與—偏壓電流以輸出一回授訊號至冪次轉換迴路，同時電壓緩衝迴路亦輸出一電壓控制 =號以控制放大電路的電流増益，冪次轉換迴路係與線性心數轉換迴路與電壓緩衝迴路電性連接以接收指數控制 π號與回m並將指數控制訊號與回授訊號之乘積開方後乘2再加上偏壓電流以輸出一冪次訊號至線性指數轉換迴路，放大電路則接收一輸入訊號，並與電壓緩衝迴路電性連接以接收電難制喊，並減電雜制訊號謂整放大電路之增益以放大輸入訊號。承上所述，因依據本發明之増益調整裝置及可調式増益放大器，係利用線性指數轉換迴路以輸出指數控制訊號 1328343 分別至電壓緩衝迴路及冪次轉換迴路，而電壓缓衝迴路係依據指數控制訊號及偏壓電流以輸出回授訊號至冪次轉換迴路，及輸出電壓控制訊號以控制放大器之電流增益，而冪次轉換迴路係依據指數控制訊號、回授訊號以及偏壓電流，先將指數控制訊號、回授訊號相乘後再開方乘2，再與偏壓電流相加而得到冪次訊號。與習知技術相較，由於增加冪次轉換電路，並與電壓緩衝迴路及線性指數轉換迴路相配合，使線性控制訊號及電壓控制訊號產生指數關係，進而使線性控制訊號與放大器之電流增益為對數線性關係，故使放大器因符合規格需求，即電流增益隨著線性控制訊號影響而呈現對數線性改變，而大大的提升了放大器品質而不需額外的增益補償電路。【實施方式】以下將參照相關圖式，說明依本發明實施例之具增益調整裝置之可.調式增益放大器，其中相同的元件將以相同的參照符號加以說明。請參照圖4所示，本發明實施例之增益調整裝置3係用以控制一放大電路6。其中，增益調整裝置3包含一線性指數轉換迴路31、一電壓緩衝迴路32以及一冪次轉換迴路33。圖5為顯示依本發明實施例之增益調整裝置3之電路之示意圖，。請同時參照圖4與圖5所示，線性指數轉換迴路31係包含一電阻R、一第一電晶體Ml以及一第二電晶 10 體M2。第一電晶體Ml之汲極係電性連接冪次轉換迴路 33以接收一冪次訊號Isc，而第一電晶體Ml之閘極係電性連接電阻R之一端與第一電晶體Ml之汲極。第二電晶體M2之閘極係接收一線性控制訊號Ic且電性連接電阻R 之另一端，並轉換線性控制訊號Ic以輸出一指數控制訊號 ID1於汲極，而指數控制訊號ID1並藉由電流鏡的方式分別複製並送至電壓缓衝迴路32及冪次轉換迴路33。再請同時參照圖4與圖5所示，電壓緩衝迴路32係包含一第三電晶體M3以及一第四電晶體M4,其中第三電晶體Μ 3之汲極係與線性指數轉換迴路31電性連接以接收指數控制訊號Idi ’而第四電晶體Μ4之源極係與第三電晶體M3之源極電性連接以產生一回授訊號ID2於汲極，並於第三電晶體M3之閘極以及第四電晶體M4之閘極產生一電壓控制訊號Vc以控制放大電路6。於本實施例中，第三電晶體M3以及第四電晶體M4係操作於飽和區。另外，電壓缓衝迴路32更包含一電流源I、一第一電流鏡以及一苐二電流鏡’其中電流源I係產生*一偏壓電流Ibias，第' 電流鏡係由電晶體Μ9與電晶體Μ10構成，並與電流源I 電性連接以複製偏壓電流IBIAS至第三電晶體M3以及第四電晶體M4之源極，而第二電流鏡則由電晶體M9、Mil、 M14與M15構成，並與電流源I電性連接以複製偏壓電流 Ibias至冪次轉換迴路33。於本實施例中，由於電壓緩衝迴路32、第一電流鏡以及第二電流鏡具有穩定電流之作用，故使電流不受原電路負載影響而跟著變動。 11 1328343 請同時參照圖4、圖5與圖6所示，冪次轉換迴路3 3 則包含一第五電晶體M5、一第六電晶體M6、一第七電晶體M7、一第八電晶體M8以及一第三電流鏡。第六電晶體 M6之汲極係電性連接第五電晶體M5之閘極，第六電晶體 M6之閘極係電性連接第五電晶體M5之源極，其中指數控制訊號ID1與回授訊號ID2係分別輸入至第五電晶體M5之汲極與第六電晶體M6之汲極，或指數控制訊號ID1與回授訊號ID2亦可分別輸入至第六電晶體M6之汲極與第五電晶體M5之汲極（圖未示）。第七電晶體M7之閘極係電性連接第五電晶體M5之閘極，第八電晶體M8之汲極係電性連接其閘極與第七電晶體M7之源極以產生一冪次轉換訊號IST，第三電流鏡係由電晶體M12與電晶體M13構成，且第三電流鏡與第七電晶體M7電性連接以複製冪次轉換訊號1st，其中幕次轉換訊號1st、指數控制訊號Idi與回授訊號〗D2之間的關係式為. ’ST = 2·\ΙIDl * ID2 ° 第三電流鏡並與第二電流鏡電性連接以將複製後之幕次轉換訊號1st與偏壓電流Ibias相加以產生幕次訊號 Isc，且輸出冪次訊號Isc至線性指數轉換迴路31，其中冪次訊號Isc、幕次轉換訊號1st與偏壓電流Ibias之間的關係式為. ’SC = ’BMS + * ’D2 ° 另外，本實施例中之第五電晶體M5、第六電晶體 M6、第七電晶體M7以及第八電晶體M8係操作於次臨界 12 1328343 區。再請參照圖4與圖5，本實施例之增益調整裝置3係作動如下：線性指數轉換迴路31係接收線性控制訊號Ic，並轉換線性控制訊號Ic以輸出指數控制訊號ID1，並將指數控制訊號ID1分別傳送至電壓緩衝迴路32與冪次轉換迴路33 ;此時，電壓缓衝迴路32内部之電晶體係操作於飽和區，而電壓緩衝迴路32係接收指數控制訊號ID1，並依據指數控制訊號ID1及電壓緩衝迴路32内部之偏壓電流 IbiaS，產生回授訊號ID2以輸入至冪次轉換迴路33，並於產生回授訊號ID2同時，亦產生電壓控制訊號Vc以控制放大電路6之電流增益Gi，以使放大電路6於外部接收輸入訊號Ip後，係依據電壓控制訊號Vc調整而放大輸入訊號 Ip為輸出訊號Op後輸出。而冪次轉換迴路33係接收指數控制訊號Idi、回授訊號ID2以及電壓缓衝迴路32内部之偏壓電流Ibias ’並將指數控制訊號〗D1、回授訊號Id2相乘後再開方乘2，再與偏壓電流IBias相加而得到幕次訊號 Isc，並將冪次訊號Isc傳送至線性指數轉換迴路31，此時，冪次轉換迴路33内部之電晶體則操作於次臨界區。當線性指數轉換迴路31接收冪次訊號Isc時，冪次訊號Isc與指數控制訊號〗di之間的關係式為. =-m________ = cxp-^—， I sc I BIAS 十 D D2 其中，Idi為指數控制訊號’〗D2為回授訊號’ Isc為幕次訊號’ Ic為線性控制訊號’ R為電阻’〗bias為偏壓電流’ 13 1328343 VT為臨界電壓。由於指數控制訊號ID1與線性控制訊號Ic呈指數關係，而電壓控制訊號Vc係隨著指數控制訊號影響而改變’故電壓控制訊號vc與線性控制訊號Ic呈指數關係。此時，接收電壓控制訊號vc之放大電路6所產生的電流增益Gi為：2 1 (-Rl*Icl^ 1 + 2 Gu • * exp , 2nVr > IB J If the transistor Q1 operates in the secondary region and the transistor Q2 operates in the saturation region, the current gain G is: nVr , where 'G is electricity, "il gain' IB is the bias current, II and 12 are the currents flowing through the transistors Q1 and Q2, respectively, Ri is the resistance, Icl is the current control signal, and VT is the threshold voltage. Due to the requirements of the specifications of the WCDMA communication system, the current gain G needs to have an exponential linearity when using an amplifier of the m〇S electric 7 1328343 crystal, but in practical applications, regardless of the operation of the transistors Q1 and Q2 in that region, The current gain G has an exponential nonlinear characteristic. For example, as shown in FIG. 3, it is a relationship between the current gain G and the current control signal Icl when an amplifier of the MOS transistor is used, wherein the curve of the slope A is The ideal current gain G for the transistors Q1 and Q2 operating in the saturation region, and the slope B curve is for the transistor Q1 to operate in the subcritical region, and the transistor Q2 operates at the ideal current gain G of the saturation region. However, in practical applications When the current gain G is high In time, the current gain G will differ from the slope A curve by about 3 dB (as indicated by the solid line). To compensate for this 3 dB difference, a gain compensation circuit is usually designed to compensate the current gain, while the conventional gain is used. The compensation circuit is bulky and complicated, which will greatly increase the difficulty of system design. As mentioned above, how to provide an adjustable gain amplifier with a gain adjustment device that can solve the above problems is one of the current important topics. SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a gain adjustment apparatus capable of obtaining an exponential linear current gain and a related adjustable gain amplifier. The present invention provides a gain adjustment apparatus for an adjustable gain amplifier, comprising a linear index a conversion loop, a voltage buffer loop, and a power conversion loop. The linear exponential loop receives a linear control signal and converts the linear control signal to output an exponential control signal, and the voltage buffer loop is electrically coupled to the linear exponential loop. Connect to receive the index control g signal And according to the index control signal and a bias current to output a feedback signal to the power conversion loop, and the voltage buffer circuit also outputs a voltage control signal to control the current gain of the adjustable gain amplifier, the power conversion circuit and the The linear exponential conversion loop is electrically connected to the voltage buffer loop to receive the exponential control signal and the returning duty, and the product of the exponential control signal and the feedback signal is squared, multiplied by 2, and the bias current is output to output a power signal to The present invention further provides an adjustable gain amplifier with a gain adjustment device, including a gain adjustment device and an amplification circuit, wherein the gain adjustment device comprises a linear exponential conversion circuit, a voltage buffer circuit and a power Secondary conversion loop. The linear subtraction_loop receives the linear control signal and converts the linear control signal to output an exponential control signal. The voltage buffer circuit is electrically connected to the linear exponential conversion circuit to receive the exponential control, the number, and the index control signal and the bias voltage. The current outputs a feedback signal to the power conversion loop, and the voltage buffer circuit also outputs a voltage control = number to control the current benefit of the amplifying circuit, and the power conversion circuit is electrically connected with the linear card number conversion circuit and the voltage buffer circuit. Controlling the π number and returning m with the receiving index and multiplying the product of the exponential control signal and the feedback signal by 2 and then adding the bias current to output a power signal to the linear exponential conversion circuit, and the amplifying circuit receives an input signal. And electrically connected with the voltage buffer circuit to receive power failure, and reduce the power of the mixed signal is the gain of the amplifier circuit to amplify the input signal. According to the above, the benefit adjusting device and the adjustable gain amplifier according to the present invention use a linear exponential conversion circuit to output an index control signal 1338343 to a voltage buffer circuit and a power conversion circuit, respectively, and the voltage buffer circuit is based on an index. Control signal and bias current to output feedback signal to power conversion loop, and output voltage control signal to control amplifier current gain, and power conversion loop is based on index control signal, feedback signal and bias current, first The exponential control signal and the feedback signal are multiplied and then multiplied by 2, and then added to the bias current to obtain a power signal. Compared with the prior art, the power conversion circuit is added, and the voltage buffer circuit and the linear exponential conversion circuit are matched, so that the linear control signal and the voltage control signal are exponentially related, so that the linear control signal and the current gain of the amplifier are The logarithmic linear relationship makes the amplifier exhibit a logarithmic linear change due to the specification requirements, that is, the current gain changes with the linear control signal, which greatly improves the amplifier quality without additional gain compensation circuit. [Embodiment] Hereinafter, a tunable gain amplifier having a gain adjusting device according to an embodiment of the present invention will be described with reference to the accompanying drawings, wherein like elements will be described with the same reference numerals. Referring to FIG. 4, the gain adjusting device 3 of the embodiment of the present invention is used to control an amplifying circuit 6. The gain adjustment device 3 includes a linear index conversion circuit 31, a voltage buffer circuit 32, and a power conversion circuit 33. Figure 5 is a diagram showing the circuit of the gain adjustment device 3 according to an embodiment of the present invention. Referring to FIG. 4 and FIG. 5 simultaneously, the linear exponential conversion circuit 31 includes a resistor R, a first transistor M1, and a second transistor 10 M2. The drain of the first transistor M1 is electrically connected to the power conversion circuit 33 to receive a power signal Isc, and the gate of the first transistor M1 is electrically connected to one end of the resistor R and the first transistor M1. pole. The gate of the second transistor M2 receives a linear control signal Ic and electrically connects the other end of the resistor R, and converts the linear control signal Ic to output an exponential control signal ID1 at the drain, and the index control signal ID1 is The current mirrors are copied and sent to the voltage buffer circuit 32 and the power conversion circuit 33, respectively. Referring to FIG. 4 and FIG. 5 simultaneously, the voltage buffer circuit 32 includes a third transistor M3 and a fourth transistor M4, wherein the third transistor of the third transistor Μ 3 is electrically connected to the linear index conversion circuit 31. The first connection of the fourth transistor Μ4 is electrically connected to the source of the third transistor M3 to generate a feedback signal ID2 at the drain, and is connected to the third transistor M3. The gate and the gate of the fourth transistor M4 generate a voltage control signal Vc to control the amplifying circuit 6. In the present embodiment, the third transistor M3 and the fourth transistor M4 are operated in a saturation region. In addition, the voltage buffer circuit 32 further includes a current source I, a first current mirror and a second current mirror 'where the current source I generates * a bias current Ibias, the 'current mirror is from the transistor 与 9 and the electricity The crystal crucible 10 is configured and electrically connected to the current source I to replicate the bias currents IBIAS to the sources of the third transistor M3 and the fourth transistor M4, and the second current mirror is composed of the transistors M9, Mil, M14 and M15. It is constructed and electrically connected to the current source I to replicate the bias current Ibias to the power conversion loop 33. In this embodiment, since the voltage buffering circuit 32, the first current mirror, and the second current mirror have a function of stabilizing current, the current is not affected by the original circuit load and is changed. 11 1328343 Please also refer to FIG. 4, FIG. 5 and FIG. 6, the power conversion circuit 3 3 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, and an eighth transistor. M8 and a third current mirror. The drain of the sixth transistor M6 is electrically connected to the gate of the fifth transistor M5, and the gate of the sixth transistor M6 is electrically connected to the source of the fifth transistor M5, wherein the index control signal ID1 and the feedback The signal ID2 is input to the drain of the fifth transistor M5 and the drain of the sixth transistor M6, respectively, or the index control signal ID1 and the feedback signal ID2 can be input to the drain and the fifth of the sixth transistor M6, respectively. The drain of the transistor M5 (not shown). The gate of the seventh transistor M7 is electrically connected to the gate of the fifth transistor M5, and the drain of the eighth transistor M8 is electrically connected to the gate of the gate and the seventh transistor M7 to generate a power The conversion signal IST, the third current mirror is composed of the transistor M12 and the transistor M13, and the third current mirror is electrically connected with the seventh transistor M7 to copy the power conversion signal 1st, wherein the scene switching signal 1st, the index control The relationship between the signal Idi and the feedback signal 〖D2 is . 'ST = 2·\ΙIDl * ID2 ° The third current mirror is electrically connected to the second current mirror to convert the copied screen transition signal 1st and partial The voltage current Ibias is added to generate the screen signal Isc, and the power signal Isc is outputted to the linear exponential conversion circuit 31, wherein the relationship between the power signal Isc, the screen switching signal 1st and the bias current Ibias is . 'BMS + * 'D2 ° In addition, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8 in this embodiment operate in the sub-critical 12 1328343 region. Referring to FIG. 4 and FIG. 5, the gain adjustment device 3 of the present embodiment operates as follows: the linear index conversion circuit 31 receives the linear control signal Ic, converts the linear control signal Ic to output the index control signal ID1, and controls the index. The signal ID1 is respectively transmitted to the voltage buffer circuit 32 and the power conversion circuit 33; at this time, the electro-crystal system inside the voltage buffer circuit 32 operates in the saturation region, and the voltage buffer circuit 32 receives the index control signal ID1 and is controlled according to the index. The signal ID1 and the bias current IbiaS inside the voltage buffer circuit 32 generate the feedback signal ID2 to be input to the power conversion circuit 33, and simultaneously generate the feedback signal ID2, and also generate the voltage control signal Vc to control the current of the amplifying circuit 6. The gain Gi is such that after the amplifier circuit 6 receives the input signal Ip externally, the input signal Ip is amplified according to the voltage control signal Vc and is output as the output signal Op. The power conversion circuit 33 receives the index control signal Idi, the feedback signal ID2, and the bias current Ibias ' inside the voltage buffer circuit 32, and multiplies the index control signal D1 and the feedback signal Id2 by two squares. Then, the threshold current Isc is added to obtain the screen signal Isc, and the power signal Isc is transmitted to the linear exponential conversion circuit 31. At this time, the transistor inside the power conversion circuit 33 operates in the subcritical region. When the linear exponential conversion circuit 31 receives the power signal Isc, the relationship between the power signal Isc and the exponential control signal 〗 Di is: =-m________ = cxp-^-, I sc I BIAS ten D D2 where Idi is The index control signal 'D2' is the feedback signal 'Isc is the screen signal' Ic is the linear control signal 'R is the resistance'〗 The bias is the bias current ' 13 1328343 VT is the threshold voltage. Since the index control signal ID1 is exponentially related to the linear control signal Ic, and the voltage control signal Vc is changed as the index control signal is affected, the voltage control signal vc is exponentially related to the linear control signal Ic. At this time, the current gain Gi generated by the amplifying circuit 6 receiving the voltage control signal vc is:

Gi νζτ+ν^οΓGi νζτ+ν^οΓ

則當電流增益Gi平方時，則與冪次訊號Isc與指數控制訊號ID1之間的關係式相等： _ ’D1 + ’D2 +Then, when the current gain Gi is squared, the relationship between the power signal Isc and the index control signal ID1 is equal: _ ’D1 + ’D2 +

IscIsc

Gi2 其中，Gi為電流增益’ ID1為指數控制訊號，為回授訊號’ Isc為冪次訊號，Ic為線性控制訊號，R為電阻， Ibias為偏壓電流’ VT為臨界電壓。由上述方程式中可得知，線性控制訊號Ic與電流增益Gi呈對數線性之關係。由於增益調整裝置3係利用冪次轉換迴路33將指數控制訊號ID1、回授訊號1〇2相乘後再開方乘2，再與偏壓電流IBIAS相加，以得到冪次訊號Isc，並藉由線性指數轉換迴路31與電壓缓衝迴路32而得到線性控制訊號Ic與電 14 壓控制訊號Vc為指益Gi呈對數線性 ’、’足線性控制訊號Ic與電流增 V linear in \ 路6符合規格需求， 15)關係’故使後級之放大電因而無需另外設計—而大大的提升了放大電路6之品質，地亦簡化了放大電敗3边補償電路來補償電流增益，相對請參照圖7所示6:::f難度。放大器4係包含一線性t明之另一實施例之可調式增益 42、一冪次轉換迴路'數轉換迴路4卜一電壓緩衝迴路本實施例之線性护^及―放大電路44。以及—冪次轉換迴路日43轉換迴路4i、電壓緩衝迴路42 施例中之線性指數轉換、回之作動、特徵及功效皆與前述實次轉換迴路33(如圖4、。路31、電壓缓衝迴路32以及冪本實施例之放大電:二相:’故此不再贅述。壓缓衝迴路42電性連接、’、接收一輸入訊號V並與電電塵控制訊號電馳職號V。，並依據 v並轉繼:=電：^之物放大輪入訊號，，’不上所述，因依據本發明之掸益放大器，_料性指_^以調式增分別至電壓緩衝迴路及冪次轉換: 依據指數控制訊號及偏壓電流以輪出回授訊換迴路，及輸出電壓控制訊號以控制放大器之電流增益，而冪次轉換迴路係依據指數控制訊號、回授訊號以及偏壓電流，先將指數控制訊號、回授訊號相乘後再開方乘2，再與偏壓電流相加而得到冪次訊號。與習知技術相較由 15 1328343 於增加冪次轉換電路，並與電壓緩衝迴路及線性指數轉換迴路相配合，使線性控制訊號及電壓控制訊號產生指數關係，進而使線性控制訊號與放大器之電流增益為對數線性關係，故使放大器因符合規格需求，即電流增益隨著線性控制訊號影響而呈現對數線性改變，而大大的提升了放大器品質而不需額外的增益補償電路。以上所述僅為舉例性，而非為限制性者。任何未脫離本發明之精神與範疇，而對其進行之等效修改或變更，均應包含於後附之申請專利範圍中。【圖式簡單說明】圖1為顯示習知之放大器之示意圖；圖2為顯示習知之MOS電晶體構成之放大器之電路之不意圖，圖3為顯示習知之電流增益與電流控制訊號之關係之不意圖，圖4為顯示依本發明實施例之增益調整裝置之示意圖，圖5為顯示依本發明實施例之增益調整裝置之電路之不意圖，圖6為顯示依本發明實施例之冪次轉換迴路之電路之示意圖；以及圖7為顯示依本發明另一實施例之可調式增益放大器之示意圖。 16 1328343 元件符號說明： 1、2、4 放大器 11、21 指數電流轉換電路 12 電壓缓衝電路 22 、 32 、 42 電壓緩衝迴路 6、13、23、44 放大電路 3 增益調整裝置 31、41 線性指數轉換迴路 33、43 冪次轉換迴路 A、B 斜率 G、Gi I 電流增益電流源 IB、IBIAS 偏壓電流 11、12 電流 Ic 線性控制訊號 Icl 電流控制訊號 Idi 指數控制訊號 Id2 回授訊號 Input ' Ip 輸入訊號 Io 電流輸出訊號 Isc 冪次訊號 1st 冪次轉換訊號 17 1328343Gi2 where Gi is the current gain' ID1 is the exponential control signal, the feedback signal ' Isc is the power signal, Ic is the linear control signal, R is the resistance, and Ibias is the bias current ' VT is the threshold voltage. As can be seen from the above equation, the linear control signal Ic is logarithmicly linear with the current gain Gi. Since the gain adjustment device 3 multiplies the exponential control signal ID1 and the feedback signal 1〇2 by the power conversion circuit 33, and then multiplies the square by 2, and then adds the bias current IBIAS to obtain the power signal Isc, and borrows The linear control signal Ic and the voltage 14 of the voltage buffer circuit 32 are obtained by the linear index conversion circuit 31 and the voltage buffer circuit 32. The voltage control signal Vc is logarithmic linear, and the linear control signal Ic is matched with the current increase V linear in \6 The specification requirements, 15) relationship 'so that the latter stage of amplification and thus no additional design - greatly improve the quality of the amplifier circuit 6, the ground also simplifies the amplification of the power failure 3 side compensation circuit to compensate the current gain, please refer to the figure 7 shows the difficulty of 6:::f. The amplifier 4 is comprised of a linear gain, an adjustable gain of another embodiment, a power conversion circuit, a digital conversion circuit, a voltage buffer circuit, and a linear protection circuit of the present embodiment. And - the power conversion circuit day 43 conversion circuit 4i, the voltage buffer circuit 42 in the embodiment of the linear exponential conversion, back to the action, features and effects are all with the aforementioned real conversion circuit 33 (Figure 4, the road 31, the voltage is slow The circuit 32 and the power of the power amplifier embodiment are two phases: 'There is no further description here. The voltage buffer circuit 42 is electrically connected, ', receives an input signal V and is electrically connected to the electric dust control signal V. And according to v and relay: = electricity: ^ the object to amplify the wheel signal, 'not mentioned, because the benefit amplifier according to the invention, _ material refers to _ ^ to increase the voltage buffer loop and power Sub-conversion: according to the index control signal and the bias current to rotate the feedback loop, and the output voltage control signal to control the current gain of the amplifier, and the power conversion loop is based on the index control signal, the feedback signal and the bias current First, the exponential control signal and the feedback signal are multiplied and then multiplied by 2, and then added to the bias current to obtain a power signal. Compared with the prior art, 15 1328343 is used to increase the power conversion circuit, and the voltage Buffer circuit and line The exponential conversion loop cooperates to make the linear control signal and the voltage control signal have an exponential relationship, so that the linear control signal and the current gain of the amplifier are log-linear, so that the amplifier meets the specification requirement, that is, the current gain is affected by the linear control signal. The logarithmic linear change is presented, and the quality of the amplifier is greatly improved without the need for an additional gain compensating circuit. The above is merely exemplary and not limiting. Any one without departing from the spirit and scope of the present invention Equivalent modifications or changes are to be included in the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram showing a conventional amplifier; FIG. 2 is a circuit showing an amplifier composed of a conventional MOS transistor. 3 is a schematic diagram showing a relationship between a conventional current gain and a current control signal, FIG. 4 is a schematic diagram showing a gain adjustment apparatus according to an embodiment of the present invention, and FIG. 5 is a diagram showing gain adjustment according to an embodiment of the present invention. The circuit of the device is not intended, and FIG. 6 is a diagram showing a power conversion circuit according to an embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Figure 7 is a schematic diagram showing an adjustable gain amplifier according to another embodiment of the present invention. 16 1328343 Component Symbol Description: 1, 2, 4 Amplifier 11, 21 Index Current Conversion Circuit 12 Voltage Buffer Circuit 22, 32, 42 voltage buffer circuit 6, 13, 23, 44 amplifier circuit 3 gain adjustment device 31, 41 linear exponential conversion circuit 33, 43 power conversion circuit A, B slope G, Gi I current gain current source IB, IBIAS bias Current 11, 12 Current Ic Linear Control Signal Icl Current Control Signal Idi Index Control Signal Id2 Feedback Signal Input ' Ip Input Signal Io Current Output Signal Isc Power Signal 1st Power Conversion Signal 17 1328343

Ml 第一電晶體 M2 第二電晶體 M3 第三電晶體 M4 第四電晶體 M5 第五電晶體 M6 第六電晶體 M7 第七電晶體 M8 第八電晶體 M9-M15 電晶體 Op ' Output 輸出訊號 Q1、Q2 MOS電晶體 R、R1 電阻 Vc -Vcl 電壓控制訊號 Vdd 電源 D 汲極 S 源極 18Ml first transistor M2 second transistor M3 third transistor M4 fourth transistor M5 fifth transistor M6 sixth transistor M7 seventh transistor M8 eighth transistor M9-M15 transistor Op ' Output output signal Q1, Q2 MOS transistor R, R1 resistance Vc - Vcl voltage control signal Vdd power supply D drain S source 18

Claims

十、申請專利範圍：卜一種應用於可調式增益放大器之增益調整裝置，包含：一線性指數轉換迴路，係接收一線性控制訊號，並轉換該線性控制訊號以輸出一指數控制訊號；一電壓緩衝迴路，係與該線性指數轉換迴路電性連接以接收該指數控制訊號，並依據該指數控制訊號與一偏壓電流以輸出一回授訊號，同時亦輸出一電壓控制訊號以控制一可調式增益放大器；以及一冪次轉換迴路，係與該線性指數轉換迴路與該電壓緩衝迴路電性連接以接收該指數控制訊號與該回授訊號，並將該指數控制訊號與該回授訊號之乘積開方後乘2再加上該偏壓電流以輸出一冪次訊號至該線性指數轉換迴路。 2、如申請專利範圍第1項所述之應用於可調式增益放大器之增益調整裝置，其中該線性控制訊號與該電壓控制訊號係呈指數關係，該線性控制訊號與該可調式增益放大器之一增益值係呈對數線性關係。 3、如申請專利範圍第1項所述之應用於可調式增益放大器之增益調整裝置，其中該線性指數轉換迴路係包含：一電阻；一第一電晶體，其汲極係電性連接於該冪次轉換迴路以接收該冪次訊號，其閘極係電性連接於該電阻之一 1328343 端與該第一電晶體之該汲極；以及一第二電晶體，其閘極係接收該線性控制訊號且電性連接於該電阻之另一端，並轉換該線性控制訊號以輸 - 出該指數控制訊號於其汲極。〜 4、如申請專利範圍第1項所述之應用於可調式增益放大 … 器之增益調整裝置，其中該電壓緩衝迴路係包含：一第三電晶體，其汲極係與該線性指數轉換迴路電性 • 連接以接收該指數控制訊號；以及一第四電晶體，其源極係與該第三電晶體之源極電性連接以產生該回授訊號於其汲極，並於該第三電晶體以及該第四電晶體之閘極產生該電壓控制訊號以控制該可調式增益放大器。 5、如申請專利範圍第4項所述之應用於可調式增益放大器之增益調整裝置，其中該第三電晶體以及該第四電 * 隸賴作於飽和卜 6、如申請專利範圍第4項所述之應用於可調式增益放大器之增益調整裝置，其中該電壓緩衝迴路更包含： - 一電流源，係產生該偏壓電流；一第一電流鏡，係與該電流源電性連接以複製該偏壓電流至該第三電晶體以及該第四電晶體之源極；以及一第二電流鏡，係與該電流源電性連接以複製該偏壓 20 1328343 電流至該冪次轉換迴路。 7、如申請專利範圍第6項所述之應用於可調式增益放大 • 器之增益調整裝置，其中該冪次轉換迴路係包含： . 一第五電晶體；一第六電晶體，其 >及極係電性連接該第五電晶體之閘 ·- 極，其閘極係電性連接該第五電晶體之源極，其中該指數控制訊號與該回授訊號係分別輸入至該第五電 • 晶體之汲極與該第六電晶體之汲極，或該指數控制訊號與該回授訊號係分別輸入至該第六電晶體之汲極與該第五電晶體之汲極；一第七電晶體，其閘極係電性連接該第五電晶體之閘極；一第八電晶體，其汲極係電性連接其閘極與該第七電晶體之源極以產生一冪次轉換訊號；以及一第三電流鏡，係與該第七電晶體電性連接以複製該 ^ 冪次轉換訊號，並與該第二電流鏡電性連接以將複製後之該冪次轉換訊號與該偏壓電流相加以產生該冪次訊號，且輸出該冪次訊號至該線性指數轉換迴路。 — 8、如申請專利範圍第7項所述之應用於可調式增益放大器之增益調整裝置，其中該冪次轉換訊號係將該指數控制訊號與該回授訊號相乘後再開方乘2而得到。 21 1328343 9、如申請專利範圍第7項所述之應用於可調式增益放大器之增益調整裝置，其中該第五電晶體、該第六電晶體、該第七電晶體以及該第八電晶體係操作於次臨界 - 區〇 … 10、一種具增益調整裝置之可調式增益放大器，包含： *· 一增益調整裝置，其包含：一線性指數轉換迴路，係接收一線性控制訊號，並轉 • 換該線性控制訊號以輸出一指數控制訊號；一電壓緩衝迴路，係與該線性指數轉換迴路電性連接以接收該指數控制訊號，並依據該指數控制訊號與一偏壓電流以輸出一回授訊號，同時亦輸出一電壓控制訊號；一冪次轉換迴路，係與該線性指數轉換迴路與該電壓緩衝迴路電性連接以接收該指數控制訊號與該回授訊號，並將該指數控制訊號與該回授訊號之乘積開 I 方後乘2再加上該偏壓電流以輸出一冪次訊號至該線性指數轉換迴路；以及一放大電路，係接收一輸入訊號，並與該電壓緩衝迴 ‘路電性連接以接收該電壓控制訊號，並依據該電壓 - 控制訊號調整該放大電路之增益以放大該輸入訊號。 11、如申請專利範圍第10項所述之可調式增益放大器， 22 1328343 其中該線性控制訊號與該電壓控制訊號係呈指數關係，該線性控制訊號與該放大電路之一增益值係呈對數線性關係。 . 12、如申請專利範圍第10項所述之可調式增益放大器，一其中該線性指數轉換迴路係包含： - 一電阻；一第一電晶體，其汲極係電性連接於該冪次轉換迴路 • 以接收該冪次訊號，其閘極係電性連接於該電阻之一端與該第一電晶體之該汲極；以及一第二電晶體，其閘極係接收該線性控制訊號且電性連接於該電阻之另一端，並轉換該線性控制訊號以輸出該指數控制訊號於其汲極。 13、如申請專利範圍第10項所述之可調式增益放大器，其中該電壓緩衝迴路係包含： ® —第三電晶體，其汲極係與該線性指數轉換迴路電性連接以接收該指數控制訊號；以及一第四電晶體，其源極係與該第三電晶體之源極電性連接以產生該回授訊號於其汲極，並於該第三電晶體以及該第四電晶體之閘極產生該電壓控制訊號。 14、如申請專利範圍第13項所述之可調式增益放大器，其中該第三電晶體以及該第四電晶體係操作於飽和 23 1328343 區。 15、如申請專利範圍第13項所述之可調式增益放大器， - 其中該電壓緩衝迴路更包含： . 一電流源，係產生該偏壓電流；一一第一電流鏡，係與該電流源電性連接以複製該偏壓 v · 電流至該弟二電晶體以及該第四電晶體之源極，以及 • 一第二電流鏡，係與該電流源電性連接以複製該偏壓電流至該冪次轉換迴路。 16、如申請專利範圍第15項所述之可調式增益放大器，其中該冪次轉換迴路係包含：一第五電晶體；一第六電晶體，其汲極係電性連接該第五電晶體之閘極，其閘極係電性連接該第五電晶體之源極，其中 ® 該指數控制訊號與該回授訊號係分別輸入至該第五電晶體之沒極與該第六電晶體之〉及極，或該指數控制訊號與該回授訊號係分別輸入至該第六電晶 • 體之汲極與該第五電晶體之汲極； • 一第七電晶體，其閘極係電性連接該第五電晶體之閘極；一第八電晶體，其汲極係電性連接其閘極與該第七電晶體之源極以產生一冪次轉換訊號；以及 1328343 一第三電流鏡，係與該第七電晶體電性連接以複製該冪次轉換訊號，並與該第二電流鏡電性連接以將複製後之該冪次轉換訊號與該偏壓電流相加以產生該冪次訊號，且輸出該冪次訊號至該線性指數轉換迴路。 17、如申請專利範圍第16項所述之可調式增益放大器，其中該第五電晶體、該第六電晶體、該第七電晶體以 '及該第八電晶體係操作於次臨界區。 18、如申請專利範圍第16項所述之可調式增益放大器，其中該冪次轉換訊號係將該指數控制訊號與該回授訊號相乘後再開方乘2而得到。X. Patent application scope: A gain adjustment device applied to an adjustable gain amplifier, comprising: a linear exponential conversion circuit for receiving a linear control signal and converting the linear control signal to output an exponential control signal; The loop is electrically connected to the linear index conversion loop to receive the index control signal, and according to the index control signal and a bias current to output a feedback signal, and also output a voltage control signal to control an adjustable gain An amplifier and a power conversion circuit are electrically connected to the linear index conversion circuit and the voltage buffer circuit to receive the index control signal and the feedback signal, and to multiply the index control signal by the feedback signal The square is multiplied by 2 and the bias current is applied to output a power signal to the linear exponential conversion loop. 2. The gain adjustment device for an adjustable gain amplifier according to claim 1, wherein the linear control signal is exponentially related to the voltage control signal, and the linear control signal and the adjustable gain amplifier are The gain values are log-linear. 3. The gain adjustment device for an adjustable gain amplifier according to claim 1, wherein the linear index conversion circuit comprises: a resistor; a first transistor having a drain electrically connected thereto a power conversion circuit to receive the power signal, the gate is electrically connected to one end of the resistor 1323383 and the drain of the first transistor; and a second transistor whose gate receives the linear The control signal is electrically connected to the other end of the resistor, and converts the linear control signal to output the exponential control signal to its drain. The gain adjustment device for the adjustable gain amplifier according to the first aspect of the invention, wherein the voltage buffer circuit comprises: a third transistor, the drain system and the linear exponential conversion circuit Electrically connected to receive the index control signal; and a fourth transistor having a source electrically coupled to the source of the third transistor to generate the feedback signal at the drain thereof, and The transistor and the gate of the fourth transistor generate the voltage control signal to control the adjustable gain amplifier. 5. The gain adjusting device for an adjustable gain amplifier according to claim 4, wherein the third transistor and the fourth electric device are respectively used for saturation, as in the fourth application patent scope. The voltage adjusting device is applied to the gain adjusting device of the adjustable gain amplifier, wherein the voltage buffer circuit further comprises: - a current source for generating the bias current; a first current mirror electrically connected to the current source for copying The bias current is connected to the third transistor and the source of the fourth transistor; and a second current mirror is electrically coupled to the current source to replicate the bias voltage 20 1328343 to the power conversion circuit. 7. The gain adjusting device for an adjustable gain amplifier according to claim 6, wherein the power conversion circuit comprises: a fifth transistor; a sixth transistor, > And the pole is electrically connected to the gate of the fifth transistor, and the gate is electrically connected to the source of the fifth transistor, wherein the index control signal and the feedback signal are respectively input to the fifth The drain of the crystal and the drain of the sixth transistor, or the index control signal and the feedback signal are respectively input to the drain of the sixth transistor and the drain of the fifth transistor; a seventh transistor having a gate electrically connected to a gate of the fifth transistor; an eighth transistor having a drain electrically connected to a gate thereof and a source of the seventh transistor to generate a power a conversion signal; and a third current mirror electrically connected to the seventh transistor to replicate the power conversion signal, and electrically connected to the second current mirror to convert the power conversion signal after the copy The bias currents are added to generate the power signal, and the output is Power signal to the linear exponential conversion loop. 8. The gain adjustment device for an adjustable gain amplifier according to claim 7, wherein the power conversion signal multiplies the index control signal by the feedback signal and then multiplies by 2 to obtain . The invention relates to a gain adjusting device applied to an adjustable gain amplifier according to claim 7, wherein the fifth transistor, the sixth transistor, the seventh transistor, and the eighth electro-crystal system Operating in the sub-critical region 10... 10, an adjustable gain amplifier with a gain adjustment device, comprising: *· a gain adjustment device comprising: a linear exponential conversion circuit for receiving a linear control signal and transposing The linear control signal outputs an index control signal; a voltage buffer circuit is electrically connected to the linear index conversion circuit to receive the index control signal, and according to the index control signal and a bias current to output a feedback signal And outputting a voltage control signal; a power conversion circuit is electrically connected to the linear index conversion circuit and the voltage buffer circuit to receive the index control signal and the feedback signal, and the index control signal is The product of the feedback signal is turned on by I square, multiplied by 2, and the bias current is output to output a power signal to the linear exponential conversion. Passage; and an amplifier circuit provided for receiving an input signal, and the buffer back to the voltage 'electrically passage connected to receive the voltage control signal, and according to the voltage - gain control signal to adjust the amplifying circuits to amplify the input information number. 11. The adjustable gain amplifier of claim 10, wherein the linear control signal is exponentially related to the voltage control signal, and the linear control signal is logarithmic to the gain value of the amplifier circuit. relationship. 12. The adjustable gain amplifier of claim 10, wherein the linear index conversion circuit comprises: - a resistor; a first transistor, the drain of which is electrically connected to the power conversion a circuit for receiving the power signal, the gate is electrically connected to one end of the resistor and the drain of the first transistor; and a second transistor, the gate receives the linear control signal and is electrically The switch is connected to the other end of the resistor and converts the linear control signal to output the exponential control signal to its drain. 13. The adjustable gain amplifier of claim 10, wherein the voltage buffer circuit comprises: ® - a third transistor, the drain of which is electrically connected to the linear index conversion loop to receive the index control And a fourth transistor, the source of which is electrically connected to the source of the third transistor to generate the feedback signal at the drain thereof, and the third transistor and the fourth transistor The gate generates the voltage control signal. 14. The tunable gain amplifier of claim 13, wherein the third transistor and the fourth transistor system operate in a region of saturation 23 1328343. 15. The adjustable gain amplifier of claim 13, wherein the voltage buffer circuit further comprises: a current source that generates the bias current; a first current mirror coupled to the current source Electrically connecting to reproduce the bias voltage v · current to the second transistor and the source of the fourth transistor, and a second current mirror electrically coupled to the current source to replicate the bias current to The power conversion loop. The adjustable gain amplifier of claim 15, wherein the power conversion circuit comprises: a fifth transistor; a sixth transistor, wherein the drain is electrically connected to the fifth transistor a gate electrically connected to a source of the fifth transistor, wherein the index control signal and the feedback signal are respectively input to the fifth electrode of the fifth transistor and the sixth transistor 〉 and the pole, or the index control signal and the feedback signal are respectively input to the drain of the sixth transistor and the drain of the fifth transistor; • a seventh transistor whose gate is electrically Sexually connecting the gate of the fifth transistor; an eighth transistor having a drain electrically connected to the gate of the seventh transistor and a source of the seventh transistor to generate a power conversion signal; and a 13243343 third current The mirror is electrically connected to the seventh transistor to replicate the power conversion signal, and is electrically connected to the second current mirror to add the copied power conversion signal to the bias current to generate the power Secondary signal, and output the power signal to the linear Index conversion loop. 17. The tunable gain amplifier of claim 16, wherein the fifth transistor, the sixth transistor, and the seventh transistor operate in a subcritical region with 'and the eighth transistor system. 18. The adjustable gain amplifier of claim 16, wherein the power conversion signal is obtained by multiplying the index control signal by the feedback signal and then multiplying by 2.

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