1328272 ASEK3848 22565twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種晶片構裝及其製程，且特別是有 關於一種堆疊式的晶片構裝及製程。 【先前技術】 向效能、高積集度、低成本、輕薄短小皆為長久以來 電子產品設計製造上所追尋之目標。為了達成上述需求， 積體電路封裝技術也跟著朝向微型化、高密度化發展。除 了韦見的球格陣列式構裝(Ball Grid Array，BGA)、晶片尺 寸構裝(Chip-Scale Package，CSP)、覆晶構裝(Fiip Chip package，F/C package)之外，為了進一步整合多功能的晶 片組，近來更提出堆疊式的晶片構裝技術，以藉由堆疊多 個晶片構裝單元來提高整體的構裝密度。 堆疊式晶片構裝可以整合不同功能之晶片，將例如處 理裔(processor)晶片及記憶體(mem〇ry)晶片，或者邏輯電 ，(Logic)晶片及記憶體晶片（包括DRAM&Flash Mem〇ry) 等封裝在一起，藉以降低成本，縮小構裝體積，並提升訊 號傳輸效能。 田圖1繪示習知之一種堆疊式晶片構裝100，其藉由堆 登的方式整合了數位晶片114、記憶體晶片124以及類比 晶^ 134。數位晶片114以打線接合方式經由第一導線川 ”第基板112接合。數位晶片114的表面堆疊類比晶片 134與140 ’其中類比晶片i34也是採用打線接合方 式經由第三導線138與數位晶片114以及第-基板112電 1328272 ASEK1848 22565twf.doc/n 性連接。包含記憶體晶片124的内部堆疊模組(inside stacked module，ISM)120位於間隙物14〇上。在内部堆疊 模組120中，8¼'體晶片124採用打線接合方式配置於第 二基板122上，且第二基板122上配置有第二封裝膠體 126’用以包覆第二晶片以及連接於第二基板122與第二晶 片124之間的第二導線128。 ^ 此外，内部堆疊模組120與 ，、个 少，κ人m九|aj休扣i1328272 ASEK3848 22565twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a wafer package and a process thereof, and more particularly to a stacked wafer package and process. [Prior Art] The performance, high accumulation, low cost, light weight and shortness are the long-term goals pursued in the design and manufacture of electronic products. In order to achieve the above requirements, the integrated circuit packaging technology has also been developed toward miniaturization and high density. In addition to Weijian's Ball Grid Array (BGA), Chip-Scale Package (CSP), and Fip Chip package (F/C package), Incorporating a versatile wafer set, a stacked wafer structuring technique has recently been proposed to increase the overall bulk density by stacking a plurality of wafer structuring units. The stacked wafer assembly can integrate different functional wafers, such as processor chips and memory chips, or logic (Logic) chips and memory chips (including DRAM & Flash Mem〇ry). ) Packaged together to reduce costs, reduce the size of the package, and improve signal transmission performance. Field 1 depicts a conventional stacked wafer assembly 100 that integrates a digital wafer 114, a memory wafer 124, and an analog crystal 134 by stacking. The digital wafer 114 is bonded in a wire bonding manner via the first conductor "the substrate 112. The surface of the digital wafer 114 is stacked with the analog wafers 134 and 140'. The analog wafer i34 is also wire bonded through the third wire 138 and the digital wafer 114 and The substrate 112 is electrically connected to the substrate stacking module. The wafer 124 is disposed on the second substrate 122 by wire bonding, and the second substrate 122 is disposed with a second encapsulant 126 ′ for covering the second wafer and connected between the second substrate 122 and the second wafer 124 . The second wire 128. ^ In addition, the internal stacking module 120 with, less, κ people m nine | aj suspension i
線接合方式經由多條第四導線148相互電性連接，而第_ 封裝膠體116配置於第一基板112上，用以包覆上述之; 位晶片114、類比晶片134、内部堆疊模組12〇、間隙物14( 第-導線118、第三導、線138以及第四導線148。另外，〈 一基板112底部可配置多個焊球15〇，以供堆疊式晶片i 裝100與外部電路連接。 “在上述的堆豐式晶片構裝100中，内部堆疊模组L :错由間隙物140堆疊於數位晶片114上方。然而，由; : 側。如此的設計，容易導致1 暴命減上㈣料4额12(3因為不平衡而傾斜，甚-裝=進而影響整體堆疊式晶片; 良率。此外1二封裝膠體1: 衡内部堆4模組120本身的不· 内部堆疊=:ί'34也可能在製程中受到傾斜1 雄壯 0屋迫而党損。再者，前述的雄聶彳曰0 、100在製作上共f進行的3 7 1328272 ASEKI848 22565twf.doc/n 作，包含數位晶片 心丨思體晶片124、類比晶片134 以及間隙物140的配置，因此步驟較為繁複，製程上也有 較兩的風險。 【發明内容】 本發明關於-種堆疊式晶片構裝，其具有較佳的可靠 度。 、本發明另關於-種堆疊式晶片構裝製程，用以製作上 述之堆疊式晶片構裝，並具有較佳的製程良率。 為，《述本發明之内容，在此提出—種堆疊式晶片 if/主要包括一第—基板、一第一晶片、一内部堆疊The wire bonding method is electrically connected to each other via a plurality of fourth wires 148, and the first package encapsulant 116 is disposed on the first substrate 112 for covering the above; the bit wafer 114, the analog wafer 134, and the internal stacking module 12〇 The spacer 14 (the first conductor 118, the third conductor 138, and the fourth conductor 148. In addition, a plurality of solder balls 15 可 may be disposed at the bottom of the substrate 112 for the stacked wafers 100 to be connected to an external circuit. "In the above-described stack-up wafer assembly 100, the internal stacking module L: is stacked by the spacers 140 over the digital wafer 114. However, by: side. Such a design is likely to cause a fatality loss. (4) The amount of material 4 is 12 (3 is tilted due to imbalance, and even - loaded = and then affects the overall stacked wafer; yield. In addition, 1 2 package colloid 1: balance internal stack 4 module 120 itself does not · internal stack =: ί '34 may also be tilted in the process of 1 majestic 0 house and party damage. Moreover, the above-mentioned Xiong Nie 0, 100 in the production of a total of f carried out 3 7 1328272 ASEKI848 22565twf.doc / n, including digital The configuration of the wafer core wafer 124, the analog wafer 134, and the spacer 140, The method is more complicated, and there are two risks in the process. SUMMARY OF THE INVENTION The present invention relates to a stacked wafer package, which has better reliability. The present invention further relates to a stacked wafer assembly process. In order to produce the stacked wafer package described above, and having a better process yield. For the purpose of the present invention, a stacked wafer if/mainly includes a first substrate, a first wafer, An internal stack
Stacked module，腿）、—第三晶片以及一第一 體。第-晶片配置於第一基板上’並電性連接至第 有性連接至第—基板’且内部堆疊 =基，’並電性連接至第二基板”,外，第曰== 片朝向第一晶片而堆疊於第一晶片卜纟:权、乂弟―曰日 開內·^弟片方。第三晶片配置於 -義板Hi連接至第二基板。第—封裝膠體配置於第 包封第—晶片、内部堆疊模組與第三晶片 括實施例中’上述之堆疊式晶片構農更包 曰 1隙物，其配置於内部堆疊模組與第一晶片之間。 括發L之—實施例中，上述之堆疊式晶片構裝更包 疊模組;第二::弟:J片面上’用以連接内部堆 ~弟a曰片。此外，膠層内更例如可具有多個填充 8 1328272 ASEK1848 22565twf.doc/n 物’而谬層的材質例如是環氧樹脂(ep〇xyresin)。 在本發明之-實施财，上述之内料疊模組更包括 一第二封體’其配置於與第二晶片同-側的第二基板 上並覆蓋第-晶片。内部堆疊模組係藉由第二封體 堆疊於第一晶片上方。 在本發明之-實施例中，上述之第一晶片例如是採打 ΐ合ΐ式與第—基板接合。第二晶片例如是採打線接合 ^二、與第—基板接合。第二晶片例如是採打線接合方式與 第二基板接合。此外，内部堆疊模組例如是採打線接合方 式電性連接至第一基板。 在本發明之-實施例中，上述之第二基板的開孔暴露 出第二晶片。 在本發明之一實施例中，上述之堆疊式晶片構裝更包 括多個焊球，其配置於第一基板遠離第一晶片的一側。 —在本發明之一實施例中，上述之第一晶片、第二晶片 與第三晶片例如分別為數位晶片、記憶體晶片與類比晶片。 —本發明另提出一種堆疊式晶片構裝製程，首先提供一 第—基板，並接合一第一晶片於第—基板上，以使第二晶 片电I1 生連接至第一基板。接著，提供一内部堆疊模組，此 内。Ρ堆豐模組具有一第二基板與—第二晶片，其中第二晶 片配置於第二基板上，並電性連接至第二基板;;然後丁 ς 内部堆疊模組以第二晶片朝向第—晶片而堆疊於第—晶片 上方。並且，在製作内部堆疊模組時或是將内部堆疊模蚯 堆疊於第-晶片上方之後，形成—開孔於第二基板遠離第 9 1328272 ASEK1848 22565twf.doc/n 晶 片 亡晶片的一側。之後，配置一第三晶片於開孔内，並使第 三晶片電性連接至第二基板。接著，電性連接内部堆疊模 組與第一基板，並且形成一第一封裝膠體於第一基板上， 以使第一封裝膠體包封第一晶片、内部堆疊模組與第 在本發明之一實施例中，上述之堆疊式晶片構裝製程 更包括在接合第-晶片與第—基板之後，配置—間隙物於 第 晶片上 在本發明之—實施例中，上述之堆叠式晶片構袭製程 更包括形成一膠層於第一晶片的一表面，用以連接第一晶 片與内部堆疊模組。所轉層可岐多個填絲 質例如是環氧樹脂。 八 在本發明之一實施例中，上述之堆疊式晶片構 的内部堆疊模組更包括—第二封裝膠體，其配置於 二:曰片同-側的第二基板上’並覆蓋第二晶片。並且？ 堆疊内部堆疊模組與第—晶片時，使 二封裝膠體堆疊於第—晶片上方。 ，本發明之-實施例中，上述之堆疊式晶片構裝 例如疋採用打線接合方式來接合第一晶片與第一義柩 也同樣可採用打線接合方式來接合第二晶 板，以及第三晶片與第二基板。 、—基 ^發明之—實施例中，電性連接内部堆 —基板的方法例如是進行一打線接合製程 、、一弟 在本發明之一實施例中，上述之堆疊式晶片構裝製程 1328272 ASEK1848 22565twf.doc/n 在第二基板上所形成的開孔可暴露出第二晶片。 在本發明之一實施例中’上述之堆疊式晶片構農 用以形成開孔的方法包括機械鑽孔或雷射鑽孔。 在本發明之一實施例中，上述之堆疊式晶片構裝制 更包括在形成第二封裝膠體之後，配置多個焊球於^二程 板遠離第一晶片的一側。 、弟—基 基於上述，本發明將第二晶月配置於内部堆聂 上’使得第-晶片的表面具有充分的空間可 & 曲片Stacked module, leg), a third wafer, and a first body. The first wafer is disposed on the first substrate 'and electrically connected to the first substrate to the first substrate' and is internally stacked = base, and is electrically connected to the second substrate. A wafer is stacked on the first wafer: 权, 乂 曰 曰 开 开 · ^ ^ ^ 。 。 。 。 。 。 。 。 。 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三 第三The wafer, the internal stacking module and the third wafer include the above-mentioned stacked wafer cultivating device, which is disposed between the internal stacked module and the first wafer. In the example, the stacked wafer assembly described above is more in a stacking module; the second: brother: J is used to connect the inner stack to the inner stack. In addition, the glue layer may have multiple fills, for example. 1328272 ASEK1848 22565twf.doc/n and the material of the layer is, for example, epoxy resin (ep〇xyresin). In the invention, the above-mentioned inner stack module further includes a second envelope 'configuration On the second substrate on the same side as the second wafer and covering the first wafer. The internal stacked module is sealed by the second package Stacked on the first wafer. In the embodiment of the present invention, the first wafer is bonded to the first substrate, for example, the second wafer is, for example, a tapping wire bond and a first substrate. The second wafer is bonded to the second substrate by, for example, tapping bonding. Further, the internal stacking module is electrically connected to the first substrate by, for example, wire bonding. In the embodiment of the present invention, the second The opening of the substrate exposes the second wafer. In an embodiment of the invention, the stacked wafer assembly further includes a plurality of solder balls disposed on a side of the first substrate away from the first wafer. In one embodiment of the invention, the first wafer, the second wafer, and the third wafer are, for example, a digital wafer, a memory wafer, and an analog wafer, respectively. The present invention further provides a stacked wafer fabrication process, which first provides a first a substrate, and bonding a first wafer on the first substrate to electrically connect the second wafer to the first substrate. Next, an internal stacking module is provided, wherein the Ρ Ρ 丰 module has a first a second substrate and a second wafer, wherein the second wafer is disposed on the second substrate and electrically connected to the second substrate; and then the internal stacking module is stacked on the first wafer with the second wafer facing the first wafer And, when the internal stacking module is fabricated or after the internal stacking mold is stacked on the first wafer, the hole is formed on the side of the second substrate away from the second substrate 1893328 ASEK1848 22565twf.doc/n wafer die Then, a third chip is disposed in the opening, and the third chip is electrically connected to the second substrate. Then, the internal stacking module and the first substrate are electrically connected, and a first encapsulant is formed on the first On the substrate, the first encapsulant encapsulates the first wafer, the internal stack module, and in an embodiment of the present invention, the stacked wafer assembly process is further included after bonding the first wafer and the first substrate In the embodiment of the present invention, the stacked wafer structuring process further includes forming a glue layer on a surface of the first wafer for connecting the first wafer and the inner wafer. Stacking modules. The layer to be transferred may be a plurality of fillers such as an epoxy resin. In an embodiment of the present invention, the internal stacking module of the stacked wafer structure further includes a second encapsulant disposed on the second substrate of the same side of the cymbal and covering the second wafer. . and? When the internal stacking module and the first wafer are stacked, the two encapsulants are stacked on top of the first wafer. In the embodiment of the present invention, the stacked wafer assembly, for example, the bonding of the first wafer to the first germanium by wire bonding, and the bonding of the second crystal plate, and the third wafer, may also be performed by wire bonding. And a second substrate. In the embodiment, the method of electrically connecting the internal stack-substrate is, for example, performing a wire bonding process, and in one embodiment of the present invention, the above-mentioned stacked wafer mounting process 1328272 ASEK1848 22565twf.doc/n An opening formed in the second substrate exposes the second wafer. In one embodiment of the invention, the above-described method of stacking wafers for forming openings includes mechanical drilling or laser drilling. In an embodiment of the invention, the stacked wafer assembly system further includes: after forming the second encapsulant, disposing a plurality of solder balls on a side of the two-way board away from the first wafer. Based on the above, the present invention arranges the second crystal moon on the inner stack to make the surface of the first wafer have sufficient space.
θ 、 ......^ --π g己置 是間隙物等，如此内部堆疊模組可穩固地堆疊於 。 士方:且第三晶片在製程中不易受到破壞，因此有二二 升堆豐式晶片構裝的可靠度。 為讓本發明之上述和其他目的、特徵和 易懂’下文特舉較佳實施例，並配合所式·^月ς貝 明如下。 、V砰細說 【實施方式】 本發明所提出的堆疊式晶片構裝可應 之晶片的整合’如—般常見的數位晶片、類比8曰員型 體晶片等。為了涵蓋上述變化，下文_ 、=或兄憶 二晶片與第三晶片來指稱不同類型的晶片。—晶片、第 本發明之堆叠式晶片構裝主要是在第— 苐-晶片，並使内部堆疊模組中的第二·土十配置 片’而將内部堆疊模峰疊於第—晶Βθ 。第-晶 叠模組的第二基板背面具有可容納第三以=，内部堆 二晶片配置於開口内並與内部堆疊模組電性連;!另：第 11 1328272 ASEK1848 22565twf.doc/n 第基板上配置有第一封裝膠體，用以包封第一晶片、内 部堆疊模組與第三晶片。 另一方面，内部堆疊模組與第一晶片之間可進一步配 置間隙物或是膠層，用以加強内部堆賴組與第—晶片之 間的接合效果’並有效維持内部堆疊齡與第―晶片之間 的間隙。膠層内可具有多個填充物，用以支撐内部堆疊模 組。 圖2緣示本發明之—實施例的一種堆疊式晶片構裝。 如圖2所不，堆疊式晶片構裝2〇〇包括第一基板212、第 一晶片214、内部堆疊模組22〇、第三晶片234以及第一封 裝膠體216。第-晶片214例如是採打線接合方式與第一 基板212接合，以經由多條第一導線218電性連接至第一 基板=2。本實施例之内部堆疊模組22〇包括第二基板 M2、第二晶片224、封裝膠體226與第二導線228，其中 第二晶片224採打線接合方式配置於第二基板222上，並 經由多條第二導線228電性連接至第二基板222。 在内部堆疊模組220中，第二基板222遠 224的-側具有-開孔222a，且内部堆疊模組22^匕 晶片222朝向第-晶片214而堆疊於第一晶片2i4上方。 本實施例在内部堆疊模組⑽與第—晶片214之間 膠層260,用以連接内部堆疊模組22㈣第二封鱗體挪 與第-^ 214。膠層26G的材_如是環氧樹脂或立他 適當材質，而為了有效特内部堆麵組22q*第一 2U之間的間隙’更可採用内部具有多個填充物(未^ 32 1328272 ASEK1848 22565twf.d〇c/n 的膠層260 ’以藉由填充物來支撐内部堆疊模組220。 請再參考圖2，第三晶片234配置於開孔222a内，並 採打線接合方式藉由多條第三導線238電性連接至第二美 板222。值得注意的是，本實施例之開孔222&的深度可二 依據實際需求進行調整，例如考量堆疊後的高度或&熱問 題，則可增加開孔222a的深度或甚至使開孔222a暴露出 第二晶片224。此外，多條第四導線施連接於内部堆最 模，220與第一基板212之間，而第一封裝膠體216配^ 於第一基板212上，用以包封第一晶片214、内部堆疊模 組220、第三晶片234、膠層26〇與相關的第一導線Mg、 第三導線238以及第四導線248。 在本實施例中，堆疊式晶片構裝2〇〇可包括多個焊球 250’其配置於第一基板212遠離第一晶片叫的—側（即 第一基板212的底部）’用以供堆疊式晶片構裝2〇〇連接至 外部電路。此外，前述的第一晶月214、第二晶片224與 第二晶片234例如分別為數位晶片、記憶體晶片盘類比晶 片。當然，上述的晶片類型僅為舉例之用，並非用以限^ 本發明。 在上述實施例中，由於將第三晶片234配置於 疊模組220上，因此可在第一晶片214表面的適當位置處 配置朦層260 ’用以使内部堆疊模組22〇穩固地$疊於第 -晶片214上方。如此-來’不僅可提升内部堆疊模二挪 與第-基板212之_接合效果，亦有助於改 曰 片構裝的可靠度。此外，由於在内部堆雜組^曰 13 1328272 ASEK1848 22565twf.doc/n 第二基板222上形成開口 222a，用以容納第三晶片234， 因此可降低堆疊式晶片構裝2〇〇的整體高度，有利於堆疊 式晶片構裝200的小型化發展。 請參考圖3，其繪示本發明之另一實施例的一種堆疊 •式晶片構裝。本實施例之堆疊式晶片構裝3〇〇與前述實施 例之堆g式晶片構裝200的差異之處在於以間隙物270來 取代膠層260,而本實施例與前述實施例相似的其他構件 則以相同的標號來表示，關於其說明也請參照前述實施 例’此處不再贊述。 為更進一步說明本發明的技術内容，下文再以前述堆 豐式晶片構裝200的製程為例進行討論。請參照圖 4A〜4E，其依序繪示本發明之一實施例的一種堆疊式晶片 構裝製程。本實施例以相同的標號來表示與前述實施例相 似的構件，其中部分構件的說明可能在本實施例被省略， 然其皆可在前述實施例中找到對應的敘述。 首先，如圖4A所示，提供第一基板212，並且在第 鲁 一基板212上形成膠層26〇。此外，採用打線接合的方式 來接合第一晶片214與第一基板212，以使第一晶片214 經由第一導線218電性連接至第一基板。值得注意的是， 此步驟可先在第一基板212上形成膠層260 ,再進行打線 接合;1¾知。另一方面，右是採用如圖3所示的間隙物270 來取代膠層260，則可以待完成打線接合製程之後，再於 第一基板212上配置間隙物270。 接著，如圖4B所示，提供内部堆疊模組22〇，並將 1328272 ASEK1848 22565twf.doc/n 内部堆疊模組220以第二晶片224 曰 疊於第-晶片2M上方。更詳1向：：曰曰片214而堆 的驻腴μ I &，内部堆疊模組220 的弟-封跡肢226會經由膠層26()與 合。此外，本實施例可以選擇 #笛一 s μ &擇在將内部堆疊模組220堆疊 上方i後或是製作内部堆疊模組挪時， 於弟一基板222上形成開孔222a。θ , ......^ -- π g is a spacer, etc., so that the internal stacking modules can be stably stacked. Shifang: And the third wafer is not easily damaged during the process, so there is a reliability of the 22-liter stack wafer structure. The above and other objects, features and advantages of the present invention are set forth in the <RTIgt; DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The stacked wafer structure of the present invention can be integrated with a wafer such as a commonly used digital wafer, an analog 8-bit wafer, or the like. In order to cover the above variations, the following wafers and third wafers are referred to as different types of wafers. - The wafer, the stacked wafer assembly of the present invention is primarily on the first - wafer, and the second stack of the internal stacking module is arranged to stack the internal stacked mode peaks to the first wafer θ. The back surface of the second substrate of the first-stacked module has a third to be accommodated, and the internal stack of two wafers is disposed in the opening and electrically connected to the internal stacking module; Another: 11 1328272 ASEK1848 22565twf.doc/n A first encapsulant is disposed on the substrate for encapsulating the first wafer, the internal stacking module and the third wafer. On the other hand, a spacer or a glue layer may be further disposed between the internal stacking module and the first wafer to enhance the bonding effect between the internal stacking layer and the first wafer and effectively maintain the internal stacking age and the first The gap between the wafers. There may be multiple fillers within the glue layer to support the internal stacked mold set. Figure 2 illustrates a stacked wafer assembly of an embodiment of the present invention. As shown in FIG. 2, the stacked wafer package 2 includes a first substrate 212, a first wafer 214, an internal stacked module 22A, a third wafer 234, and a first package of glue 216. The first wafer 214 is bonded to the first substrate 212 by, for example, tapping wire bonding to be electrically connected to the first substrate = 2 via the plurality of first wires 218. The internal stacking module 22 of the present embodiment includes a second substrate M2, a second wafer 224, an encapsulant 226 and a second wire 228. The second wafer 224 is disposed on the second substrate 222 by wire bonding. The second wire 228 is electrically connected to the second substrate 222. In the internal stacking module 220, the second substrate 222 has an opening 222a on the side of the 224, and the internal stacking module 22 is stacked above the first wafer 2i4 toward the first wafer 214. In this embodiment, a glue layer 260 is disposed between the internal stacking module (10) and the first wafer 214 for connecting the internal stacking module 22 (4) to the second scale and the -^214. The material of the glue layer 26G_such as epoxy resin or the appropriate material, and in order to effectively the internal internal stack 22q* the gap between the first 2U' can be used internally with multiple fillers (not ^ 32 1328272 ASEK1848 22565twf The glue layer 260' of the .d〇c/n supports the internal stacking module 220 by the filler. Referring to FIG. 2 again, the third wafer 234 is disposed in the opening 222a, and the wire bonding method is adopted by a plurality of wires. The third wire 238 is electrically connected to the second color plate 222. It should be noted that the depth of the opening 222& of the embodiment can be adjusted according to actual needs, for example, considering the height after stacking or the thermal problem. The depth of the opening 222a may be increased or even the opening 222a may be exposed to the second wafer 224. Further, a plurality of fourth wires are connected between the inner stack most mold 220 and the first substrate 212, and the first encapsulant 216 The first substrate 212, the internal stack module 220, the third wafer 234, the glue layer 26, and the associated first wire Mg, third wire 238, and fourth wire 248 are disposed on the first substrate 212. In this embodiment, the stacked wafer package can be packaged. The plurality of solder balls 250' are disposed on the side of the first substrate 212 away from the first wafer (ie, the bottom of the first substrate 212) for connecting the stacked wafer assembly 2 to an external circuit. The first crystal 214, the second wafer 224 and the second wafer 234 are, for example, digital wafers and memory wafer disc analog wafers. Of course, the above wafer types are for illustrative purposes only and are not intended to limit the invention. In the above embodiment, since the third wafer 234 is disposed on the stack module 220, the germanium layer 260' may be disposed at an appropriate position on the surface of the first wafer 214 for the internal stack module 22 to be firmly stacked. Above the first wafer 214. Such a 'together' not only enhances the bonding effect of the internal stacking die and the substrate-substrate 212, but also contributes to the reliability of the slab assembly. In addition, due to the internal stacking group ^曰13 1328272 ASEK1848 22565twf.doc/n An opening 222a is formed in the second substrate 222 for accommodating the third wafer 234, thereby reducing the overall height of the stacked wafer assembly 2, which is advantageous for the stacked wafer assembly 200 Miniaturization. Referring to Figure 3, there is shown a stacked wafer assembly of another embodiment of the present invention. The stacked wafer assembly 3 of the present embodiment is different from the stacked wafer assembly 200 of the previous embodiment. The glue layer 260 is replaced by the spacer 270, and other components of the embodiment similar to those of the previous embodiment are denoted by the same reference numerals. For the description thereof, please refer to the foregoing embodiment, which is not mentioned here. The technical content of the present invention will be further described, and the process of the aforementioned stacking wafer structure 200 will be discussed below as an example. Referring to FIGS. 4A-4E, a stacked wafer fabrication process in accordance with an embodiment of the present invention is sequentially illustrated. The present embodiment is denoted by the same reference numerals as the members of the foregoing embodiments, and the description of the parts may be omitted in the present embodiment, and the corresponding descriptions may be found in the foregoing embodiments. First, as shown in Fig. 4A, a first substrate 212 is provided, and a glue layer 26 is formed on the second substrate 212. In addition, the first wafer 214 and the first substrate 212 are bonded by wire bonding to electrically connect the first wafer 214 to the first substrate via the first wire 218. It should be noted that this step may first form a glue layer 260 on the first substrate 212, and then perform wire bonding; On the other hand, if the spacer 270 is replaced by the spacer 270 as shown in FIG. 3, the spacer 270 may be disposed on the first substrate 212 after the bonding process is completed. Next, as shown in FIG. 4B, an internal stacking module 22 is provided, and a 1328272 ASEK1848 22565 twf.doc/n internal stacking module 220 is stacked over the first wafer 2M with the second wafer 224. More detailed 1 :: 曰曰 214 and the pile 的 μ I &, the internal stacking module 220 of the brother-sealing limb 226 will be merged via the glue layer 26 (). In addition, in this embodiment, it is possible to select #笛一 s μ &; when the internal stacking module 220 is stacked above the i or when the internal stacking module is moved, the opening 222a is formed on the substrate 222.
内^^，^^所不’配置第三晶片234於開孔222a "二使日片電性連接至第二基板222。盆中， 例如疋_打線接合的方式來接合第三晶片23技第二基 板2之2 ’以使第三晶片234妹由 '、 第二基板222。 I由第二導線现電性連接至 笛道^ 4D所不’再進行打線接合製程，以藉由 弟四導線248電性連接内部堆疊模組22〇與第一基板犯。The third wafer 234 is disposed in the opening 222a and the second substrate 222 is electrically connected to the second substrate 222. In the basin, for example, a 疋_wire bonding method is used to bond the third substrate 23 to the second substrate 2 to make the third wafer 234 from the ', second substrate 222. I is electrically connected to the flute 4 4D and then the wire bonding process is performed to electrically connect the internal stack module 22 to the first substrate by the four wires 248.
之後，如圖4E所示，形成第—封裝膝體216於第一 土板212上，以大致完成堆疊式晶片構裝2⑻的製作。 -封裝膠體216包封第-晶片214、膠層、内部堆叠模 組220、第三晶片234以及相關的第一導線218、第三導線 2土38 =及第四導線248。此外，本實施例可在第—基板犯 遠離第-晶片214的-側（即第一基板212的底部)形成焊 球250，用以使堆疊式晶片構裝2〇〇經由焊球25〇 外部電路。 上述實施例在第一晶片214上形成膠層26〇，用以接 合内部堆疊模組220與第—晶片214。相較於習知採用間 隙物的堆疊技術，可以減少—道晶片配置(Die Attach)的動 15 ASEK1848 22565twf.doc/n $ ’有助於簡化製程，提高生產效率。此外，由 ==軌物的膠層，因此可有效維部 乡且220與第一晶片214之間的間隙。 隹立棋 所採發明所提出的堆疊式晶片構裝及其製程 =用的4物方式可降低堆叠式晶片構裝的整體堆疊 阿度’並有利於堆疊式晶片構裝的小型化發展。 晶^具有適當的區域來配置膠層或間隙物，因此 :、内^堆遽組提供穩固的支撐，有助於提升内部堆叠 往基板之間的接合效果，並可改善堆疊式晶片構 、、可靠度以及堆疊式晶片構裝製程的良率。另一方面， 本發明之堆疊式晶#構裝製程具有較為簡化的製程步驟， 有助於降低製程上的風險，並可提高生產效率。 …雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明’任何所屬領域中具有通常知識者，在不脫離 本發明之精神和範圍内’當可作些許之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為 準。 【圖式簡單說明】 圖1繪示習知之一種堆疊式晶片構裝。 圖2繪不本發明之一實施例的一種堆疊式晶片構裝。 圖3緣示本發明之另一實施例的一種堆疊式晶片構 裝。 圖4Α〜4Ε依序繪示本發明之一實施例的一種堆疊式 晶片構裝製程。 16 1328272 ASEK1848 22565twf.doc/n 【主要元件符號說明】 100、200、300 :堆疊式晶片構裝 112、212 :第一基板 114、214 :第一晶片 116、216 :第一封裝膠體 118、218 :第一導線 120、220 :内部堆疊模組 122、222 :第二基板 222a :開孔 124、224 :第二晶片 126、226 :封裝膠體 128、228 :第二導線 134、234 ·•第三晶片 138、238 :第三導線 140 :間隙物 148、248 :第四導線 150、250 :焊球 260 :膠層 270 :間隙物 17Thereafter, as shown in Fig. 4E, a first package knee 216 is formed on the first earth plate 212 to substantially complete the fabrication of the stacked wafer package 2 (8). The encapsulant 216 encloses the first wafer 214, the glue layer, the inner stack module 220, the third wafer 234, and the associated first conductor 218, third conductor 2 soil 38 = and fourth conductor 248. In addition, in this embodiment, the solder ball 250 may be formed on the side of the first substrate that is away from the first wafer 212 (ie, the bottom of the first substrate 212) for the stacked wafer assembly 2 to pass through the solder ball 25 Circuit. The above embodiment forms a glue layer 26 on the first wafer 214 for bonding the internal stacking module 220 and the first wafer 214. Compared to the conventional stacking technique using spacers, it is possible to reduce the movement of the Die Attachment 15 ASEK1848 22565twf.doc/n $ ' to help simplify the process and increase production efficiency. In addition, the glue layer of == rails can effectively maintain the gap between the home and the first wafer 214. The stacked wafer assembly and its process proposed by the invention of the invention can reduce the overall stacking of stacked wafer structures and facilitate the miniaturization of stacked wafer structures. The crystal has an appropriate area for arranging the glue layer or the spacer, so that the inner stacking layer provides a stable support, which helps to improve the bonding effect between the inner stack and the substrate, and can improve the stacked wafer structure, Reliability and yield of stacked wafer fabrication processes. On the other hand, the stacked crystal# fabrication process of the present invention has a relatively simplified process step, which helps to reduce the risk in the process and improve the production efficiency. The present invention has been disclosed in its preferred embodiments as a matter of course, and is not intended to limit the invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a conventional stacked wafer package. 2 depicts a stacked wafer package in accordance with an embodiment of the present invention. Figure 3 illustrates a stacked wafer assembly in accordance with another embodiment of the present invention. 4A to 4D illustrate a stacked wafer fabrication process in accordance with an embodiment of the present invention. 16 1328272 ASEK1848 22565twf.doc/n [Main component symbol description] 100, 200, 300: stacked wafer assembly 112, 212: first substrate 114, 214: first wafer 116, 216: first encapsulant 118, 218 : first wire 120, 220: internal stacking module 122, 222: second substrate 222a: opening 124, 224: second wafer 126, 226: encapsulant 128, 228: second wire 134, 234 · • third Wafers 138, 238: third wire 140: spacers 148, 248: fourth wires 150, 250: solder balls 260: glue layer 270: spacers 17