1325612 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種液晶顯示器之製造方法 適用於液晶顯示器之互補式金氧半導 曰 TFT)之製造方法。 牛導體相電晶體（CMOS 【先前技術】 10 隨著數位時代的來臨與平面顯示器的興起，低溫複晶 矽技術已成為高畫質顯示器的代名詞。在輕、薄、低耗電 等產品需求下’具備高效能、高解析等特點的低溫複晶石夕 顯示器產品備受矚目’應用領域包括可攜式資訊產品、數 位相機、數位攝影機、筆記型電腦、行動電話與高解析大 型視訊家電等等。 由於低溫複晶矽薄臈電晶體可克服移動率的問題，並 15提供互補式（Complementary)電路技術，在元件縮小化、面 板開口率、畫面品質與解析度上也絕對的優勢。因此，主 •動式液晶顯示裝置逐漸朝向採用互補式金氧半導體薄膜電 晶體（CMOS TFT)，作為周邊電路以及畫素之開關元件。然 ' 而，由於互補式金氧半導體薄膜電晶體中，N型金氧半導體 -20 場效電晶體會因為熱載子作用，而在關狀態（0ff state)時有 閘極漏電流的問題，所以N型金氧半導體場效電晶體通常會 设汁有輕摻雜閘極（Hghtly doped drain，LDD)區域，用來減 低閘極漏電流。 1325612 圖以至⑴為習知採用互補式金氧半導體薄膜電 之薄膜電晶體陣列基板之製作方法示意圖。以設計有^捧 雜汲極的互補式金氧半導體薄膜電晶體為例，此薄臈電： 體陣列基板最常見的製程步驟需要八道光罩的製程。' " ‘5 10 15 首先’請參閱圖1A，提供一基板1〇〇，該基板ι〇〇具有 —N型金氧半導體（NMOS)區210以及一 p型金氧半導體 (PMOS)區220 ’其中該NMOS區210包含第一摻雜區211、輕 摻雜區212、第一閘極區213與電容區214，該pM〇sg22〇 包含第二穆雜區221與第二閘極區222。 續參閱圖1A，於s玄基板上形成一緩衝層ι1〇。接著， 於該緩衝層110上形成一低溫複晶矽層（圖未示），再進行一 次微影蝕刻以圖案化該低溫複晶矽層（圖未示），而形成第一 半導體層121與第二半導體層122,其中該第一半導體層121 位於該NMOS區210中，該第二半導體層122位於該pm〇S區 22〇中。然後，於該基板100上形成一介電層13〇(例如氮化 石夕）’使該介電層130覆蓋於該第一半導體層12]1、該第二半 導體層122與部分該基板1〇〇上。 接著’請參閱圖1B，經由一次曝光顯影，形成一圖案 化之第一光阻層141於該介電層130上，使該NMOS區210之 第一摻雜區211露出。然後，以該第一光阻層141為罩幕， 進行N型離子（例如磷離子或砷離子）之重摻雜離子植入 910(n+-i〇ns impiantati〇n)，藉此形成NMOS元件之源極/汲極 121a。 20 丄 325612 其次，請參閱圖ic，移除該第一光阻層141。然後，進 行一次微影蝕刻，形成一圖案化之金屬層15〇於該介電層 .U〇上，該金屬層150覆蓋於該第一閘極區213、該電容區214 .與該第二閘極區222上。接著，以該金屬層15〇為罩幕，進 行1^里離子之輕摻雜植入（11._丨〇如丨1^^加如的)92〇，藉此形 成輕摻雜汲極（LDD)121b。 其次，請參閱圖1D，進行一次曝光顯影，形成一圖案 化之第一光阻層142覆蓋於該金屬層15〇與部分該介電層 130上，並使該1>]^〇8之第二摻雜區22ι露出。然後，以該第 10二光阻層142與該金屬層15〇為罩幕，進行P型離子（例如硼 離子）之重摻雜離子植入（p\i〇ns implantati〇n)㈣，藉此形 成PMOS元件之源極/没極122ae最後，再移除該第二光阻 層142’即完成包含互補式金氧半導體薄膜電晶體與儲存電 容之驅動電路。 15 ，其次，請參閱圖1E，於該基板100上形成一保護層160。 然後，利用一次微影蝕刻定義出貫穿該保護層16〇與該介電 層130之通孔I60a’以顯露_金氧半導體之部分源極級極 121a與P型金氧半導體之部分源極/汲極^以。接著，沉積金 屬於該保護層16G上與該通孔跡中，再進行-次微影餘刻 20定義出祕/祕導線17卜在本實施财，該祕級極導 線170填滿該通孔16Ga且覆蓋於該保護層160之部分表面。 最後，如圖1F所示，於該保護層16〇上形成一平坦層 180 ’再利用一次微影银刻定義出貫穿該平坦層U〇之通孔 驗。然後’沉積—透明電極層19〇,再利用—次微影製程 1^25612 使其圖案化，即完成一液晶顯示裝置之薄膜電晶體陣列基 板0 然而，由於製作過程冗長且複雜，因此不僅成本昂貴， 並且容易引發製程缺陷，因此如何減少光罩道數已成為薄 •5 膜電晶體陣列基板製作發展之重要課題。 此故，目前亟需一種互補式金氧半導體薄膜電晶體之 製作方法，可簡化微影蝕刻之製程步驟以降低製程困難 度，以達到提高產能與降低製造成本之雙重效果。 10 【發明内容】 有鑑於此，本發明提供一種半導體元件之製造方法， 使半導體7L件所需之光罩道數減少至兩道，藉此簡化微影 钱刻之製程步驟'提高產能與降低製造成本。 本發明提供一種半導體元件之製造方法，包括下列步 π (Α)提供一基板，該基板具有一 Ν型金氧半導體（NMOS) 與—P型金氧半導體（PM〇S)區，其中該NMOS區包含-一摻雜區輕摻雜區與一第一閘極區，該pm〇S區包含 _丰、摻雜區與—第二閘極區；⑻於該基板上全面性形成 “、體層，（〇於該nm〇S區與該PMOS區上之該半導體層 20 上形成_笛—止 s ’阻層，其中於該NMOS區與該PMOS區之該 區上之該第—光阻層之厚度大於其餘該第一光阻層 減小广’（D)去除未被該第一光阻層覆蓋之該半導體層；（E) ^，’光阻層之厚度，以暴露該PMOS區之該第二摻雜 °° &半導體層；⑺以剩餘之該第-光阻層為罩幕，進 1325612 • π”離子之重摻雜離子植人㈣成ϋ極/¾極；⑹ 移除剩餘之該第一光阻層，·（Η)依序於該基板與該半導體層 ^全面性形成一介電層與一金屬層；⑴於區之該 . 卜間極區與該輕摻雜區上與該PMOS區之該第二閘極區 .5上形成一第一光阻層；（J)去除未被該第二光阻層覆蓋之該 金屬層，（κ)以該第二光阻層為罩幕，進行N型離子之重摻 雜離子植入而形成一第二源極/汲極；（L)縮小該第二光阻層 之寬度，使於該NMOS區之該輕摻雜區上之該金屬層暴露出 • I ; (M)去除未被該第二光阻層覆蓋之該金制；（N)以剩 1〇餘之該第二光阻層為罩幕，進行N型離子之輕摻雜離子植 入；以及（Ο)移除該第二光阻層，而形成一第一閘極與—第 二閘極。 承上，本發明之半導體元件之製造方法，可再包括下 列步驟： 15 形成一保護層於該介電層上，使其覆蓋該第一閘極與 S玄第二閘極； • 形成多個第一通孔於該保護層與該介電層中，該些第 一通孔暴露出部分該第一源極/汲極以及該第二源極^及 極；以及 / .20 形成一第一源極/汲極導線以及一第二源極/汲極導線 於該些第一通孔中，該第一源極/汲極導線與該第二源極/ 汲極導線分別電性連接到所對應的該第一源極/及極與該 第二源極/汲極。 〇 1325612 承上，本發明之半導體元件之製造方 下列步驟： 還可再包括 形成一平坦層於該保護層上，使其覆 極導線與該第二源極/汲極導線； 〜第—源極/沒 -.5 15 形成-第二通孔於該平坦層中，該第二 第一源極/沒極導線；以及 、 〇乂 形成一透明電極層於該平坦層上，复 經由該第二通孔連接到該第二源極/沒極導:該透明電極層 在本發:之半導體元件之製造方法中，該基 不限疋，較佳為一玻璃基板或一石英基板。 在本發明之半導體元件之製造 導體層之間可選㈣包含有— +該基板與該半 疋悍旺包3有一綾衝層，且該緩衝層中 型離子與P型離子。該緩衝層係用以阻隔玻璃基板中的金屬 離子擴散至該半導體層中，隊/如〜 f㈣Μ ’降低扮演缺时心形成與漏電 ’爪。因此’該緩衝層之材料不限定，較佳為單層二氧 化石夕（Si0x)或雙層二氧化石夕/氮化石夕（si〇x/siNx)。 一在本發明之半導體元件之製造方法中，該半導體層為 複晶外IMysiU叫層。該步驟（B)中該複晶碎層之形成方 法不限疋，可以任何習用之方法形成複晶^該步驟⑻之 -較佳實施方式為：以化學氣相沉積(C—— deposition) ’於該基板表面形成一非晶矽（am〇rph〇us ⑶n) ^ 乂及以雷射回火（Laser annealing)，使該非晶矽層變成 一複晶珍層。 20 1325612 在本發明之半導體元件之製造方法中，該步驟（c)中該 第一光阻層係以半調式（Half-tone)光罩或灰調式光罩 (Gray-tone)曝光顯影形成，藉以該第—光阻層具有兩種以 上的不同厚度。 在本發明之半導體元件之製造方法中，該介電層之材 料不限定，較佳為氧化矽（Si〇x)層、氮化矽層（SiNx)或其組 合0 在本發明之半導體元件之製造方法中，該金屬層之材[Technical Field] The present invention relates to a method of manufacturing a liquid crystal display, which is suitable for a method of manufacturing a complementary gold-oxide semiconductor TFT of a liquid crystal display. Cattle conductor phase transistor (CMOS [Prior Art] 10 With the advent of the digital age and the rise of flat panel displays, low temperature polysilicon technology has become synonymous with high-quality displays. Under the demand for light, thin, low power consumption, etc. 'High-temperature, high-resolution and high-performance low-temperature Crysite display products are attracting attention' applications include portable information products, digital cameras, digital cameras, notebook computers, mobile phones and high-resolution large-scale video appliances. Because low-temperature polysilicon and thin germanium transistors can overcome the problem of mobility, and 15 provides complementary circuit technology, it also has absolute advantages in component reduction, panel aperture ratio, picture quality and resolution. The main-active liquid crystal display device gradually adopts a complementary MOS film transistor (CMOS TFT) as a peripheral circuit and a switching element of a pixel. However, due to the complementary MOS film, the N-type The MOS-20 field effect transistor will have a gate leakage current in the off state (0ff state) due to the action of the hot carrier. The problem is that N-type MOS field-effect transistors usually have a Hughly doped drain (LDD) region to reduce the gate leakage current. 1325612 Figure to (1) is a conventional complementary A schematic diagram of a method for fabricating a thin film transistor array substrate of a MOS thin film. For example, a complementary MOS thin film transistor designed with a ruthenium-doped ruthenium electrode is required. The most common process steps of the bulk array substrate are required. Process of eight masks. ' " '5 10 15 First, please refer to FIG. 1A, a substrate 1 is provided, which has an N-type metal oxide semiconductor (NMOS) region 210 and a p-type gold oxide. a semiconductor (PMOS) region 220 ′, wherein the NMOS region 210 includes a first doped region 211 , a lightly doped region 212 , a first gate region 213 , and a capacitor region 214 , where the pM〇sg22〇 includes a second doped region 221 and The second gate region 222. Referring to FIG. 1A, a buffer layer ι1〇 is formed on the s-shaped substrate. Then, a low-temperature polysilicon layer (not shown) is formed on the buffer layer 110, and then a lithography is performed. Etching to pattern the low temperature polysilicon layer (not shown) The first semiconductor layer 121 and the second semiconductor layer 122 are formed, wherein the first semiconductor layer 121 is located in the NMOS region 210, and the second semiconductor layer 122 is located in the pm〇S region 22〇. Then, the substrate 100 is Forming a dielectric layer 13〇 (eg, nitride nitride) to cover the dielectric layer 130 on the first semiconductor layer 12]1, the second semiconductor layer 122, and a portion of the substrate 1〇〇. Referring to FIG. 1B, a patterned first photoresist layer 141 is formed on the dielectric layer 130 by one exposure development to expose the first doping region 211 of the NMOS region 210. Then, using the first photoresist layer 141 as a mask, heavily doped ion implantation 910 (n+-i〇ns impiantati〇n) of N-type ions (for example, phosphorus ions or arsenic ions) is performed, thereby forming an NMOS device. Source/drain 121a. 20 丄 325612 Next, referring to FIG. ic, the first photoresist layer 141 is removed. Then, a lithography process is performed to form a patterned metal layer 15 on the dielectric layer. The metal layer 150 covers the first gate region 213 and the capacitor region 214. On the gate region 222. Then, using the metal layer 15 as a mask, a lightly doped implant (11. _ 丨 ^ ^ 加 ) 〇 〇 〇 〇 〇 〇 离子 离子 离子 〇 〇 〇 〇 〇 ( ( ( ( ( ( ( ( ( LDD) 121b. Next, referring to FIG. 1D, an exposure and development is performed to form a patterned first photoresist layer 142 overlying the metal layer 15 and a portion of the dielectric layer 130, and the first > The two doped regions 22 ι are exposed. Then, the 10th second photoresist layer 142 and the metal layer 15 are used as a mask to perform heavily doped ion implantation (p\i〇ns implantati〇n) of the P-type ions (for example, boron ions). The source/ditpole 122ae of the PMOS device is formed. Finally, the second photoresist layer 142' is removed to complete the driving circuit including the complementary MOS film transistor and the storage capacitor. 15 . Next, referring to FIG. 1E , a protective layer 160 is formed on the substrate 100 . Then, a through-hole I60a' penetrating the protective layer 16 and the dielectric layer 130 is defined by one lithography to expose a part of the source-pole 121a of the MOS transistor and a part of the source of the P-type MOS/ Bungee ^ to. Then, a metal is deposited on the protective layer 16G and the through-hole trace, and then a lithography residue 20 is defined to define a secret/secret wire 17 in which the secret electrode 170 fills the via hole. 16Ga covers a portion of the surface of the protective layer 160. Finally, as shown in Fig. 1F, a flat layer 180' is formed on the protective layer 16', and a through-hole lithography is used to define a through-hole through the flat layer U. Then, the deposition-transparent electrode layer 19 is patterned by using the lithography process 1^25612 to complete the thin film transistor array substrate of a liquid crystal display device. However, since the fabrication process is lengthy and complicated, it is not only costly. It is expensive, and it is easy to cause process defects. Therefore, how to reduce the number of masks has become an important issue in the development of thin-film dielectric array substrates. Therefore, there is a need for a method for fabricating a complementary MOS thin film transistor, which simplifies the process of lithography etching to reduce process difficulty, thereby achieving the dual effects of increasing throughput and reducing manufacturing costs. [Invention] In view of the above, the present invention provides a method for fabricating a semiconductor device, which reduces the number of photomasks required for a semiconductor 7L device to two, thereby simplifying the process steps of lithography and improving throughput and reduction. manufacturing cost. The present invention provides a method of fabricating a semiconductor device, comprising the steps of: π (Α) providing a substrate having a germanium-type gold oxide semiconductor (NMOS) and a -P-type metal oxide semiconductor (PM〇S) region, wherein the NMOS The region includes a doped region lightly doped region and a first gate region, the pm 〇 S region includes a _ abundance, a doped region and a second gate region; (8) a comprehensive formation of the body layer on the substrate Forming a _ flute-stop s-resist layer on the semiconductor layer 20 on the NMOS region and the PMOS region, wherein the first photoresist layer on the NMOS region and the PMOS region The thickness of the first photoresist layer is wider than the rest of the first photoresist layer (D) to remove the semiconductor layer not covered by the first photoresist layer; (E) ^, the thickness of the photoresist layer to expose the PMOS region The second doped region & semiconductor layer; (7) with the remaining first photoresist layer as a mask, into the 1325612 • π" ion heavily doped ion implanted (four) into a drain / 3⁄4 pole; (6) removed The remaining first photoresist layer, (Η) sequentially forms a dielectric layer and a metal layer in a comprehensive manner on the substrate and the semiconductor layer; (1) in the region. Forming a first photoresist layer on the polar region and the light-doped region and the second gate region .5 of the PMOS region; (J) removing the metal layer not covered by the second photoresist layer, κ) using the second photoresist layer as a mask, performing heavily doped ion implantation of N-type ions to form a second source/drain; (L) reducing the width of the second photoresist layer to enable The metal layer on the lightly doped region of the NMOS region is exposed to I; (M) removing the gold that is not covered by the second photoresist layer; (N) leaving the second light remaining The resist layer is a mask, performing light doping ion implantation of N-type ions; and removing the second photoresist layer to form a first gate and a second gate. The manufacturing method of the semiconductor device may further include the following steps: 15 forming a protective layer on the dielectric layer to cover the first gate and the S second gate; • forming a plurality of first via holes In the protective layer and the dielectric layer, the first vias expose a portion of the first source/drain and the second source; and /20 forms a first source/drain Wire and a second source/drain wire in the first via hole, the first source/drain wire and the second source/drain wire are electrically connected to the corresponding first source/ And the second source/drain. 〇1325612, the semiconductor device of the present invention is manufactured by the following steps: further comprising forming a planar layer on the protective layer to cover the electrode and the first Two source/drain wires; ~first-source/n-.5 15 forming-second vias in the planar layer, the second first source/no-pole wire; and, 〇乂 forming a transparent The electrode layer is connected to the second source via the second via hole to the second source/no pole: the transparent electrode layer is not limited to the method of manufacturing the semiconductor device of the present invention. It is preferably a glass substrate or a quartz substrate. Optionally, (4) between the fabrication of the conductor layers of the semiconductor device of the present invention comprises: - the substrate and the semiconductor package 3 have a buffer layer, and the buffer layer has medium ions and P-type ions. The buffer layer is used to block the diffusion of metal ions in the glass substrate into the semiconductor layer, and the team/such as ~f(tetra)Μ' reduces the formation of the missing core and the leakage of the claw. Therefore, the material of the buffer layer is not limited, and is preferably a single layer of SiO 2 (Si0x) or a double layer of SiO2/Si 〇 / (si〇x/siNx). In the method of fabricating a semiconductor device of the present invention, the semiconductor layer is a polycrystalline external IMysiU layer. The method for forming the polycrystalline fracture layer in the step (B) is not limited, and the composite crystal can be formed by any conventional method. The step (8) is preferably: chemical vapor deposition (C-deposition) An amorphous germanium (am〇rph〇us (3)n) ^ 乂 and a laser annealing are formed on the surface of the substrate to transform the amorphous germanium layer into a complex crystal layer. 20 1325612 In the manufacturing method of the semiconductor device of the present invention, the first photoresist layer in the step (c) is formed by exposure and development of a half-tone mask or a gray-tone mask. The first photoresist layer has two or more different thicknesses. In the method of fabricating the semiconductor device of the present invention, the material of the dielectric layer is not limited, and preferably a yttrium oxide (Si〇x) layer, a tantalum nitride layer (SiNx), or a combination thereof is used in the semiconductor device of the present invention. In the manufacturing method, the metal layer material
10 1510 15
20 料不限定，較佳係選自由鋁、鎢、鉻、鉬、鈦及其組合所 組成之群組。 、β 在本發明之半導體元件之製造方法中，該步驟減少 該第-光阻層厚之方法不限定，較佳係利用灰化(Ash)減少 該第一光阻層之厚度。 _在本發明之半導體元件之製造方法中，該步驟（F)中p 型離子之重摻雜離子植入製程係植入硼離子。 在本發明之半導體元件之製造方法中，該步驟⑴中該 弟：光阻層之形成方法不限定’較佳係以一曝光顯影製程 形成。 第二 該第 重疊 在本發明之半導體元件之製造方法中，該步驟⑴中該 光阻層與該第二摻雜區可部分重疊或不重疊，較佳為 二光阻層與該第二摻雜區部分重疊，以利於後續^作 (Overlap)型 pm〇S 元件。 ，於步驟 ’剩餘之 因此，在本發明之半導體元件之製造方法中 (J)’未被該第二光阻層覆蓋之該金屬料去除後 12 ⑽612 金屬層與5亥第一摻雜區可部分重疊或不重疊，較佳為剩 餘之該金屬層與該第二摻雜區部分重疊，形成一重疊 (0乂打比{))型1)]^03元件’以提高pM〇s元件之載子移動率與 輸出特性。 一The material is not limited, and is preferably selected from the group consisting of aluminum, tungsten, chromium, molybdenum, titanium, and combinations thereof. In the method of manufacturing a semiconductor device of the present invention, the method of reducing the thickness of the first photoresist layer in this step is not limited, and it is preferable to reduce the thickness of the first photoresist layer by ashing (Ash). In the method of fabricating a semiconductor device of the present invention, the heavily doped ion implantation process of the p-type ions in the step (F) implants boron ions. In the method of fabricating a semiconductor device of the present invention, in the step (1), the method of forming the photoresist layer is not limited to being formed by an exposure and development process. The second overlap is in the manufacturing method of the semiconductor device of the present invention. In the step (1), the photoresist layer and the second doped region may partially overlap or not overlap, preferably the two photoresist layer and the second doping layer. The miscellaneous areas are partially overlapped to facilitate subsequent Overlap type pm〇S components. Therefore, in the step of the remaining, in the manufacturing method of the semiconductor device of the present invention (J) 'the metal material not covered by the second photoresist layer is removed 12 (10) 612 metal layer and 5 hai first doped region Partially overlapping or non-overlapping, preferably the remaining metal layer partially overlaps the second doped region to form an overlap (0 beat ratio {)) type 1)]^03 element 'to improve the pM〇s element Carrier mobility and output characteristics. One
,在本發明之半導體元件之製造方法中，該步驟（K)*N 型離子之重摻雜離子植入製程係植入砷離子或磷離子。 在本發明之半導體元件之製造方法中，該步驟（L)縮小 该第二光阻層寬度之方法不限定，較佳係以灰化縮小該第 二光阻層之寬度。 ,在本發明之半導體元件之製造方法中，該步驟（N)*N 型離子之輕摻雜離子植入製程係植入砷離子或磷離子。 本發明之半導體元件之製造方法所形成之NM0S元件 可位於該基板之像素陣列區内，用來作為—液晶顯示裝置 之像素單元的開關元件。 本發明之半導體元件之製造方法所形成之PM0S元件 與NMOS元件可位一液晶顯示裝置之周邊電路區内，用來作 為該液晶顯示裝置之周邊電路的邏輯元件。 【實施方式】 圖2A至2H繪示本發明之一種半導體元件之一實施例 的製作方法。本實施例為採用互補式金氧半導體薄膜電晶 體之薄膜f晶體㈣基板之製作方法示意圖。本實施例製 作之薄膜電晶體陣列基板中，互補式金氧半導體薄膜電晶 體與儲存電容之製作僅需要使㈣道光罩，並且設計有輕 13 1325612 摻雜汲極（LDD)型之NMOS元件與重疊（Overlap)型之PMOS 元件，以有效提昇互補式金氧半導體薄膜電晶體之效能。 首先’請參閱圖2A，提供一基板300，該基板300具有 •一N型金氧半導體（N]V[〇S)區510、一P型金氧半導體（PM0S) *5 區520與一電容區530，其中該NMOS區510包含一第一摻雜 區51卜一輕摻雜區512與一第一閘極區513,該PMOS區520 包含一第二摻雜區52 1與一第二閘極區522。本實施例採用 之基板300為一玻璃基板。 繼續參閱圖2A ’於該基板上沉積二氧化矽（Si〇2)作為 10 緩衝層3 10。接著’以化學氣相沉積（chemical vapor deposition)於該緩衝層3 10上形成一非晶石夕（amorphous silicon)層（圖中未不），再以雷射回火（Laser annealing)使該 非晶矽層變成一複晶矽層320。然後，於該複晶矽層320上 形成一光阻層（圖未示），隨之對該光阻層（圖未示）進行一次 15 半色調曝光顯影，形成具有兩種以上不同厚度之第一光阻 層341。在本實施例中，該第一光阻層341位於該NMOS區 510、該PMOS區520與該電容區530上，並且該NMOS區510 以及該PMOS區520之第二閘區522上之第一光阻層341厚度 大於該電容區530以及該PMOS區520之第二摻雜區521上之 20 第一光阻層341厚度。另外，該第一光阻層341之周緣最好 略微大於該NMOS區510、該PMOS區520與該電容區530， 以避免通道摻雜的情形發生。 其次，請參閱圖2B，以該第一光阻層341為罩幕，利用 乾或濕蝕刻去除部分複晶矽層320，而形成位於該NMOS區 1325612 510上之第一半導體層321、位於該PMOS區520上之第二半 導體層322與位於該電容區530上之第三半導體層323。在本 實施例中’該複晶石夕層320被過度餘刻，以符合該NM0S區 * 510、該PMOS區520與該電容區530。 -•5 其次，請參閱圖2C，利用灰化（Ash)來減少該第一光阻 . 層341之厚度，以暴露該第三半導體層323以及位於該PM〇s 區520之第二摻雜區52丨上之第二半導體層322。 其次’凊參閱圖2D，以剩餘之第一光阻層341為罩幕， 丨進行P型離子（硼離子）之重摻雜離子植入83〇β藉此，於該第 10二半導體層322中形成PMOS元件之源極/汲極322&。需別注 忍的疋，PMOS元件之源極/汲極3 2 2 a在後續Ν型離子之重換 雜離子植入810與N型離子之輕摻雜離子植入82〇時會裸露 出來，故P型離子的濃度必須遠高於後續N型離子的濃度， 以避免極性改變。 15 其次，參閱圖2E，移除剩餘之第一光阻層34卜然後， 形成一層氮化矽（SiNx)或氧化矽（Si〇x)或兩者之組合覆蓋於 部分該緩衝層310、該第一半導體層321、該第二半導體層 322與該第三半導體層323上作為介電層33〇 ^接著，於該 NMOS區510之該第一閘極區513與該輕摻雜區512上、該 20 PM〇S區520之該第二閘極區U2上以及部分該電容區53〇二 形成一圖案化之金屬層3 50與一圖案化之第二光阻層342。 在本實施例中，該第二光阻層342係經由一次曝光^影形 成；該金屬層350係以該第二光阻層342為罩幕’經由蝕刻 去除其未被該第二光阻層342覆蓋之部分所形成。另外，為 15 1325612 了製作重疊（Overlap)型PMOS元件’本實施例之該第二光阻 層342以及該金屬層350之周緣會略大於該PMOS區520之該 第二閘極區522，也就是與該第二摻雜區521部分重疊。 • 繼續參閱圖2E。隨後’以該第二光阻層342與該金屬層 -5 350為罩幕，進行N型離子（砷離子）之重摻雜離子植入81〇。 藉此’於該第一半導體層321中形成NMOS元件之源極/汲極 321a。這裡需特別提醒的是，由於pMOS元件之源極/汲極 322a此時裸露出來’所以需注意於控制n型離子之植入濃度 ^ 與深度。另外’由於該緩衝層310此時亦裸露出來，因此該 10 緩衝層310中會同時含有n型離子與p型離子。 其次’參閱圖2F ’利用灰化（Ash)來縮小該第二光阻層 342之寬度，以暴露出位於該1^]“〇8區51〇之該輕摻雜區512 上之该金屬層350 ;再以該被縮小寬度之第二光阻層342為 罩幕，將暴露出來的金屬層350去除。然後，以被縮小寬度 15之第二光阻層342以及金屬層350為罩幕，進行N型離子（磷 離子）之輕摻雜離子植入82〇。藉此，於該第一半導體層32 i 中形成輕摻雜汲極（LDD)321b。同樣的，由於pM〇s元件之 源極/汲極322a此時裸露出來，所以這裡也需注意控制^^型 離子之植入濃度與深度。 20 其次，參閱圖2G，去除該第二光阻層342以形成第一 閘極352與第二閘極351，從而形成包含]^^〇8元件⑺盥 ^MOS元件20之互補式金氧半導體薄膜電晶體以及儲存電 合30。在本實施例中，部分該>?%〇8元件係設置於液晶顯 示裝置之顯示區内，用來作為像素單元的開關元件部分 1325612 該PMOS兀件20與該NMOS元件1 〇係設置液晶顯示裝置之 周邊電路，用來作為周邊電路的邏輯元件。 其次，請參閱圖2Η，於該基板300上形成一保護層 / 360。然後，利用一次微影蝕刻定義出貫穿該保護層36〇與 “5 §亥介電層33〇之通孔360a，以顯露NMOS元件之部分源極/ 汲極321a、PMOS元件之部分源極/汲極322a以及部分第三 半導體層323。接著，沉積金屬於該保護層36〇上與該通孔 360a中，再進行一次微影蝕刻定義出第一源極/汲極導線π〗 i 以及第二源極/汲極導線371。在本實施例中，該第一源極/ 10汲極導線372以及該第二源極/汲極導線371填滿該通孔360a 且覆蓋於該保護層360之部分表面。 最後，如圖21所示，於該保護層36〇上形成一平坦層 380，再利用一次微影蝕刻定義出貫穿該平坦層38〇之通孔 380a。然後，沉積一透明電極層39〇,再進行一次微影蝕刻 15使其圖案化，而形成一液晶顯示裝置之薄膜電晶體陣列基 板。 土 由本實施例可見，本實施例製作互補式金氧半導體薄 膜電晶體僅需兩道光罩，而製作薄膜電晶體陣列基板則需 /、道光罩，因此，可簡化微影蝕刻之製程步驟以降低製程 20困難度，以達到提高產能與降低製造成本之雙重效果。 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 於上述實施例。 又 17 1325612 【圖式簡單說明j 圓i A至圖IF係習知採用互補式全齑 補式金虱+導體薄膜電晶體之薄 膜電晶體陣列基板之製作方法剖面示意圖。 ， 圖2A至圖21繪示本發明 < 一種+導體元件《一實施例的製 -*5 作方法。 主要元件符號說明 ίο 10 20 30 100 、 300 110 ' 310 15 121、321 121a > 321a 121b 、 321b 1 122 ' 322 122a ' 322a 20 130、330 141 、 341 142 、 342 150 ' 350 160 ' 360 25 160a、180a NMOS元件 PMOS元件 儲存電容 基板 緩衝層 第一半導體層 NMOS元件之源極/汲極 輕摻雜汲極 第二半導體層 PMOS元件之源極/汲極 介電層 第一光阻層 第二光阻層 金屬層 保護層 、360a、380a 通孔 18 1325612 170 ' 370 源極/汲極導線 180 ' 380 平坦層 - 190 ' 390 透明電極層 • 210 、 510 N型金氧半導體（NMOS)區 5 211 、 511 第一摻雜區 - 212 、 512 輕摻雜區 213 、 513 第一閘極區 214 ' 530 電容區 • 220 、 520 P型金氧半導體（PMOS)區 10 221 ' 521 第二摻雜區 222 ' 522 第二閘極區 320 複晶矽層 323 第三半導體層 351 第二閘極 15 352 第一閘極 371 第二源極/汲極導線 372 第一源極/汲極導線 • 810 、 910 N型離子之重摻雜離子植入 820 、 920 N型離子之輕摻雜離子植入 20 830 ' 930 P型離子之重摻雜離子植入 19 (S )In the method of fabricating a semiconductor device of the present invention, the heavy-doped ion implantation process of the step (K)*N-type ions is implanted with arsenic ions or phosphorus ions. In the method of fabricating the semiconductor device of the present invention, the method of reducing the width of the second photoresist layer in the step (L) is not limited, and it is preferable to reduce the width of the second photoresist layer by ashing. In the method of fabricating a semiconductor device of the present invention, the lightly doped ion implantation process of the (N)*N type ion is implanted with arsenic ions or phosphorus ions. The NMOS device formed by the method of fabricating the semiconductor device of the present invention can be located in the pixel array region of the substrate for use as a switching element of a pixel unit of a liquid crystal display device. The PMOS element and the NMOS element formed by the method of manufacturing a semiconductor device of the present invention can be used as a logic element of a peripheral circuit of the liquid crystal display device in a peripheral circuit region of a liquid crystal display device. [Embodiment] Figs. 2A to 2H illustrate a method of fabricating an embodiment of a semiconductor device of the present invention. This embodiment is a schematic diagram of a method for fabricating a thin film f crystal (four) substrate using a complementary MOS film. In the thin film transistor array substrate fabricated in this embodiment, the fabrication of the complementary MOS film transistor and the storage capacitor only requires a (four) reticle, and is designed with a light 13 1325612 doped drain (LDD) type NMOS device and Overlap type PMOS components to effectively enhance the performance of complementary MOS thin film transistors. First, please refer to FIG. 2A, a substrate 300 is provided. The substrate 300 has an N-type metal oxide semiconductor (N]V[〇S) region 510, a P-type metal oxide semiconductor (PM0S), a *5 region 520 and a capacitor. The NMOS region 510 includes a first doped region 51 and a lightly doped region 512 and a first gate region 513. The PMOS region 520 includes a second doped region 52 1 and a second gate. Polar zone 522. The substrate 300 used in this embodiment is a glass substrate. Further, as shown in Fig. 2A', a cerium oxide (Si 〇 2) is deposited as a 10 buffer layer 3 10 on the substrate. Then, an amorphous silicon layer (not shown) is formed on the buffer layer 3 10 by chemical vapor deposition, and the amorphous is made by laser annealing. The germanium layer becomes a poly germanium layer 320. Then, a photoresist layer (not shown) is formed on the polysilicon layer 320, and then the photoresist layer (not shown) is subjected to a 15 halftone exposure development to form a layer having two or more different thicknesses. A photoresist layer 341. In this embodiment, the first photoresist layer 341 is located on the NMOS region 510, the PMOS region 520 and the capacitor region 530, and the first region of the NMOS region 510 and the second gate region 522 of the PMOS region 520 The thickness of the photoresist layer 341 is greater than the thickness of the first photoresist layer 341 on the capacitor region 530 and the second doping region 521 of the PMOS region 520. In addition, the periphery of the first photoresist layer 341 is preferably slightly larger than the NMOS region 510, the PMOS region 520 and the capacitor region 530 to avoid channel doping. Next, referring to FIG. 2B, the first photoresist layer 341 is used as a mask, and a portion of the polysilicon layer 320 is removed by dry or wet etching to form a first semiconductor layer 321 located on the NMOS region 1325612 510. The second semiconductor layer 322 on the PMOS region 520 and the third semiconductor layer 323 on the capacitor region 530. In the present embodiment, the polycrystalline layer 320 is excessively entrapped to conform to the NMOS region * 510, the PMOS region 520, and the capacitor region 530. -•5 Next, referring to FIG. 2C, ashing (Ash) is used to reduce the thickness of the first photoresist layer 341 to expose the third semiconductor layer 323 and the second doping in the PM 〇 s region 520. The second semiconductor layer 322 is on the region 52. Next, referring to FIG. 2D, the remaining first photoresist layer 341 is used as a mask, and heavily doped ion implantation of P-type ions (boron ions) is performed on the 〇β, whereby the 10th second semiconductor layer 322 is used. The source/drain 322& of the PMOS device is formed. Need to be patient, the source/drain of the PMOS device 3 2 2 a will be exposed when the subsequent cesium-type ion-exchanged ion implantation 810 and the N-type ion light-doped ion implantation 82 裸 are exposed. The concentration of P-type ions must be much higher than the concentration of subsequent N-type ions to avoid polarity changes. 15, referring to FIG. 2E, removing the remaining first photoresist layer 34 and then forming a layer of tantalum nitride (SiNx) or tantalum oxide (Si〇x) or a combination of the two to cover a portion of the buffer layer 310, The first semiconductor layer 321 , the second semiconductor layer 322 and the third semiconductor layer 323 are followed by a dielectric layer 33 , and the first gate region 513 and the lightly doped region 512 of the NMOS region 510 . A patterned metal layer 305 and a patterned second photoresist layer 342 are formed on the second gate region U2 of the 20 PM 〇S region 520 and a portion of the capacitor region 〇2. In this embodiment, the second photoresist layer 342 is formed by one exposure; the metal layer 350 is masked by the second photoresist layer 342. It is removed by etching without the second photoresist layer. The portion covered by 342 is formed. In addition, for the 15 1325612, an overlap type PMOS device is formed. The second photoresist layer 342 of the embodiment and the periphery of the metal layer 350 are slightly larger than the second gate region 522 of the PMOS region 520. That is, it partially overlaps with the second doping region 521. • Continue to Figure 2E. Subsequently, the second photoresist layer 342 and the metal layer -5 350 are used as masks to perform heavily doped ion implantation of N-type ions (arsenic ions) 81 〇. Thereby, the source/drain 321a of the NMOS device is formed in the first semiconductor layer 321. It should be specially noted here that since the source/drain 322a of the pMOS device is exposed at this time, it is necessary to pay attention to controlling the implantation concentration of the n-type ion ^ and the depth. In addition, since the buffer layer 310 is also exposed at this time, the 10 buffer layer 310 contains both n-type ions and p-type ions. Next, referring to FIG. 2F, the width of the second photoresist layer 342 is reduced by ashing (Ash) to expose the metal layer on the lightly doped region 512 of the ^8 region 51〇. And removing the exposed metal layer 350 by using the reduced width second photoresist layer 342 as a mask. Then, the second photoresist layer 342 and the metal layer 350 having the reduced width 15 are used as a mask. Lightly doped ion implantation of N-type ions (phosphorus ions) is performed 82. Thereby, a lightly doped drain (LDD) 321b is formed in the first semiconductor layer 32 i. Similarly, due to the pM〇s element The source/drain 322a is exposed at this time, so it is also necessary to pay attention to controlling the implantation concentration and depth of the ions. 20 Next, referring to FIG. 2G, the second photoresist layer 342 is removed to form the first gate 352. And the second gate 351, thereby forming a complementary MOS film transistor including the MOS device 20 and storing the electricity 30. In this embodiment, part of the >?%〇 8 components are disposed in the display area of the liquid crystal display device, and are used as a switching element portion of the pixel unit 1325612. The S device 20 and the NMOS device 1 are provided with peripheral circuits of the liquid crystal display device for use as logic elements of the peripheral circuit. Next, referring to FIG. 2, a protective layer / 360 is formed on the substrate 300. Then, A lithography etch defines a via 360a extending through the protective layer 36 and the "5 § dielectric layer 33" to expose a portion of the source/drain 321a of the NMOS device and a portion of the source/drain 322a of the PMOS device. And a portion of the third semiconductor layer 323. Next, a metal is deposited on the protective layer 36 and the via 360a, and a photolithographic etching is performed to define a first source/drain wire π〗 and a second source/drain wire 371. In this embodiment, the first source/10 drain wire 372 and the second source/drain wire 371 fill the through hole 360a and cover a part of the surface of the protective layer 360. Finally, as shown in Fig. 21, a flat layer 380 is formed on the protective layer 36, and a via 380a penetrating the flat layer 38 is defined by a single photolithography. Then, a transparent electrode layer 39 is deposited, and then subjected to a photolithography etching 15 to pattern it to form a thin film transistor array substrate of a liquid crystal display device. It can be seen from the present embodiment that in this embodiment, only two photomasks are required for fabricating a complementary MOS film, and a photomask is required for the fabrication of the thin film transistor array substrate. Therefore, the process steps of the lithography etching can be simplified to reduce The process 20 is difficult to achieve the dual effects of increasing production capacity and reducing manufacturing costs. The above-described embodiments are merely examples for the convenience of the description, and the scope of the claims is intended to be limited by the scope of the claims. 17 1325612 [Simplified illustration of j-circle i A to Figure IF is a schematic cross-sectional view of a conventional method for fabricating a thin film transistor array substrate using a complementary full-filled metal 虱 + conductor thin film transistor. 2A to 21 illustrate a method of fabricating a +-conductor element of the present invention. Main component symbol description ίο 10 20 30 100 , 300 110 ' 310 15 121, 321 121a > 321a 121b , 321b 1 122 ' 322 122a ' 322a 20 130, 330 141 , 341 142 , 342 150 ' 350 160 ' 360 25 160a 180a NMOS device PMOS device storage capacitor substrate buffer layer first semiconductor layer NMOS device source/drain lightly doped drain second semiconductor layer PMOS device source/drain dielectric layer first photoresist layer second Photoresist layer metal layer protection layer, 360a, 380a via hole 18 1325612 170 ' 370 source/drain conductor 180 '380 flat layer - 190 ' 390 transparent electrode layer • 210, 510 N-type metal oxide semiconductor (NMOS) region 5 211, 511 first doped region - 212, 512 lightly doped region 213, 513 first gate region 214 ' 530 capacitor region • 220, 520 P-type metal oxide semiconductor (PMOS) region 10 221 '521 second doping Region 222 ' 522 second gate region 320 poly germanium layer 323 third semiconductor layer 351 second gate 15 352 first gate 371 second source/drain conductor 372 first source/drain conductor • 810 , 910 N-type heavy doped ion implantation 820, 920 N-type light-doped ion implantation 20 830 ' 930 P-type ion heavily doped ion implantation 19 (S )