TWI317486B - Architecture for finite state machine decomposition - Google Patents
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- TWI317486B TWI317486B TW095134164A TW95134164A TWI317486B TW I317486 B TWI317486 B TW I317486B TW 095134164 A TW095134164 A TW 095134164A TW 95134164 A TW95134164 A TW 95134164A TW I317486 B TWI317486 B TW I317486B
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1317486 '•九、發明說明: 【發明所屬之技術領域】 ' 本發明係有關於—種電路分解架構,尤其是-種低功率 : 有限狀態機電路之分解架構。 【先前技術】 » 將-個有限狀態機_切她machine; FSM)電路切割成 备干個次狀態機(SUb-machine)電路,已被證明可以有效地大幅 降低整體有限狀態機電路之平均功率(average p〇wer)。其原理 是當此有限狀態機運作時,只驅動其中之—之次狀態機電路, 並停止其它*需使狀:欠狀g機電路之運作藉此,降低整體 有限狀_電财之娜動作(switching activities),進而達到 降低平均功率之目地。 以在之文獻大多只討論如何降低有限狀態機電路之平均 ' 功率’本發明提出一種新的改良架構’不僅可以降健體有限 狀賴f路之平均神’並且亦可降健體有限狀態機電路之 峰值功率(peak power;)。 隨著積體f路之複雜度增加與王作鮮提高,功率消耗 之問題變得愈來愈嚴重,也愈來愈重要。動態功率消耗以電路 中之信號切換動作為主,其原理係當電路中之邏輯%之輪入值 5 ⑧ 1317486 • 有變動時’寄生電容會有一電流經由VDD或Vss進行充放電。 因此,動態功率消耗與電路中之信號切換動作係具有一成正比 . 之關係存在。 : 一個有限狀態機可被定義成6組集合{I,S,δ, 〇, λ,S〇}, 其中I係輸入(input)之集合’ S係狀態(State)之集合,δ係IxS—2s 是狀態轉移之函數’ 〇係輸出(output)之集合,λ係lxS-^20是 輸出之函數,最後S〇eS是初始狀態之集合。一個有限狀態機 鲁 亦可以用狀態轉換圖(state transition graph ; STG)來加以描述, 有限狀態機Μ之STG可記成Gm(Vm,Em),其中Vm係節點 (node)之集合’代表 M之狀態(state)集合;Em = {<u,v>,u, 係邊(edge)之集合,每一邊代表在M之中由一狀態u跳至另一 狀態v ’所有之邊都被標上一組輸入及輸出,其在STG圖中係 代表輸入觸發狀態之變動以及產生相對之輸出。 φ 對有限狀態機電路而言,一種有效降健號切換動作之 方式係關掉整體有限狀態機電路中暫時沒有使用之部份,亦即 ' 豸-有赚祕電路蝴成若干個次狀誠電路,並且只驅動 料之—以及停止其它不需使用之次狀態機電路。然而,值得 注忍的是’-個分割出來之次狀態機電路與原來傳統未作分割 之有限狀誠·係麵碑,亦特—個錄顏電路係會 存在-些從另-個次狀態機電路出發或到達另—個次狀態機 電路之狀態,而這將會使得電路在分割及設計上更趨複雜。 ⑧ 6 1317486 ·. · 一種有限狀態機電路之切割方式係稱為“循序邏輯分解 (sequential logic decomposition; SLD)’’之切割架構(如第一 a 圖 , 所示)。以將一有限狀態機電路切割成兩個次有限狀態機Ml、 ^ M2為例,其利用鎖住次有限狀態機Ml、M2之時脈,把其中 不需使用之次有限狀態機Ml或M2之暫存器停止,藉此使得 被停止時脈之次有限狀態機Ml或M2之處理下一狀態之組合 電路之輸入不會改變,進而降低次有限狀態機Ml、M2整體 • 電路之輸入信號改變。更詳細資料可以參閱J. C. Monterio and A. L. Oliveria,“Finite State Machine Decomposition for Low1317486 '• Nine, invention description: [Technical field to which the invention pertains] The present invention relates to a circuit decomposition architecture, in particular, a low power: decomposition architecture of a finite state machine circuit. [Prior Art] » Cutting a finite state machine _ cutting her machine; FSM) circuit into a sub-state machine (SUb-machine) circuit, which has been proven to effectively reduce the average power of the overall finite state machine circuit. (average p〇wer). The principle is that when the finite state machine is in operation, only the state machine circuit of the second state is driven, and the other * need to be made: the operation of the under-glyph circuit is used to reduce the overall finite shape. (switching activities), thereby achieving the goal of reducing the average power. In the literature, most of them only discuss how to reduce the average 'power' of finite state machine circuits. The present invention proposes a new improved architecture that can not only reduce the average finite shape of the body, but also reduce the finite state machine. The peak power of the circuit (peak power;). As the complexity of the integrated circuit and Wang Zuosheng increase, the problem of power consumption becomes more and more serious and more and more important. The dynamic power consumption is dominated by the signal switching action in the circuit. The principle is that the logic value of the circuit is rounded up. 5 8 1317486 • When there is a change, the parasitic capacitance will be charged and discharged via VDD or Vss. Therefore, the dynamic power consumption has a proportional relationship with the signal switching action in the circuit. : A finite state machine can be defined as a set of six sets {I, S, δ, 〇, λ, S〇}, where the set of I-inputs is the set of S-states, and the δ-system IxS— 2s is the function of the state transition 'the output of the output system, the λ system lxS-^20 is the output function, and finally S〇eS is the set of the initial state. A finite state machine can also be described by a state transition graph (STG). The finite state machine STG can be recorded as Gm (Vm, Em), where the set of Vm nodes (node) represents M State set; Em = {<u, v>, u, set of edges, each side represents a state u jumping from M to another state v 'all sides are A set of inputs and outputs are indicated, which in the STG diagram represent changes in the input trigger state and produce a relative output. φ For the finite state machine circuit, an effective way to switch the action of the health is to turn off the part of the overall finite state machine circuit that is not used temporarily, that is, '豸-have a profitable circuit. The circuit, and only drives the material - and stops other state machine circuits that do not need to be used. However, it is worthy of being tolerant that the 'statement circuit that is segmented out and the finite shape of the original tradition are not divided, and the system of facial recordings is also present. The circuit starts or reaches the state of another state machine circuit, which will make the circuit more complicated in segmentation and design. 8 6 1317486 · · · A finite state machine circuit cutting method is called "sequential logic decomposition (SLD)" cutting structure (as shown in the first a figure, shown) to a finite state machine The circuit is cut into two sub-finite state machines M1, ^ M2 as an example, which uses the clocks of the secondary finite state machines M1 and M2 to stop the register of the finite state machine M1 or M2 which is not needed to be used. Thereby, the input of the combined circuit of the next state of the finite state machine M1 or M2 of the stopped clock is not changed, thereby reducing the input signal change of the overall circuit of the sub-finite state machine M1, M2. More details can be See JC Monterio and AL Oliveria, "Finite State Machine Decomposition for Low
Power55, Proc. Design Automaton Conference, 1998, pp. 758-763 與 L. Benini and G. De Micheli,“State Assignment for Low Power Dissipation’’,in the Solid-State Circuits, IEEE Journal ofPower55, Proc. Design Automaton Conference, 1998, pp. 758-763 and L. Benini and G. De Micheli, "State Assignment for Low Power Dissipation", in the Solid-State Circuits, IEEE Journal of
Volume 30, Issue 3, 1995, pp. 258-268 ° 而另一種有限狀態機電路之切割方式係稱為“組合邏輯 分解(combinational logic decomposition ; CLD)”之切割架構(如 . 第一 B圖所示)。以切割成兩個次有限狀態機Ml、M2為例, 其利用數個及閘(AND gate)對不須使用之次有限狀態機M1或 M2之輸入進行阻擋。例如:當次有限狀態機M1電路在關閉 之狀態時,係由解碼器送出一邏輯〇之信號給次有限狀態機 Ml電路前之三個及閘,藉此將次有限狀態機Ml電路之輸入 變為邏輯0。如果次有限狀態機Ml電路之後還是一直為關閉 1317486 狀態時’送入次有限狀態機Ml電路之輸入亦將恆為邏輯0。 藉此’此分解架構亦可以降低輸入次有限狀態機ΜΙ、M2之 輸入轉換頻率以減少電路中之信號切換動作。更詳細資料可以 參閱 S. H. Chow, Y. C. Ho, T. Hwang and C. L. Liu,“Low Power Realization of Finite State Machine-A Decomposition Approach’’, ACM TODAES,vol. 1,1996, pp. 315-340。 然而,根據上述之組合邏輯分解之切割架構,如果利用 及閘來控制次有限狀態機Ml、M2之動作與否時,當要關掉 其中一個次有限狀態機Ml或M2時,及閘會強迫被關掉之次 有限狀態機Ml或M2之輸入全部為邏輯〇。因此,在次有限 狀態機Ml、M2轉移之瞬間,會造成兩個次有限狀態機M1 與M2都會有輸入信號之切換動作,其效果係等同兩個次有限 狀態機Ml、M2同時運作。舉例來說,從次有限狀態機mi 跳至次有限狀態機M2時,次有限狀態機M1前之及閘會強迫 次有限狀態機Ml之所有輸入全部為邏輯〇,而此同時,儲存 狀態之暫存器FF。、FFl、ff2 t把内容值灌進次有限狀態機 M2。所以在次有限狀態機Ml轉移至M2這一瞬間,次有限 狀態機Ml、M2都會有輸入信號之切換動作,此一現象將會 造成很大之峰值功率(因為次有限狀態機Μι、m2—起變動)。 鑒於以上所述之有限狀態機電路分解架構之缺點’實有 需要持續發展新的改良電路分解架構以克服㈣技藝之各項 1317486 缺失。所以,如何避免有限狀態機電路同時進行狀態切換以及 如何降低有限狀態機電路之峰值功率與平均功率等,是此技術 : 領域必然會遭遇之問題,亦是本發明所要解決之問題。 【發明内容】 鑒於上述之發明背景,為符合產業上某些利益之需求, φ 本發明&供一種有限狀態機電路之分解架構,以解決上述傳統 有限狀態機電路分解架構未能達成之標的。 本發明揭露一種有限狀態機電路之分解架構,其藉由一 儲存模組依一選擇信號選取輸出一狀態信號,並閃鎖其他未被 選取之狀態信號,藉此’僅改變一有限狀態機次電路之輸入以 降低有限狀癌機整體電路之峰值功率(peak power)與平均功率 (average power);並藉由一緩衝模組調整信號傳遞時間,使得 # 此狀態信號與此選擇信號可以同時被此儲存模組接收,藉此, 避免因信號處理之級數差異而產生延遲錯誤。 本發明提供一種有限狀態機電路之分解架構,其包含: 複數個有限狀態機次模組,係對應接收複數個第一狀態信號與 一第一輸入信號,並對應輸出複數個第二狀態信號、複數個輸 出信號與複數個第一選擇信號;一選擇模組,係接收此些第二 狀態信號、此些輸出信號、此些第一選擇信號與一第二選擇信 1317486 號’並依此第二選擇信號選取此些第二狀態信號其中之一、此 些輸出信號其中之一與此些第一選擇信號其中之一輸出;一暫 存模組,係接收此選擇模組輸出之第二狀態信號與第一選擇信 號’並暫存後輸出此第二狀態信號與此第二選擇信號;—解碼 模組,係接收此第二選擇信號,並解碼後輸出一第三選擇信 號;以及一儲存模組,係接收一第二輸入信號、此第二狀態信 號與此第三選擇信號’並輸出此些第一狀態信號與此第一輸入 h號’其中此儲存模組係以此第二輸入信號取代此第一輸入信 號’並以此第二狀態信號取代此第三選擇信號所選之第一狀態 信號。 本發明更提供一種有限狀態機電路之分解架構,其包 含··兩有限狀態機次模組,係對應接收兩第一狀態信號與一第 一輸入信號,並對應輸出兩第二狀態信號、兩輸出信號與兩第 一選擇信號;複數個多工器,係對應接收此兩第二狀態信號、 此兩輸出信號、此兩第一選擇信號與一第二選擇信號,並依此 第二選擇信號選取此兩第二狀態信號其中之一、此兩輸出信號 其中之一與此兩第一選擇信號其中之一輸出;複數個正反器, 係對應接收此些多工器輸出之第二狀態信號與第一選擇信 號’並暫存後輸出此第·一狀態信號與此第二選擇信號;一解碼 器,係接收此第二選擇信號’並解碼輸出一第三選擇信號;複 數個儲存裝置,係對應接收一第二輪入信號、此第二狀態信號 1317486 與此第三選擇信號’並且輸出此兩第一狀態信號與此第一輸入 信號’其中此些儲存裝置係以此第二輸入信號取代此第一輸入 信號’並以此第二狀態信號取代此第三選擇信號所選取之第一 狀態信號;以及一緩衝模組,係用以使此第二狀態信號與此第 三選擇信號可同時輸出至此些儲存裝置。 【實施方式】 本發明在此所探討的方向為一種有限狀態機電路之分解 架構。為了能夠徹底地瞭解本發明,將在下列描述中提出詳盡 之步驟及組成。顯然地,本發明之施行並未限定於此項領域之 技藝者所熟習之特殊細節。另一方面,果所周知之組成或步驟 亦並未描述於細節中,避免造成本發明不必要之限制。本發明 之較佳實施例會洋細描述如下,然而除了這些詳細描述之外, 本發明還可以廣泛地施行在其他之實施例中,且本發明之範圍 亦不受限定,其以之後之專利範圍為準。 凊參照第一圖,其為本發明之一較佳實施例之概略系統 方塊圖。複數個有限狀態機次模組、M:2、...、Mn,係對應 接收複數個第一狀態信號與一第一輪入信號(其中此第一輸入 信號搭配此複數個第一狀態信號形成複數個信號丨〇4),並對應 輪出複數個第二狀態信號112、複數個輸出信號116與複數個 第一選擇信號114。在本實施例中,有限狀態機次模組Μι、 11 1317486 '* M2、...、Mn係由切割一有限狀態機電路110所形成,且其等 之架構係可依實際絲切躺成,並不受限等分糊之架構, . 其中,η 22且η為自然數。在本實施例中,第一輸入信號係 . 包含一 1位元資料(丨> 〇且i為自然數);每一第一狀態信號係 包含一 j位元資料(j > 〇且j為自然數);每一第二狀態信號112 係包含一 j位元資料;每一輸出信號116係包含一 q位元資料 (q>0且q為自然數);以及每一第一選擇信號114係包含_k • 位元資料(k > 〇且k為自然數),其中,每一 m位元信號1〇4 係由一 i位元第一輸入信號與一 j位元第一狀態信號所組成, 亦即m = i+j ’而第一選擇信號114之位元數k與有限狀態機 次模組Μ〗、M2、…、Mn之個數η的關係為n$2k。 一選擇模組120,係接收上述之第二狀態信號112、輸出 信號116、第一選擇信號114與一第二選擇信號134,並依據 第二選擇信號134選取此些第二狀態信號112其中之一、輸出 籲 信號116其中之一與第一選擇信號114其中之一輸出,其中, 選擇模組120輪出之信號124 (包含第二狀態信號與第一選擇 信號)與輸出信號122係由有限狀態機次模組、M2、...、 Mn其中之一所產生。在本實施例中,第二選擇信號134係一 相對第一選擇信號114之k;位元資料,ρ位元k说124係由一 j位元第一狀態信號與一 k位元第一選擇信號114所組成,即 p=j+k° 12 1317486 一暫存模組130,係接收選擇模組120所輪出之作號 (包含第二狀態信號與第一選擇信號),並且暫存後輪出此第一 狀態信號132與上述之第二選擇信號134。 一解碼模組140,係接收暫存模組丨30所輸出之第二選擇 信號134 ’並且解碼後輸出一第三選擇信號142,其中,第二 選擇彳§號142係包含一 r位元資料(r = 2k)。 一儲存模組150,係接收一第二輸入信號1〇2、暫存模組 130所輸出之第二狀態信號132與解碼模組14〇所輪出之第= 選擇佗號142,並輸出有限狀態機次模組Mi、Ms、...、μ所 對應接收之複數個信號104 (第一狀態信號與第一輸入信號)。 在本實施例中,儲存模組150係以第二輸入信號1〇2取代第一 輸入信號,並以第二狀態信號132取代第三選擇信號142所選 之第一狀態信號,亦即,儲存模組15〇係依據第三選擇信號 142選取一第一狀態信號,並以第二狀態信號132取代此第一 狀態信號,而其他未被選取之第一狀態信號則維持不變,藉此 僅改變一有限狀態機次模組之輸入以避免有限狀態機電路11〇 之所有輸入狀態同時改變,以降低有限狀態機電路11()之峰值 力率(peak power)與平均功率(average p0wer)。 一緩衝模組160’係用以使得暫存模組130所輸出之第二 狀態信號132與解碼模組14〇所輸出之第三選擇信號142可以 同時抵達儲存模組150 ’藉此,避免因信號處理之級數不同而 1317486 產生延遲錯誤。在本實施例中,緩衝模組16〇係延遲暫存模組 130處理第二狀態信號132電路之時脈⑹,而所延遲之時脈 162之時間係相等於解碼模組14〇將第二選擇信號134解碼成 第三選擇信號142所需之時間,藉此,暫存模組13〇所輸出之 第二狀態信號132與解碼模組14〇所輪出之第三選擇信號142 即可同時輸出至儲存模組150以避免因信號處理之級數不同 而產生延遲錯誤。在另一實施例中,亦可將緩衝模組16〇加在 暫存模組130與儲存模組150之間以作為第二狀態信號132之 資料緩衝,藉此,使得信號處理之級數相同以避免上述之延遲 錯誤。 請參照第三圖’其為一有限狀態機之狀態轉換圖(state transition graph ; STG)。在本實施例中,此有限狀態機係僅用 以說明本發明之範例’其並非用以限定本發明之實施。此有限 狀態機係包含7個狀態,其等分別為Sl(狀態為〇〇〇)、S2(狀態 為001)、S3(狀態為111)、S4(狀態為010)、S5(狀態為1〇0)、 S6(狀態為011)以及S7(狀態為101),其中此7個狀態被分割 成為兩個狀態之子集合S’ = {Sl,S4, S6}與S” = {S2, S3, S5, S7},然後分別利用S’與S”構成稍後說明之有限狀態機次模組 Mi、Μ〗之分解架構。 當S1(狀態為000)輸入為〇時’狀態變成S6(狀態為oil) 且輸出為00 ;當S1輸入為1時,狀態變成S4(狀態為01〇)且 1317486 · 輸出為㈧。當S4(狀態為010)輸入為〇時,狀態變成S6(狀態 為011)且輸出為00 ;當S4輸入為1時,狀態變成S6且輸出 為10。當S6(狀態為011)輸入為〇時,狀態變成Sl(狀態為〇〇〇) ' 且輸出為01 ;而當S6輸入為1時,狀態變成不同子集合之 S2(狀態為001)且輸出為01。當S2(狀態為001)輪入為〇時, 狀態變成S5(狀態為1〇〇)且輸出為00 ;當S2輸入為1,狀態 變成S3(狀態為m)且輸出為〇〇。當S3(狀態為111)輸入為〇 鲁時,狀態變成S5(狀態為1〇〇)且輸出為〇〇 ;當S3輸入為1時, 狀態變成S7(狀態為101)且輸出為〇〇。當S5(狀態為1〇〇)輸入 為〇時’狀態變成不同子集合之Sl(狀態為〇〇〇)且輸出為1〇 ; 當S5輸入為1時,狀態變成S2(狀態為〇〇1)且輸出為1〇。當 S7(狀態為101)輸入為〇時,狀態變成S5(狀態為1〇〇)且輸出 為00,而當S7輸入為1時,狀態變成不同子集合之S6(狀維 為011)且輸出為10。下列表一係上述之有限狀態機之真值表, • 其中FFO欄位係控制有限狀態機次模組、m2開關之暫存器 FFO之内容值(稱後說明)。Volume 30, Issue 3, 1995, pp. 258-268 ° and another finite state machine circuit is cut by a "combinational logic decomposition (CLD)" cutting architecture (eg. Show). Taking the two finite state machines M1, M2 cut as an example, it uses several AND gates to block the input of the secondary finite state machine M1 or M2 that is not needed. For example, when the secondary finite state machine M1 circuit is in the off state, the decoder sends a logic signal to the third gate of the secondary finite state machine M1 circuit, thereby inputting the secondary finite state machine M1 circuit. Becomes a logic 0. If the sub-finite state machine M1 circuit is still turned off after the 1317486 state, the input to the sub-finite state machine M1 circuit will also be a logic 0. In this way, the decomposition architecture can also reduce the input switching frequency of the input finite state machine ΜΙ, M2 to reduce the signal switching action in the circuit. For more details, see SH Chow, YC Ho, T. Hwang and CL Liu, "Low Power Realization of Finite State Machine-A Decomposition Approach'', ACM TODAES, vol. 1, 1996, pp. 315-340. According to the above-mentioned combination logic decomposition cutting structure, if the gate and the gate are used to control the action of the secondary finite state machine M1, M2, when one of the secondary finite state machines M1 or M2 is to be turned off, the gate will be forced to be shut down. The input of the finite state machine M1 or M2 is all logical 〇. Therefore, at the moment when the secondary finite state machines M1 and M2 are transferred, the two finite state machines M1 and M2 will have the switching action of the input signal. The effect is equivalent to the operation of two sub-finite state machines M1, M2. For example, when jumping from the sub-finite state machine mi to the sub-finite state machine M2, the gate before the sub-finite state machine M1 forces the sub-finite state machine Ml All the inputs are all logical, and at the same time, the storage state registers FF, FF1, ff2 t pour the content value into the secondary finite state machine M2. Therefore, the moment when the secondary finite state machine M1 shifts to M2 The secondary finite state machine M1, M2 will have the switching action of the input signal, this phenomenon will cause a large peak power (because the secondary finite state machine Μι, m2 - change). In view of the above finite state machine circuit decomposition The shortcomings of the architecture 'there is a need to continue to develop new improved circuit decomposition architectures to overcome the lack of (4) various 1317486 techniques. Therefore, how to avoid the state switching of finite state machine circuits and how to reduce the peak power and average power of finite state machine circuits Etc., this technology: the problem that the field will inevitably encounter, and the problem to be solved by the present invention. [Invention] In view of the above-mentioned background of the invention, in order to meet the needs of certain interests in the industry, φ the present invention & The decomposition architecture of the state machine circuit solves the problem that the conventional finite state machine circuit decomposition architecture fails to achieve. The present invention discloses a decomposition architecture of a finite state machine circuit, which selects an output state according to a selection signal by a storage module. Signal and flash other unselected status signals, thereby 'changing only one The input of the finite state machine circuit reduces the peak power and average power of the finite cancer computer circuit; and adjusts the signal transmission time by a buffer module, so that this state signal and this selection The signal can be received by the storage module at the same time, thereby avoiding delay errors caused by the difference in the level of signal processing. The present invention provides a decomposition architecture of a finite state machine circuit, which includes: a plurality of finite state machine modules, Receiving a plurality of first state signals and a first input signal, and correspondingly outputting a plurality of second state signals, a plurality of output signals, and a plurality of first selection signals; and a selection module receiving the second states The signal, the output signals, the first selection signals and a second selection signal 1317486', and selecting one of the second status signals according to the second selection signal, one of the output signals and the One of the first selection signals is output; a temporary storage module receives the second status signal outputted by the selection module and the first selection signal And outputting the second state signal and the second selection signal; the decoding module receives the second selection signal and outputs a third selection signal after decoding; and a storage module receives a second input signal The second state signal and the third selection signal 'and output the first state signal and the first input h number 'where the storage module replaces the first input signal with the second input signal and The second status signal replaces the first status signal selected by the third selection signal. The invention further provides a decomposition architecture of a finite state machine circuit, comprising: two finite state machine modules, corresponding to receiving two first state signals and a first input signal, and correspondingly outputting two second state signals, two The output signal and the two first selection signals; the plurality of multiplexers correspondingly receive the two second state signals, the two output signals, the two first selection signals and a second selection signal, and accordingly the second selection signal Selecting one of the two second state signals, one of the two output signals and one of the two first selection signals; the plurality of flip-flops corresponding to the second state signal receiving the outputs of the plurality of multiplexers And the first selection signal 'and temporarily storing the first state signal and the second selection signal; a decoder receiving the second selection signal 'and decoding and outputting a third selection signal; a plurality of storage devices, Correspondingly receiving a second round-in signal, the second state signal 1317486 and the third selection signal 'and outputting the two first state signals and the first input signal' The storage device replaces the first input signal with the second input signal and replaces the first state signal selected by the third selection signal with the second state signal; and a buffer module is used to make the second The status signal and the third selection signal can be simultaneously output to the storage devices. [Embodiment] The direction of the invention discussed herein is a decomposition architecture of a finite state machine circuit. In order to fully understand the present invention, detailed steps and compositions will be set forth in the following description. It is apparent that the practice of the invention is not limited to the specific details familiar to those skilled in the art. On the other hand, well-known components or steps are not described in detail to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention will be described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited, and the scope of the invention is Prevail. Referring to the first figure, which is a schematic block diagram of a preferred embodiment of the present invention. a plurality of finite state machine modules, M: 2, ..., Mn, corresponding to receiving a plurality of first state signals and a first wheeling signal (where the first input signal is coupled with the plurality of first state signals) A plurality of signals 丨〇4) are formed, and a plurality of second state signals 112, a plurality of output signals 116, and a plurality of first selection signals 114 are correspondingly rotated. In this embodiment, the finite state machine module Μι, 11 1317486 '* M2, ..., Mn is formed by cutting a finite state machine circuit 110, and its architecture can be cut according to the actual wire. , is not limited to the structure of the paste, where η 22 and η are natural numbers. In this embodiment, the first input signal system includes a 1-bit data (丨> i and i is a natural number); each first state signal includes a j-bit data (j > 〇 and j a natural number); each second state signal 112 includes a j-bit data; each output signal 116 includes a q-bit data (q > 0 and q is a natural number); and each first selection signal The 114 series contains _k • bit data (k > 〇 and k is a natural number), where each m-bit signal 1〇4 is composed of an i-bit first input signal and a j-bit first state The signal consists of m = i + j ' and the relationship between the number k of the first selection signal 114 and the number η of the finite state machine modules Μ, M2, ..., Mn is n$2k. The selection module 120 receives the second state signal 112, the output signal 116, the first selection signal 114 and a second selection signal 134, and selects the second state signals 112 according to the second selection signal 134. 1. Outputting one of the output call signals 116 and one of the first selection signals 114, wherein the signals 124 (including the second state signal and the first selection signal) and the output signal 122 of the selection module 120 are limited by One of the state machine modules, M2, ..., Mn is generated. In this embodiment, the second selection signal 134 is a relative to the first selection signal 114; the bit data, the p-bit k is 124 is selected by a j-bit first state signal and a k-bit first selection The signal 114 is composed of p=j+k° 12 1317486. A temporary storage module 130 receives the number of the selection module 120 (including the second status signal and the first selection signal), and is temporarily stored. The first state signal 132 and the second selection signal 134 are rotated. A decoding module 140 receives the second selection signal 134 ′ output by the temporary storage module 并且 30 and outputs a third selection signal 142 after decoding, wherein the second selection § § 142 includes an r bit data. (r = 2k). A storage module 150 receives a second input signal 1 〇 2, a second status signal 132 output by the temporary storage module 130, and a first selection 佗 142 rotated by the decoding module 14 ,, and the output is limited. The state machine module Mi, Ms, ..., μ corresponds to a plurality of signals 104 (first state signal and first input signal) received. In this embodiment, the storage module 150 replaces the first input signal with the second input signal 1〇2, and replaces the first status signal selected by the third selection signal 142 with the second status signal 132, that is, stores The module 15 selects a first state signal according to the third selection signal 142, and replaces the first state signal with the second state signal 132, while the other unselected first state signals remain unchanged, thereby Changing the input of a finite state machine module avoids simultaneous changes in all input states of the finite state machine circuit 11 to reduce the peak power and average p0wer of the finite state machine circuit 11(). A buffer module 160' is configured to enable the second status signal 132 output by the temporary storage module 130 and the third selection signal 142 output by the decoding module 14 to arrive at the storage module 150' at the same time, thereby avoiding The number of stages of signal processing is different and 1317486 produces a delay error. In this embodiment, the buffer module 16 is configured to delay the clock (6) of the circuit of the second state signal 132 by the temporary storage module 130, and the time of the delayed clock 162 is equal to the decoding module 14 and the second The time required for the selection signal 134 to be decoded into the third selection signal 142, whereby the second state signal 132 output by the temporary storage module 13 is simultaneously with the third selection signal 142 rotated by the decoding module 14 Output to the storage module 150 to avoid delay errors due to different levels of signal processing. In another embodiment, the buffer module 16 can be added between the temporary storage module 130 and the storage module 150 as a data buffer of the second status signal 132, thereby making the signal processing level the same. To avoid the above delay errors. Please refer to the third figure, which is a state transition graph (STG) of a finite state machine. In the present embodiment, this finite state machine is only used to illustrate the example of the present invention, which is not intended to limit the implementation of the present invention. The finite state machine system includes seven states, which are respectively S1 (state 〇〇〇), S2 (state 001), S3 (state 111), S4 (state 010), and S5 (state 1). 0), S6 (state 011) and S7 (state 101), wherein the 7 states are divided into subsets of two states S' = {Sl, S4, S6} and S" = {S2, S3, S5 , S7}, and then use S' and S respectively to form a decomposition structure of the finite state machine module Mi, Μ, which will be described later. When S1 (state 000) input is 〇, the state changes to S6 (state is oil) and the output is 00; when S1 input is 1, the state changes to S4 (state is 01〇) and 1317486 · output is (eight). When the S4 (state 010) input is 〇, the state changes to S6 (state 011) and the output is 00; when the S4 input is 1, the state changes to S6 and the output is 10. When the input of S6 (state 011) is 〇, the state becomes Sl (state 〇〇〇) ' and the output is 01; and when the S6 input is 1, the state becomes S2 of different subsets (state 001) and the output Is 01. When S2 (state 001) is rounded, the state changes to S5 (state is 1〇〇) and the output is 00; when S2 input is 1, the state changes to S3 (state is m) and the output is 〇〇. When the S3 (state 111) input is 〇, the state changes to S5 (state is 1 〇〇) and the output is 〇〇; when the S3 input is 1, the state changes to S7 (state 101) and the output is 〇〇. When the input of S5 (state 1〇〇) is 〇, the state becomes Sl of different subsets (state is 〇〇〇) and the output is 1〇; when the input of S5 is 1, the state becomes S2 (state is 〇〇1) And the output is 1〇. When S7 (state 101) input is 〇, the state changes to S5 (state is 1〇〇) and the output is 00, and when S7 input is 1, the state becomes S6 of different subsets (shape is 011) and the output Is 10. The following list is the truth table of the finite state machine mentioned above, • The FFO field controls the content value of the finite state machine module and the register FFO of the m2 switch (refer to the following description).
目前狀態 D2D1D0 輸入 下一狀態 Q2Q1Q0 輪出 FFO Ml S1 000 0 S6 011 ___〇〇 〇 — 1 S4 010 00 0 15 1317486 S4 010 0 S6 011 00 0 1 S6 011 10 0 S6 011 0 S1 000 01 0 1 S2 001 01 1 M2 S2 001 0 S5 100 00 1 1 S3 111 00 1 S3 111 0 S5 100 00 1 1 S7 101 00 1 S5 100 0 S1 000 10 0 1 S2 001 10 1 S7 101 0 S5 100 00 1 1 S6 011 10 0 表一上述之有限狀態機之真值表Current state D2D1D0 Input next state Q2Q1Q0 Round FFO Ml S1 000 0 S6 011 ___〇〇〇-1 S4 010 00 0 15 1317486 S4 010 0 S6 011 00 0 1 S6 011 10 0 S6 011 0 S1 000 01 0 1 S2 001 01 1 M2 S2 001 0 S5 100 00 1 1 S3 111 00 1 S3 111 0 S5 100 00 1 1 S7 101 00 1 S5 100 0 S1 000 10 0 1 S2 001 10 1 S7 101 0 S5 100 00 1 1 S6 011 10 0 Table 1 The truth table of the above finite state machine
請參照第四圖’其為本發明依第三圖之實施例所實施之 一較佳有限狀態機電路之分解架構圖。兩有限狀態機次模組 Μ卜M2,係對應接收兩第一狀態信號與一第一輸入信號(其中 此第一輸入信號係分別搭配此兩第一狀態信號),並對應輸出 兩第二狀態信號、兩輸出信號與兩第一選擇信號。其中,有限 狀態機次模組Μ!、Μ2係切割一有限狀態機電路11〇所形成, 且其等之架構係可依實際需求切割而成,並不受限等分切割之 1317486 架構,例如:Ml具有上述S,= {Sl,S4, S6}之狀態子集合;而 M2具有上述s - { S2, S3, S5, S7}之狀態子集合。在本實施例 中,第一輸入信號係包含一 i位元資料(i > 〇且i為自然數); 每一第一狀態信號係包含一 j位元資料(j > 0且j為自然數); 每一第二狀態信號係包含一 j位元資料;每一輸出信號係包含 一 q位元資料(q> 〇且q為自然數);以及每一第一選擇信號係 包含一 k位元資料(k>0且k為自然數),其中,i==1、j = 3、 1、q = 2,然不限於此,其等可依實際需求而加以調整,而 第一選擇信號之位元數k與有限狀態機次模組之個數n的關係 為 η $ 2k。 複數個多工器MUX (係對照第二圖之選擇模組12〇),係 對應接收上述之第二狀態信號、輸出信號、第一選擇信號與一 第二選擇信號’並依第二選擇信號選取此兩第二狀態信號其中 之一、輸出信號其中之一與第一選擇信號其中之一輪出,並且 在本實施例中,此些多工器MUX輸出之第二狀態信號、第一 選擇信號與輸出信號係由有限狀態機次模組Ml、M2其中之一 所產生。此外,第二選擇信號係一相對第一選擇信號之k位元 資料,然不限於此。 複數個正反器FF3、FF2、FF1、FFO (對照第二圖之暫存 模組130) ’係對應接收複數個多工器MUX所輸出之第-狀雜 信號與第一選擇信號,並暫存後輸出此第二狀態信號(由FF3= (S) 17 1317486 FF2與FH輸出)與上述之第二選擇信號(由輸出),此第二 選擇信號即上述控制有限狀態機次模組Mi、M2開關之暫存器 FFO之内容值。 一解碼器(係對照第二圖之解碼模組14〇),係接收正反器 FFO所輸出之第二選擇信號,並解碼後輸出一第三選擇信號, 其中’此第二選擇信號係包含一 1*位元資料(r = 2k)。因此,當 k=l時,2位元之第三選擇信號即可以直接控制兩有限狀態機 次模組Ml、M2開關。 複數個閂鎖器(對照第二圖之儲存模組15〇),係對應接收 一第二輸入信號、正反器FF3、FF2與FF1所輸出之第二狀態 信號與解碼器所輸出之第三選擇信號,並且輸出兩有限狀態機 次模組Ml、M2所對應接收之兩第一狀態信號與一第一輸入 信號。在本實施例中’此些閂鎖器係以第二輸入信號取代第一 輸入信號,並以第二狀態信號取代第三選擇信號所選取之第一 狀態信號’亦即’此些閂鎖器係依據第三選擇信號將第二狀態 仏號傳送到開啟之有限狀態機次模組Ml或M2以取代原第— 狀態信號,而其他未被選取之第一狀態信號則維持不變,藉此 僅改變一有限狀態機次模組之輸入以避免有限狀態機電路11〇 之所有輸入狀態同時改變,並降低有限狀態機電路丨丨〇之峰值 功率與平均功率。在另一實施例中,上述之複數個閂鎖器亦可 用記憶體等儲存裝置取代。 18 1317486 一緩衝器(第二圖之儲械組_,_以使得 FF3、FF2、FF1所輸出之第二狀態信號與解碼HHO所輪出之 第三選擇信號可同時抵達複數個閃顧,藉此,避免信號處理 級數關而產生延遲錯誤。在本實施例中,緩触16〇係^遲 正反器FF3〜FF1之時脈,而所延遲之時脈係相等於解竭器⑽ 將第二選擇信號解碼成第三選擇錢所需之脈係,藉此正反器 FF3〜FF1所輸出之第二狀態信號與解碼器⑽輸出之第三選擇 信號即可同時輸出至複數個問鎖器以避免上述之延遲錯誤。 請參照第五A圖與第五b圖,其等係分別為第三圖所示 之實施例以習知組合邏輯分解(CLD)之切_構與以第四圖 之分解架構實施之信驗形®。此兩波形_翻以說明縱向 所示之信號彼此間的相互關係,而其橫向係代表時間軸,至於 其他未標示之單位(例如電壓單位、時間單位)在此均省略以求 圖示之簡潔。 請參照第五A圖,在Ts時間點時,狀態從有限狀態機次 模組Ml之S6跳至有限狀態機次模組m2之S2,且信號 MI-ΟΝ從1變〇 (表示關閉有限狀態機次模組M1),信號 M2—ON從0變1 (表示開啟有限狀態機次模組μ),因此, Ml輸入從ion變〇〇〇〇 ’而M2輸入從0000變丨。在丁9 時間點時’狀態從M2之S5跳至Ml之S1,且信號Μ1_ΟΝ 從0變1 (表示開啟Ml),信號μ2_ΟΝ從1變〇 (表示關閉 19 1317486 M2),因此,Ml輸入從〇〇〇〇變〇〇〇〇,而M2輸入從0100變 0000。在T13時間點時,狀態從Ml之S6跳至M2之S2,且 ; 信號Ml_ΟΝ從1變〇 (表示關閉Ml),信號M2_ON從0變1 ; (表示開啟M2),因此,Ml輸入從1011變0000,而M2輸入 從 0000 變 1001。 請參照第五B圖,在T5時間點時,狀態從有限狀態機次 | 模組Ml之S6跳至有限狀態機次模組M2之S2,且信號Please refer to the fourth figure, which is an exploded structural diagram of a preferred finite state machine circuit implemented according to the embodiment of the third embodiment of the present invention. The two finite state machine modules M2 receive corresponding two first state signals and a first input signal (where the first input signal is respectively matched with the two first state signals), and correspondingly output two second states The signal, the two output signals and the two first selection signals. Among them, the finite state machine module Μ!, Μ 2 system is cut into a finite state machine circuit 11〇, and its architecture can be cut according to actual needs, and is not limited to the dicing 1317486 architecture, for example :Ml has the state subset of S, = {Sl, S4, S6}; and M2 has the state subset of s - {S2, S3, S5, S7} above. In this embodiment, the first input signal includes an i-bit data (i > and i is a natural number); each first state signal includes a j-bit data (j > 0 and j is a natural number); each second state signal system includes a j-bit data; each output signal includes a q-bit data (q> and q is a natural number); and each of the first selection signals includes one K-bit data (k>0 and k is a natural number), where i==1, j=3, 1, q=2, but it is not limited thereto, and the like can be adjusted according to actual needs, and the first The relationship between the number of bits k of the selection signal and the number n of finite state machine modules is η $ 2k. a plurality of multiplexer MUXs (corresponding to the selection module 12A of the second figure), corresponding to receiving the second state signal, the output signal, the first selection signal and a second selection signal 'and according to the second selection signal Selecting one of the two second state signals, one of the output signals and one of the first selection signals, and in the embodiment, the second state signal, the first selection signal output by the multiplexer MUX The output signal is generated by one of the finite state machine modules M1, M2. Further, the second selection signal is a k-bit data relative to the first selection signal, but is not limited thereto. A plurality of flip-flops FF3, FF2, FF1, FFO (cf. the temporary storage module 130 of the second figure) are corresponding to receiving the first-shaped hetero-signal and the first selection signal outputted by the plurality of multiplexers MUX, and temporarily And storing the second state signal (outputted by FF3=(S) 17 1317486 FF2 and FH) and the second selection signal (by output), the second selection signal being the control finite state machine module Mi, The content value of the register FFO of the M2 switch. a decoder (comprising the decoding module 14A of the second figure) receives the second selection signal output by the flip-flop FFO, and decodes and outputs a third selection signal, where 'this second selection signal includes A 1* bit data (r = 2k). Therefore, when k=l, the third selection signal of the two bits can directly control the switches of the two finite state machine modules M1 and M2. A plurality of latches (comprising the storage module 15A of the second figure) are corresponding to receiving a second input signal, a second state signal output by the flip-flops FF3, FF2, and FF1, and a third output by the decoder. The signal is selected, and the two first state signals corresponding to the two finite state machine modules M1 and M2 and the first input signal are output. In this embodiment, the latches replace the first input signal with the second input signal, and replace the first state signal selected by the third selection signal with the second state signal, that is, the latches. The second state signal is transmitted to the open finite state machine module M1 or M2 according to the third selection signal to replace the original first state signal, and the other unselected first state signals remain unchanged. Only the input of a finite state machine module is changed to avoid simultaneous changes in all input states of the finite state machine circuit 11 and to reduce the peak power and average power of the finite state machine circuit. In another embodiment, the plurality of latches described above may be replaced by a storage device such as a memory. 18 1317486 A buffer (the storage group _, _ in the second figure enables the second status signal output by FF3, FF2, FF1 and the third selection signal rotated by the decoding HHO to simultaneously reach a plurality of flashes, Therefore, the signal processing stage is prevented from being turned off and a delay error is generated. In this embodiment, the clock of the 〇3/FF1 is delayed, and the delayed clock system is equal to the decompressor (10). The second selection signal is decoded into a pulse system required for the third selection money, whereby the second state signal output by the flip-flops FF3 FFFF1 and the third selection signal output by the decoder (10) can be simultaneously output to the plurality of challenge locks. In order to avoid the above-mentioned delay error, please refer to the fifth A diagram and the fifth b diagram, which are respectively the fourth embodiment shown in the third figure, with the conventional combinational logic decomposition (CLD) and the fourth The decomposition of the diagram is implemented in the letter of perception. These two waveforms are used to illustrate the relationship between the signals shown in the longitudinal direction, while the horizontal system represents the time axis, as for other unlabeled units (such as voltage units, time units). ) are omitted here for the sake of simplicity. Please refer to the fifth. In Figure A, at the time of Ts, the state jumps from S6 of the finite state machine module M1 to S2 of the finite state machine module m2, and the signal MI-ΟΝ changes from 1 (indicating that the finite state machine module is turned off) M1), the signal M2—ON changes from 0 to 1 (indicating that the finite state machine module μ is turned on), therefore, the M1 input changes from ion to 'the M2 input changes from 0000 to □. The state jumps from S5 of M2 to S1 of M1, and the signal Μ1_ΟΝ changes from 0 to 1 (indicating that M1 is turned on), and the signal μ2_ΟΝ changes from 1 (indicating that 19 1317486 M2 is turned off), therefore, the M1 input changes from 〇〇〇〇. 〇〇, and the M2 input changes from 0100 to 0000. At the time T13, the state jumps from S6 of M1 to S2 of M2, and; the signal Ml_ΟΝ changes from 1 to 〇 (indicating that M1 is turned off), and the signal M2_ON changes from 0 to 1; Indicates that M2 is turned on. Therefore, the M1 input changes from 1011 to 0000, and the M2 input changes from 0000 to 1001. Please refer to Figure 5B. At the T5 time, the state jumps from the finite state machine | module M1 to the limited S2 of the state machine module M2, and the signal
Ml_〇N從1變0 (表示關閉有限狀態機次模組Ml),信號 M2_ON從0變1 (表示開啟有限狀態機次模組M2),因此, Ml輸入從1011變1011,而M2輸入從xxxx變1001。在T9 時間點時,狀態從M2之S5跳至Ml之S1,且信號Μ1_ΟΝ 從0變1 (表示開啟Ml),信號Μ2_ΟΝ從1變0 (表示關閉 M2),因此,Ml輸入從1011變0000,而M2輸入從0100變 0100。在T13時間點時,狀態從Ml之S6跳至M2之S2,且 B 信號Μ1_ΟΝ從1變0 (表示關閉Ml),信號M2_ON從0變1 . (表示開啟M2) ’因此,Ml輸入從1011變1011,而M2輸入 從 0100 變 1001。 狀態在Ml、M2間 互相轉移 Ml之輸入值變化 M2之輸入值變化 Ml—M2 1011—0000 0000—1001 20 1317486 M2—Ml 〇〇〇〇—〇〇〇〇 0100—0000 Ml—M2 1011—0000 0000—1001 表二A使用組合邏輯分解之切割架構,狀態在Ml、M2 之間互相轉移時,輸入有限狀態機次模組Ml、M2之輸入值 變動狀況 狀態在Ml、M2間 互相轉移 Ml之輸入值變化 M2之輸入值變化 Ml—>M2 1011—1011 xxxx—1001 1011-^0000 0100—0100 1011—1011 0100—1001 表二B使用第四圖之分解架構,狀態在Ml、M2間互相 轉移時,輸入有限狀態機次模組Ml、M2之輸入值變動狀況 (xxxx表任意值或隨意值) 表二A與表二B係分別為使用組合邏輯分解之切割架構 與使用第四圖之分解架構,狀態在有限狀態機次模組Ml、M2 之間互相轉移時,輸入有限狀態機次模組Ml、M2之輸入值 變動狀況。根據上述之波形圖與下列表格資料,在第五A圖 與表二A中,當Ml與M2間互相狀態轉移時,會有M1與 1317486 M2之輸入同時改變之情況,此時mi、M2都會有信號切換之 動作’亦即增加電路之峰值功率。另一方面,在第五B圖與 表一 B中,當Ml與M2間互相狀態轉移時,並不會發生Ml 與M2之輸入同時產生變化之情況,一定會有一個Μ〗或M2 之輸入疋保持不動’例如:當目前狀態從Ml轉移至M2時, Ml之輸入是ion—維持不變。因此,本發明之分解架構 對整體有限狀態機電路之峰值功率(peak power)係具有明顯地 降低之功效。Ml_〇N changes from 1 to 0 (indicating that the finite state machine module M1 is turned off), and the signal M2_ON changes from 0 to 1 (indicating that the finite state machine module M2 is turned on), therefore, the M1 input changes from 1011 to 1011, and the M2 input Change from xxxx to 1001. At time T9, the state jumps from S5 of M2 to S1 of M1, and the signal Μ1_ΟΝ changes from 0 to 1 (indicating that M1 is turned on), and the signal Μ2_ΟΝ changes from 1 to 0 (indicating that M2 is turned off), therefore, the M1 input changes from 1011 to 0000. And the M2 input changes from 0100 to 0100. At the time T13, the state jumps from S6 of M1 to S2 of M2, and the B signal Μ1_ΟΝ changes from 1 to 0 (indicating that M1 is turned off), and the signal M2_ON changes from 0 to 1. (Indicating that M2 is turned on) 'So, M1 is input from 1011. Change 1011, and the M2 input changes from 0100 to 1001. The state changes between M1 and M2. The input value of M1 changes M2. The input value changes Ml_M2 1011—0000 0000—1001 20 1317486 M2—Ml 〇〇〇〇—〇〇〇〇0100—0000 Ml—M2 1011—0000 0000—1001 Table 2A uses the cutting logic of the combinatorial logic decomposition. When the state transitions between M1 and M2, the state of the input value change of the input finite state machine modules M1 and M2 transfers M1 to each other between M1 and M2. Input value change M2 input value change Ml -> M2 1011 - 1011 xxxx - 1001 1011 - ^ 0000 0100 - 0100 1011 - 1011 0100 - 1001 Table 2 B uses the decomposition diagram of the fourth figure, the state is between Ml, M2 During the transfer, input the change of the input value of the finite state machine module Ml, M2 (any value or random value of the xxxx table). Table 2A and Table 2B are respectively the cutting structure using the combinational logic decomposition and the use of the fourth figure. The decomposition architecture, when the state transitions between the finite state machine modules M1 and M2, inputs the change of the input values of the finite state machine modules M1 and M2. According to the above waveform diagram and the following table data, in the fifth A diagram and the second table A, when the state transition between M1 and M2, the input of M1 and 1317486 M2 will change at the same time, at this time, mi and M2 will be There is a signal switching action 'that is to increase the peak power of the circuit. On the other hand, in the fifth B and the table B, when M1 and M2 are mutually transferred, the input of M1 and M2 does not change at the same time, and there must be an input of Μ or M2.疋 Stay still', for example: When the current state is transferred from M1 to M2, the input of Ml is ion-maintained. Thus, the decomposition architecture of the present invention provides a significant reduction in peak power for the overall finite state machine circuit.
Ml之輸入值變化 M2之輸入值變化 1 1000->1010 1 0000—1001 2 1010—1011 2 1001—0001 3 1011—0000 3 0001-^0100 4 〇〇〇〇一〇〇11 4 0100—0000 5 0011—1011 5 0000—1001 6 1011—0000 6 1001—1111 7 1111—1101 8 1101—0101 9 0101—0100 表三A使用組合邏輯分解之切割架構,Μ卜M2之所有 輸入變動 22 1317486M1 input value change M2 input value change 1 1000->1010 1 0000-1001 2 1010-1011 2 1001—0001 3 1011—0000 3 0001-^0100 4 〇〇〇〇一〇〇11 4 0100—0000 5 0011—1011 5 0000—1001 6 1011—0000 6 1001—1111 7 1111—1101 8 1101—0101 9 0101—0100 Table 3A uses the combination logic to decompose the cutting architecture, and all the input changes of M2 22 1317486
Ml之輸入值變化 M2之輸入值變化 1 1000—1010 1 χχχχ^ΙΟΟΙ 2 1010—1011 2 1001—0001 3 1011—^0000 3 0001—0100 4 0000-^0011 4 0100-^1001 5 0011—4011 5 1001—1111 6 1111—1101 7 1101-^0101 8 0101—0100M1 input value change M2 input value change 1 1000-1010 1 χχχχ^ΙΟΟΙ 2 1010—1011 2 1001—0001 3 1011—^0000 3 0001—0100 4 0000-^0011 4 0100-^1001 5 0011—4011 5 1001—1111 6 1111—1101 7 1101-^0101 8 0101—0100
表三B使用第四圖之分解架構,μ卜M2所有輸入變動 (xxxx表任意值或隨意值) 表三Α與表三Β係分別為使用組合邏輯分解之切割架構 與使用第四圖之分解架構,有限狀態機次模組Ml、M2所有 輸入變動。就平均功率(average P〇wer)而言,平均功率之大小 係與Ml、M2總輸入變化次數有關。因此,比較表三A以及 表三B,從表三A中可發現,使用組合邏輯分解(CLD)之切割 架構時’ Ml、M2輪入變動次數之總和是15 ;而從表三β中 可發現’使用本發明之分解架構時,]VII、M2輸入變動次數之 總和是13。由此’本發明之分解架構對整體有限狀態機電路Table 3B uses the decomposition structure of the fourth figure, all the input changes of the μB M2 (any value or random value of the xxxx table). Table 3Α and Table 3 are respectively the cutting structure using the combinational logic decomposition and the decomposition using the fourth figure. Architecture, finite state machine module Ml, M2 all input changes. In terms of average power (average power), the average power is related to the total number of input changes of M1 and M2. Therefore, comparing Table 3A and Table 3B, it can be found from Table 3A that when using the combination logic decomposition (CLD) cutting architecture, the sum of the number of changes in the Ml and M2 rounds is 15; It was found that when using the decomposition architecture of the present invention, the sum of the number of input changes of VII and M2 is 13. Thus the decomposition architecture of the present invention is directed to the overall finite state machine circuit
23 1317486 之平均功率係具有明顯地降低之效果。 請參照第六圖,其為第三圖所示之實施例以第四圖分解 架構並以不同輸入實施之信號波形圖。此波形圖係僅用以說明 縱向所示之信號彼此間的相互關係,而其橫向係代表時間軸, 至於其他未標示之單位(例如電壓單位、時間單位)在此均省略 以求圖示之簡潔。在丁5時間點時,狀態從有限狀態機次模組 之S6跳至有限狀態機次模組m2之S2,且信號Μ1」)Ν 從1變〇 (表示關閉有限狀態機次模組Ml),信號M2J3N從〇 變1 (表示開啟有限狀態機次模組M2),因此,Ml輸入從l〇u 變1001,而M2輸入從χχχχ變1〇〇1。在tu時間點時,狀態 從M2之S7跳至Ml之S6,且信號Μ1_ΟΝ從0變1 (表開啟 Ml),信號M2—ON從1變〇 (表關閉M2),因此,Ml輸入從 1011變1011 ’而M2輸入從1101變11〇1。在τ13時間點時, 狀態從Ml之S6跳至M2之S2,且信號Μ1_ΟΝ從1變〇 (表 不關閉Ml) ’信號Μ2_ΟΝ從0變1 (表示開啟M2),因此, Ml輸入從1011變ι〇11,而m2輸入從n〇1變1〇〇1。根據此 波形圖’有限狀態機次模組Mi、M2之輸入並不會同時改變, 例如:在時間點Ts時,僅改變m2之輸入;在時間點丁13時, 僅改變M2之輸入;甚至在時間點Tll時,有限狀態機次模組 Μ卜M2之輸入均維持原輸入。 顯然地,依照上面實施例中之描述,本發明可能有許多 24 ⑧ 1317486 之修正與差異。耻需要在其附加之糊要求項之細内加以 理解,除了上述詳、細之描料,本發明還可以廣泛地在其他之 實施例中施行。上述僅為本發明之較佳實_而已,並非用以 限定本發明之巾請專利麵;凡其它紐離本發明所揭示精神 下所完成之等效改變或修飾’均應包含相下所述之巾請專利 範圍内。 【圖式簡單說明】 第一 A圖係有限狀態機電路之一種習知循序邏輯分解 (sequential logic decomposition ; SLD)之切割架構; 第一 B圖係有限狀態機電路之一種習知組合邏輯分解 (combinational logic decomposition ; CLD)之切割架構; 第二圖係本發明之一較佳實施例之概略系統方塊圖; 第三圖係一有限狀態機之狀態轉換圖(state杜姐8出〇11 graph ; STG); 第四圖係本發明依第三圖之實施例所實施之一較佳分解 架構圖; 第五A圖係第三圖之實施例以習知組合邏輯分解之切割 架構所實施之信號波形圖;The average power of 23 1317486 has a significantly reduced effect. Please refer to the sixth figure, which is a signal waveform diagram of the embodiment shown in the third figure, which is decomposed by the fourth figure and implemented with different inputs. This waveform diagram is only used to illustrate the relationship between the signals shown in the longitudinal direction, and the horizontal system represents the time axis. Other unlabeled units (such as voltage units and time units) are omitted here for illustration. concise. At time D, the state jumps from S6 of the finite state machine module to S2 of the finite state machine module m2, and the signal Μ1") Ν changes from 1 (indicating that the finite state machine module M1 is turned off) The signal M2J3N changes from 〇 to 1 (indicating that the finite state machine module M2 is turned on), therefore, the M1 input changes from l〇u to 1001, and the M2 input changes from χχχχ1 to 1. At the time of the tu, the state jumps from S7 of M2 to S6 of M1, and the signal Μ1_ΟΝ changes from 0 to 1 (the table turns on M1), and the signal M2_ON changes from 1 (the table turns off M2), therefore, the M1 input is from 1011. Change 1011 ' and the M2 input changes from 1101 to 11〇1. At the time of τ13, the state jumps from S6 of M1 to S2 of M2, and the signal Μ1_ΟΝ changes from 1 to 〇 (the table does not turn off M1) 'Signal Μ2_ΟΝ changes from 0 to 1 (indicating that M2 is turned on), therefore, the M1 input changes from 1011 〇11, and the m2 input changes from n〇1 to 1〇〇1. According to this waveform diagram, the input of the finite state machine module Mi, M2 does not change at the same time, for example: at the time point Ts, only the input of m2 is changed; at the time point, only the input of M2 is changed; At the time point T11, the input of the finite state machine module M2 maintains the original input. Obviously, the invention may have many modifications and differences of 24 8 1317486 in accordance with the description in the above embodiments. The shame needs to be understood within the scope of its additional paste requirements, and the present invention can be widely practiced in other embodiments in addition to the detailed and detailed description above. The above is only the preferred embodiment of the present invention, and is not intended to limit the scope of the invention. Any equivalent changes or modifications made by the spirit of the present invention should include the following. The towel is within the scope of the patent. [Simplified Schematic] The first A picture is a conventional sequential logic decomposition (SLD) cutting architecture of the finite state machine circuit; the first B picture is a conventional combinational logic decomposition of the finite state machine circuit ( The cut-off architecture of the combinational logic decomposition; CLD); the second diagram is a schematic system block diagram of a preferred embodiment of the present invention; the third diagram is a state transition diagram of a finite state machine (state Du Jie 8 out 11 graph; The fourth diagram is a preferred decomposition architecture diagram of the embodiment of the present invention according to the third embodiment; the fifth diagram is the signal implemented by the conventional combination logic decomposition scheme. Waveform diagram
25 1317486 第五B圖係第三圖之實施例以第四圖之分解架構實施之 信號波形圖;以及 第六圖係第三圖之實施例以第四圖之分解架構並以不同 輸入實施之信號波形圖。25 1317486 Figure 5B is a signal waveform diagram of the embodiment of the third figure implemented by the decomposition architecture of the fourth figure; and the embodiment of the third figure of the sixth figure is implemented by the decomposition structure of the fourth figure and implemented with different inputs. Signal waveform diagram.
【主要元件符號說明】 110 有限狀態機電路 120 選擇模組 130 暫存模組 140 解碼模組 150 儲存模組 160 緩衝模組 102 第二輸入信號 104 第一輸入信號與第一狀態信號 112、 132 第二狀態信號 114 第一選擇信號 116、 122 輸出信號 124 第二狀態信號與第一選擇信號 134 第二選擇信號 142 第三選擇信號 162 延遲時脈 26[Description of main component symbols] 110 finite state machine circuit 120 selection module 130 temporary storage module 140 decoding module 150 storage module 160 buffer module 102 second input signal 104 first input signal and first state signal 112, 132 Second state signal 114 first select signal 116, 122 output signal 124 second state signal and first select signal 134 second select signal 142 third select signal 162 delay clock 26
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