1313911 . 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種封裝基板之導電結構及其製造方 法，尤指一種適用於以化學鍍方式形成電鍍晶種層之封裝 5 基板導電結構及其製造方法。 、 【先前技術】 # 隨著電子產業的蓬勃發展，電子產品亦逐漸進入多功 能、高性能的研發方向。為滿足半導體封裝件高積集度 10 (Integrati〇n)以及微型化（Miniaturization)的封裝要求，提供 多數主被動元件及線路連接之電路板，亦逐漸由單層板演 變成多層板，以使在有限的空間下，藉由層間連接技術 (Interlayer connecti〇n)擴大電路板上可利用的佈線面積而 配&南電子德·度之積體電路（Integrate(j circuit)需求。 15 以增層（Bund-uP)方式製作之多層封裝基板，是在基板 φ (例如電路板）的一面或雙面，使介電層與導體層順序增層， 而構成咼密度之導體佈線圖形，常見之製作方法如圖丨A至 1E所示。首先’凊參閱圖1A，提供一基板ιοί，此基板1〇1 之表面具有複數個電性連接墊1 〇2、以及一介電層丨03。此 20 電性連接墊1〇2之材料一般為銅，用以導通電路。而介電層 103則有複數個開口 104以露出電性連接墊1〇2，此介電層之 材料一般為 ABF(Ajinomoto Build-up Film)。隨之，於該基 板101上形成一晶種層1〇5(參閱圖iB)，作為後述進行電鍍 製程所需之電流傳導路徑。然後，如圖1C所示，於該封裝 5 1313911 • 基板101上再形成-具有複數個開口 i〇6之阻層107，且此開 口 1〇6位置對應於介電層103之開口 104。接著，於開口 106 以電鍍封示形成電鍍金屬層丨〇8(參閱圖1D)。最後，移除阻 層107以及阻層107覆蓋之晶種層105(參閲圖1Ε),即完成 5 層之封裝基板。重複上述步驟，依所需要之層數層疊上 去即可製作多層封裝基板。 目月】夕層封裝基板在製作增層結構時，多利用化學 ❿ 敎Τ式形成晶種層’其中最常見者為化銅層。所謂化學 鍛疋在不通電的情況下，利用與金屬離子共同存在於锻 :的還:原州於固體表面藉由化學反應將金屬離子還原 至屬而’儿積於固體表面。而且化學鍵之錄液中除 了含有金屬離子、以及還原劑之外，還含有其他活化劑， 如錯口 d ΡΗ質調整劑等等。因此，晶種層（化銅層）的結 構較為鬆散，且含有許多雜質。此故，參閱圖1E’電性連 15接墊102和电鍍金屬層⑽的接點界面殘留的晶種層由 於結構較電鍍金屬層1轉散，而且含有較多雜質，導致晶 種層105在後續的熱處理製程下，產生微小孔洞，甚至斷 € ’造成界面品質劣化’而降低封裝基板的可靠度。 另外，明參閱圖2 ,位於基板2〇丨之電性連接墊2〇2、與 20金屬凸塊203(金屬凸塊2〇3上以回焊技術形成錫球別句界面 的晶種層205，也具有同樣的問題。 因此，如何避免多層封襄基板之晶種層品質劣化，並 提高封裝基板的可靠度，實為蛋待解決之課題。 6 1313911 【發明内容】 於此’本發明提供—種封裝基板之導電結構之製 =法’其㈣包括：⑷提供—絲，縣板表面具有複 數個電性連接墊及一絕緣声， 1 5 15 a且β亥、吧緣層具有複數個絕緣 ^ 口以曝露出該等電㈣接墊；（Β)以化學财式於該絕 尽曰I緣層開口及電性連接墊之表面形成-第一晶種 層；（C)於該第一晶種声类 不 士々H表面形成一阻層，該阻層具有複數 口 “ 口、’且㈣阻層開口之位置對應於該等絕緣層開 置U曝路出部分該第-晶種層；(D)將曝露出之該 、= 種層置換為一第二晶種層，其中，該第二晶種層之 還原電位低於該第—晶錄展 „ 口内電鑛形成一金紗.二：V⑻於該等阻層開 覆蓋之該第-晶種層。日，（)移除該阻層及被該阻層所 由於利用化學鍵來形成第一晶種層需伴隨還原劑、以 他活化劑之添加，才能使第-晶種層沉積於不導電之 介電層或防焊層)上。因此，第-晶種層二; 立差):將含雜質且緻密度差的第一晶種丄 曰插爲b銅層），自發性的置換為另一種還原電位較第— :曰低之金屬(如金、或銀)，也就是第二晶種層。由於置 需要還原劑等活化劑，故第二晶種 質 餘雜質’且敏密度較第一晶種層高。藉^ 门、、土板的晶種層品質，而提高封裝基板的可靠度。 20 1313911 本發明導電結構之製造方法可應用在多層基板之增層 部分、或單層基板與多層基板之表面部分。當本發明導電 結構之製造方法應用在多層基板之增層時，該絕緣層為介 電層。該介電層之材料不限定，較佳係選自ABF(Ajin〇m〇t〇 5 仙似-叩Film)、雙順丁醯二酸醯亞胺/三氮阱 (BT，Bismaleimide triazine)、聯二苯環 丁二稀 (benZ〇Cylobutene ; BCB)、液晶聚合物（u"quid Polymer)、聚亞醯胺（p〇lyimide ; 、聚乙烯醚 (P〇ly(Phenylene etW))、聚四敦乙烯（Poly (tetra- 1〇 flU〇r〇ethylene))、芳香尼龍（八職也）、環氧樹脂以及玻璃 纖維所組成之群組。 15 並且，當該絕緣層為介電層時，該絕緣層開口之形成 方法不限^ ’較佳得、以雷射鑽孔或曝光、顯影形成。惟當 利用雷射鑽孔形成絕緣層開口時，復需進行除膠清 (De韻ear)作業以移除因鑽孔所殘留於絕緣層開口内的膠</ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; Its manufacturing method. [Prior Art] # With the rapid development of the electronics industry, electronic products have gradually entered the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration 10 and miniaturization, most active and passive components and circuit-connected circuit boards are provided, and gradually evolved from single-layer boards to multi-layer boards, so that In a limited space, the interlayer wiring technology (Interlayer connecti〇n) is used to expand the available wiring area on the circuit board to match the integrated circuit of the circuit (Integrate (j circuit). 15 The multilayer package substrate produced by the layer (Bund-uP) method is a conductor wiring pattern which forms a germanium density on the one or both sides of the substrate φ (for example, a circuit board), and the dielectric layer and the conductor layer are sequentially layered. The manufacturing method is as shown in FIG. A to FIG. 1E. First, referring to FIG. 1A, a substrate ιοί is provided, the surface of the substrate 110 has a plurality of electrical connection pads 1 and 2, and a dielectric layer 丨03. The material of the electrical connection pad 1〇2 is generally copper for conducting the circuit, and the dielectric layer 103 has a plurality of openings 104 to expose the electrical connection pads 1〇2, and the material of the dielectric layer is generally ABF ( Ajinomoto Build-up Film). Subsequently, a seed layer 1〇5 (see FIG. iB) is formed on the substrate 101 as a current conduction path required for the plating process to be described later. Then, as shown in FIG. 1C, the package 5 1313911 • the substrate 101 A resist layer 107 having a plurality of openings i 〇 6 is formed thereon, and the opening 1 〇 6 position corresponds to the opening 104 of the dielectric layer 103. Then, a plating metal layer 丨〇 8 is formed by electroplating at the opening 106 ( Referring to FIG. 1D), finally, the resist layer 107 and the seed layer 105 covered by the resist layer 107 are removed (see FIG. 1A), that is, the 5-layer package substrate is completed. The above steps are repeated, and the layers are stacked according to the required number. A multi-layer package substrate can be produced. In the case of making a build-up structure, a seed layer is formed by chemical ❿ ', the most common one being a copper layer. The so-called chemical forging is not energized. Under the use of metal ions in the forging: also: the original state on the solid surface by chemical reaction to reduce the metal ions to the genus and 'child accumulation on the solid surface. And the chemical bond in the recording liquid in addition to metal ions, and reduction In addition to the agent, it also contains Other activators, such as smear d enamel conditioner, etc. Therefore, the seed layer (copper layer) has a loose structure and contains many impurities. Therefore, refer to FIG. 1E' electrical connection 15 pads 102 and The seed layer remaining at the interface of the electroplated metal layer (10) is dispersed due to the structure of the electroplated metal layer 1, and contains more impurities, resulting in the micropores of the seed layer 105 under the subsequent heat treatment process, even breaking The quality of the interface is degraded, and the reliability of the package substrate is lowered. In addition, referring to FIG. 2, the electrical connection pads 2〇2 and 20 of the substrate 2 are replaced by metal bumps 203 (metal bumps 2〇3). The technique of forming the seed layer 205 of the tin ball interface also has the same problem. Therefore, how to avoid deterioration of the quality of the seed layer of the multi-layer sealed substrate and improve the reliability of the package substrate is a problem to be solved. 6 1313911 SUMMARY OF THE INVENTION [The present invention provides a method for manufacturing a conductive structure of a package substrate.] (4) includes: (4) providing a wire, the surface of the county plate having a plurality of electrical connection pads and an insulating sound, 1 5 15 a and β hai, the edge layer has a plurality of insulating openings to expose the electrical (four) pads; (Β) is formed on the surface of the rim I edge layer and the electrical connection pad by a chemical formula - a first seed layer; (C) forming a resist layer on the surface of the first seed acoustic type ,H, the resist layer having a plurality of ports "ports," and (four) resist layer openings corresponding to the insulating layers Opening the U to expose a portion of the first seed layer; (D) replacing the exposed layer, the seed layer, with a second seed layer, wherein the second seed layer has a reduction potential lower than the first - Crystal Recording „ The intra-oral electric ore forms a gold yarn. Two: V(8) is the first seed layer covered by the resist layer. Day, () removing the resist layer and using the chemical bond to form the first seed layer by the resist layer, accompanied by the addition of a reducing agent and an activator, so that the first seed layer can be deposited on the non-conductive layer. On the electric layer or solder resist layer). Therefore, the first seed crystal layer 2; the difference): the first seed crystal containing impurities and the poor density is intercalated into the b copper layer), and the spontaneous replacement is another reduction potential. A metal such as gold or silver, that is, a second seed layer. Since an activator such as a reducing agent is required, the second seed is rich in impurities and has a higher density than the first seed layer. The reliability of the package substrate is improved by the quality of the seed layer of the door and the earth plate. 20 1313911 The manufacturing method of the conductive structure of the present invention can be applied to a build-up portion of a multilayer substrate, or a surface portion of a single-layer substrate and a multilayer substrate. When the method of fabricating the conductive structure of the present invention is applied to a buildup of a multilayer substrate, the insulating layer is a dielectric layer. The material of the dielectric layer is not limited, and is preferably selected from the group consisting of ABF (Ajin〇m〇t〇5 仙like-叩Film), bis(Bismaleimide triazine), Biphenyl cyanobutene (BCB), liquid crystal polymer (u"quid Polymer), polydecylamine (P〇lyimide;, polyvinyl ether (P〇ly (Phenylene et W)), poly four a group of Poly (tetra- 1〇flU〇r〇ethylene), aromatic nylon (eight jobs), epoxy resin, and glass fiber. 15 Also, when the insulating layer is a dielectric layer, The method for forming the opening of the insulating layer is not limited to being formed by laser drilling or exposure or development. However, when the opening of the insulating layer is formed by laser drilling, the degumming is required. Work to remove glue remaining in the opening of the insulation due to drilling
…々沄應用在皁層基 板或夕層基板之表面時，續頌鏠爲 層為防焊層。該防焊層 之材枓不限疋，較佳係為綠漆或 20 ^ ^ a ^ ~ T /含忑’”、漆。亚且，當該絕緣層 為防;^層％ ’該絕緣層開 眼#心— 成法不限定，較佳係以 曝先、顯影方式形成。 在本發明導電結構 連接墊之材料不限定， 之製造方法中，於步驟(Α)中該電性 可為任何能將電路導通之金屬，較 8 1313911 佳為銅、錫、鎳、鉻、鈦、銅_鉻合金以及錫_錯合金中所組 成之群組之一者，更佳則為銅。 在本發明導電結構之製造方法中，於步驟（5)中該第一 晶種層之材料不限定，較佳係選自銅、錫、鎳、鉻、鈦、 銅=各合金、以及錫/鉛合金所組成之群組，更佳為銅。由於 4第3Θ種層係以化學鍍方式形成，因此含雜質且緻密度 10 15 本發明導電結構之製造方法中，於步驟（c)中該阻層 之材料不限定，較佳地係使用感光性高分子，例如.^ 或液態光阻，更佳係使用乾膜。另外，該等阻層開口:形 成方法不限定，較佳地係使用曝Μ及顯影方式形成。y ，本發明導電結構之製造方法中，於步驟⑼該基板係 用汉於6亥弟二晶種層之鹽類溶液中、或利用浸於溶解有 該第二晶種層材料之溶液中’而將該基板曝露出阻層開口 =一晶種層置換為該第二晶種層。由於置換反應是利 ^ 便遇原電位較高之第一晶種層自發性 的置換為還原電位較低之第_ 弟一日日種層，故不需添加還原劑 =活化劑H在本發料電結構之製造方法中，於步 :::第广晶種層可為任何還原電位低於該第-晶種 層之材料，較佳為金、咬#，φ u & β ^ ^ ^ — 更铨為金。由於該第二晶種 層係以置換反應的方式形忐 較户。 成因此含雜質量較少且緻密度 此外，本發明亦提供— —曰 種封破基板之導電結構，包括： —日日種層，係位於—基板 汉上之電性連接墊，其中，該基板 20 1313911 、表面具有複數個電性連接墊及一絕緣層，該絕緣層具有 複^個絕緣層開口以顯露出該等電性連接墊，且該晶種層 係藉由置換反應形成；以及一電鐘金屬層，係位於該晶種 層上。 5 在本發明之導電結構中，該晶種層之形成方法係先利 用化學鍍方式形成一銅層，再利用置換反應將該銅 成金或銀。 • 在本發明之導電結構中，該絕緣層可為任何不導電之 材料，較佳為一介電層或一防焊層。該介電層之材料不限 1〇定’較佳係選自鑛(邱__ Build_up Fiim)、雙順丁醯 — 亞胺 /二氮阱（BT，Bismaleimide Hazine)、聯二苯環 丁二烯（benzocylobutene，BCB)、液晶聚合物（Liquid Polymer) '聚亞醯胺（p〇lyimide，ρι)、聚乙烯醚 (P〇iy(Phenylene ether))、聚四氟乙烯（p〇iy 如加 15 flU〇r〇ethylene))、芳香尼龍（A職也）、環氧樹脂、以及玻 魏維所組成之群組。該防焊層之材料不限^，較佳為綠 _ 漆或黑漆。 在本發明之導電結構中，該電性連接塾之材料不限 定，較佳係選自銅、錫、鎳、路、鈦、銅-絡合金以及錫_ 20錯合金中所組成之群組，更佳為銅。 【實施方式】 本發明之實施例中該等圖式均為簡化之示意圖。惟嗜 等圖示僅顯示與本發明有關之元件，其所顯示支元件非為 10 1313911 實際實施時之態樣，其實際會 例Am 丁、貫施時之元件數目、形狀等比 例為一選擇性之設計，且豆 τ 實施例ι 4件佈局型態可能更複雜。 請參閱圖3A至3F，Α λ欲 專ι 明—較佳實_之封襄基板 V %結構之製造方法剖面示意 M T先’如圖3A所示，提 4、一基板301，該基板3G1表面具有複數個電性連接墊302、 以及-介電層303。此介電層3〇3具有複數個介電層開口 30且’丨电層開口 3〇4之位置對應該電性連接塾3〇2，以頌 露出電性連接墊302。另外，右太山 在本貝施例中，部分電性連接 墊3 02與一導通孔3 1〇連接，此邋 迕按此導通孔310内壁具有銅金屬層 311，並以樹脂312填滿該導通孔31〇。 在圖3A中，該介電層303之材料可選自ABF(Ajin_〇 Biuld-up Film)、雙順丁醯二酸醯亞胺/三氮阱 (BT’Bumaleimide triazine) ' 聯二苯環 丁二烯 15 20 (benZ〇Cylobutene ; BCB)、液曰曰曰聚合 * (uquid P〇_er)、聚亞釀胺（P〇lyimide ; ρι)、聚乙烯醚 (P〇ly(phenyiene ether))、聚四氟乙烯（p〇ly (肋^ flU〇r〇ethylene))、芳香尼龍（Aramide)、環氧樹脂以及玻璃 纖維所組成之群組。在本實施例中，介電層3〇3之材料為 ABF，電性連接墊302之材料為銅，介電層開口 3〇4係以曝 光、顯影方式形成。 接者，於圖3A中的A區域放大來看，由於其餘電性連 接墊22表面的結構皆與其大致相同，故不再贅述。如圖3B 所示，以化學鍵方式於介電層303、介電層開口 3〇4以及電 11 1313911 性連接塾302之表面形成一第一晶種層3〇5。在本實施例 中，。亥第一晶種層3〇5係為一化學鍍銅層。在本實施例中， 化孚錄銅之鑛液主要包括有銅鹽、以及還原劑，並可選擇 性的含有錯合劑、PH調整劑、或其他添加物。該還原劑可 為甲醛（f〇maldehyde)、次磷酸鈉（hyp〇ph〇sphite)、乙醛酸 (glyoxyhc acid)、聯胺（hydeazine)、硼氮化納⑽1聰匕⑽口 hydride)、或二甲基胺钱（dim吻—b_e)。在本實 施例中，該還原劑為甲醛。 、 10 15 20 隨之’ &圖3C所不，於第一晶種層3〇5表面形成一阻層 3〇6，且阻層306具有複數個阻層開口 307。此阻層開口 3〇7 之位置對應於介電層開口 3〇4之位置，以曝露出部分第一晶 ^ f °在本實施例中’阻磨開口斯係以曝光、顯影方 式形成。 然後’將該基板3 〇丨浸在—溶液中進行置換反應，以將 ?阻層306覆蓋之第-晶種層3〇5置換為第二晶種層 308，而阻層306所覆蓋之部分仍為坌曰從赶 曰 苐一晶種層305，其結構 ，所不。此置換反應係利用利用還原電位的不同，使 還原電位較高之第一晶種層3〇5 袭 〜性的置換為退原電位 晶種層308，故溶液中不需添加還原劑等活化 :類、4 t進行置換反應之溶液可為含有該第二晶種層之 液中、或溶解有該第二晶種層材料之溶液。在本實 ^ ^ 句玉而進行置換反應用之 心液含有金、以及溶解金之溶劑。 12 1313911 由於進行置換反應之溶液只需要包含第二晶種層材 料、以及可溶解第二晶種層材料之溶劑，不需要額外的添 =劑，並且第一晶種層包含之雜質會隨著第—晶種層一併 ▼出，故第二晶種層不含雜質或僅含有少量殘餘雜質，且 敏岔度較第一晶種層高。 10 15 20 完成上述步驟之後，以電鍍方式於阻層開口 3〇7内形成 至屬層309 ’則§玄第二晶種層3〇8夾置於金屬層與電性 連接墊302之間，該第一晶種層3〇5夾置於阻層鳩與介電層 303之間，其結構如圖3E所示。此金屬層3〇9之材料可 、Cu/Ni/Au、或Cu/Ni/pd/Au。在本實施例中金屬層· 之材料為銅。 ★最後，如圖3F所示，移除阻層3〇6及被阻層3〇6所覆蓋 :第-晶種層305’即可得到本實施例之封裝基板導電結 3〇Q、A_外’本實施例之封裝基板導電結構還可將該金屬層 n裂基板之電性連接墊，重複上述步驟得到如圖4 構：之結構’或依所需要之層數層疊上去製作更多層之結 置換施例中’含有雜質且緻密度低的第-晶種層被 曰曰：ΪΙ質(或僅含有少量殘餘雜質)且敏密度較第-的第二晶種層，故可降低界 封裝基板的可靠度。 貝《化而k同 實施例2 13 1313911 =閱圖咖’為本發明另—較佳實施例 構之製造方法剖面示意圖。首先，.如圖从所示， 土板501 ’該基板5〇1表面具有複數個電性連接墊 皿、以及—防焊層503。此防焊層503具有複數個防焊層開 口 04,且防焊層開口 5〇4之位置對應該電性連接墊如，以 顯露出電性連接墊如。在本實施例中，該電性連接墊502 之材料為銅，該防焊層503之材料為綠漆，該防焊層開口 504 係以曝光 '顯影方式形成。 10 接者，如圖5B所示，以化學鍍方式於防焊層5〇3、 層開口 5 0 4以及電性連接墊5 〇 2之表面形成一第一晶 5 0 5一。在本實施例中，該第_晶種層5 q $係為—化學鑛銅 本實施例採用之鍍液成分與實施例丨相同。 防焊 種層... When applied to the surface of a soap layer substrate or a slab substrate, the layer is continued as a solder resist layer. The material of the solder resist layer is not limited, but is preferably green paint or 20 ^ ^ a ^ T T / containing 忑 '", lacquer. And when the insulating layer is protected; ^ layer % 'the insulating layer Open eye #心-forming method is not limited, and is preferably formed by exposure and development. The material of the conductive structure connection pad of the present invention is not limited, and in the manufacturing method, the electrical property may be any energy in the step (Α) The metal that conducts the circuit is preferably one of a group consisting of copper, tin, nickel, chromium, titanium, copper-chromium alloy, and tin-stagger alloy, preferably copper. In the manufacturing method, the material of the first seed layer in the step (5) is not limited, and is preferably selected from the group consisting of copper, tin, nickel, chromium, titanium, copper = each alloy, and a tin/lead alloy. The group, more preferably copper. Since the 4th third layer is formed by electroless plating, the impurity is contained and the density is 10 15 . In the manufacturing method of the conductive structure of the present invention, the material of the resist layer in the step (c) is not Preferably, a photosensitive polymer, for example, a liquid photoresist, or a dry film is used, preferably, a dry film is used. Isocratic layer opening: the forming method is not limited, and is preferably formed by exposure and development. y. In the manufacturing method of the conductive structure of the present invention, in the step (9), the substrate is used in the layer of 6 haidi two seed crystals. In the salt solution, or by immersing in a solution in which the material of the second seed layer is dissolved, the substrate is exposed to the resist opening = a seed layer is replaced by the second seed layer. ^ The spontaneous replacement of the first seed layer with higher original potential is the first day of the lower reduction potential, so there is no need to add reducing agent = activator H in the manufacture of the electrical structure of the present invention. In the method, the step::: the first seed layer may be any material having a lower reduction potential than the first seed layer, preferably gold, bite #, φ u & β ^ ^ ^ - more gold Since the second seed layer is formed in a manner of displacement reaction, the quality of the impurity is less and the density is increased. In addition, the present invention also provides a conductive structure for the substrate to be sealed, including: The daily seed layer is an electrical connection pad located on the substrate, wherein the substrate 20 1313911, The surface has a plurality of electrical connection pads and an insulating layer, the insulating layer has a plurality of insulating layer openings to expose the electrical connection pads, and the seed layer is formed by a displacement reaction; and an electric clock metal The layer is located on the seed layer. 5 In the conductive structure of the present invention, the seed layer is formed by first forming a copper layer by electroless plating, and then forming the copper into gold or silver by a displacement reaction. In the conductive structure of the present invention, the insulating layer may be any non-conductive material, preferably a dielectric layer or a solder resist layer. The material of the dielectric layer is not limited to a preferred one selected from the group consisting of Qiu__ Build_up Fiim), Bis-butyl bismuth - Bismaleimide Hazine, benzocylobutene (BCB), Liquid Polymer - Polyimide (p〇lyimide, ρι), polyvinyl ether (P〇ylene (Phenylene ether)), polytetrafluoroethylene (p〇iy such as 15 flU〇r〇ethylene), aromatic nylon (A job), epoxy Resin, and a group of Buffalo. The material of the solder resist layer is not limited, and is preferably green lacquer or black lacquer. In the conductive structure of the present invention, the material of the electrical connection germanium is not limited, and is preferably selected from the group consisting of copper, tin, nickel, road, titanium, copper-coalloy, and tin-20 alloy. More preferably copper. [Embodiment] These drawings are simplified schematic views in the embodiments of the present invention. However, the pictograms only show the components related to the present invention, and the displayed branch components are not in the actual implementation of 10 1313911, and the actual number of components, the number of components, and the shape of the components are an optional The design, and the bean τ embodiment ι 4 piece layout may be more complicated. Referring to FIGS. 3A to 3F, the manufacturing method of the V 结构 structure of the 襄 欲 专 较佳 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ There are a plurality of electrical connection pads 302, and a dielectric layer 303. The dielectric layer 3〇3 has a plurality of dielectric layer openings 30 and the locations of the germanium layer openings 3〇4 correspond to the electrical connections 塾3〇2 to expose the electrical connection pads 302. In addition, in the case of the Ben Taishan, a part of the electrical connection pad 302 is connected to a via hole 31 1 , and the inner wall of the via hole 310 has a copper metal layer 311 and is filled with the resin 312. The via hole 31 is. In FIG. 3A, the material of the dielectric layer 303 may be selected from the group consisting of ABF (Ajin_〇Biuld-up Film), bis-bismuthimide imide triazine, and BT'Bumaleimide triazine. Butadiene 15 20 (benZ〇Cylobutene; BCB), liquid helium polymerization* (uquid P〇_er), polystyrene (P〇lyimide; ρι), polyvinyl ether (P〇ly (phenyiene ether) ), a group of polytetrafluoroethylene (p〇ly (ribs), aromatic polyamide (Aramide), epoxy resin, and glass fiber. In this embodiment, the material of the dielectric layer 3〇3 is ABF, the material of the electrical connection pad 302 is copper, and the opening of the dielectric layer 3〇4 is formed by exposure and development. As shown in Fig. 3A, the structure of the surface of the remaining electrical connection pads 22 is substantially the same, and therefore will not be described again. As shown in FIG. 3B, a first seed layer 3〇5 is formed on the surface of the dielectric layer 303, the dielectric layer opening 3〇4, and the dielectric layer 13302 by chemical bonding. In this embodiment, The first seed layer 3〇5 is an electroless copper plating layer. In the present embodiment, the mineral liquid of Huafu Copper mainly includes a copper salt and a reducing agent, and optionally contains a wrong agent, a pH adjuster, or other additives. The reducing agent may be formaldehyde (f〇maldehyde), sodium hypophosphite (hyp〇ph〇sphite), glyoxyhc acid, hydeazine, sodium borohydride (10)1 (10) hydride), or Dimethylamine money (dim kiss - b_e). In this embodiment, the reducing agent is formaldehyde. 10 15 20 then, a resist layer 3〇6 is formed on the surface of the first seed layer 3〇5, and the resist layer 306 has a plurality of resist opening 307. The position of the resist opening 3〇7 corresponds to the position of the dielectric layer opening 3〇4 to expose a portion of the first crystal φ° which is formed in the present embodiment by the exposure and development. Then, the substrate 3 is immersed in a solution for a displacement reaction to replace the first seed layer 3〇5 covered by the resist layer 306 with the second seed layer 308, and the portion covered by the resist layer 306. It is still a smashing of a seed layer 305, its structure, no. In the replacement reaction, the first seed layer having a higher reduction potential is replaced by the depolarization potential seed layer 308 by using the difference in the reduction potential, so that no activation agent such as a reducing agent is required in the solution: The solution in which the displacement reaction is carried out in a type of 4 t may be a solution containing the second seed layer or a solution in which the material of the second seed layer is dissolved. The core solution for the displacement reaction in the present invention contains gold and a solvent for dissolving gold. 12 1313911 Since the solution for performing the displacement reaction only needs to contain the second seed layer material and the solvent capable of dissolving the second seed layer material, no additional additive is required, and the impurities contained in the first seed layer will follow The first seed layer is added together, so the second seed layer contains no impurities or only a small amount of residual impurities, and the sensitivity is higher than that of the first seed layer. 10 15 20 After the above steps are completed, the silicate layer 309 ′ is formed in the resist layer opening 3〇7 by electroplating, and then the second seed layer 3〇8 is sandwiched between the metal layer and the electrical connection pad 302. The first seed layer 3〇5 is sandwiched between the resist layer 介 and the dielectric layer 303, and its structure is as shown in FIG. 3E. The material of the metal layer 3〇9 may be Cu/Ni/Au or Cu/Ni/pd/Au. In the present embodiment, the material of the metal layer is copper. ★ Finally, as shown in FIG. 3F, the resist layer 3〇6 and the resist layer 3〇6 are covered: the seed layer 305′ can obtain the conductive substrate 3〇Q, A_ of the package substrate of the embodiment. Further, the conductive structure of the package substrate of the present embodiment may further electrically connect the metal layer to the substrate, and repeat the above steps to obtain the structure of FIG. 4 or stack the layers according to the required number to form more layers. In the case of the junction replacement, the first seed layer containing impurities and having a low density is entangled: enamel (or only a small amount of residual impurities) and the second seed layer having a lower density than the first one, so that the boundary can be lowered. The reliability of the package substrate. The present invention is a schematic cross-sectional view showing a manufacturing method of another preferred embodiment of the present invention. First, as shown, the earth plate 501' has a plurality of electrically connected pads and a solder resist layer 503 on the surface of the substrate 5''. The solder resist layer 503 has a plurality of solder mask openings 04, and the positions of the solder resist openings 5〇4 correspond to the electrical connection pads, for example, to expose the electrical connection pads. In the present embodiment, the material of the electrical connection pad 502 is copper, the material of the solder resist layer 503 is green paint, and the solder resist layer opening 504 is formed by exposure 'development. 10, as shown in FIG. 5B, a first crystal 105 is formed on the surface of the solder resist layer 5〇3, the layer opening 504, and the electrical connection pad 5〇2 by electroless plating. In the present embodiment, the first seed layer 5 q $ is - chemical copper. The plating composition used in this embodiment is the same as that of the embodiment. Anti-welding
15 隨之，如圖5C所示，於第一晶種層5〇5表面形成一阻層 506,且阻層5〇6具有複數個阻層開口 5〇7。此阻層開口 π? 之位置對應於防焊層開口 5〇4之位置，以曝露出部分第一晶 種層505。在本實施例中，阻層開口 5〇7係以曝光、顯影方 式形成。 然後，將該基板501浸在一溶液中進行置換 未被阻層撕覆蓋之第-晶種層奶置換為第:晶種^ 20 5〇8 ’而阻層506所覆蓋之部分仍為第一晶種層505 ,其結構 如圖5D所示。此置換反應係利用利用還原電位的不同，使 遇原電位較高之第一晶種層5〇5自發性的置換為還原電位 較低之第—H曰種層5 〇 8。在本實施例中，第二晶種層$ 〇 8之 14 1313911 材料為金，而進行置換反應用之溶液含有金、以及溶解金 之溶劑。 完成上述步驟之後，以電鍍方式於阻層開口 5〇7内形成 「金屬柱509,則該第二晶種層5〇8夾置於金屬柱5〇9與電性 5連接墊502之間，該第一晶種層505夾置於阻層506與防焊層 503之間，其結構如圖5E所示。此金屬柱5〇9之材料可選自 鋼、鎳、鉻、鈦、銅/鉻合金以及錫/鉛合金所組成之群組。 在本實施例中’該金屬柱5〇9之材料為銅。 接著，如圖5F所示，移除阻層506及其所覆蓋之第一晶 10種層505，即可得到本實施例之封裝基板導電結構。明 最後，如圖5G所示，利用迴焊的技術於金屬柱5〇9上 形成一焊料錫球510。此焊料錫球51〇主要在用以使基板5〇1 與一晶片接合。 在本實施例中，含有雜質且緻密度低的第一晶種層被15 Subsequently, as shown in Fig. 5C, a resist layer 506 is formed on the surface of the first seed layer 5?5, and the resist layer 5?6 has a plurality of resist opening 5?7. The position of the resist opening π? corresponds to the position of the solder resist opening 5〇4 to expose a portion of the first seed layer 505. In the present embodiment, the resist opening 5〇7 is formed by exposure and development. Then, the substrate 501 is immersed in a solution for replacement of the first seed layer milk which is not covered by the resist layer, and replaced by the seed crystal 20 20 〇 8 ′ and the portion covered by the resist layer 506 is still the first The seed layer 505 has a structure as shown in Fig. 5D. This displacement reaction utilizes the difference in the reduction potential to spontaneously replace the first seed layer 5〇5 having a higher original potential with the first-H曰 seed layer 5 〇 8 having a lower reduction potential. In the present embodiment, the material of the second seed layer $ 〇 8 14 1313911 is gold, and the solution for the displacement reaction contains gold and a solvent for dissolving gold. After the above steps are completed, a metal pillar 509 is formed in the barrier opening 5〇7 by electroplating, and the second seed layer 5〇8 is sandwiched between the metal pillar 5〇9 and the electrical 5 connection pad 502. The first seed layer 505 is sandwiched between the resist layer 506 and the solder resist layer 503, and its structure is as shown in Fig. 5E. The material of the metal post 5〇9 can be selected from steel, nickel, chromium, titanium, copper/ A group consisting of a chrome alloy and a tin/lead alloy. In the present embodiment, the material of the metal post 5〇9 is copper. Next, as shown in FIG. 5F, the resist layer 506 and the first cover thereof are removed. The conductive structure of the package substrate of the present embodiment can be obtained by crystallizing 10 layers 505. Finally, as shown in FIG. 5G, a solder ball 510 is formed on the metal post 5〇9 by a reflow soldering technique. 51〇 is mainly used to bond the substrate 5〇1 to a wafer. In this embodiment, the first seed layer containing impurities and having a low density is
，換為不含雜質（或僅含有少量殘餘雜質）且緻密度較^一 晶種層高的第二晶種層，故可降低界面品質劣化，而提高 封裝基板的可靠度。 呵 上述實施例僅係為了方便說明而舉例而已，本發明所 主張之權利範圍自應以申請專利範圍所述為準，而非僅限 20 於上述實施例。 、 【圖式簡單說明】 圖IA至〗E係習知之封裝基板導電結構之製造方法剖面示意 15 1313911 圖2係另一習知之封裝基板導電結構D 圖3A至SF係本發明—較佳實施例之 造方法剖面示意圖。 、衣土板導電、，.„構之製 圖4係本發明一較佳實施 BI 5A 5 ^ π 之封衣基板導電結構。 圖5A至5G係本發明另—較 之製造方法剖面示意圖。實―之封裝基板導電結構 【主要元件符號說明】 基板 101，201，301，501 介電層103,303 晶種層1 〇 5 電鍍金屬層108 錫球204 第一晶種層305,505 第二晶種層308,508 導通孔310 樹脂312 防焊層開口 504 焊料錫球5 10 電性連接墊102,202,302,502 開口 104,106 阻層 107,306,506 金屬凸塊203 介電層開口 304 阻層開口 307,507 金屬層309 銅金屬層3 11 防焊層503 金屬柱509 10 16The second seed layer having no impurity (or only a small amount of residual impurities) and having a higher density than the seed layer can be used to reduce the deterioration of the interface quality and improve the reliability of the package substrate. The above-described embodiments are merely examples for convenience of description, and the scope of the claims is intended to be limited to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 3 are a schematic view of a conventional method for manufacturing a package substrate conductive structure. 15 1313911 FIG. 2 is another conventional package substrate conductive structure D. FIG. 3A to SF are the present invention - a preferred embodiment Schematic diagram of the method of making. Figure 5 is a cross-sectional view showing the conductive structure of the present invention. Package substrate conductive structure [Main component symbol description] Substrate 101, 201, 301, 501 Dielectric layer 103, 303 Seed layer 1 〇 5 Electroplated metal layer 108 Tin ball 204 First seed layer 305, 505 Second seed layer 308, 508 Via hole 310 Resin 312 solder mask opening 504 solder solder ball 5 10 electrical connection pad 102, 202, 302, 502 opening 104, 106 resist layer 107, 306, 506 metal bump 203 dielectric layer opening 304 resist opening 307, 507 metal layer 309 copper metal layer 3 11 solder mask 503 metal column 509 10 16