1312181 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種高效能之積體電路的製作’且特別 疋有關於一種形成比如是電感元件之高效能的電子元件於晶 片之表面上的方法，可以降低因為晶片所導致的電磁損耗。 【先前技術】 半導體技術持續所追求的目標係能夠在具競爭性的價格 下製造出南效能的半導體元件。隨著半導體製程及材料的研 發，再配合新型且精緻的元件設計，如此半導體元件的尺寸 可以大幅縮小。大部分的半導體元件係用來處理數位資料， J而也有#分之半導體元件整合有類比的功能，如此半導體 兀件便可關時處理數位資料及類比資料，或者半導體元件 亦可以僅具有類比的魏。製造類比電路駐制難點之— 是在於許多用_比電路的電子元件甚大，難以與次微米級 的電子兀件整合，尤其是針對電容元件及電感元件而言，此 乃因為電容元件及電感元件的尺寸過於龐大。 一般而言’電感元件係應用在移動通訊的領域中，比如 是應用在配置有軸放大器（RF amplifier)之半導體元件 上’而射頻放大器主要包括有調整電路(tUnedcircuit)，其 中調整電路財電感元件及電容元件。輕電路之電感元件 的電感值、電容元件之電容值及頻率均會影響由調整 產生的阻抗’針對某一頻率的訊號，調整電路可以是具有言 1312181 二抗:::低阻抗的。調整電路可以阻隔或導通訊號之傳 如此亚^照轉的頻率，調整電路還可以放大類比訊號。 魏輕输㈣，細輸一頻率之 疋姆由處理類比訊號之電路所產生的雜訊。利用 jx共振的原理，調攀雷 路亦了峰生r%的電？阻抗，藉以抵 ，邛分線路中之寄生電容效應。當電感元件形成於半導體 ^底之表面上時，會產生下述的問題，就是在螺旋狀之電 U件與位在下面之基底之間所產生的寄生電容會有自我共 振的效應目此纽制當在設計高頻電路時，魏元件的使 用。另外，藉由電感元件的設計，可以減少電感元件與位在 下面之基底之間的電容耦合。 在高頻電財，由魏元件所纽的電輯會使得石夕基 底内產生㉟電流(eddy eurrent)的現象。由於祕底係為一 種電阻型導體，因此㈣流會損耗電磁能量，產生嚴重的能 量損耗’而形成一低品質參數之電感元件，使得丨/厄之共振 頻率限制了辭的上限。另外，由電感元件所產生的渦電流 會干擾减f感元狀電路魏。由於金屬電阻性的原因， 用來形成縣元件之細金祕路亦會雜能量，如此亦會形 成一低品質參數之電感元件。 在製作高頻類比半導體元件時，必須要提供一關鍵的元 件，就是電感元件，藉以形成LC共振電路。在現今半導體業 1312181 界’均朝向高元件密度的趨勢發展，因此基底表面的使用率 «大从加’即使如此’電感元件還是形成在極小化之基底 表面上，亚且電感元件還要維持在高品質參數的情況下。一 般而言’形成在基底表面上的電感元件係在一平面上呈現螺 旋狀的樣式，此伟縣行於龜之表面。魏製造電感元 件於基底之表面上的方法杨下所述之闕。大部分高品質 係數的電感元件係配置在混合元件結構⑽出如心 ⑽figuration)中、單晶微波積體電路（M〇n〇Hthic1312181 IX. Description of the Invention: [Technical Field] The present invention relates to the fabrication of a high-performance integrated circuit, and particularly relates to a high-performance electronic component such as an inductor component on a surface of a wafer. The method can reduce the electromagnetic loss caused by the wafer. [Prior Art] The goal pursued by semiconductor technology is to be able to manufacture south-efficiency semiconductor components at competitive prices. With the development of semiconductor processes and materials, coupled with new and sophisticated component designs, the size of such semiconductor components can be significantly reduced. Most of the semiconductor components are used to process digital data, and J has semiconductor components integrated with analog functions, so that semiconductor devices can process digital data and analog data when they are off, or semiconductor components can be analogous. Wei. The difficulty in manufacturing analog circuits is that many electronic components that use _ than circuits are so large that they are difficult to integrate with sub-micron electronic components, especially for capacitive and inductive components, because of capacitive and inductive components. The size is too large. Generally speaking, 'inductive components are used in the field of mobile communication, for example, on semiconductor components equipped with a shaft amplifier (RF amplifier), and the RF amplifier mainly includes an adjustment circuit (tUnedcircuit), in which the adjustment circuit is a financial component. And capacitive components. The inductance value of the inductive component of the light circuit, the capacitance value and the frequency of the capacitor component all affect the impedance generated by the adjustment. The signal for a certain frequency can be a low impedance of the 1312181 secondary antibody:::. The adjustment circuit can block or guide the transmission of the communication number. The adjustment circuit can also amplify the analog signal. Wei light loses (4), and the frequency of the transmission of a frequency is the noise generated by the circuit that processes the analog signal. Using the principle of jx resonance, it is also the peak of r% electricity. Impedance, by which the parasitic capacitance effect in the line is divided. When the inductive component is formed on the surface of the semiconductor, there is a problem that the parasitic capacitance generated between the spiral U-shaped member and the underlying substrate has a self-resonance effect. The use of Wei components when designing high frequency circuits. In addition, the capacitive coupling between the inductive component and the underlying substrate can be reduced by the design of the inductive component. In high-frequency electricity, the electricity generated by the Wei component will cause 35 currents (eddy eurrent) in the base of Shi Xiji. Since the secret bottom is a resistive conductor, (4) the flow will lose electromagnetic energy, causing a serious energy loss' to form a low-quality parameter of the inductance element, so that the resonance frequency of the 丨/厄 limits the upper limit of the speech. In addition, the eddy current generated by the inductive component interferes with the subtractive sense circuit. Due to the electrical resistance of the metal, the fine gold road used to form the county component will also be mixed with energy, which will also form an inductive component with low quality parameters. When fabricating high frequency analog semiconductor components, it is necessary to provide a key component, that is, an inductor component, to form an LC resonant circuit. In today's semiconductor industry, the 1312181 world's trend toward high component density, so the use of the substrate surface «large from plus 'even so' the inductor element is formed on the surface of the minimized substrate, and the inductive component is still maintained In case of high quality parameters. In general, the inductive element formed on the surface of the substrate exhibits a spiral pattern on a plane, which is on the surface of the turtle. Wei's method of manufacturing an inductive component on the surface of the substrate is described by Yang. Most of the high-quality coefficient inductance components are arranged in the hybrid component structure (10), such as the heart (10) figure, the single crystal microwave integrated circuit (M〇n〇Hthic
Microwave Integrated Circuits，MMICas)中或者是由分開 配置之tg件所提供’然社述電子元件之製造係不易與積體 電路衣k之基本製程整合。若是將作為類比資料控制及類比 資料貯存之電路與作為數位龍控制及數位資料貯存之電路 整合並製造在半導體大型基底上，則會達到許多顯著的優 點，而整合的優點包括降低製造成本及降低能量消耗。形成 在半_基絲社之駿狀的賴元件由於受到實際尺寸 的限制’轉縣感元件之線路與下面基底之間產生^生電 容’並且受到位在下面之電阻性魏底的影響，電感元件= _電磁能量損耗的發生。當調整電路之共振頻率突然下降 時，寄生電容會對LC電路產生嚴重的負面效果。 值得注意的是，由電感元件所產生的電磁場會使得電阻 性之碎基底内產生渦電流的現象，而產生嚴重的能量損耗， 1312181 如此會形成-低品質參數之電感元件。 〃另外可以藉由品質參數⑼來代表電狀魏。品質參 數係定^卜Es/El，財Es係代表畴在元件之反應部 刀的月匕里㊉E1係代表在元件之反應部分所失去的能量。當 元件的抑質愈心，元件之電雜會愈趨近於零，此時元件 之品質參數_近於餘A。_成在魏紅之電感元件 而言，由騎到位在下蚊電陳之絲底·響及受到形 成電感元件之金屬線路所影響，使得電磁能量會顯著地下 降就元件而Q，ϋσ貝參數係用來量測元件之反應純度 (PU曲)錄齡(SUSGeptanGe)，細電陳之雜底、電 阻性之金麟路及介電_騎降低邱她。在實際上， 電路總是配置有部分會浪之驗树，減會減少能 夠被補償(細败叙能量。品f參_為鮮位的就裝 配在印刷t路板⑽)上之分開配置的電感元件而言，當品質 參數大於⑽日夺’係認定為具有甚高的品質參數：然而就形 成在積體電路中之電感元件㈣，品胖數係大约介於3到 10之間。 電感元件可以糊傳統的轉體製鄉成在具有半導體 元件之大型基底上，此時由電感元件所產生之寄生電容會限 制截止頻賴上限’細物_在許錢用上是不能被接 受的’因此必棘計具雜高品質參數之贼元件，比如是 1312181 50歧高’其中品質參數會受至|JLC電路之共振頻率所影響。 在^技術中，必須要配置彼此分離的元件才能提供較高的 =參數’而這些分開的元件要與觸元件的魏整合。但 疋虽要將麵元件及這制圍的元件配置於轉體基底上而 =成大型電路結構時，便無法達成高品f參數的目的。若 疋採用非切的電路結構，必須魏置_的線路藉以連接 裴置之附屬7L件，而此類似網路形式之用來連接的線路亦會 產生額夕^寄生電容及電阻損耗。在RF放大器之許多應^ 上’比如疋可攜式電池充電的用品，此時電力的消耗是一項 重要的考I點’並且是要愈低愈好。藉由提高電力的消耗， 係可以部分地補償寄生電容效應及電阻能量損耗，但是這個 方法還是有-些_。而上述的這綱題均發生在市場快速 擴張的無線輕用品上’比如是摘電話，其帽積體電路 之整合係為最重要的挑戰之一。另外，藉由顯著地增加操作 頻率’比如是增加到1驗到刪Z之間，可以部分解決上 ^問題，然而在如此高的操作頻率之下，受到石夕基底的影響， 電感7C件的品質參數會顯著地下降。為了要使產品能夠在此 頻率下運作’研發出大型電感元件，其係利用除了秒以外的 材貝作為襄作電感凡件之基底，而這種大型電感元件比如可 从利用藍寳石(Sapphire)或是砰化鎵(⑽)作為基底，較 於石夕基底’這些形成在非石夕材質之基底上的電感元件具有較 1312181 低的基底損耗，此關林會形成渦電餘ddy current)， 因此便不會有電磁能量的損耗 參數之電感元件。並且，=Γ製作出具有高品質 J用上述方式所形成之電合 產衡料_，_抛物^酵Ρ終 然而’获需要更複_翻，還是必須制时作為美底 來形成電感元件，此乃因為若是要卿除了独外的材質， 比如是坤化鎵’作為基祕為絲麻_，並且在形成半導 體兀件時’會遇到需多技術上的挑戰。由於石申化鎵在高頻下 係為半絕緣的㈣，耻可喊知騎化雜底所導致的 電磁損耗’域可明加軸料化職紅之電感元件的 品質參數。然而4化鎵之RF W物_貴的，若是賴 避免使純b鎵之RF⑼，職触上具雜麵成本優 勢。 在不犧牲7G件效能的情況下（比如是因為基底損耗而犧 牲兀件效能），有許多方法可以將電感元件與半導體環境整 合。其中法便是顧侧献微顧加玉的方式將位 在電感元件底部之德底麵性地絲，因此可以減少基底 之電阻能量耗損及寄生效應。另外—種方法便是彻多層金 屬層連線’其材質比如是銘，或是利用陰刻法(如瞭咖） 所形成之銅金屬層連線。 而另外一種方法，便是利用高電阻性之矽基底，如此可 1312181 減夕由⑪基底所產生的電峨損。而由基底所產生的電随 損耗會顯著地影響以石夕作為材質之電感元件的品質參數。另 外’偏壓井(biased well)可以配置在螺旋狀之電感元件下， 因此可Μ❹基勒之電雜損。而另外—種複雜方法是 =主動性之電感元件，其可以利用主動電路模擬電感元件 ^子雜。然而模擬的電感元件會導致高功率的消耗並且 有雜°孔的產生’故此方法不能應用在低功率及高頻率的產 的方法均有共同的目的，就是要提高電感元件之 :質參數及_電感树縣造场絲積，喊重 =是_磁_耗撕，細輪能量會使 石夕基底產生渦電流。 :積體電路之體積縮小之際，每片晶片之成本會降低， ㈣2進0曰片某方面之效能。用來連接晶月與其他線路或 變得較為重要’並且隨著積體電路逐漸縮小 '丁、I金屬連線會對線路效能產生嚴重地負面衝擊。由 缩他修，叫物以效能 顯者地下降，其中最明顯的衝擊 流排之電麵及關鍵樣f、 排及接地匯 輯及關鍵訊號電路之電阻電容遲嫌de㈣效 應。若是為了降低電阻而採用寬的金屬線路，則又會導致金 屬線路具有較高的電容。 ' 在現今的技術中，當電感元件欲形成在半導體基底上 1312181 時’可以利用細線路的技術，並且將電感元件形成在保護層 下。如此會使縣感元件很接近基底的表面， =之她的雜縣上_丨嶋韻麵基底牛内、 會導致南電麵耗生’且會降低電阻元件之品質參數。 美國專利公告第5,212，侧雜akanishi)揭露—種形 成線路連線财法’其巾崎及外部讀路連祕形成在位 於晶片上之線路基底内，並且邏輯線路的設計會取決於線路 連線的長度。 美國專利公告第5,5〇1，〇〇6號(6吐11^11，了1'.0士31.)揭 露一種積體電路與線路基底之間具有絕緣層之結構，而藉由 为散出去的引腳可以是晶片之接點與基板之接點電性連接。 美國專利公告第5, 〇55, 907號(Jacobs)揭露一種整合型 半導體結構，可以允許製造商將一薄膜多層線路形成在支撐 基板上或晶片上，藉以整合位在晶片外之電路。 美國專利公告第5,1〇6,461號(Volfson et al.)揭露— 種多層連線結構，其係藉由TAB結構並利用聚醯亞胺 (polyimide)之介電層及金屬層交互疊合於晶片上而成。 美國專利公告第5, 635, 767號(Wenzel et al.)揭露一種 在PBGA結構中降低電阻電容遲緩效應之方法，其中多層金屬 層係分開配置。 美國專利公告第5, 686, 764號(Fulcher)揭露一種覆晶 12 1312181 基板’藉由將電源線與輪入輸出引線分開配置，可以降低電 阻電容遲緩效應。 美國專利公告第6, _，⑽號⑽㈣以ai.)揭露一種 利用兩層金屬層所形成之螺旋狀電感元件，其中此兩層金屬 層可以利用導通^^連接。 美國專利公告第5,372,967號(Sundarain的^ )揭露一 種螺旋狀電感元件。 美國專利公告第5, 576, 68〇號(Ling)及笫5, 884, _號鲁 (Burghartz et al.)揭露—種其他形式之螺旋狀電感元 【發明内容】 口此本發明目的之—就是提供―種高效能之晶諸構， 尤其可以改善RF之效能。 - 本發明目的之二就是提供一種具有高品質係數之電感元-件的製造方法。 本發明目的之二就是可以利用砍晶片來代替神化嫁晶 片’並且在⑪晶片上可以製作出高品㈣數之電感元件。 本發明目的之喊是可以使形成切基絲面上之電感 元件的頻率範圍延伸。 本發明目的之五就是可以使形成高品f之被就件_ 基底的表面上。 有關於在健層上製作厚聚合漏及在此厚聚合物層上 製作又寬又厚的金屬線路之製程可以參照美國專利公告第 13 1312181 W趿⑽號。本發明係延伸自美國專利公告第&娜籼 諕，並且在本發明還揭露可以形成高性能之電子元件於保護 f上或是厚聚合物層上，射電子树比如是概元件、電 容元件或電阻元件。另外，本發明還提供—種將已經製作完 成的被動元件接合到晶片之表面上的方法。 為讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式’作詳細說明 【實施方式】 美國專利公告第6，娜，⑽號係讓渡於與本發明相同之 讓渡人’其揭露-種晶片結構具有重配置線路層及金屬連線 層，係配置在聚合物層上，其中聚合物層係位於傳統晶片之 保遵層上。保護層係位於積體電路上，而厚的聚合物層係選 擇性地缝雜鶴上，寬喊厚的麵連_位在保護層 上。 吳國專利公告第6，綱，423號係讓渡於與本發明相同之 減^細-_咖_⑽元件於晶片 構。此種具編質麵繩元件可以應 用在_路巾，並且可喊少魏_。在此案中，還 揭:電谷讀及電阻元件，可以形成姆基底的表面上，藉 以減少位於魏釘之電子树糊發㈣寄生效應。 请參照弟1圖，其緣示依照美國專利公告第6,娜，916 14 1312181 號之晶片結構的剖面示意圖。半導體基底！ 〇(比如是石夕基底) 的表面具有電晶體n及其他元件㈤會示於第i圖》半導體 基底ίο的表面係覆蓋有内部介電層12⑽），位於上述之電 子7G件上。金屬/介電層14係位於内部介電層12上，金屬/ /丨包層I4包括至少一層之介電層’而至少一金屬連線係 位在金屬/介電層14巾，金屬連線13雜成電子連接的網 路而最上層之金屬層具有部分區域係定義為電子接點， 這些電子接點16可以與位於半導體基底H)之表面上絲面 内之電晶體11或其他树電性連接。保護層18雜於金屬/ 介電層14上’藉以避免移動離子（比如是納離子）、濕氣、過 渡金屬（比如疋金、娘、銅）或其他污雜進人到晶片内，其 中保濃層18比如疋由氧魏合物錢魏合物所構成之複 合層。保護層18係用來保護位在下面之比如是電晶體、多晶 石夕電阻元件❹抑j轉電容元件之電子元件及細金屬 線路。 美國專利λ σ第6,383, 916號之關鍵步驟係起始於沈積 厚的聚合物層20㈣，其株合物㈣係沈積在保護層18 上。為了要與電子接點16連接，開口 22、36、38會穿過聚 口物層20及保挪18，纽會對準於電子接點μ。透過位 於聚合物㈣内之開σ22、36、38，電子接點Μ可以將電 性延伸至聚合物層20中。 15 1312181 在較佳的情況下，聚合物層20之材質比如是聚醯亞胺 (polyimide)，而聚合物層20比如是感光材料。而聚合物層 20之材質亦可以是苯基環丁烯(benzocyclobutene，BCB)、 聚亞芳香基醚(parylene)或者是以環氧樹脂為基礎之材料， 比如是SU-8環氧樹脂（可以從Sotec Microsystems，Renens， Switzerland 獲得）。 在形成開口 22、36、38之後，可以進行一金屬化製程， 藉以形成金屬連接線路26、28，並且可以連接電子接點16。 而金屬連接線路26、28可以是任何設計形式之寬度及厚度， 以符合所需的電路設計，且金屬連接線路26、28可以作為電 源匯流排、接地障流排或訊號匯流排之用。經由打線導線或 凸塊可以使金屬連接線路26、28連接於晶片外之電路。 電子接點16係位在金屬/介電層14(如第1圖所示）的頂 部，並且電子接點16之尺寸可以縮小，藉以減少位於下面之 金屬層的電容值。若是電子接點16之尺寸過大時，會影響金 屬層之繞線。 在硬化之後’比如是聚醯亞胺之聚合物層2〇的厚度可以 超過2微米’而聚合物層2〇之厚度比如是介於2微米到15〇 微米之間’視電子設計之需求而定。而就較厚的聚合物層2〇 而e ’可以彻多次旋塗及魏的方式，形成料合物薄膜。 美國專利公告第6, 383,⑽號揭露利用厚或寬之金屬連 16 1312181 接線路28所形成如第丨圖所示之具有不财向的路徑洲、 32、34，可以作為電路間的電性連接之用。相較於位在下層 之、、、田的金屬連線13 ’厚或寬之金屬連接線路28具有較小的 電随值及電容值’並且較容易製造，且成本較低。 明乡…、第2圖，其係修改自美國專利公告第6, 383, 91Θ 號’並且還形成電感元件40於聚合物層20上。電感元線4〇 係為平_形式，並且可以平行於半導體基底㈣表面而 透過夕層12、14、18、20、结構所構成之高度，可以使得電咸 元:40遠離半導體基底1〇之表面。第2 _示係以垂錄· 半導體基底H)之表神剖崎形成之賊元件4()之剖面結 構。藉由寬及厚之金屬的設計，可以減少電阻能量的損耗。 其中可以利用電鑛的方式，形成比如是金、銀或鋼之低電 阻金屬，而其金屬厚度比如是大約2〇微米。 相較於將電感元件形成於保護層下之習知技術，藉由增 電感元件與⑪基底之p摘距離，可以減少⑪基底所產生的 電磁場，並且電感元件之品質參數可以提高。電感元件可以 形成在保護層上’或者可以形成在位於保護層上之聚合物層 (比如是聚酿亞胺)上。另外，利用寬且厚的金屬所形成之電 感元件，具有較小的寄生電阻。 本發月之另—重點，就是保護層18之開口 19的寬度可 以小至G. 1微米。因此，電子接點16可以是很小的如此可 17 1312181 以提升位在頂層之細線路金屬層之繞線能力，並且具有較低 之電容值。 而本發明之另一重要特徵，就是聚合物層2〇之開口 22、 36、38可以是大於保護層18之開口 19，而聚合物層2〇之開 口 22、36、38係對準於保護層18之開口 19。將聚合物層2〇 »又《十有較大的開口 22、36、38係為一種選擇性的設計，並且 較谷易製作完成’且將聚合物層2〇設計有較大的開口 22、 36、38可以配合厚金屬層的設計使用，藉以完成本發明在形 成保護層18後之金屬沈積製程。 笫2圖繪示金屬連接線路26及電感元件4〇，其中電感 兀件40包括兩個接點41、43，透過聚合物層20可以與電子 接點16電性連接。 另外，請參照第2圖，依照本發明之另一觀點，還可以 形成另一聚合物層於如第2圖所示的結構上。 第24a圖及第24b圖繪示本發明之另一特徵，其中連接 卿感元狀接點的方賴獨於如第2目所示之兩個向下 連接的接點。如第24a圖所示，其中聚合物層35係形成在金 屬連接線路26及電感元件4〇上，而聚合物層35之材質比如 是聚醯亞胺。接點開口 36a會連通至電感元件4〇之一端，並 且可以將賴元件40之-端暴露於外。賴元件4{)具有一 向上連接之接點及一向下連接之接點39，其係為“一上一 1312181 下”的結構。 第24b圖緣示另外一種結構，其中具有兩個朝上的接點 開口 36a、38a ’係暴露出電感元件4〇，其係為“均為朝上” ‘的結構。 在第24a谓及第24b圖中，電感元件之朝上的接點可以 透過打線财絲是形成凸塊的方式與料元件紐連接。 就打線製程而言’電感元件4〇元件之上表面必須要形成一可 與打線導線接合的金屬，其㈣比如是金_。就凸塊連接# 而言，凸塊底層金屬(_可以形成在朝上的接點開口中，藉 以形成凸塊。 在第施圖及第24b圖中，利用形成與金屬連接線路26 及電感元件40相同之方法來形成連接線路，可以使電感元件 40經由接點開口 36a、38a與晶片上之其他接點或如前所述 之外部元件電性連接。 請參照第24c圖’其綠示本發明之另一特徵，其中一延 ^ 伸線路89會連接至電感轉4〇，而接點開口娜會暴露出 延伸線路89 ’其中接點開口 的位置比如是在晶片的邊 緣’而可以方便進行打線製程，如此電感元件40可以透過延 伸線路89改變對外連接的位置。接點開口娜的配置係如前 所述。延伸線路89、金屬連接線路26與電感元件4〇係同時 製作完成。 19 1312181 延伸線路89可以連接至電感元件40，藉以改變電感元 件40對外連接的位置，其中延伸線路⑽可以具有向下連接 的接點(未緣示，但是此概念之前已敘述過），取代向上連接 的接點。 當電感元件的接點係位在中間區域時，比如是第处圖 之接點開π 38b所暴露之接點，此時位在電感元件4()之中間 區域的接點係無法藉由延伸線路89而改變其對外連接的位 置’但是位在電感元件40之中間區域的接點可以向上連接或 是向下連接。 第3圖繪示螺旋狀電感元件4〇之上視圖，其中電感元件 40係位在聚合物層20之表面上，第2圖所示的電感元件4〇 係為第.3圖中沿者剖面線2-.2之剖面示意圖。 第4圖繪示電感元件40之剖面示意圖，藉由增加一導電 片44a可以隔絕電感元件40對半導體基底1〇的影響，其中 導電片44a係大致上位在電感元件4〇下，而導電片44a比如 是銅或金之導電材料。導電片44a係在保護層18之表面上延 伸，且電感元件40係對準於導電片44a且位在導電片44a 上。導電片44a可以稱微地超過電感元件4〇之邊界區域，如 此更可以增進遮蔽半導體基底10的能力，藉以避免半導體基 底10受到電感元件40之電磁場的影響。 請參照第4圖，電感元件40至少百分之五十以上的區域 20 1312181 與半導體基底10之間係在力 下，雷電月44a，在較佳的情況 40至少百分之八十以上的區域與半 i=:r_44a，蝴调罐半導趙墓 ★導電片他可以電性連接於電感元件40之其中—電極 (如第4圖所示’導電片他可以與電感元件4〇之最右端作 :、、，電極之接點43電性連接），而導電片拖可以是處在浮動 電壓之準位，或者是可以與其他的電壓準位連接，取決於系 .統的電子設計。 製作導電片44a的方法及材質可以是利用如後所述之製 作金屬連接線路26及電感元件4G的方法及材f。在製作導 電片44a B夺可以同時形成導體44 ’而藉由導體44可以將位 在上層之厚金屬連接至電子接點16，如第4圖所示。 聚合物層47可以是選擇性地形成在電感元件4〇上及金 屬連接線路26上，可以對金屬結構提供额外的保護。 請參照第12圖至第23圖，其繪示依照本發明保護層上 形成電感元件或其他被動元件之方法。如第12圖所示，基底 80係為位在下層之介電層，而金屬接點81的材質比如是在呂。 藉由圖案化的步驟可以形成開口 82,貫穿保護層84,而開口 82可以暴露出金屬接點81。比如是聚醯亞胺之聚合物層86 可以是形成在保護層84上及金屬接點81上，而比如是聚酿 21 1312181 亞胺之聚合物層86比如是利用旋塗的方式完成，或者亦可以 利用網板印刷的方式完成，或者亦可以是利用壓合聚合物乾 膜的方式完成。 第13圖係繪示形成聚合物層86之開口 87的製程，其中 聚合物層86之開口 87之最大寬度係大於保護層84之開口 82之最大寬度(請參見第12圖），開口 87具有傾斜的側壁 85。在剛開始時’聚合物層86之開口 87具有垂直之侧壁85， 然而在經過硬化步驟之後，侧壁85會呈現傾斜的樣式，而開 壽 口 87可以是呈現半錐形的樣式’而侧壁85的傾斜角度比如 是45度或是更大，基本上大約是介於5〇度到6〇度之間。另 外’侧壁85的傾斜角度亦可以是小至2〇度。 在本實施例中，較大的導通孔線路(vias)可以是穿過比 如是聚醯亞胺之聚合物層86，且對準於較小之位在下層之保 護層84的開口 82，並且還連接位在下層之次微米金屬層。 fk著由次微米金屬層往寬金屬層級的方向，次微米金屬之導 鲁 通孔線路之尺寸可以是逐漸加大。 雜續參照第13圖’其繪示依照本發明形成保護層上連 接線路及電感元件之方法及金屬結構。首先可以利賊鍍的 方式，形成-黏著/阻障層88 ’其材質包括鈦鶴合金、鈦氮 化合物、组或组氮化合物等’而黏著/阻障層88的厚度比如 是介於500埃(angstro_ 5_埃之間。接著，可以利用濺 22 1312181 鍍的方式形成比如是金的種子 帽子>90的… 者阻障層挞上’其 層略度比如是介於_ _ _埃之間。 屬声接著可輯物的方式，形成一厚金 f曰、材質比如是金’其中厚金屬層92的厚度比如是 ^微米到2咖之間。而在進行電難程之前，會先形 "阻94，而光阻94的厚度大於或等於厚金屬層犯的厚Microwave Integrated Circuits (MMICas) are provided by separate tg parts. The manufacturing of electronic components is not easy to integrate with the basic process of integrated circuit k. If the circuit for analog data control and analog data storage is integrated with the circuit for digital digital control and digital data storage and fabricated on a large semiconductor substrate, many significant advantages are achieved, and the advantages of integration include reducing manufacturing costs and reducing energy consumption. The element formed in the semi-baseline is subject to the actual size limitation. 'The capacitance is generated between the line of the sense element and the underlying substrate' and is affected by the resistive Wei bottom located below. Component = _ Electromagnetic energy loss occurs. When the resonant frequency of the adjustment circuit suddenly drops, the parasitic capacitance will have a serious negative effect on the LC circuit. It is worth noting that the electromagnetic field generated by the inductive component causes eddy currents in the resistive broken substrate, which causes severe energy loss. 1312181 thus forms an inductive component with low quality parameters. In addition, the quality parameter (9) can be used to represent the electrical dimension. The quality parameter is determined by Es/El, and the Es is the domain of the reaction part of the component. The eleventh E1 system represents the energy lost in the reaction part of the component. When the component is more and more resistant, the component's electrical noise will become closer to zero. At this time, the component's quality parameter is close to the remaining A. In the case of Wei Hong's inductive components, it is affected by the metal wire that forms the inductive component when riding in place, so that the electromagnetic energy will drop significantly on the component and Q, ϋσ shell parameter is used to measure The reaction purity of the component (PU song) recorded age (SUSGeptanGe), the fineness of the fine electric Chen, the resistance of Jinlin Road and the dielectric _ ride down Qiu she. In fact, the circuit is always equipped with a partial test of the wave, and the reduction will be able to be compensated (the fine energy is lost. The product is a separate component on the printed t-board (10)). In the case of an inductive component, when the quality parameter is greater than (10), the system is considered to have a high quality parameter: however, the inductive component (4) formed in the integrated circuit has a product fat number of between about 3 and 10. Inductive components can be spliced into a conventional large-scale substrate with semiconductor components. At this time, the parasitic capacitance generated by the inductive components limits the upper limit of the cut-off frequency, which is unacceptable in terms of money. Therefore, it is necessary to count the thief components with high quality parameters, such as 1312181 50 high, where the quality parameters will be affected by the resonance frequency of the JLC circuit. In the technique, components separated from each other must be configured to provide a higher = parameter 'and these separate components are to be integrated with the components of the touch element. However, even if the surface element and the surrounding components are placed on the base of the rotating body and the large-scale circuit structure is formed, the high-quality f-parameter cannot be achieved. If a non-cut circuit structure is used, the line that must be placed is connected to the auxiliary 7L of the device, and the line used for connection like the network form also generates parasitic capacitance and resistance loss. In many of the RF amplifiers, such as 疋 portable battery charging supplies, power consumption is an important test point at this time and is as low as possible. By increasing the power consumption, the parasitic capacitance effect and the resistance energy loss can be partially compensated, but this method still has some _. The above-mentioned problems all occur in the rapid expansion of wireless light goods in the market. For example, picking up the phone, the integration of the cap integrated circuit is one of the most important challenges. In addition, by significantly increasing the operating frequency 'for example, increasing to 1 to delete Z, the problem can be partially solved. However, under such a high operating frequency, it is affected by the base of the Shi Xi, the 7C of the inductor. Quality parameters will drop significantly. In order to enable the product to operate at this frequency, 'the development of large-scale inductive components, which uses a material other than seconds as the base for the inductors, such as Sapphire. Or gallium antimonide (10) as the substrate, compared with the Shi Xi base, these inductive components formed on the non-Shi Xi material substrate have a lower substrate loss than 1312181, which will form eddy current ddy current) Therefore, there is no inductance component of the loss parameter of electromagnetic energy. Moreover, =Γ produces a high-quality J with the above-mentioned way to form the electro-conducting material _, _ parabolic ^ yeast 然而 然而 ' 获 获 获 获 ' ' ' ' ' ' ' ' ' ' ' , , , , , , , , , , , , , , , This is because if you want to be in addition to the unique material, such as Kunhua gallium 'as the secret of the silk _, and in the formation of semiconductor components, 'has encountered a number of technical challenges. Since Shi Shenhua's gallium is semi-insulated at high frequency (4), the electromagnetic loss caused by the shame of knowing the riding of the bottom can be clearly defined as the quality parameter of the inductive component of the shaft. However, the RF W of the galvanic alloy is expensive, and if it is to avoid the RF of the pure b-gallium (9), the job has a cost advantage. There are many ways to integrate an inductive component with a semiconductor environment without sacrificing the performance of the 7G device (for example, because of substrate loss and sacrificing component performance). The method is to provide the bottom-side ground wire at the bottom of the inductor element in a way that allows for the addition of the jade, thereby reducing the resistance energy loss and parasitic effects of the substrate. In addition, the method is a multi-layer metal layer connection. The material is, for example, Ming, or a copper metal layer formed by an intaglio method (such as a coffee). The other method is to use a high-resistance ruthenium substrate, so that 1312181 can reduce the electrical damage caused by the 11 substrate. The electrical loss caused by the substrate significantly affects the quality parameters of the inductive component of the material. In addition, the biased well can be placed under the helical inductive component, so that it can be electrically entangled. The other complicated method is the = active inductive component, which can use the active circuit to simulate the inductive component. However, the analog inductive components will lead to high power consumption and the generation of miscellaneous holes. Therefore, this method cannot be applied to low-power and high-frequency methods. The common purpose is to improve the inductance components: Inductor Tree County, the market, the screaming weight = is _ magnetic _ consumption tear, the fine wheel energy will cause eddy current in the Shi Xi base. : As the volume of the integrated circuit shrinks, the cost per chip will decrease, and (4) the efficiency of a certain aspect of 2 into 0. It is used to connect the crystal moon to other lines or become more important' and as the integrated circuit is gradually reduced, the D, I metal connection will have a serious negative impact on the line performance. By shrinking it, the object is significantly reduced in efficiency. The most obvious impact of the current and the key samples f, the row and the grounding circuit and the resistance of the key signal circuit are delayed. If a wide metal line is used to reduce the resistance, the metal line will have a higher capacitance. In the current technology, when an inductive element is to be formed on a semiconductor substrate 1312181, a fine line technique can be utilized, and the inductive element is formed under the protective layer. This will make the county sense component very close to the surface of the base, = her _ 丨嶋 rhyme surface base cattle in the miscellaneous county will cause the south electric surface to consume 'and will reduce the quality parameters of the resistance element. U.S. Patent Publication No. 5,212, Akanishi, discloses a method of forming a line connection method. Its Kawasaki and external read path are formed in the circuit substrate on the wafer, and the design of the logic circuit depends on the line connection. length. U.S. Patent Publication No. 5,5,1,6 (6 vo 11^11, 1'.0 士31.) discloses a structure having an insulating layer between an integrated circuit and a circuit substrate, and The loosened pins may be electrically connected to the contacts of the substrate and the contacts of the substrate. U.S. Patent No. 5,554,907 (Jacobs) discloses an integrated semiconductor structure that allows a manufacturer to form a thin film multilayer circuit on a support substrate or on a wafer to integrate circuitry external to the wafer. U.S. Patent No. 5,1,6,461 (Volfson et al.) discloses a multilayer wiring structure in which a dielectric layer and a metal layer of a polyimide are alternately laminated by a TAB structure. Made on the wafer. U.S. Patent No. 5,635,767 (Wenzel et al.) discloses a method of reducing the resistance of a resistive capacitor in a PBGA structure in which multiple layers of metal are separately disposed. U.S. Patent No. 5,686,764 (Fulcher) discloses a flip chip 12 1312181 substrate. By detaching the power supply line from the wheel-in output leads, the resistive capacitance slowing effect can be reduced. U.S. Patent Publication No. 6, _, (10) (10) (4) discloses a spiral inductor element formed by using two metal layers, wherein the two metal layers can be connected by conduction. U.S. Patent No. 5,372,967 (Sundarain) discloses a helical inductive component. U.S. Patent Nos. 5,576,68, (Ling) and 笫5, 884, _ _ _ (Burghartz et al.) disclose other forms of helical inductor elements [invention] It is to provide a high-performance crystal structure, especially to improve the performance of RF. - The second object of the present invention is to provide a method of manufacturing an inductor element having a high quality factor. The second object of the present invention is that a chopped wafer can be used instead of a deified wafer, and a high-quality (four) number of inductive components can be fabricated on the 11 wafer. It is an object of the present invention to extend the frequency range of the inductive elements forming the surface of the dicing filament. The fifth object of the present invention is to enable the formation of a high-quality article on the surface of the substrate. A process for making thick polymeric leaks on the green layer and making a wide and thick metal line on the thick polymer layer can be found in U.S. Patent Publication No. 13 1312181 W (10). The present invention extends from U.S. Patent Publication No. & Naa, and discloses that an electronic component capable of forming high performance can be formed on a protective f or a thick polymer layer, such as an elemental component or a capacitive component. Or a resistive element. Additionally, the present invention provides a method of bonding a passive component that has been fabricated to the surface of a wafer. The above and other objects, features and advantages of the present invention will become more <RTIgt; (10) is assigned to the same transferor as the present invention. The disclosed wafer structure has a reconfiguration wiring layer and a metal wiring layer, which are disposed on the polymer layer, wherein the polymer layer is located in the conventional wafer. Follow the layer. The protective layer is located on the integrated circuit, and the thick polymer layer is selectively sewn on the crane, and the thick surface is attached to the protective layer. Wu Guo Patent Publication No. 6, Outline, No. 423 is assigned to the same structure as the present invention. Such a braided surface rope component can be used in a _ road towel, and can be called less Wei _. In this case, it is also revealed that the electric valley reading and resistive elements can be formed on the surface of the base of the base to reduce the parasitic effect of the electronic tree paste (four) located in the nail. Please refer to Figure 1 for a cross-sectional view of the wafer structure in accordance with U.S. Patent No. 6, Na, 916 14 1312181. Semiconductor substrate! The surface of the crucible (such as the Shi Xi base) has a transistor n and other components. (5) The surface of the semiconductor substrate ίο is covered with an internal dielectric layer 12 (10), which is located on the above-mentioned electronic 7G. The metal/dielectric layer 14 is on the inner dielectric layer 12, and the metal/or cladding layer I4 includes at least one dielectric layer ' and at least one metal connection is in the metal/dielectric layer 14 and the metal wiring 13 is a network of electronically connected and the uppermost metal layer has a partial region defined as an electrical contact, and these electronic contacts 16 can be connected to a transistor 11 or other tree in the surface of the surface of the semiconductor substrate H). Sexual connection. The protective layer 18 is mixed on the metal/dielectric layer 14 to avoid moving ions (such as nano ions), moisture, transition metals (such as sheet metal, mother, copper) or other impurities into the wafer. The concentrated layer 18 is, for example, a composite layer composed of oxime acetonide. The protective layer 18 is used to protect the underlying electronic components such as a transistor, a polycrystalline resistive element, a j-transfer capacitor element, and a thin metal line. The key step in U.S. Patent No. 6,383,916 is to deposit a thick polymer layer 20 (4), which is deposited on a protective layer 18. In order to be connected to the electronic contacts 16, the openings 22, 36, 38 will pass through the polylayer layer 20 and the escaping 18, which will be aligned with the electronic contacts μ. The electronic contacts Μ can be electrically extended into the polymer layer 20 through the openings σ22, 36, 38 located in the polymer (4). 15 1312181 In the preferred case, the material of the polymer layer 20 is, for example, polyimide, and the polymer layer 20 is, for example, a photosensitive material. The material of the polymer layer 20 may also be benzocyclobutene (BCB), polyarylene ether (parylene) or epoxy-based materials, such as SU-8 epoxy resin (may Obtained from Sotec Microsystems, Renens, Switzerland). After the openings 22, 36, 38 are formed, a metallization process can be performed to form the metal connection lines 26, 28 and the electronic contacts 16 can be connected. The metal connection lines 26, 28 can be of any design in width and thickness to conform to the desired circuit design, and the metal connection lines 26, 28 can be used as power bus bars, ground barriers or signal busses. The metal connection lines 26, 28 can be connected to circuitry external to the wafer via wire bonds or bumps. The electronic contacts 16 are positioned at the top of the metal/dielectric layer 14 (as shown in Figure 1), and the size of the electronic contacts 16 can be reduced to reduce the capacitance of the underlying metal layer. If the size of the electronic contact 16 is too large, the winding of the metal layer will be affected. After hardening, 'for example, the thickness of the polymer layer 2 of the polyimide may exceed 2 micrometers' and the thickness of the polymer layer 2 is, for example, between 2 micrometers and 15 micrometers. set. On the other hand, the thick polymer layer 2 〇 and e ′ can be formed by spin coating and Wei in a plurality of times to form a film of the compound. U.S. Patent Publication No. 6,383, (10) discloses the use of a thick or wide metal connection 16 1312181 to form a line 28 which has a non-financial path as shown in the figure, 32, 34, which can be used as an electrical circuit between circuits. For sexual connections. The metal connection line 28 having a thickness or width 13' thick or wide than the metal wiring 13' located in the lower layer has a smaller electrical value and capacitance value' and is easier to manufacture and lower in cost. Mingxiang, Fig. 2, which is modified from U.S. Patent No. 6,383,91, and also forming an inductive component 40 on polymer layer 20. The inductor element line 4 is in the form of a flat _, and can be parallel to the surface of the semiconductor substrate (4) and penetrates the height of the layer 12, 14, 18, 20, and the structure, so that the electric sampan: 40 is away from the semiconductor substrate surface. The second _ shows the cross-sectional structure of the thief element 4 () formed by the surface of the semiconductor substrate H). The loss of resistance energy can be reduced by the design of wide and thick metal. Among them, it is possible to form a low-resistance metal such as gold, silver or steel by means of electric ore, and the metal thickness thereof is, for example, about 2 μm. Compared with the conventional technique of forming an inductor element under a protective layer, by increasing the distance between the inductor element and the 11 substrate, the electromagnetic field generated by the 11 substrate can be reduced, and the quality parameter of the inductor element can be improved. The inductive component can be formed on the protective layer or can be formed on a polymeric layer (e.g., a chitin) located on the protective layer. In addition, an inductor element formed using a wide and thick metal has a small parasitic resistance. Another point of this month is that the width of the opening 19 of the protective layer 18 can be as small as G. 1 micron. Therefore, the electronic contact 16 can be small so that it can lift the winding capability of the fine-line metal layer at the top layer and have a lower capacitance value. Another important feature of the present invention is that the openings 22, 36, 38 of the polymer layer 2 can be larger than the opening 19 of the protective layer 18, and the openings 22, 36, 38 of the polymer layer 2 are aligned for protection. The opening 19 of the layer 18. The polymer layer 2〇»also has ten larger openings 22, 36, 38 as a selective design, and is relatively easy to make and the polymer layer 2 is designed with a larger opening 22, 36, 38 can be used in conjunction with the design of a thick metal layer to complete the metal deposition process of the present invention after forming the protective layer 18. The metal connection line 26 and the inductive element 4 are shown in FIG. 2, wherein the inductive element 40 includes two contacts 41, 43 which are electrically connected to the electronic contact 16 through the polymer layer 20. Further, referring to Fig. 2, in accordance with another aspect of the present invention, another polymer layer may be formed on the structure as shown in Fig. 2. Figs. 24a and 24b illustrate another feature of the present invention in which the connection of the sensuous contact is independent of the two downwardly connected contacts as shown in the second item. As shown in Fig. 24a, the polymer layer 35 is formed on the metal connection line 26 and the inductance element 4, and the material of the polymer layer 35 is, for example, polyimide. The contact opening 36a is connected to one end of the inductive element 4, and the end of the element 40 can be exposed to the outside. The device 4{) has an upwardly connected contact and a downwardly connected contact 39, which is a "one up one 1312181 down" configuration. Figure 24b shows another configuration in which two upwardly facing contact openings 36a, 38a' expose the inductive component 4', which is "all upwards". In the 24th and 24th figures, the upward contact of the inductive element can be connected to the material element by means of the wire being formed into a bump. As far as the wire bonding process is concerned, the upper surface of the inductive component 4 must form a metal that can be bonded to the wire bonding wire, and (4) is, for example, gold. In the case of the bump connection #, the under bump metal (_ can be formed in the upward contact opening to form the bump. In the first and the 24th, the formation and metal connection line 26 and the inductance element are utilized. 40. The same method is used to form the connection line, and the inductance element 40 can be electrically connected to other contacts on the wafer or external components as described above via the contact openings 36a, 38a. Please refer to Figure 24c for its green version. According to another feature of the invention, an extension line 89 is connected to the inductor turn 4〇, and the contact opening Na exposes the extension line 89' where the position of the contact opening is, for example, at the edge of the wafer, which is convenient The wire bonding process, such that the inductive component 40 can change the position of the external connection through the extension line 89. The configuration of the contact opening is as described above. The extension line 89, the metal connection line 26 and the inductive component 4 are simultaneously fabricated. 19 1312181 The extension line 89 can be connected to the inductive element 40 to change the position of the inductive element 40 to the external connection, wherein the extension line (10) can have contacts that are connected downwards (not shown, but The concept has been described before), instead of the contact that is connected upwards. When the contact point of the inductive component is in the middle region, for example, the junction of the junction of the figure is exposed by π 38b, at this time in the inductor component The contact of the intermediate portion of 4() cannot change the position of the external connection by the extension line 89. However, the contact at the intermediate portion of the inductance element 40 can be connected upward or downward. Fig. 3 The spiral inductor element 4 〇 is a top view, wherein the inductor element 40 is tied on the surface of the polymer layer 20, and the inductor element 4 shown in FIG. 2 is the section line 2-.2 along the line in Fig. 3. FIG. 4 is a schematic cross-sectional view of the inductor element 40. The influence of the inductor element 40 on the semiconductor substrate 1 隔绝 can be insulated by adding a conductive strip 44a, wherein the conductive strip 44a is substantially above the inductor element 4, The conductive sheet 44a is made of a conductive material such as copper or gold. The conductive sheet 44a extends on the surface of the protective layer 18, and the inductive element 40 is aligned on the conductive sheet 44a and is positioned on the conductive sheet 44a. The conductive sheet 44a can be called Micro ground exceeds the inductance element 4〇 The boundary region can further enhance the ability to shield the semiconductor substrate 10, so as to prevent the semiconductor substrate 10 from being affected by the electromagnetic field of the inductance element 40. Referring to FIG. 4, the inductor element 40 is at least 50% of the area 20 1312181 and The semiconductor substrate 10 is under tension, the lightning month 44a, in the preferred case 40, at least 80% of the area and half i=: r_44a, the butterfly canister semi-guided tomb ★ conductive sheet he can be electrically The electrode is connected to the inductor element 40 (as shown in FIG. 4, the conductive sheet can be electrically connected to the rightmost end of the inductor element 4, and the contact 43 of the electrode), and the conductive sheet can be It is at the level of the floating voltage, or it can be connected to other voltage levels, depending on the electronic design of the system. The method and material for producing the conductive sheet 44a may be a method and a material f for producing the metal connecting line 26 and the inductance element 4G as will be described later. The conductor 44a can be formed simultaneously to form the conductor 44' and the thick metal in the upper layer can be connected to the electronic contact 16 by the conductor 44, as shown in Fig. 4. Polymer layer 47 may be selectively formed on inductive component 4 and metal connection circuitry 26 to provide additional protection to the metal structure. Referring to Figures 12 through 23, there is shown a method of forming an inductive component or other passive component on a protective layer in accordance with the present invention. As shown in Fig. 12, the substrate 80 is a dielectric layer located in the lower layer, and the material of the metal contact 81 is, for example, Lu. The opening 82 can be formed by a patterning step through the protective layer 84, and the opening 82 can expose the metal contacts 81. For example, the polymer layer 86 of polyimine may be formed on the protective layer 84 and the metal contact 81, and the polymer layer 86 such as the polyamide 21 1312181 imine may be completed by spin coating, for example, or It can also be done by screen printing, or it can be done by pressing the polymer dry film. Figure 13 is a diagram showing the process of forming the opening 87 of the polymer layer 86, wherein the maximum width of the opening 87 of the polymer layer 86 is greater than the maximum width of the opening 82 of the protective layer 84 (see Figure 12), the opening 87 has Sloped side wall 85. The opening 87 of the polymer layer 86 has a vertical side wall 85 at the beginning, however, after the hardening step, the side wall 85 will assume a slanted pattern, and the opening opening 87 may be in a semi-tapered pattern. The angle of inclination of the side wall 85 is, for example, 45 degrees or more, and is substantially between about 5 degrees and 6 degrees. Alternatively, the angle of inclination of the side wall 85 can be as small as 2 degrees. In this embodiment, the larger vias may be through the polymer layer 86, such as polyimide, and aligned to the opening 82 of the lower protective layer 84, and Also connected to the sub-micron metal layer in the lower layer. The fk is oriented from the sub-micron metal layer to the wide metal level, and the size of the sub-micron metal via hole can be gradually increased. Referring to Figure 13, there is shown a method and metal structure for forming a connection line and an inductance element on a protective layer in accordance with the present invention. Firstly, the thief plating method can be formed to form an adhesion/barrier layer 88' which is made of titanium alloy, titanium nitride compound, group or group nitrogen compound, etc. and the thickness of the adhesion/barrier layer 88 is, for example, 500 angstroms. (angstro_ 5_ between the angstroms. Then, you can use the method of splashing 22 1312181 to form a seed hat such as gold > 90... The barrier layer on the layer 'the layer is slightly _ _ _ 埃The sound is then recorded in a way that forms a thick gold, such as gold. The thickness of the thick metal layer 92 is between 2 micrometers and 2 milligrams. Shape " resistance 94, and the thickness of the photoresist 94 is greater than or equal to the thickness of the thick metal layer
度透過微衫步驟，光阻94會暴露出種子層⑽，接著才以 電鍍的方式形成厚金屬層92。 在電鐘製程之後，可以將光阻94去除，如第15圖所示。 _厚金屬㈣作為侧祕，賴由姆獅可以去除黏 者/阻障層88及種子層9G ’如第16 _示。在圖示中，僅 綠不出電感元件40之其中-線圈，細熟悉該項技藝者應 知，整個電感元件40可以在此步驟完成。Through the micro-shirt step, the photoresist 94 exposes the seed layer (10), and then the thick metal layer 92 is formed by electroplating. After the clock process, the photoresist 94 can be removed, as shown in FIG. _Thick metal (4) as a side secret, relying on the lion to remove the adhesive/barrier layer 88 and the seed layer 9G ’ as shown in the 16th _. In the illustration, only the coil of the inductive component 40 is green, as is well understood by those skilled in the art, the entire inductive component 40 can be completed in this step.
如第17圖及第18圖所示，厚金屬層92亦可以是僅填入 於開口 87 t’分區域，如此可以設計麟路密度高且線路 甚、、、田之迅感元件。而在本實施例中，聚合物層86的開口 之尺寸D比如疋約15微米，而電感元件4〇之金屬線路之間 距係小至4微米。因此，將位於聚合物層86之開口耵内之 金屬圖案化亦是本發明的重要特徵。 如前所述，可以利用濺鍍的方式，形成一黏著/阻障層 88及比如是金的種子層9〇，並且還形成一光阻95，如第17 23 1312181 圖所示。接著可以利用電鍍的方式形成比如是金的厚金屬層 92。之後’可以將光阻95去除，並且蝕刻掉先前位在光阻 95下方之黏著/阻障層88及種子層90，如第18圖所示。 在本發明之另一實施例中，可以利用銅來作為位在保護 層上之金屬結構中之厚金屬層的材質。剛開始之結構係如第 13圖所示，接著請參照第19圖，可以利用濺鍍的方式形成 比如是鉻或鈦之黏著/阻障層100，其厚度比如是介於2〇〇埃 到2000埃之間，接著，可以利用濺鍍的方式形成比如是銅之 種子層102，其厚度比如是介於2000埃到1〇〇〇〇埃之間。接 著，可以利用電鍍的方式形成比如是銅之厚金屬層1〇4，其 厚度比如是介於3微米到20微米之間，而可以利用光阻9如 及傳统的微影製程定義出欲電鍍的區域。接著，可以選擇性 地利用電鍍的方式形成比如是鎳的金屬頂層106，其中金屬 頂層106的厚度比如是介於〇. 1微米到3微米之間。 請參照第20圖，接著可以將光阻94a去除並暴露出比如 是銅的種子層102。接著，可以比如是銅的厚金屬層1〇4 作為蝕刻罩蔽，並藉由蝕刻方式可以去除黏著/阻障層1〇〇 及比如是銅之種子層1〇2，如第21圖所示。 如果有形成比如是鎳的金屬頂層1〇6，則在蝕刻黏著/阻 P早層100及種子層102的過程中，金屬頂層106可以作為蝕 刻終止層’此雜可赠崎銅侧速報快賴刻劑來银 24 1312181 刻種子層⑽，如此可以減少厚金屬層遍之銅金屬的消耗。 在圖不中’僅4會示出電感元件4〇之其中一線圈，然而熟 悉該項技藝麵知，魏電感元件4G可以在此步驟完成。 如弟22圖及第23圖所示，厚金屬層104亦可以是僅填 入於開口 87中之部分區域，如厚金屬層104填入於開口 87 中的厚金屬層92所示。如前所述，可以糊離的方式，形 成黏者/阻障層1〇〇及比如是銅的種子層102，並且還形成 一光阻95a ’如第22圖所示。接著可以利用電鍍的方式形成 比如疋銅的厚金屬層104。之後，可以將細娜去除，並 且蝕刻掉黏著/阻障層⑽及種子層搬，如第23圖所示。 睛參照第5a圖，其金屬結構係如前所述，值得注意的 是，在本實施例中並未形成比如是聚醯亞胺之聚合物層於保 護層18上。電感元件i9a係直接形成在保護層18上，其中 用來形成電感元件19a之金屬線路的電阻值要愈低愈好，為 了達到上述目的，當在製作電感元件19a時，可以形成比如 是金的厚金屬層。在上述之設計中，針對2· 4GiJz的應用，電 感元件19a之品質參數可以從5提升至20。 如前所述’第5a圖之電感元件i9a可以與其他的元件連 接’比如是與位在下層之接點連接，如第4圖所示，而電感 元件19a之連接方向可以是“一上一下，，的結構，如第24a 圖所示；或者電感元件19a之連接方向可以是“均為朝上” 25 1312181 的結構’如第24b圖所示。 而一聚合物層（未繪示）可以選擇性地形成於電感元件 19a 上。 另外，聚合物可以是僅形成在電感元件下，而不形成在 保護層上之其他地方’如此相較於面積較大之聚合物層，小 面積之聚合物塊具有較低的内應力，如第5b圖或第5c圖所 不，其分別繪示依照本發明形成於聚合物塊上之電感元件的 剖面不意圖及上視圖。每一聚合物塊上具有至少一電感元 件’其中第5c圖繪示電感元件4〇a及電感元件4〇b。 請參照第5b圖，聚合物塊2〇a之形成方式比如是先沈積 -聚合物層’然後再贿化聚合物層，如此便形成聚合物塊 20a。而聚合物塊20a亦可以藉由網板印刷的方式所形成，或 是壓合乾膜而成。在形成聚合物塊2Qa之後，可以形成電感 元件40a、40b於聚合物塊2〇a上。 第5b圖之電感το件40a、40b之對外連接方法可以是如 則所述，其中電感兀件40b比如具有兩個朝下的接點41a、 43a，其可以連接至電子接點16。而電感元件術並不具有 接點，但是卻可以向上連接至外界電路，如前所述。 第5c圖係繪示依照本發明之電感元件的上視圖，而第 5b圖係在第5c圖中沿著剖面線5b，之剖面示意圖。如第 5c圖所示’聚合物塊施之間係為相互隔離的，且聚合物塊 26 1312181 20a係僅形成在電感元件下，而其他未形成聚合物塊20a的 區域，保護層18可以暴露於外。 而另外的一聚合物保護層（未繪示）可以選擇性地形成在 電感元件40a、40b上。 而如第5b圖及第5c圖所示之聚合物塊亦可以形成在其 他的元件下，舉例而言，可以形成在比如是電阻元件及電容 元件之被動元件下。 第:6a圖及第6b圖緣示依照本發明之另一較佳實施例。 如第6a圖所示，聚合物層47係位在底層線圈60與上層線圈 62之間，而聚合物層20、47、64可以是利用如前所述的材 質所製成。而開口 66係位在最上層之聚合物層64中，可以 暴露出上層線圈62。 第6b圖繪示依照本發明另一較佳實施例之晶片結構的 剖面示意圖。其中底層線圈60可以直接形成在保護層18上。 第6c圖繪示電感元件19a係為螺線管(solenoid)形式之 立體示意圖，其中電感元件19a係形成在保護層18上，電感 元件19a係包括導通孔金屬23、底層金屬結構25及頂層金 屬結構27 ’其中導通孔金屬23係位在聚合物層20中，其係 為垂直的金屬結構。透過導通孔金屬23可以使底層金屬結構 25及頂層金屬結構27電性連接。 第6d圖繪示電感元件19a係為螺線管形式之立體示意 27 I312181 圖’其中電感元件19a係形成在第一聚合物層29上，而電感 兀件19a具有導通孔金屬23，位在形成於第一聚合物層四 上之第二聚合物層中。 第6e圖係繪示第6c圖及第6d圖中螺線管形式之電感元 件的上視不意圖，其中透過導通孔金屬23可以使底層金屬結 構25及頂層金屬結構27電性連接。 第阖繪不第6c圖到第6e圖中之電感元件的剖面示意 圖’其中第6f圖係繪示第6e圖中沿著剖面線，6f之剖面 · 示意圖。 請參照第6g圖及第6h圖，其緣示依照本發明之超環面 (toroidal)形式之電感元件的示意圖，其中電感元件係類似 壞繞形狀之螺線圈。在第6g圖巾’其繪示電感元件之立體示 意圖’其中電感元件68係包括導通孔金屬23a、底層金屬結 構25a及頂層金屬結構27a，而導通孔金屬撕係連接底層 金屬結構25a及頂層金屬結構27a。 鲁 第6h圖繪示第6g圖中環面(t〇r〇idal)形式之電感元件 68的上視不意圖。而電感元件68之繞線特點已在之前的較 佳實施例中闡述，在此便不再贅述。 第7a圖繪示依照本發明之電容元件形成在半導體基底 10上的剖面示意圖，其中絕緣層係位在保護層18上。金屬/ 介電層14及電子接點16係位在半導體基底1〇上，且保護層 28 Ϊ312181 18係形成在金屬/介電層14上，而保護層18具有開口，可 以暴露出電子接點16。 热習該項技藝者應知，電容元件係由一下電極、一電容 介電層及一上電極所構成，而電容介電層係位在上電極與下 電極之間。第7a圖所示之電容元件具有一下電極42、—電 谷介電層46及一上電極45。上電極45及下電極42比如是 利用如前所述之電鍍方式形成金或銅之厚金屬層而完成，而 可以選擇性地形成比如是聚醯亞胺之聚合物保護層於電容元 鲁 件上。電容元件之接點對外連接方式比如是如前所述，（電容 疋件之接·如是喃下連接、—上—τ的連接或是均朝上 連接）。 下電極42的厚度比如是介於〇. 5微米到2〇微米之間， 介電層46的厚度比如是介於5〇〇埃到5〇〇〇〇埃之間，而上電 極45的厚度比如是介於〇. 5微米到2〇微米之間。 如第7a圖所示之在保護層上形成電容元件之結構，具有 籲 下列優點： 1. 可以減少電容元件與下層石夕基底之間的寄生電容。 2. 可以利用厚金屬層形成電容元件之電極，如此可以減 少電容元件之電阻值，特別是可以應用在無線的領域中。 3. 可以形成高介電常數之材質在電容元件之上電極與下 電極之間，其材質比如是二氧化鈦（Tia)、五氧化二鈕 29 1312181 (TaA)、高分子聚合物、氮石夕化合物⑸3N4)或氧發化合物 (Si〇2)等’如此可以提高電容元件之電容值。 而如第7a圖所示之電容元件亦可以形成在位於保護層 18上之聚合物層上，其概念係類似如第4圖所述之將電感元 件40形成在位於保護層18上之聚合物層2〇上的結構。 w電層46係為南介電常數之材質，比如是利用化學氣象 沈積的方式沈積氮矽化合物(ShN4)、四乙烷基氧矽甲烷 (TEOS)、五氧化二组（Ta2〇5)、二氧化鈦（Ti〇2)、鈦酸銷（SrTi〇3) 或氮氧矽化合物(SiON)等。 第7b圖及第7(：圖缚示電容元件之剖面示意圖。如第7|^ 圖所示，聚合物層20可以形成在保護層18上，並且透過圖 案化製程，可以使聚合物層20暴露出電子接點16，而聚合 物層20之導通孔的直徑係小於保護層開口之直徑。然而，在 較佳的情況下，聚合物層20之導通孔係與保護層開口連通， 而聚合物層20之導通孔的直徑係大於保護層開口之直徑。藉 由聚合物層20的配置’可以使下電極42、上電極45及介電 層46之配置向上移動約等於聚合物層2〇之厚度的距離，如 此電容元件配置可以在更遠離基底的地方。如前所述，比如 是聚醯亞胺之聚合物層20的厚度可以是介於2微米到15〇 微米之間。如此，電容元件與位在下層之金屬線路結構及矽 基底之間的距離可以增加，故可以大幅降低寄生電容的發生。 30 1312181 第7a圖及第7c圖均綠示電容元件之接點係向下連接， 而電容元件亦可岐—上—下的連齡式，如第25圖所示， 或是電容元件均是朝上連接，如第她圖所示的概念。 如第7a圖至第7c圖所示之電容元件之上電極45可以經 由位在上電極n合物層35之開口 37，社與一電路 零性連接，如第25社勤、轉_。財料物層35係 形成在電谷讀之上電極45上，經由貫絲合物層邪之開 37可以暴4出電谷元件之上電極，藉以使上電極與 一外部線路電性連接。 而一聚合物保護層（未繪示）可以選擇性地形成在如第 7a圖至第7c圖所示之電容元件上。 第8圖繪示半導體基底10的剖面示意圖，半導體基底 10上形成有一保護層18，而電阻元件48係位在保護層18 上。熟習該項技藝者應知，電阻元件48係由能夠提供電性阻 值之材質所構成’且電流能夠流經該材質。電阻元件48之材 質比如是鈕氮化合物(TaN)、鎳鉻合金(NiCr)、鎳錫合金 (NiSn)、鎢(W)、鈦鎢合金(TiW)、鈦氮化合物(TiN)、鉻(Cr)、 鈦(Ti)、鎳(Ni)或鈕石夕化合物(TaSi)等。在上述的這些材質 中，鎳鉻合金能夠提供最佳的電阻溫度係數(Temperature Coefficient of Resistance)，可以小至 5 ppm/°C。電阻元 件48之長度、厚度及寬度可以依照不同的應用而設計。而可 31 1312181 :::如第7a圓至第7c圖所示之配置電容元件的概念 之電阻元件48’其，電阻元崎形成 =9a圖及第％圖繪示依照本發明形成在聚合物層如 上之電P且元件48的剖面示意圖，其中電阻元件仙可以與電 子接點16連接。藉由增加電阻元件與基底之間的距離(所增 加的距離係大致上等於聚合物層2〇的厚度），可以降低電^ 凡件與基底之_寄生效應，如此可以改善f阻元件的 性能（由於可以減少寄生電容關耗，故可以提升在高頻運作 下的電性效能）。 如第8圖、第9a圖及第9b圖所示之電阻元件的接點 均疋向下連接。然而電阻元件48亦可以是一上一下的連接， 如第26圖所示，或是電阻元件48之接點均是朝上連接，其 可以參考如第24b圖中電感元件4〇均是朝上連接的概念。 而另一聚合物層可以選擇性地形成在如第8圖、第如 圖及第9b圖所示之電阻元件48上，藉以保護電阻元件48。 請參照第10圖及第11圖’其繪示依照本發明在保護層 上之另一種製程。在本實施例中，可以藉由形成凸塊使電子 接點16與位在上面之電子元件電性連接，比如是與已製作完 成之電感元件、電容元件、電阻元件或是其他的被動元件電 性連接。而凸塊底層金屬50可以形成在聚合物層2〇之開口 32 1312181 内’其中聚合物層20之開口係對準於較小之保護層μ的開 口 ’如此凸塊底層金屬50可以與電子接點16連接，作為凸 塊底層金屬（UBM)之用。利用傳統的電鑛製程、植球製程或網 板印刷製程，可以形成凸塊52於凸塊底層金屬5〇上，而在 助銲劑形成於凸塊52上之後，可以進行回銲的步驟。接著， 已製作完成的電子元件54可以連接到凸塊52上，其中已製 作完成的電子元件54具有銲料53，如此可以提升接合性。 上述之製程係類似於常應用在電子元件與印刷電路板接 合的表面黏著技術。已製作完成的電子元件54比如是電感元 件、電容元件或是電阻元件。 第11圖繪示利用凸塊56及凸塊底層金屬5〇將已製作完 成的電子元件54直接形成於保護層18上的結構。 由於已製作完成的電子元件54並不是如習知技術係形 成在印刷電路板上，因此如第10圖及第U圖所示之已製作 完成的電子元件54具有較佳的效能，且成本並不高。 而凸塊底層金屬50可以是如本發明之第12圖到第23 圖所示之金屬結構，然而若是利用金作為厚金屬層時，凸塊 底層金屬50的厚度可以是介於〇.1微米到2〇微米之間，在 較佳的情況下，凸塊底層金屬50係為較薄的尺寸，如此在製 作元成之後’可以避免在凸塊底層金屬5〇之介面附近的凸塊 材質具有高濃度的金。 33 1312181 上述之被動元件之配置方式至少具有下列的優點： 1.由於已製作完成的電子元件可以提供適當的參數，並 且可以接合在靠近晶片中線路的位置，因此藉由本發明之被 動元件的設計概念可以達到真正的系統化晶片的表現。 2·由於已製作完成的電子元件可以接合在靠近晶片中線 路的位置，因此能夠減少寄生現象的發生。 3.在本發明中’由於可以選擇具有適當設計參數之已製 作凡成的電子元件製配在保護層上，此種設計可以減少已製 鲁 作完成的電容元似已f作完成的域元狀效應，為 了更清楚的說明，下面有針對習知技術與本發明作比較說明： 習知技術係利用細的金屬導線來製作電感元件，而若是 為了要減少電阻效應，必須製作較寬的線圈，則會使得電感 元件之表面面積增加。另外，習知技術會具有較大之電感元 — 件之寄生電谷的現象，並且在基底内會有嚴重的渦電流損耗。 然而本發明，係採用厚金屬層作為線路，因此可以減少 馨 電阻效應。料’聚合㈣和録祕耕與下層結構之 間’如此可以減少寄生效應，由於寄生效應的減少，會使得 共振頻率提高，故適合高頻電路的操作。 雖然本發明已以較佳實施例揭露如上，然其並非用以限 疋本發明，任何熟習此技藝者，在不脫離本發明之精神和範 圍内’當可作各種之更動與潤斜，因此本發明之隔離範圍當 34 1312181 視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 第1圖繪示依照美國專利公告第6,383,916號之連接線 路結構的剖面示意圖。 第2圖緣雜照本發明之電感元件形成在厚聚酸亞胺層 上之剖面示意圖。 第3圖繪示依照本發明之電感元件之上視示意圖。 第4圖緣示依照本發明之晶片結構的剖面示意圖，其中 電感元件係軸在厚聚醯亞胺層上，並且藉由—導電材質可 以避免電感元件影響到位在下層的矽基底。 第5a圖緣示依照本發明之電感元件形成在保護層上之 剖面示意圖。 第5b圖、繪示依照本發明之多個電感元件形成在比如是 咼分子聚合物之絕緣層上的剖面示意圖。 第5c圖綠示依照本發明之多個電感元件形成在比如是 局分子聚合物之絕緣層上的上視圖。 第6a _示依照本购之懸轉成在比如是高分子 聚合物之絕緣層上的勤轉圖，針絕緣層餘在保護層 上。 第6b圖繪示依照本發明之變壓器的剖面示意圖，其中位 在下方的線圈係位在保護層上。 第6c圖繪示依照本發明另一較佳實施例之螺線管形狀 35 1312181 的賊元狀續示意圖，其中電献件餘秘護層上。 第6d圖繪不依照本發明另一較佳實施例之螺線管形狀 的電感元件之立體示賴，其中電感元件餘在比如是高分 位在保護層上。 第6e圖係為第6c圖及第6d圖之電感元件的上視示意 圖。 立體示意圖。 第6f圖係為第6e圖中沿著剖面線㈣之剖面示意圖。 第故圖繪示依照本發明之環形線圈形狀的電感元件之 第6h圖繪示第6g圖中環形始節取， g ® T 形狀的電感元件之上視 示意圖。 護層上的 第7a圖繚示依照本發明之電容元件形成在保 剖面示意圖。 第7bi7c圖繪示依照本發明之電容元件形成在比如; =·絕緣層上的剖面示意圖，其中絕緣層_ 面示=齡示賴树伙恤树軸拽護層上咖 λ 元件形成在比 巴緣層上㈣，其中厚絕 第9a圖及第9b圖!會示依照本發明之電阻天 如是高分子聚合物之厚、絕 緣 層係位在保護層上。 1312181 第10圖繪示依照本發明之晶片結構的剖面示意圖，其中 已製作7Ό成的電子元件係利用表面黏著技術黏著於比如是高 分子聚合物之厚絕緣層上。 第11圖繪示依照本發明之晶片結構的剖面示意圖，其中 已製作完成的電子元件係利用表面黏著技術黏著於保護層 上。 第I2圖至第I8圖繪示依照本發明以金為材質之金屬結 構的剖面^意® ’其巾金屬結獅穿過比如是高分子聚合物 之絕緣層。 第I9圖至第23圖繪示依照本發日月以鋼為材質之金屬結 構的剖面示其中金屬結構係穿過比如是高分子聚合物 之絕緣層。 第24a圖至第24c圖繪示依照本於明裒 个知月另一種連接電感元 件的方法。 第25圖及第26 ®分別繪示依照本發明另一種連接電容 元件及電阻元件的方法。 【主要元件符號說明】 10 :半導體基底 11 電晶體 12 :内部介電層 13 金屬連線 14 :金屬/介電層 16 電子接點 18 :保護層 19 開口 19a :電感元件 20 聚合物層 37 1312181 22 :開口 23 :導通孔金屬 25 :底層金屬結構 27 :頂層金屬結構 26 :金屬連接線路 29 :第一聚合物層 30 :路徑 34 :路徑 36 :開口 36b:接點開口 38 :開口 38b :接點開口 40 :電感元件 40b :電感元件 41 :接點 42 :下電極 43a :接點 44a :導電片 46 :介電層 48 :電阻元件 52 :凸塊 20a :聚合物塊 23a :導通孔金屬 25a :底層金屬結構 27a :頂層金屬結構 28 :金屬連接線路 22 :開口 32 :路徑 35 :聚合物層 36a :接點開口 37 :開口 38a :接點開口 39 :接點 40a :電感元件 40c :電感元件 41a :接點 43 :接點 44 :導體 45 :上電極 47 :聚合物層 50 :凸塊底層金屬 53 :銲料 1312181 54 :已製作完成的電子元件 56 :凸塊 60 ··底層線圈 62 :上層線圈 64 :聚合物層 66 :開口 68 ··電感元件 80 :基底 81 :金屬接點 82 :開口 84 :保護層 85 :侧壁 86 :聚合物層 87 :開口 88 :黏著/阻障層 89 :延伸線路 90 :種子層 92 :厚金屬層 94 :光阻 94a :光阻 95 :光阻 95a :光阻 100 :黏著/阻障層 102 :種子層 106 :金屬頂層 104 :厚金屬層 39As shown in Fig. 17 and Fig. 18, the thick metal layer 92 may be filled only in the region of the opening 87 t', so that it is possible to design a fast sensing element with a high density of the lining and a line. In the present embodiment, the size D of the opening of the polymer layer 86 is, for example, about 15 μm, and the distance between the metal lines of the inductive element 4 is as small as 4 μm. Therefore, patterning the metal located in the opening of the polymer layer 86 is also an important feature of the present invention. As previously described, an adhesion/barrier layer 88 and a seed layer 9, such as gold, may be formed by sputtering, and a photoresist 95 is also formed, as shown in Figures 17 23 1312181. A thick metal layer 92, such as gold, can then be formed by electroplating. Thereafter, the photoresist 95 can be removed and the adhesion/barrier layer 88 and the seed layer 90 previously positioned below the photoresist 95 can be etched away, as shown in FIG. In another embodiment of the invention, copper may be utilized as the material for the thick metal layer in the metal structure on the protective layer. The structure at the beginning is as shown in Fig. 13. Next, referring to Fig. 19, an adhesion/barrier layer 100 such as chrome or titanium may be formed by sputtering, and the thickness thereof is, for example, 2 〇〇 to Between 2000 angstroms, a seed layer 102, such as copper, may be formed by sputtering, for example between 2000 angstroms and 1 angstrom. Then, a thick metal layer 1 such as copper may be formed by electroplating, for example, between 3 micrometers and 20 micrometers, and the photoresist 9 may be defined by a conventional lithography process. Area. Next, a metal top layer 106, such as nickel, may be selectively formed by electroplating, wherein the thickness of the metal top layer 106 is, for example, between 0.1 and 3 microns. Referring to Figure 20, the photoresist 94a can then be removed and exposed to a seed layer 102 such as copper. Then, a thick metal layer 1 〇 4 such as copper may be used as an etch mask, and the adhesion/barrier layer 1 〇〇 and the seed layer 1 〇 2 such as copper may be removed by etching, as shown in FIG. 21 . . If there is a metal top layer 1〇6 formed of, for example, nickel, the metal top layer 106 can serve as an etch stop layer during the etching/resistance of the P early layer 100 and the seed layer 102. The engraving agent is silver 24 1312181 engraved seed layer (10), which can reduce the consumption of copper metal throughout the thick metal layer. In the figure, only 4 will show one of the inductor elements 4, but it is known in the art that the Wei inductor element 4G can be completed in this step. As shown in FIG. 22 and FIG. 23, the thick metal layer 104 may also be a portion of the region that is only filled in the opening 87, as shown by the thick metal layer 92 in which the thick metal layer 104 is filled in the opening 87. As described above, the adhesive layer/barrier layer 1 and the seed layer 102 such as copper may be formed in a paste-off manner, and a photoresist 95a' is also formed as shown in Fig. 22. A thick metal layer 104 such as beryllium copper can then be formed by electroplating. Thereafter, the fine layer can be removed and the adhesion/barrier layer (10) and the seed layer removed, as shown in Fig. 23. Referring to Fig. 5a, the metal structure is as described above, and it is noted that a polymer layer such as polyimine is not formed on the protective layer 18 in this embodiment. The inductive component i9a is formed directly on the protective layer 18, wherein the lower the resistance of the metal line used to form the inductive component 19a, the better, in order to achieve the above object, when the inductive component 19a is formed, for example, gold may be formed. Thick metal layer. In the above design, the quality parameter of the inductive element 19a can be increased from 5 to 20 for the application of 2.4 GiJz. As mentioned above, the inductive component i9a of Fig. 5a can be connected to other components, for example, to the contact at the lower layer, as shown in Fig. 4, and the connection direction of the inductive component 19a can be "one up" , the structure of, as shown in Figure 24a; or the connection direction of the inductance element 19a may be "all upwards" 25 1312181 structure 'as shown in Figure 24b. And a polymer layer (not shown) can Optionally formed on the inductive component 19a. In addition, the polymer may be formed only under the inductive component and not formed elsewhere on the protective layer. [This is compared to a larger polymer layer, a small area of polymerization. The block has a lower internal stress, as shown in Fig. 5b or Fig. 5c, which respectively shows a cross-sectional view and an upper view of the inductive component formed on the polymer block in accordance with the present invention. Having at least one inductive component 'where is shown in FIG. 5c as the inductive component 4〇a and the inductive component 4〇b. Referring to FIG. 5b, the polymer block 2〇a is formed by depositing a polymer layer first and then Bribing the polymer layer, so The polymer block 20a is formed. The polymer block 20a can also be formed by screen printing or by pressing a dry film. After forming the polymer block 2Qa, the inductive elements 40a, 40b can be formed into the polymer. The external connection method of the inductors το 40a, 40b of FIG. 5b may be as described above, wherein the inductor element 40b has, for example, two downward-facing contacts 41a, 43a, which can be connected to the electrons. Contact 16. The inductive component does not have a contact, but can be connected up to the external circuit as previously described. Figure 5c shows a top view of the inductive component in accordance with the present invention, and Figure 5b is in the Figure 5c is a cross-sectional view along section line 5b. As shown in Figure 5c, the polymer blocks are isolated from each other, and the polymer blocks 26 1312181 20a are formed only under the inductive component, while others The region of the polymer block 20a is not formed, and the protective layer 18 may be exposed to the outside. Another polymer protective layer (not shown) may be selectively formed on the inductive elements 40a, 40b. As shown in Fig. 5b and The polymer block shown in Figure 5c can also be shaped Other components, for example, may be formed under passive components such as resistive components and capacitive components. Figures 6a and 6b illustrate another preferred embodiment in accordance with the present invention. As shown, the polymer layer 47 is positioned between the bottom layer coil 60 and the upper layer coil 62, while the polymer layers 20, 47, 64 can be made of the material described above, while the opening 66 is positioned at the uppermost layer. In the polymer layer 64, the upper layer coil 62 may be exposed. Fig. 6b is a schematic cross-sectional view showing a wafer structure according to another preferred embodiment of the present invention, wherein the bottom layer coil 60 may be directly formed on the protective layer 18. The figure shows that the inductive component 19a is in the form of a solenoid, wherein the inductive component 19a is formed on the protective layer 18, and the inductive component 19a includes the via metal 23, the underlying metal structure 25 and the top metal structure 27 'Where the via metal 23 is in the polymer layer 20, which is a vertical metal structure. The underlying metal structure 25 and the top metal structure 27 can be electrically connected through the via metal 23. Figure 6d shows a perspective view of the inductor element 19a in the form of a solenoid. 27 I312181 Figure 2 wherein the inductor element 19a is formed on the first polymer layer 29, and the inductor element 19a has a via metal 23 in place. In the second polymer layer on the first polymer layer 4. Figure 6e is a top view of the inductor element in the form of a solenoid in Figures 6c and 6d, wherein the underlying metal structure 25 and the top metal structure 27 are electrically connected through the via metal 23. The cross-sectional schematic diagram of the inductive component in the sixth to the sixth e-figure is shown in Fig. 6f, and the cross-section of the cross-sectional line, 6f, is shown in Fig. 6e. Referring to Figures 6g and 6h, there is shown a schematic view of a toroidal form of an inductive component in accordance with the present invention, wherein the inductive component is a spiral coil of similar shape. In the 6th drawing, a schematic view of the inductive component is shown, wherein the inductive component 68 includes a via metal 23a, an underlying metal structure 25a and a top metal structure 27a, and the via metal tearing connects the underlying metal structure 25a and the top metal. Structure 27a. Lu 6h shows the upper view of the inductive component 68 in the form of a torus (t〇r〇idal) in the 6th diagram. The winding characteristics of the inductive component 68 have been described in the prior preferred embodiments and will not be described again. Fig. 7a is a schematic cross-sectional view showing the formation of a capacitor element in accordance with the present invention on a semiconductor substrate 10, wherein the insulating layer is tied to the protective layer 18. The metal/dielectric layer 14 and the electronic contacts 16 are on the semiconductor substrate 1 , and the protective layer 28 Ϊ 312181 18 is formed on the metal/dielectric layer 14 , and the protective layer 18 has an opening to expose the electronic contacts 16. It should be understood by those skilled in the art that the capacitive element is composed of a lower electrode, a capacitor dielectric layer and an upper electrode, and the capacitor dielectric layer is located between the upper electrode and the lower electrode. The capacitive element shown in Fig. 7a has a lower electrode 42, a valley dielectric layer 46 and an upper electrode 45. The upper electrode 45 and the lower electrode 42 are formed by forming a thick metal layer of gold or copper by electroplating as described above, and a polymer protective layer such as polyimide may be selectively formed on the capacitor element. on. The external connection method of the contact of the capacitor element is as described above, (the connection of the capacitor element is the connection of the squirm, the connection of the - τ or the upward connection). The thickness of the lower electrode 42 is, for example, between 0.5 μm and 2 μm, and the thickness of the dielectric layer 46 is, for example, between 5 μA and 5 μL, and the thickness of the upper electrode 45. For example, it is between 微米. 5 microns and 2 〇 microns. The structure in which the capacitive element is formed on the protective layer as shown in Fig. 7a has the following advantages: 1. The parasitic capacitance between the capacitive element and the underlying substrate can be reduced. 2. The electrode of the capacitor element can be formed by a thick metal layer, so that the resistance value of the capacitor element can be reduced, and in particular, it can be applied in the field of wireless. 3. A material with a high dielectric constant can be formed between the upper electrode and the lower electrode of the capacitor element, such as titanium dioxide (Tia), pentoxide pentoxide 29 1312181 (TaA), high molecular polymer, nitrous oxide compound (5) 3N4) or an oxygen generating compound (Si〇2), etc. 'This can increase the capacitance value of the capacitive element. The capacitive element as shown in Fig. 7a can also be formed on the polymer layer on the protective layer 18, the concept of which is similar to that of the polymer element 40 formed on the protective layer 18 as described in Fig. 4. The structure on layer 2〇. w electrical layer 46 is the material of the south dielectric constant, such as the deposition of nitrogen bismuth compound (ShN4), tetraethyl oxymethane (TEOS), pentoxide group (Ta2 〇 5) by chemical meteorological deposition. Titanium dioxide (Ti〇2), titanate pin (SrTi〇3) or oxynitride compound (SiON). Fig. 7b and Fig. 7: a schematic cross-sectional view of the capacitive element. As shown in Fig. 7|, the polymer layer 20 may be formed on the protective layer 18, and the polymer layer 20 may be formed through a patterning process. The electrical contact 16 is exposed, and the diameter of the via hole of the polymer layer 20 is smaller than the diameter of the opening of the protective layer. However, in a preferred case, the via hole of the polymer layer 20 is in communication with the opening of the protective layer, and the polymerization is performed. The diameter of the via hole of the object layer 20 is larger than the diameter of the opening of the protective layer. The arrangement of the polymer layer 20 can move the arrangement of the lower electrode 42, the upper electrode 45 and the dielectric layer 46 upward by about equal to the polymer layer 2〇. The distance of the thickness, such that the capacitive element configuration can be further away from the substrate. As previously mentioned, the polymer layer 20, such as polyimide, can have a thickness between 2 microns and 15 microns. The distance between the capacitive element and the metal wiring structure and the germanium substrate in the lower layer can be increased, so that the occurrence of parasitic capacitance can be greatly reduced. 30 1312181 Both the 7a and 7c diagrams are green and the contacts of the capacitive element are connected downward. And electricity The components can also be connected to the upper-lower age, as shown in Figure 25, or the capacitive elements are connected upwards, as shown in the figure above. Figure 7a to 7c The upper electrode 45 of the capacitor element can be connected to a circuit zero through the opening 37 of the upper electrode n-layer 35, such as the 25th commutation, the _ material layer 35 is formed in the electric valley reading On the upper electrode 45, the upper electrode of the electric grid element can be violently connected via the cross-linking layer 37, so that the upper electrode is electrically connected to an external line. A polymer protective layer (not shown) can be Optionally, it is formed on the capacitive element as shown in Figures 7a to 7c. Figure 8 is a schematic cross-sectional view of the semiconductor substrate 10 with a protective layer 18 formed thereon and the resistive element 48 is protected. It is known to those skilled in the art that the resistive element 48 is made of a material capable of providing electrical resistance and that current can flow through the material. The material of the resistive element 48 is, for example, a nitrogen compound (TaN). Nickel-chromium alloy (NiCr), nickel-tin alloy (NiSn), tungsten (W), titanium-tungsten alloy (TiW), Titanium nitride compound (TiN), chromium (Cr), titanium (Ti), nickel (Ni) or yoke compound (TaSi), etc. Among the above materials, nickel-chromium alloy can provide the best temperature coefficient of resistance ( Temperature Coefficient of Resistance) can be as small as 5 ppm/° C. The length, thickness and width of the resistive element 48 can be designed for different applications. 31 1312181 ::: as shown in Figures 7a to 7c The resistive element 48' of the concept of arranging a capacitive element, wherein the resistance element is formed = 9a and the % diagram shows a cross-sectional view of the element P formed on the polymer layer in accordance with the present invention, wherein the resistive element can be The electronic contacts 16 are connected. By increasing the distance between the resistive element and the substrate (the increased distance is substantially equal to the thickness of the polymer layer 2〇), the parasitic effect of the device and the substrate can be reduced, which can improve the performance of the f-resistance element. (Because the parasitic capacitance can be reduced, it can improve the electrical performance under high frequency operation). The contacts of the resistive elements as shown in Fig. 8, Fig. 9a and Fig. 9b are connected downwards. However, the resistive element 48 can also be a top-to-bottom connection, as shown in FIG. 26, or the contacts of the resistive element 48 are connected upwards, which can be referred to as the inductive component 4 of FIG. 24b. The concept of connectivity. The other polymer layer can be selectively formed on the resistive element 48 as shown in Fig. 8, Fig. 9 and Fig. 9b, thereby protecting the resistive element 48. Referring to Figures 10 and 11, there is shown another process on the protective layer in accordance with the present invention. In this embodiment, the electronic contacts 16 can be electrically connected to the electronic components located thereon by forming bumps, such as the completed inductive components, capacitive components, resistive components, or other passive components. Sexual connection. The under bump metal 50 can be formed in the opening 32 1312181 of the polymer layer 2, wherein the opening of the polymer layer 20 is aligned with the opening of the smaller protective layer μ. Thus, the bump underlying metal 50 can be connected to the electron. Point 16 is connected for use as bump underlayer metal (UBM). The bump 52 can be formed on the under bump metal 5〇 by a conventional electro-mine process, a ball-making process, or a screen printing process, and after the flux is formed on the bump 52, the step of reflow can be performed. Next, the finished electronic component 54 can be attached to the bump 52, wherein the finished electronic component 54 has the solder 53 so that the bondability can be improved. The above process is similar to the surface bonding technique commonly used in the bonding of electronic components to printed circuit boards. The finished electronic component 54 is, for example, an inductive component, a capacitive component or a resistive component. Fig. 11 is a view showing the structure in which the completed electronic component 54 is directly formed on the protective layer 18 by using the bump 56 and the bump underlayer metal 5?. Since the completed electronic component 54 is not formed on a printed circuit board as in the prior art, the completed electronic component 54 as shown in FIGS. 10 and U has better performance and cost. not tall. The bump underlayer metal 50 may be a metal structure as shown in FIGS. 12 to 23 of the present invention. However, if gold is used as the thick metal layer, the bump underlayer metal 50 may have a thickness of 〇.1 μm. Between 2 microns and micrometers, in the preferred case, the under bump metal 50 is of a relatively thin size, so that after the fabrication of the element, the bump material near the interface of the under bump metal can be avoided. High concentration of gold. 33 1312181 The configuration of the passive components described above has at least the following advantages: 1. The passive component design by the present invention is provided because the fabricated electronic component can provide appropriate parameters and can be bonded to a location near the line in the wafer. The concept can achieve the performance of a truly systematic wafer. 2. Since the fabricated electronic component can be bonded to a position close to the line in the wafer, the occurrence of parasitic phenomena can be reduced. 3. In the present invention, since the electronic component which has been fabricated with appropriate design parameters can be selected and disposed on the protective layer, the design can reduce the domain element that has been completed and the capacitor element is completed. For the sake of clearer explanation, the following is a description of the prior art and the present invention: The prior art uses a thin metal wire to make an inductance component, and if it is to reduce the resistance effect, a wider coil must be fabricated. This will increase the surface area of the inductive component. In addition, conventional techniques have the phenomenon of parasitic electric valleys of large inductance elements, and there is a serious eddy current loss in the substrate. However, in the present invention, a thick metal layer is used as the wiring, so that the sinusoidal effect can be reduced. The material 'polymerization (4) and between the secret cultivation and the underlying structure' can reduce the parasitic effect, and the resonance frequency is increased due to the reduction of the parasitic effect, so it is suitable for the operation of the high-frequency circuit. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the scope of the present invention. The scope of the invention is defined by the scope of the patent application, which is incorporated herein by reference. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view showing the structure of a connecting line in accordance with U.S. Patent No. 6,383,916. Fig. 2 is a schematic cross-sectional view showing the formation of the inductance element of the present invention on the thick acid imide layer. Figure 3 is a top plan view of an inductive component in accordance with the present invention. Figure 4 is a schematic cross-sectional view of the wafer structure in accordance with the present invention, wherein the inductive component is axially on the thick polyimide layer and the conductive material is used to prevent the inductive component from affecting the underlying germanium substrate. Figure 5a is a schematic cross-sectional view showing the formation of an inductor element in accordance with the present invention on a protective layer. Figure 5b is a schematic cross-sectional view showing the formation of a plurality of inductive elements in accordance with the present invention on an insulating layer such as a germanium molecular polymer. Figure 5c is a top view of a plurality of inductive elements in accordance with the present invention formed on an insulating layer such as a local molecular polymer. The 6a_ shows the suspension of the product in accordance with the purchase of the insulation layer on the insulating layer such as a polymer, and the needle insulating layer remains on the protective layer. Figure 6b is a cross-sectional view of the transformer in accordance with the present invention in which the coils located below are tied to the protective layer. FIG. 6c is a schematic diagram showing the sinusoidal shape of the solenoid shape 35 1312181 according to another preferred embodiment of the present invention, wherein the electro-deployment is on the secret layer. Figure 6d depicts a perspective view of a solenoid-shaped inductive component that is not in accordance with another preferred embodiment of the present invention, wherein the inductive component remains, for example, at a high level on the protective layer. Figure 6e is a top plan view of the inductive components of Figures 6c and 6d. Stereoscopic view. Figure 6f is a schematic cross-sectional view along section line (4) in Figure 6e. The figure 6h shows the inductive component of the toroidal coil shape according to the present invention. FIG. 6h is a top view of the inductive component of the g ® T shape in the 6th diagram. Fig. 7a on the sheath shows a schematic view of the capacitor element formed in accordance with the present invention. 7bi7c is a schematic cross-sectional view showing the formation of a capacitor element according to the present invention on, for example, an insulating layer, wherein the insulating layer _ surface indicates that the aging member of the tree is formed on the edge of the rib layer. The above (4), in which the 9a and 9b are thickened, it is shown that the resistance in accordance with the present invention is as thick as the polymer, and the insulating layer is tied to the protective layer. 1312181 FIG. 10 is a cross-sectional view showing the structure of a wafer in accordance with the present invention in which an electronic component which has been fabricated is adhered to a thick insulating layer such as a high molecular polymer by surface adhesion. Figure 11 is a cross-sectional view showing the structure of a wafer in accordance with the present invention in which the fabricated electronic components are adhered to the protective layer by surface adhesion techniques. Figures I2 through I8 illustrate a cross section of a metal structure made of gold in accordance with the present invention. The metal lion of the towel is passed through an insulating layer such as a polymer. Figs. I9 to 23 show a cross section of a metal structure made of steel in accordance with the present invention, wherein the metal structure is passed through an insulating layer such as a polymer. Figures 24a through 24c illustrate another method of connecting an inductive element in accordance with the present invention. Fig. 25 and Fig. 26 respectively illustrate another method of connecting a capacitive element and a resistive element in accordance with the present invention. [Main component symbol description] 10: Semiconductor substrate 11 Transistor 12: Internal dielectric layer 13 Metal wiring 14: Metal/dielectric layer 16 Electronic contact 18: Protective layer 19 Opening 19a: Inductive element 20 Polymer layer 37 1312181 22: opening 23: via metal 25: bottom metal structure 27: top metal structure 26: metal connection line 29: first polymer layer 30: path 34: path 36: opening 36b: contact opening 38: opening 38b: Point opening 40: Inductive element 40b: Inductive element 41: Contact 42: Lower electrode 43a: Contact 44a: Conductive sheet 46: Dielectric layer 48: Resistive element 52: Bump 20a: Polymer block 23a: Via metal 25a : bottom metal structure 27a: top metal structure 28: metal connection line 22: opening 32: path 35: polymer layer 36a: contact opening 37: opening 38a: contact opening 39: contact 40a: inductive element 40c: inductive element 41a: Contact 43: Contact 44: Conductor 45: Upper electrode 47: Polymer layer 50: Bump underlayer Metal 53: Solder 1312181 54: Finished electronic component 56: Bump 60 · Bottom coil 62: Upper layer Coil 64: polymer layer 66 : Opening 68 · Inductive element 80: Substrate 81: Metal contact 82: Opening 84: Protective layer 85: Side wall 86: Polymer layer 87: Opening 88: Adhesive/barrier layer 89: Extension line 90: Seed layer 92 Thick metal layer 94: photoresist 94a: photoresist 95: photoresist 95a: photoresist 100: adhesion/barrier layer 102: seed layer 106: metal top layer 104: thick metal layer 39