TWI309868B - The method for testing wafer - Google Patents

Description

1309868 _案號91138172_^年3月曰 修正_ 五、發明說明（1) (一） 、[發明所屬之技術領域】 本發明係關於一種半導體晶圓的測試方法，特別有關 於一種分割後之晶圓的測試方法。 (二） 、【先前技術】 . 半導體積體電路的製造需要多個製程，包含設計、製 造、封裝以及測試。一般而言，測試可分成功能性 (functional)、參數性（parametric)以及燒機（老化 測試）（burn-in)等方法。在這些方法中，該半導體元件可 能以晶圓、晶片或封裝構造的型態測試。雖然封裝係為一 個相對而言較昂貴的步驟，但是半導體製造業者仍經常在 封裝之後（也就是擔保半導體元件具有合適性質和功能之 前）才進行測試。隨著半導體元件的結構日趨複雜化，迫 使製造業者必須在封裝製程之前對晶圓型態或晶片型態的 元件進行測試，如此一來，才能降低封裝到無法正常操作 之元件的可能。此外，隨著多晶片封裝構造的出現，由於 每一半導體裝置僅為多個設置在多晶片承載件上的其中之 一晶片，卻可能因這其中之一有損壞而使整個模組無法正 常操作而遭到淘汰，大大地廉費製造成本，因此晶片或晶 圓尺寸的測試在此更為必要。 一般而言，積體電路係被製造於一半導體晶圓上，每 一個晶圓一般而言包含5 0到1 0 0 0個獨立的積體電路。晶圓 上之積體電路之間係被稱為道標（street indices)的空 間，將獨立的積體電路分隔開。然後在一個分割的製程1309868 _ Case No. 91138172_^年月月曰曰Amendment_5. Description of the invention (1) (1) [Technical field of invention] The present invention relates to a method for testing a semiconductor wafer, and more particularly to a segmented crystal Round test method. (2) [Previous Technology] The manufacture of semiconductor integrated circuits requires multiple processes, including design, fabrication, packaging, and testing. In general, testing can be divided into methods such as functional, parametric, and burn-in. In these methods, the semiconductor component may be tested in the form of a wafer, wafer or package construction. Although packaging is a relatively expensive step, semiconductor manufacturers often test after packaging (that is, before securing semiconductor components with appropriate properties and functionality). As the structure of semiconductor components becomes more complex, manufacturers are forced to test wafer-type or wafer-type components before the packaging process, thus reducing the possibility of packaging components that are not functioning properly. In addition, with the advent of multi-chip package construction, since each semiconductor device is only one of a plurality of wafers disposed on the multi-wafer carrier, the entire module may not operate properly due to damage of one of the devices. However, it has been eliminated and the cost of manufacturing is greatly reduced. Therefore, wafer or wafer size testing is more necessary here. In general, integrated circuits are fabricated on a semiconductor wafer, and each wafer typically contains 50 to 1 000 integrated integrated circuits. The integrated circuits on the wafer are referred to as spaces of street indices, separating the separate integrated circuits. Then in a split process

^09868 _#號 9113817? 發明說明（2)^09868 _#号 9113817? Description of the invention (2)

五 I!多：Π道標分割晶圓，分離晶圓上的獨立積體電路形 I 日日片。而晶圓上的獨立積體電路係以陣列的方 < 替 ㈣分:布：便於以系列的方式加以測試，因此 | -人的測试能降低測試的時間以及花費。 曰 然而，現行之晶圓測試係在前述分割製程前進行，1 係利用整個晶圓之中心為準，以定位各個晶片。惟，二 割製程後得到的晶片座標與原來未分割前之座標有些微2 莫，故在測試過程中造成很大困擾，使得晶圓上之部分待 測晶片無法與測試機台的連接接點精確對齊，而無法正_ |地測試該晶片。 請參考圖1’其係為一典型之半導體晶圓之局部放大 圖。該半導體晶圓1 〇 〇主要包含有複數個陣列排列之曰 102’其係由複數個道標104( street index)所區隔0曰， 一晶片1 0 2上具有複數個接點丨〇 6。圖2則是圖^之 曰 圓1 0 0經分割後之上視圖。 曰曰 一般而言，晶圓的分割製程係將待分割之晶圓ι〇〇設 置在一膠帶1〇8(如圖3所示）上，並將該膠帶固定於 〆晶圓架（waf er fraffle)中央開口處，再將該晶圓架固 ^妾於一分割機器，以刀具沿著晶圓上之道標1〇4分割（如 圖1所示），以侍到複數個獨立的晶片1〇2 (如圖2所 示）。雖然該晶圓1〇〇已被分割成複數個獨立的晶片1〇2, 惟仍黏接在膠=上。8上，故仍保持原來陣列式的分佈。.然 丨而經過刀具分利後’複數個晶片1〇2各自有不同程度的位 置戒角度偏移’使得晶片102間不再具有分割前之規則平Five I! Multi: The wafer is divided into wafers, and the independent integrated circuit on the wafer is separated. The independent integrated circuit on the wafer is in the square of the array. (4): cloth: It is easy to test in a series, so the human test can reduce the test time and cost.曰 However, current wafer testing is performed prior to the aforementioned singulation process, and 1 is based on the center of the entire wafer to locate individual wafers. However, the wafer coordinates obtained after the two-cut process are slightly different from those of the original undivided, which causes great trouble in the test process, so that some of the wafers to be tested on the wafer cannot be connected to the test machine. Exact alignment, and the wafer cannot be tested. Please refer to FIG. 1' which is a partial enlarged view of a typical semiconductor wafer. The semiconductor wafer 1 〇 〇 mainly includes a plurality of array arrays ’ 102 ′ which are separated by a plurality of track indexes 104 ( street index), and a wafer 1 0 2 has a plurality of contacts 丨〇 6 . Figure 2 is a top view of the circle after the division of the circle 1 0.曰曰 In general, the wafer singulation process is to set the wafer to be divided on a tape 1 〇 8 (as shown in FIG. 3 ), and fix the tape on the 〆 wafer holder (waf er Fraffle) at the central opening, the wafer holder is fixed to a split machine, and the tool is divided along the track on the wafer by 1〇4 (as shown in Figure 1) to serve a plurality of independent wafers 1 〇 2 (as shown in Figure 2). Although the wafer has been divided into a plurality of individual wafers 1〇2, it is still bonded to the glue=. 8, so the original array distribution is still maintained. However, after the tool is divided, the plurality of wafers 1〇2 each have different degrees of position or angular offset, so that the wafers 102 no longer have the rule before the division.

第9 i 1309868 _案號91138172_年3月曰 修正_ 五、發明說明（3) 行的相對位置關係，而造成測試時定位晶片的困擾。 因此需要一種測試方法用以克服或至少改善上述問 題。 (三）、【發明概要】 - 有鑑於上述課題，本發明之目的係提供一種測試分割 後之晶圓的方法，能克服或改善分割製程造成的晶片位移 "問題，以降低整體測試的時間以及花費。 緣是，為了達成上述目的，本發明提供一種測試方 法，用以測試分割後之晶圓，該晶圓包含複數個陣列排列 之晶片，每一個晶片具有複數個接點。該方法包含以下步 驟。首先，利用一個.影像系統拍攝下前述之多個晶片之一 的影像。再將該影像與一預先設定之樣版比對，藉此得到 該晶片的座標，並根據該晶片的座標放置一檢測器之連接 接點，使該檢測器之連接接點與該晶片的接點電性連接。 同時，對該晶圓之另一晶片重複拍攝、比對以及測試的步 驟，以此類推，直到該晶圓上的晶片都被測試完為止。其 中’該比對步驟所得之座標係包含§亥晶片在5亥晶圓被測表 面上之X軸座標、Y軸座標，以及該晶片相對於垂直該晶圓 被測表面之Z軸的旋轉角度。 承上所述，依本發明所提供之測試方法，除可兼顧晶 圓層次測試的特性，以系列的方式測試一晶圓上所有晶 片，又能具有晶片層次偵測的特性，確認每一晶片是否為 可正常操作的晶片，以得到已知良好晶片（Known Good9th i 1309868 _ Case No. 91138172_ March 曰 Correction _ V. Invention Description (3) The relative positional relationship of the rows, causing troubles in locating the wafer during testing. There is therefore a need for a test method to overcome or at least ameliorate the above problems. (III) [Summary of the Invention] - In view of the above problems, an object of the present invention is to provide a method for testing a wafer after division, which can overcome or improve the wafer displacement caused by the division process to reduce the overall test time. And the cost. Accordingly, in order to achieve the above object, the present invention provides a test method for testing a wafer after dicing, the wafer comprising a plurality of arrays of wafers, each wafer having a plurality of contacts. The method includes the following steps. First, an image of one of the plurality of wafers described above is taken using an image system. And comparing the image with a preset pattern, thereby obtaining a coordinate of the wafer, and placing a connection connection of the detector according to the coordinates of the wafer, so that the connection point of the detector is connected to the wafer Electrical connection. At the same time, the other wafers of the wafer are repeatedly photographed, aligned, and tested, and so on, until the wafers on the wafer are tested. The coordinate obtained by the comparison step includes the X-axis coordinate, the Y-axis coordinate of the WI-ray on the surface to be measured of the 5 liter wafer, and the rotation angle of the wafer relative to the Z-axis perpendicular to the surface to be measured of the wafer. . According to the above test method, in addition to the characteristics of the wafer level test, all the wafers on a wafer can be tested in a series manner, and the characteristics of the wafer level detection can be confirmed to confirm each wafer. Whether it is a normal operation of the wafer to get a known good wafer (Known Good

第10頁 1309868 _案號91138172_Tf年3月ίΐ曰 修正_ 五、發明說明（4)Page 10 1309868 _ Case No. 91138172_Tf Year March ΐ曰 Correction _ V. Invention Description (4)

Die， KGD)。 (四）、【實施方式】 以下將參照相關圖式，說明依本發明較佳實施例之晶 圓測試方法。 . 如圖4所示，本發明提供之測試方法包含以下步驟。 首先，提供一影像系統2 1 0 ( v i s i οn s y s ΐ em)，例如一電 掎耦合裝置（CCD)，用以得到待測晶片202之影像。另 夕卜，提供一檢測器2 1 2，如經常用於晶圓級測試系統 (wafer level testing system)之偵測卡(probe card)。該偵測卡包含複數個針狀連接接點2 1 4用以與被 測晶片2 0 2之複數個接點2 0 6產生暫時性電性連接。 接著，選擇欲測之晶片2 0 2，利用影像系統2 1 0拍攝下 該晶片2 0 2之影像。根據本發明之一實施例，該影像會被 傳送至一處理系統（未示於圖中），該處理系統包含一預 '先設定之樣版，該樣版係包含晶片2 0 2的邊界以及其上接 .點2 0 6之相對位置等資訊，經由比對影像與樣版，使該處 理系統得到該晶片2 0 2之準確座標，其包含該晶片2 0 2在該 晶圓被測表面上之X轴座標、Y轴座標，以及該晶片相對於 _垂直該晶圓被測表面之Z軸的旋轉角。 再者，如圖5所示，該檢測器2 1 2接著沿該晶圓被測表 面為準之Γ， Y軸移動，以移動到待測晶片2 0 2的上方，再 以+ Z轴為準而轉動作角度調整，補償晶片2 0 2在角度上 (Θ )的偏移，使得檢測器2 1 2的之連接接點2 1 4能準確地Die, KGD). (4) [Embodiment] A crystal circle test method according to a preferred embodiment of the present invention will be described below with reference to the related drawings. As shown in FIG. 4, the test method provided by the present invention comprises the following steps. First, an image system 2 1 0 ( v i s i οn s y s ΐ em), such as an electrical coupling device (CCD), is provided for obtaining an image of the wafer 202 to be tested. In addition, a detector 2 1 2 is provided, such as a probe card that is often used in a wafer level testing system. The detection card includes a plurality of pin-shaped connection contacts 2 1 4 for temporarily electrically connecting with a plurality of contacts 2 0 6 of the test wafer 2 0 2 . Next, the wafer 2 0 2 to be tested is selected, and the image of the wafer 2 0 2 is captured by the image system 2 10 . In accordance with an embodiment of the present invention, the image is transmitted to a processing system (not shown) that includes a pre-set pattern that includes the boundaries of the wafer 202 and The information is obtained by comparing the relative position of the point 206 to the image and the pattern, so that the processing system obtains the exact coordinates of the wafer 202, which includes the wafer 2 0 2 on the surface to be tested. The upper X-axis coordinate, the Y-axis coordinate, and the rotation angle of the wafer relative to the Z-axis of the wafer to be measured surface. Furthermore, as shown in FIG. 5, the detector 2 1 2 is then moved along the surface to be measured of the wafer, and the Y axis is moved to move above the wafer 2 0 2 to be tested, and then the + Z axis is The rotation angle adjustment is made to compensate the offset of the wafer 2 0 2 in the angle (Θ), so that the connection junction 2 1 4 of the detector 2 1 2 can accurately

第11頁 1309868 案號 91138172Page 11 1309868 Case No. 91138172

五、發明說明（5) 對準待測晶片2 0 2的接點2 0 6 ’再將檢測器21 ^ 7站罢1 ^檢测器212之連接接點晴晶請2的接點二電， 接，以執行檢測。 運 至與 203 處理 惟對晶片2 0 2進行檢測之同時，影像系統2丨〇係移 晶片20 2相鄰之另一晶片20 3之上方，以進行待測晶片 之影像擷取步驟，並進行與樣版之比對步驟，以使該 系統得到該晶片2 0 3之準確座標。 ' 承上所述，當晶片2 0 2之檢测步驟完成後，將檢測器 21 2從晶月2〇2移開至，晶片2 0 3以進行電性連接檢測步驟^ 同時，影像系統2 1 0係從晶片2 0 3移至晶片2 0 5之上方，以 進行待測晶片2 0 5之影像擷取步驟，並進行與樣版之比對 步驟，以使該處理系統得到晶片2 0 5之準確座標。以此類 推，重覆上述所有步驟，直到該晶圓上的晶片都被測試完 為止° .根據本發明另一實施例’該晶圓係置放於一晶圓台 上，該晶圓台包含—Χ〜γ轴方向調整之工作台、一 Ζ軸以及 Θ角之移動機制、以及—個晶圓支撐桌面依序設置於一個 .主要台座上。當檢測時’該晶圓被固定在該晶圓台上。該 晶圓台可藉由Ζ袖以及0角之移動機制垂直移動以及旋轉該 晶圓，並tr藉由χ_γ軸方向調整之工作台水平移動該晶 圓，以達成上述使檢測器2 1 2之連接接點2 1 4與晶片2 0 2的 接點2 0 6對準益產生電性連接的步驟。- 由上述玎知’本發明係提供一種晶圓级的測試方法， 用以至少改善晶圓在分割後因晶片產生位移而造成的定位V. Description of the invention (5) Align the contact of the wafer to be tested 2 0 2 2 0 6 ' and then the detector 21 ^ 7 stop 1 ^ The connection of the detector 212 The contact point of the crystal clear 2 , pick up to perform the test. The image system 2 is moved over the other wafer 20 3 adjacent to the wafer 20 2 to perform the image capturing step of the wafer to be tested, and is performed. The step of comparing the patterns to the system to obtain the exact coordinates of the wafer 302. As described above, after the detection step of the wafer 220 is completed, the detector 21 2 is removed from the crystal moon 2〇2, and the wafer 2 0 3 is electrically connected to the detection step. Meanwhile, the image system 2 10 is moved from the wafer 203 to the top of the wafer 205 to perform an image capturing step of the wafer to be tested 205, and a comparison step with the pattern is performed to enable the processing system to obtain the wafer 2 0 The exact coordinates of 5. By analogy, all the above steps are repeated until the wafer on the wafer is tested. According to another embodiment of the present invention, the wafer is placed on a wafer stage, the wafer stage includes - The movement mechanism of the Χ-γ axis direction adjustment table, the one axis and the corner angle, and the wafer support table are sequentially arranged on one main pedestal. When detected, the wafer is fixed on the wafer stage. The wafer stage can vertically move and rotate the wafer by the movement mechanism of the sleeve and the 0 corner, and the wafer is horizontally moved by the table adjusted by the χγ axis direction to achieve the above-mentioned detector 2 1 2 The step of connecting the contacts 2 1 4 to the contacts 2 0 6 of the wafer 2 0 2 creates an electrical connection. - From the above, the present invention provides a wafer level test method for at least improving the positioning of the wafer due to displacement of the wafer after the division.

第12頁 1309868 案號 91138172Page 12 1309868 Case No. 91138172

Tf年3月日 修正 五、發明說明（6) 問題。此方法不單適用於測試裸晶圓（bare wafer)，亦 適用於測試已經突塊化之晶圓（如圖6所示），使檢測器 2 1 2之連接接點2 1 4能順利與分割後之突塊化晶圓的突塊接 點2 1 6發生暫時性的電性連接，以使通過此測試製程之突 塊化晶 便能立刻與基板或其他結構結合。 . 此外，為配合晶片接點的高密度以及微小尺寸，用於 檢測晶片的檢測器必須極為精密，因此價格也十分昂貴， 会是其中有一個連接接點有損壞，則難以修復而需要整個 淘汰。在突塊化晶圓或晶片的過程中’有時會有兩個突塊 接點在形成時融合而形成一個大球2 1 8的情況（如圖6的晶 片2 0 3)此時若沒有提供一個檢測出大球的機制，則偵測 這一個晶片2 0 3時，檢測器的連接接點易被大球折斷，而 造成成本的損失並影響其他晶片的測試可靠性。因此本發 明亦提供一種機制能在比對的步驟中檢測出具有不正常之 突塊接點（例如大球）的晶片’並自動跳過§亥晶片不加以 偵測，以避免損壞價格昂貴的檢測器。 曰曰 綜上所述，本發明提供之測試方法除可克服分割後之 上晶片的定位問題，又可兼顧晶圓層次測試的特性， 更具有晶片級偵測的特性，故可以系列的方式測試一分割 曰-曰圓上所有晶片，直接確認每一晶片是否為可正常操作的 日"曰片，以得到已知良好晶片（Known Good Die， KGD) ’ 省去將一個一個獨立晶片分別送入測試機台的步驟，而達 到降低整體測試的時間以及花費的目的。 於本實施例之詳細說明中所提出之具體的實施例僅為March of the Tf Year Amendment V. Invention Description (6) Question. This method is not only suitable for testing bare wafers, but also for testing wafers that have been bumped (as shown in Figure 6), so that the connection junction 2 1 4 of the detector 2 1 2 can be smoothly and divided. The bump contacts 2 16 of the subsequent bumped wafer are temporarily electrically connected so that the bumps passing through the test process can be immediately bonded to the substrate or other structures. In addition, in order to match the high density and small size of the wafer contacts, the detector for detecting the wafer must be extremely precise, so the price is also very expensive, and if one of the connection contacts is damaged, it is difficult to repair and needs to be completely eliminated. . In the process of bumping a wafer or wafer, there are occasions when two bump contacts are merged to form a large ball 2 18 (as shown in wafer 6 of Figure 6). Providing a mechanism for detecting a large ball, when detecting the wafer 2 0 3 , the connection contact of the detector is easily broken by the large ball, which causes cost loss and affects the test reliability of other wafers. Therefore, the present invention also provides a mechanism for detecting a wafer having an abnormal bump contact (for example, a large ball) in the step of comparison and automatically skipping the detection of the wafer without Detecting the damage to avoid expensive damage. Detector. In summary, the test method provided by the present invention can overcome the positioning problem of the wafer after the division, and can also take into consideration the characteristics of the wafer level test, and has the characteristics of wafer level detection, so it can be tested in a series manner. Divide all the wafers on the 曰-曰 circle and directly confirm whether each wafer is a normal operating day" 曰片 to get a known good wafer (KGD)'. Save one separate wafer. Enter the steps of the test machine to achieve the purpose of reducing the overall test time and cost. The specific embodiments set forth in the detailed description of this embodiment are only

第13頁 1309868 案號 91138172 年 月 Π 修正 五、發明說明（7) 了易於說明本發明之技術内容，而並非將本發明狹義地限 制於該實施例，因此，在不超出本發明之精神及以下申請 專利範圍之情況，可作種種變化實施。Page 13 1309868 Case No. 91138172 Π Revision 5, Invention Description (7) The technical content of the present invention is easily described, and the present invention is not limited to the embodiment, and therefore, without departing from the spirit of the present invention, The scope of the following patent application can be implemented in various variations.

第14頁 1309868 _案號91138172_^年3月η曰 修正_ 圖式簡單說明 (五）、【圖式之簡單說明】 圖1為一示意圖，顯示未分割半導體晶圓的局部放大 上視圖； 圖2為一示意圖，顯示半導體晶圓經分割後之上視圖； 圖3為一示意圖，顯示習知之分割後半導體晶圓上之 晶片的主要測试步驟； 圖4為一示意圖，顯示根據本發明之一實施例，以剖 糸圖圖示測試第2圖分割後半導體晶圓上之晶片的主要步 驟； 圖5為一示意圖，顯示根據本發明之一實施例，以立 體圖圖示調整檢測器使檢測器與待測晶片對準之步驟；以 及 圖6為一示意圖，顯示根據本發明之另一實施例之突 塊化晶片剖面圖。 '元件符號說明： 1 0 0半導體晶圓 Υ1 0 2晶片 1 0 3晶片 ' 1 0 4道標 1 0 5晶片 1 0 β接點 10 8膠帶 1 1 2檢測器Page 14 1309868 _ Case No. 91138172_^ March η曰 Correction _ Simple description of the diagram (5), [Simple description of the diagram] Figure 1 is a schematic diagram showing a partial enlarged top view of the undivided semiconductor wafer; 2 is a schematic view showing a top view of the semiconductor wafer after being divided; FIG. 3 is a schematic view showing the main test steps of the wafer on the semiconductor wafer after the conventional division; FIG. 4 is a schematic view showing the image according to the present invention. In one embodiment, the main steps of testing the wafer on the semiconductor wafer after division in FIG. 2 are illustrated in a cross-sectional view. FIG. 5 is a schematic diagram showing the adjustment of the detector in a perspective view according to an embodiment of the present invention. Step of aligning the device with the wafer to be tested; and FIG. 6 is a schematic view showing a cross-sectional view of the bumped wafer according to another embodiment of the present invention. 'Component Symbol Description: 1 0 0 Semiconductor Wafer Υ 1 0 2 Wafer 1 0 3 Wafer ' 1 0 4 Mark 1 0 5 Wafer 1 0 β Contact 10 8 Tape 1 1 2 Detector

第15頁 1309868 案號 91138172 修正 圖式簡單說明 1 1 4連接接點 2 0 2晶片 2 0 3晶片 2 0 5晶片 2 0 6接點 _2 0 8膠帶 2 1 0影像系統 ^ 1 2檢測器 2 1 4連接接點 2 1 6突塊接點 2 1 8大球’Page 15 1309868 Case No. 91138172 Correction of the simplified diagram 1 1 4 connection contact 2 0 2 wafer 2 0 3 wafer 2 0 5 wafer 2 0 6 contact_2 0 8 tape 2 1 0 imaging system ^ 1 2 detector 2 1 4 connection contact 2 1 6 projection contact 2 1 8 big ball'

第16頁Page 16

Claims (1)

1309868 _案號91138172_竹年3月曰 修正_ 六、申請專利範圍 1 . 一種晶圓測試方法，包含下列步驟： a) 提供一分割過之晶圓，該晶圓係包含複數個陣列排列 之晶片，該等晶片係具有複數個接點； b) 提供一影像系統（v i s i ο n s y s ΐ e m)以及一檢測器 .(prober)，該檢測器具有複數個連接接點； .c)利用該影像系統拍攝下該等待測晶片之一的影像； d)將該等待測晶片之一的影像與一預先設定之樣版比 ' 對，藉此得到該待測晶月之座標； e )依據該待測晶片之座標以放置該檢測器之連接接點，使 該檢測器之連接接點與該待測晶片的接點電性連接； 〇在步驟e )進行的同時，該影像系統並對該晶圓下一個待 測晶片進行拍攝，以及 g)對該晶圓之下一個待測晶片重複步驟d)至步驟f)。 y 2.依申請專利範圍第1項之晶圓測試方法，其中該晶片之 接點係為突塊接點。 3 .依申請專利範圍第2項之晶圓測試方法，另包含下列步 I 驟： •提供該預先設定之樣版上突塊接點的預先設定尺寸；以及 在步驟I d)之比對動作中，當任一晶片之突塊接點尺寸與 該突塊接點預先設定尺寸的偏差大於一預先設定可容許 偏差值，則停止對該待測晶片之測試，並跳離到下一晶 片01309868 _ Case No. 91138172_Year of March 曰 Amendment _ VI. Patent Application Scope 1. A wafer testing method comprising the following steps: a) providing a divided wafer, the wafer comprising a plurality of arrays arranged a wafer having a plurality of contacts; b) providing an image system (visi ο nsys ΐ em) and a detector (prober) having a plurality of connection contacts; c) utilizing the image The system captures an image of one of the waiting wafers; d) comparing the image of one of the waiting wafers with a predetermined pattern to obtain a coordinate of the crystal moon to be tested; e) according to the Measuring the coordinates of the wafer to place the connection contact of the detector, so that the connection contact of the detector is electrically connected to the contact of the wafer to be tested; 〇 while the step e) is performed, the image system and the crystal Round the next wafer to be tested for shooting, and g) repeat steps d) to f) for the wafer under test on the wafer. y 2. The wafer test method according to claim 1 of the patent application, wherein the contact of the wafer is a bump contact. 3. The wafer test method according to item 2 of the patent application scope, further comprising the following steps: • providing a preset size of the bump contact on the preset pattern; and comparing the actions in step I d) When the deviation of the bump contact size of any of the wafers and the pre-set size of the bump contacts is greater than a predetermined allowable deviation value, the test of the wafer to be tested is stopped, and the next wafer is skipped. 第17頁 1309868 _案號91138172 年3月丨7曰 修正_ 六、申請專利範圍 4 .依申請專利範圍第1項之晶圓測試方法，其中該步驟d) 所得之座標係包含該晶片在該晶圓被測表面上之X軸座 標、Y軸座標，以及該晶片相對於垂直該晶圓被測表面之Z 軸的旋轉角度。Page 17 1309868 _ Case No. 91138172 March 丨 7曰 Amendment _ VI. Patent Application No. 4. According to the wafer test method of claim 1, wherein the coordinates obtained in the step d) include the wafer in the The X-axis coordinate, the Y-axis coordinate on the surface to be tested on the wafer, and the angle of rotation of the wafer relative to the Z-axis perpendicular to the surface to be measured of the wafer. 第18頁Page 18