TWI309076B - Semiconductor device and method for manufacturing the same - Google Patents

Description

1309076 九、發明說明： 【發明所屬之技術領域】 本發明關於一種半導體元件及其A 垂直電晶體之半導體元件及其製造方…、疋一種具有 【先前技術】 亦不= 之改良’半導體元件内部之特徵尺寸 =部之通道長】=密 具有決定性之影響。此外，料·心^70仵歧及其尺寸 微 而 ，程技術的演進而下降，然 ί=ΐΓΐ；ιΓ=^制部之通道“過短:造成記 ϊ = 產生位元㈣寫人與讀取間之錯 使得記憶體元件内“ί不件内部之漏電流’ 此在製程微縮之趨勢下存資料容易流失。因 物、電性實屬必然 件結構來達成半導體元件所需的 件操效體::牛積集度之前提下，仍维持足夠之元 立體空間。b從而發展出便由二度橫向空_向三度 體元件，以有效提高元;^積=曰。曰體(verticai 丁麵論)之記憶 1309076 然而，目前已知以垂直電晶體方式設計之記憶體元件，仍有 改善的^間。例如’源/汲極區域間仍以部份空乏(Partially Depleted) =方式操作，因此仍存在高接合漏電(juncti〇n Leakage)及高接合電 合(Junction Capacitance)問題。此外，習知垂直電晶體另有浮體效 應(Floating Boy Effect)之問題。所謂浮體效應，係指因通道區域 ^累積過多電荷，而降低元件操作電壓，影響元件操作效能之效 應。凡此種種，均有待解決。 因此，一種可免除浮體效應，甚至可以完全空乏方式操作之 ίίΪί體，便為此料所亟需’以於符合元件積集度之需求下， 仍維持甚至提升元件之操作效能。 【發明内容】 溝準ΐΪϊϋΐίΪί—種半導體元件’其包含—基材；一 二第於該溝渠電容器上方，覆蓋 直電晶體，包含一閘極結構、-上源/汲極、- 織極’其巾’該下源/祕係與該上電極接觸並 區係位於該上源/沒極與該下獅： 且位於該閘極結構與該第二介電層之間。 心门1309076 IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor element and a semiconductor device of the same for a vertical transistor, and a method for manufacturing the same, and an improved semiconductor device having the prior art The feature size = the channel length of the section] = density has a decisive influence. In addition, the material and heart ^70 仵 及其 and its size is small, the evolution of the process technology has declined, but ί = ΐΓΐ; ιΓ = ^ channel of the Ministry of "too short: caused by the record = generate bits (four) write and read The mistake of taking the memory makes the internal leakage of the internal components of the memory component. This is easy to lose data under the trend of miniaturization of the process. Because the material and electrical properties are inevitable structures to achieve the ergonomics required for the semiconductor components:: Before the cattle accumulation, it is still sufficient to maintain a sufficient dimensional space. b thus develops a second horizontal _ to three-dimensional body element to effectively improve the element; ^ product = 曰. Memory of the corpus callosum (verticai) 1.309076 However, there are still known improvements in memory elements designed in a vertical transistor. For example, the 'source/drainage regions are still operated in a partially depleted mode, so there are still problems with high junction leakage (juncti〇n Leakage) and high junction capacitance (Junction Capacitance). In addition, conventional vertical transistors have problems with the Floating Boy Effect. The so-called floating body effect refers to the effect of reducing the operating voltage of the component and affecting the operational efficiency of the component due to the accumulation of excessive charge in the channel region. All of these have to be resolved. Therefore, an operation that can eliminate the floating body effect and even operate in a completely depleted manner is urgently needed for the purpose of satisfying the component accumulation degree, and still maintains or even improves the operational performance of the component. SUMMARY OF THE INVENTION A semiconductor device includes a substrate; a second layer over the trench capacitor, covering a straight transistor, including a gate structure, - an upper source/drain, a - The underlying source/secret is in contact with the upper electrode and is located between the upper source/no pole and the lower lion: and between the gate structure and the second dielectric layer. Heart gate

含：之t目的係提供—製造半導體元件之方法，其包 =於該縣結構巾，該_結構成H I源歲極於該溝渠結構外且_亥形成一 成-第二導電層，的笛一驗*電層之該基材中；（d)形 二導電層係、與該下源/^極接觸；（===成—上電極，且該第 極；（f)去除部分該基材，以二)|電減蓋該上電 1309076 =; (g)去除部分該第二介電層，露攸環狀結構之—上部 摻雜賊上部輯，射，該上綠_位於該下 ^、/極上方，且於該上源/汲極與下源/汲極之間係存在一 ϋί目)雛結構’其係與魏道區相鄰且位於該第二介電 —情形下==積甚體至電 垂直電晶體之半導體元件，複數個; 該等半導懸元件係排 列方t ‘$—了列方向。該第二行列方向係正交於該 白且於同-行列上相鄰交會點係實質上相 陣列3體tt明^又一目的，係提供一種包含一4F2半導體元件 垂直;;該積體電路元件係包含複數個卿^ 。此外，各該 且各該位雄3接辭導體树找_結構， 沒極。财接料—仃财向上各辭導航件之該上源/ 之積體Ζ供-種包含-3,5F2半導體元件陣列 電晶體之丰·、二，70件係包含複數個上述具特殊垂直 以及複數個平行 第一 第一行 隔2個最小微影 線。其Ϊ半體複J:固平行字元線，以及複數;平行位元 第一行列件係排列為一跳棋棋盤陣列’該障 該陣列具 上相隔2個最小微影單位If·，：·行列上相鄰交會點係實質 交會點上。此外，各玆定_各5亥半導體兀件僅出現於該陣列之 體元件之該間極結構Ϊ且連接該第—行列方向上各該半導 稱且各該位4線係正交於該第-行列方向， 1309076 連接之-半導體元件之位置’ 娜月之另一目的’係提供一種包含一沈2半導體元件陣列之 體之件。該積體電路元件包含複數個上述具特殊垂晶 其中體複行字元線’以及複數個平行位元線曰: —弟一仃歹丨方向、一第二行列方向與一第四行列方命。兮势 二行列方向’並與該第三行列方向間具二5。 =現於該第一行列方向上與該第二行列方向上之以ϋ 亍列方向上與該第二行列方向上相鄰交會 暂 2;個最小微料位。此外，各該字元線錢接該第^ = 各該半導體树之該祕結構，且各該 ^ 向上 方向上各該半導體元件之該上源/難。線係連接該弟四行列 為讓本發明之上述目的、技術特徵 下文係以較佳實施例配合所附圖式進行明 隨後描述之實施方式後，本發明所屬技術領域中罝 當可輕易瞭解本發明之基本精神及其他^目知識者 採用之技術手段與較佳實施態樣。、 、’Μ及本發明所 【實施方式】 凊參閱第1圖，所示係本發明一半導妒 1 10,1 ° 以及-垂直電晶體40。為簡單說明起見 層30 電容結構。 圖僅顯不一部份之 如第1圖所示，電容器20係位於基 2卜-上電極22及—第—介電層23。H包含一下電極 導電層24與第二導電修且第-介電層23:^ 1309076 =22之間。第二介電層3G則位於電容ii 2G上方而覆蓋之 直電晶體40包含一閘極結構4卜一上源級極42、一通道區 中，下職極44係與上電極22之第二導 ^層25接觸並與基材1〇相連，通道區43位於上源/沒極幻 源/沒極44之間，且位於閘極結構41與第二介電層如之間；、 第2圖顯示使用半導體元件！之一實施態樣，作為一記， 例如，動態隨機存取記憶體(DRAM)。其中，基材1〇係一砍^ :電極21包含一位於基材10中之一離子摻雜區域211以二 212、’舉例言之（但不以此為限）’離子摻雜區域211可摻雜 一子’導電層212可為鈦/氣化鈦層。第一介電層23可為三氧化 ^銘（ai2o—3)層，至於上電極22之第一/第二導電層24/25，較佳 各自為一複合層，分別包含一氮化鈦層241/251與一多 垂直電晶體40之上源/沒極42、通道區43、以及下源/汲極44 ^上下垂直堆疊而位於—連續表面。其中，下源級極44係自基材 伸而出。此外，上源/汲極42、通道區43、以友下源/汲極44 連續表面，係沿溝渠側壁向上延伸，而圍繞該電容器2〇之 二部分…般而言’該連續表面可實質上環繞該麟側壁周長之 1M 至 2/3。 於一具體實施態樣中，係以下源/汲極44為源極，以上源/汲 ^ 42為/及極。第二介電層30則包含一氧化層31、一氧化層32， 列言之（但不以此為限），氧化層32可由四乙基酸正矽酸鹽 (TEOS)與臭氧(〇z〇ne)反應而成。 #曰ΐ一較佳實施例中，電容器20係位於一圓柱形溝渠中。垂直 4〇之上源/没極42、通道區43以及下源/没極44係構成一 、、t、、#:構5〇之一第一部分51(請參閱第26Β圖）。環狀結構50係 渠側壁向上延伸而環繞第二介電層30以及電容器20之上部 歹士上電極22之第二導電層25)，且另包含一由未經摻雜之石夕 1309076 之第二部份52 °其中’第—部份51係占環狀結構50 i接^ 舉例言之（但不以此為限），第一部份51可占環狀 t1/2。此外’第一部分51與第二部份52之厚度係5〇至 4100至200埃（如：150埃）。未經摻雜之石夕基材 1 :成第—部份52，可免除垂直電晶體40於操作時產生之浮體 效應。The purpose of providing: is to provide a method for manufacturing a semiconductor component, and the package is a structure towel of the county, and the structure is a HF source that is outside the structure of the trench and forms a scatter of the second conductive layer. (d) forming a second conductive layer in contact with the lower source/electrode; (=== into-upper electrode, and the first pole; (f) removing a portion of the base Material, to the second)|electrical reduction cover, the power-on 1309076 =; (g) remove part of the second dielectric layer, the top of the exposed ring structure - the upper doped thief upper part, shoot, the upper green _ is located under ^, / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / = a plurality of semiconductor components that are integrated into an electrical vertical transistor; the semi-conductive suspension elements are arranged in a direction t '$ - column direction. The second row and column direction is orthogonal to the white and the adjacent intersection point on the same-row column is substantially the same as the phase array 3 body, and further provides a semiconductor element comprising a 4F2 vertical; the integrated circuit The component system contains a plurality of clerk ^. In addition, each of these and each of the three male conductor trees is looking for a structure, which is infinite. The financial materials - the financial resources of the above-mentioned navigation source, the upper source / the integrated body - the type of -3,5F2 semiconductor device array transistor, the second, the 70-piece system contains a plurality of the above-mentioned special vertical and A plurality of parallel first first lines are separated by two minimum tilapia lines. The Ϊ half body complex J: solid parallel word line, and the plural; the first row of parallel elements is arranged as a checkerboard array. The barrier has two minimum lithographic units If·,: The upper adjacent intersection is at the physical intersection. In addition, each of the semiconductor elements of the array is only present in the interpole structure of the body elements of the array, and the semi-derivatives are connected in the direction of the first row and the row, and each of the four lines is orthogonal to the The direction of the first row and the row, 1309076 connected to the position of the semiconductor element 'the other purpose of 'na month' provides a member comprising a body of a sinking 2 semiconductor element array. The integrated circuit component includes a plurality of the above-mentioned special floating crystals, and a plurality of parallel character line lines ′ and a plurality of parallel bit lines —: a direction of the brother, a direction of the second row, and a row of the fourth row . The trend is in the direction of the two rows and columns and there are two fives between the direction of the third row and the column. = now in the direction of the first row and the column in the direction of the second row and column in the direction of the 行 亍 column adjacent to the direction of the second row of columns temporarily 2; the minimum micro-level. In addition, each of the character lines is connected to the secret structure of the semiconductor tree, and the source/difficulty of each of the semiconductor elements in the upward direction. The above-mentioned objects and technical features of the present invention are set forth in the following description of the preferred embodiments of the present invention. The basic spirit of the invention and other technical means and preferred embodiments adopted by those skilled in the art. EMBODIMENT OF THE INVENTION [Embodiment] Referring to Figure 1, there is shown a semi-conducting 1 10, 1 ° and - vertical transistor 40 of the present invention. Layer 30 capacitor structure for the sake of simplicity. The figure is only partially shown. As shown in Fig. 1, the capacitor 20 is located on the base 2 - the upper electrode 22 and the - dielectric layer 23. H includes a lower electrode conductive layer 24 and a second conductive trim and dielectric layer 23: ^ 1309076 = 22. The second dielectric layer 3G is located above the capacitor ii 2G and covers the straight transistor 40 including a gate structure 4, an upper source diode 42, a channel region, a lower electrode 44 and a second electrode 22 The conductive layer 25 is in contact with and connected to the substrate 1 , and the channel region 43 is located between the upper source/no-polar source/no-pole 44 and between the gate structure 41 and the second dielectric layer; The figure shows the use of semiconductor components! One embodiment, as a record, for example, a dynamic random access memory (DRAM). Wherein, the substrate 1 is chopped: the electrode 21 comprises an ion doping region 211 located in the substrate 10 at two 212, 'exemplary (but not limited thereto) 'the ion doping region 211 can be The doped one sub-conductive layer 212 may be a titanium/vaporized titanium layer. The first dielectric layer 23 may be a metal oxide layer (ai2o-3), and the first/second conductive layer 24/25 of the upper electrode 22 is preferably a composite layer each comprising a titanium nitride layer. The 241/251 is stacked vertically above and below the source/dot 42 of the multi-vertical transistor 40, the channel region 43, and the lower source/drain 44^ on a continuous surface. Among them, the lower source level 44 is extended from the substrate. In addition, the upper source/drain 42, the channel region 43, and the continuous surface of the friend source/drain 44 extend upward along the sidewall of the trench, and surround the two portions of the capacitor 2...the continuous surface can be substantially 1M to 2/3 of the circumference of the lining of the lining. In one embodiment, the source/drain 44 is the source, and the above source / 汲 ^ 42 is / and the pole. The second dielectric layer 30 includes an oxide layer 31 and an oxide layer 32, which are listed (but not limited to). The oxide layer 32 may be composed of tetraethyl acid orthosilicate (TEOS) and ozone (〇z). 〇ne) reacted. In a preferred embodiment, capacitor 20 is located in a cylindrical trench. The vertical 4 〇 source/nom 42, the channel region 43, and the lower source/dippole 44 constitute a first part 51 of one, t, and #: structure 5 (see Fig. 26). The annular structure 50 extends from the side wall of the channel to surround the second dielectric layer 30 and the second conductive layer 25 of the upper electrode 22 of the upper portion of the capacitor 20, and further comprises an undoped stone 1301309076 The first part 51 can occupy the ring t1/2. The two parts are 52 °, where the 'part' part 51 is in the ring structure 50 i, which is exemplified (but not limited thereto). Further, the thickness of the first portion 51 and the second portion 52 is 5 〇 to 4100 to 200 Å (e.g., 150 angstroms). The undoped stone substrate 1 is formed into the first portion 52, which eliminates the floating body effect of the vertical transistor 40 during operation.

啼第2圖，垂直電晶體40之閘極結構41係包含一閘極介 一問極412。舉例言之（但不以此為限），該閘極介 為—氧化層，且該閘極可為—多晶判。此外，第2 不°己μ體另包含一字元線60與一位元線7〇,分別與垂直電晶 诗之問極結構41與上源/沒極42電性連接。於一實施態樣中， 係包含—氮化鈦層6卜—氮化鱗層62以及-金屬鶴 一曰〖該位兀線70則透過一位元線接觸71接觸上源/汲極42，位 j 70與位元線接觸71冑包含一鈦層/氮化 金屬鐵層702、712。 如前述，本發明半導體元件係於基材中溝渠電容上方之一側 士 ^垂直電日日體，該垂直電晶體之源極與基材相連接，而源/汲 之通道區職溝渠電容上方之介電層相鄰。因此，本發 元件之垂直電晶體係具有一垂直絕緣層上矽（&此⑽⑽ 曰ns=t〇r; SOI)之結構，此垂直S0I結構可使該通道區於垂直電 i曰声變成-完全空乏區。從而’使得操作電流加大、操作 =$决，抑制傳統元件之高接合漏電(Juncti〇nLeakage)及高接合 ίί iu=lon Capacitance)問題。此夕卜’由於垂直電晶體之通道區 城結構5。巾未轉雜之轉材卿成之第二部份η，並 度s制傳統垂直電晶趙元件之浮體效應，提升 本發明半導體元件於應用於記憶體元件時，更可接 技術為高之積集度，以下將分別以4F2、3 5 p2、2 ρ2為修兒明之剛 10 1309076 圖，=^己憶體凡件為例’請合併參閱第3A ®至第3C 二θ中所不複數圓點巾之每—個_均具有前述半導體元 iHtr與憶的複數個介電層與複數個垂直電晶 其含一第一行列方向(以γ軸方向表示)以；^ 軸，表示)上，第—行列方向係垂直於第二 二歹=向(以下所述之3.5F2、2F2之記憶體元件亦同）。該陣列中第 之該等溝渠電容11，彼此間實質地相隔2個最小微 中第"行列方向上之該等溝渠電容器，彼此 ^實^地她2個最小郷單位，卿於4郷平方單位上 固隶小之記憶體操作單位，稱之為4F2記憶體元件。 叙加，外’此4F之記憶體元件’更包含複數個字元線饥與複 ^位7G線BL，其中每-字元線係分別電性串接該陣列中第一行 2:?上之垂直電晶體之閘極結構。而且，每-該位元線係分別 …串接該陣列中第二行列方向上之垂直電晶體之上源級極。 ，3.5p2記憶體元件為例，請合併參閱第4A圖至第4C圖， 2該陣壯之相㈣渠電容關，彼關實質 =私，亦即於3.5郷平方單位上具有—個最小之記憶體^ =。此外，此3.5F之記憶體元件，更包含複數個字元線ι鱼 =一個位tl線BL。其中，每-該字元線係分別電性串接該陣^ 方向上之垂直電晶體之閘極結構，每—該位元線係分別 電性串接辦财第-行财向上之垂直電晶體之±源/沒極。 以2F之記憶體元件為例，請合併參閱第5A圖至第圖， J中於，_中第-行财向上之該等溝縣容器，彼此間 带，=V2個最小微影單位’且於該陣列中第二行列方向上之 電^器，彼此間實質地相隔V2個最小微影單位，亦即於2微影= 方單位上具有一個最小之記憶體操作單位。此外，此迕2之 兀件，更包含複數個字元線WL與複數個位元線31，每一 1309076 線係分別電性串接該陣列中 > 結構。其中，第三行列方向;;之J直電晶體之閉極 夾角係45。。另-方面，每一^ ^方向、第二行列方向間之 四行列方向上之垂直電Θ|Α “ 糸分別電性串接該陣列中第 第三行列方向。㈣之上源_ ’細行财向係垂直於 乂下所“述者，係製造本發明半導體树之一方法。 面上=成圖，於基㈣表 接著，於錄⑽物财式進行。 103。舉例言之（但不以μ 〃電層102以及一钱刻緩衝層 騎衝層可為财玻璃層^触 ί=較τ係於形成圖案化光 =案化製程。接著，以該_化光阻層iQ4 =ί，再=爛嶋1G3，藤去除光阻層 料L\rfl1電層102以及飯刻緩衝層103作為餘刻溝 車，部份基材1() ’於基材1G中形成-溝渠祕， Ιίίίίΐίη 圓柱狀溝渠。形成溝渠ω6後，接著去除 蝕刻緩衝層103，如第7圖所示。 其次’於溝渠106中形成溝渠電容器2〇之下21。首 Ξ積子之魏璃層W於溝渠1〇6中且覆蓋基材10表 不以此為限），該離子摻_玻璃層可以是摻雜 申之矽玻璃（As Doped Silicate Glass ; ASG)層。接著，塗佈-弁 ^層^ ’以電漿餘刻之方式，去除部份該光阻層，以保留溝渠1〇6 L一定深度以下之部分光阻層應。以溝渠1〇6内之光阻層 08為罩幕，等向性蝕刻去除裸露於光阻層1〇8 矽玻璃屏 107 ’如第8圖所示。 曰 接著，請參閱第9圖，去除溝渠106内之光阻層1〇8，以四乙 基酸正石夕酸鹽(TE0S)與臭氧(OZ〇ne)反應沉積—氧曰化石夕廣（未顯 12 1309076 1)並以一加熱回火製程，將溝渠1〇6下端側壁 中之換雜離子以擴散方式進入溝渠爾之基材H)中 子摻雜區域211作為麟電容下電極之—部份。接著， =’!法去除縣1G6表Φ的氧化⑦層及下端趣表蚊魏^層 、戈參第10圖，於溝渠106中形成一襯墊層1〇9。舉例t之 艮= 概日t109可為以沉積方式形成之“化層 磨之方式去除介電層1Q2上之該多^^二^ 石夕層110位於與介電層1〇2相同之水平。接著， 、ί 二侧之方式，去除部份該溝渠廳中之 ί定;J以其ί渠:較前述之該第-2叫以及—領（叫介電層32， 110 * 化鈦層，而該襯墊層114可以日為,電層p212之用，例如··鈦/氮 次，塗佈-光阻；著並去:;份=仔留-=巧。其 ί深度之部分~-預定^係 光阻=二圖為”，裸露於 渠内之光阻115去除後，以等向“i方^去=露 1309076 i，f。之電層212，再以濕蝕刻方式去除該襯氮化矽層 中完整之下H212與離子推雜區域211便構成溝渠電容20 ALD)^^-1^ J (Atomic Layer Deposition ； 介電層23覆蓋整個晶圓‘平表面 中、之導電層21^/^溝渠纖上之領介電層32以及T電極21 叫系作為溝渠電_；=回火製程。其中，該介電層 铭層。卞〜之;,電層，其可為，但不限於，例如三氧化二 2將進行形成溝渠餘2G之上電極2 2形成一導電層241覆蓋於介電層23之上，i進= 之回火製程。導電層241可為，但不限於，例如氮化欽岸 二’ ^積一多晶碎層242填入溝渠106 t，並覆蓋整個=。In Fig. 2, the gate structure 41 of the vertical transistor 40 includes a gate dielectric 412. For example, but not limited to, the gate is an oxide layer, and the gate can be polycrystalline. In addition, the second non-compliance body further includes a word line 60 and a bit line 7〇, which are electrically connected to the vertical electromorphic body structure 41 and the upper source/depolarization 42 respectively. In one embodiment, the titanium nitride layer 6-nitride scale layer 62 and the metal crane layer are included. The bit line 70 contacts the upper source/drain 42 through a bit line contact 71. The bit j 70 and the bit line contact 71A include a titanium layer/nitrided metal iron layer 702, 712. As described above, the semiconductor device of the present invention is connected to a side of the trench capacitor in the substrate, and the source of the vertical transistor is connected to the substrate, and the source/channel is above the channel drain capacitance. The dielectric layers are adjacent. Therefore, the vertical electro-crystalline system of the present element has a structure of a vertical insulating layer (&(10)(10) 曰ns=t〇r; SOI), and the vertical S0I structure can turn the channel region into a vertical electric hum. - Completely depleted area. Thus, the operating current is increased, the operation is =$, and the problem of high junction leakage (Juncti〇nLeakage) and high bonding ίί iu=lon Capacitance of conventional components is suppressed. This is due to the channel structure of the vertical transistor. The towel is not turned into the second part of η, and the floating body effect of the conventional vertical electro-optical element is increased, and the semiconductor component of the invention is improved when applied to the memory element. For the degree of integration, the following will be 4F2, 3 5 p2, 2 ρ2 for the repair of the child just 10 1309076 map, = ^ recall the body as an example 'please refer to the 3A ® to 3C two θ Each of the plurality of dot towels has a plurality of dielectric layers of the semiconductor element iHtr and the plurality of vertical electrodes, and a first row and column direction (indicated by the γ-axis direction); The direction of the first row and the row is perpendicular to the second dimension = direction (the same is true for the memory elements of 3.5F2 and 2F2 described below). The ditch capacitors 11 of the array are substantially separated from each other by the two smallest micro-centers in the direction of the row and row, and each of them is the smallest unit of the two units. The memory operation unit of the solid on the unit is called 4F2 memory component. In addition, the '4F memory component' includes a plurality of character line hunger and complex 7G line BL, wherein each word line is electrically connected to the first line 2 of the array. The gate structure of the vertical transistor. Moreover, each of the bit lines is ... connected in series to the source level of the vertical transistor in the direction of the second row of the array. For example, the 3.5p2 memory component is combined. Please refer to Figure 4A to Figure 4C. 2 The strong phase (4) is the capacitance of the channel. The essence of the channel is private, that is, it has the smallest value in the 3.5郷 square unit. Memory ^ =. In addition, the 3.5F memory component further includes a plurality of character lines i fish = one bit tl line BL. Wherein, each of the character lines is electrically connected in series with the gate structure of the vertical transistor in the direction of the array, and each of the bit lines is electrically connected in series to the first line of the financial operation. ± source / no pole of the crystal. Take the memory component of 2F as an example, please refer to Figure 5A to Figure. In J, in _, the first container of the ditch county, with each other, = V2 minimum lithography units' The devices in the second row and column direction of the array are substantially separated from each other by V2 minimum lithography units, that is, having a minimum memory operation unit on 2 lithogram=square units. In addition, the component of the 迕2 further includes a plurality of word lines WL and a plurality of bit lines 31, and each of the 1309076 lines is electrically connected to the > structure in the array. Wherein, the third row direction; the closed angle of the J straight crystal is 45. . On the other hand, the vertical electric field in the direction of the four rows and columns in the direction of the ^^ direction and the direction of the second row and column is Α" 电 electrically connected in series with the third row and column direction in the array. (4) above the source _ 'fine line The financial system is perpendicular to the "speaker" and is a method of manufacturing the semiconductor tree of the present invention. On the surface = map, on the base (four) table, followed by the record (10) financial formula. 103. For example (but not the μ 〃 〃 102 102 and the 刻 buffer layer riding layer can be the treasury layer ^ touch ί = t θ in the formation of patterned light = case process. Then, with the _ huaguang The resistive layer iQ4 = ί, then = smashed 1G3, the vine stripping photoresist layer L \ rfl1 electric layer 102 and the rice buffer layer 103 as a residual grooved car, part of the substrate 1 () 'formed in the substrate 1G - Ditch, Ι ί ί 。 。 。 。 。 。 ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω ω The layer W is in the trench 1〇6 and the cover substrate 10 is not limited thereto. The ion-doped glass layer may be an As Doped Silicate Glass (ASG) layer. Then, the coating layer is removed by plasma remnant to remove a portion of the photoresist layer below a certain depth of the trench 1〇6 L. The photoresist layer 08 in the trench 1 is used as a mask, and the isotropic etching is removed to expose the photoresist layer 1 〇 8 矽 glass screen 107 ′ as shown in FIG. 8 . Next, please refer to Fig. 9, to remove the photoresist layer 1〇8 in the trench 106, and react with tetraethyl sulphate (TE0S) and ozone (OZ〇ne) to deposit - oxonium fossil XI Guang ( Not showing 12 1309076 1) and using a heating and tempering process, the impurity ions in the sidewall of the lower end of the trench 1〇6 are diffused into the substrate of the trench, H) the neutron doping region 211 is used as the lower electrode of the capacitor. Part. Then, the ='! method removes the 7th layer of oxidation of the 1G6 table of the county and the bottom layer of the V. sinensis, and the 10th figure of the ginseng, forming a liner layer 1〇9 in the trench 106. For example, t = _ t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t t Then, ί two sides, remove some of the gully in the trench; J with its ‧ channel: the second -2 and the collar (called the dielectric layer 32, 110 * titanium layer, The liner layer 114 can be used for the electric layer p212, for example, titanium/nitrogen, coating-resistance; and going to: part = 仔留-=巧巧. Its ί depth part ~- Predetermine the resistance of the system = the second picture is ", after the photoresist 115 exposed in the channel is removed, the lining is removed by the wet etching method in the direction of the "i square ^ go = dew 1309076 i, f. The H212 and the ion doping region 211 in the tantalum nitride layer constitute a trench capacitor 20 ALD) ^^-1^ J (Atomic Layer Deposition; the dielectric layer 23 covers the entire wafer 'flat surface, the conductive layer 21 ^/^The dielectric layer 32 and the T electrode 21 on the trench are called the trench _;= tempering process. Among them, the dielectric layer is the layer of 铭~;, the electric layer, which can be, but Not limited to, for example, bis 2 The electrode 2 2 is formed on the upper surface of the trench 2G to form a conductive layer 241 over the dielectric layer 23, and the conductive layer 241 can be, but is not limited to, for example, nitrided ^ A polycrystalline fracture layer 242 is filled into the trench 106 t and covers the entire =.

故ί 2以如化學機械研磨之方式，去除晶圓水平面之部“B ίί i部分該導電層241以及部分介電層Μ，使溝』之頂Γβ 表面與晶圓表面具同一水平高度。 、邛 請=參閱第16圖’去除溝渠内之部分多祕層2 241 方式去除。請合併參 _之_ 23上爾謝為，ί不 多晶=:部分 覆蓋下電極21，更明確而言—♦電層24 專向性濕_去除裸露於多晶發層242以外之導電層 =罩|參^ 14 1309076 第19圖，形成一圖案化光阻層in履嘗八 之溝渠，藉以裸露出部分之溝渠。之曰曰圓表面以及部分 佳係佔整個溝渠之1/4至2/3 ; 月者心裸露，分溝渠較 層117將裸露於外之介電層23以等向料2。、接著，以光阻 序將暴露it}來之部分領介電層32以及襯=彳了式絲’接著依 刻方式去除。其中，錄層⑴；等向=祕 驟前移除即可。 无〜儿積導電層251之步 請參閱第20圖，去除光阻層117， 介電層23、領介電層116、以及上 内未被移除之 子摻雜罩幕’斜角植入離子於溝渠側壁 =層24為離 渠外且鄰近第-導電層24之基材1G + j 1G巾’以於該溝 續形成之垂直電晶體40之源/汲極區域^源44 ’作為後 侧方式去除領介電層116及部份f圓、中^一。^後以等向性濕 21圖所示。 丨^圓表面之介電層1G2,如第 、賊圖’將裸露於溝渠側壁内之襯墊芦109以蓉6 Mt ί ΪΪί除。其次’繼續形成上電極22之Ϊ Si J向f 弟-導電層24接觸。其中，第二導 電層25 ’與 舉例而言’可先沉積—導電層251覆佳者係-複合層。 並於溝渠側壁與下源/汲極44接觸第-導電層24， 接著再沉積多晶石夕層252覆蓋導電^ =51可為如氮化鈦層。 ，份多晶補252，轉留溝_^彡綱方式去除 夕晶石夕層252為罩幕，刻去^^夕曰曰石夕層252。接著，以 =電層251，再以_後所保去留除下裸來路於多 = 夕層252以外之部 4去除裸露之部分介電層23，以— 電層25為罩幕，濕蝕 f強調者，地22之所以區以電| 22之第二導電層25。 1 二道製程之賴，主要係為了m電層24與第二導電層 體4〇之下源/沒極44於基材1〇 知間能形成垂直電晶 極22能接觸該下源/汲極44，作L ί ί其與溝渠電容20之上電 渠電容20間電性連結之通路。…、、$疋成之垂直電晶體40與溝 15 1309076 以下將進行第二介電層 速熱氧化製程，並以沉積方式。請參第23圖，進行一快 含溝渠底部之上電極22 電層31覆蓋整個晶圓，包 介電屬3!可為，但不限於^層25與側壁之領介電層％。 其可利用化學機械研磨 〜接著’進行-平坦化製程， 離形，其包含介電層3卜領^ 此’形成第二介電層30之 襯墊層（例如：襯墊層1〇9、32以及領介電層32外之複數 清參閱第24圖，以一等向彳 ΦTherefore, in the manner of chemical mechanical polishing, the portion of the surface of the wafer "B ίί i portion of the conductive layer 241 and a portion of the dielectric layer Μ, so that the top surface of the trench" has the same level as the surface of the wafer. = please refer to Figure 16 to remove some of the secret layers in the trench 2 241 way to remove. Please merge the _ _ 23 er er, ί 不 poly == partially cover the lower electrode 21, more specifically - ♦Electrical layer 24 Dedicated wet _Removal of conductive layer exposed outside polycrystalline layer 242=Cover|Ref. 14 1309076 Figure 19, forming a patterned photoresist layer in the mouth of the Eight Ditch, so that the exposed part The ditches and the rounded surface and some of the best systems account for 1/4 to 2/3 of the entire ditch; the moon is bare, and the ditches are exposed to the outer dielectric layer 23 to the isotropic material 2. Then, the portion of the dielectric layer 32 and the lining of the exposed layer are exposed in a photoresist order, and then removed in a timely manner. Among them, the recording layer (1); isotropically removed before the secret step. ~ Step of the conductive layer 251, please refer to Figure 20, remove the photoresist layer 117, the dielectric layer 23, the dielectric layer 116, and the upper layer The removed doped mask has an oblique implanted ion on the sidewall of the trench = layer 24 is a substrate 1G + j 1G towel that is outside the channel and adjacent to the first conductive layer 24 to form a vertical transistor for the trench 40 source / drain region ^ source 44 'as the back side way to remove the collar dielectric layer 116 and part of the f circle, the middle ^ ^. ^ is shown in the isotropic wet 21 Figure 丨 ^ round surface dielectric Layer 1G2, such as the first, thief diagram 'will remove the liner reed 109 in the side wall of the trench by the 6 Mt ί ί. Next, 'continue to form the upper electrode 22 Ϊ Si J to the f-conductive layer 24 contact. The second conductive layer 25' and, by way of example, may be deposited first - the conductive layer 251 is covered with a composite layer - and the composite layer is contacted with the lower source/drain 44 and then the polycrystalline stone is deposited. The layer 252 covers the conductive ^ = 51 can be a layer such as titanium nitride. The polycrystalline 252, the transfer ditch _ ^ 彡 方式 去除 夕 夕 夕 252 252 252 252 252 252 252 252 252 252 252 252 252 252 252 252 252 刻Then, the dielectric layer 23 is removed by the = electric layer 251, and then the remaining bare dielectric is removed from the portion 4 other than the poly layer 252. Mask Wet etch f emphasizes that the reason why the ground 22 is electricity | 22 the second conductive layer 25. 1 The second process depends on the m electric layer 24 and the second conductive layer body 4 源 source / no pole 44 can form a vertical electric crystal pole 22 between the substrate 1 and can contact the lower source/drain 44 to electrically connect the drain capacitor 20 to the trench capacitor 20. The vertical dielectric transistor 40 and the trench 15 1309076 will be subjected to a second dielectric layer thermal oxidation process and deposited. Referring to Figure 23, an electrode 22 on the bottom of the trench is covered by an electrical layer 31 covering the entire wafer, and the dielectric is 3! It can be, but is not limited to, the dielectric layer of the layer 25 and the sidewall. It can utilize chemical mechanical polishing followed by a 'peer-flattening process, which is a release layer that includes a dielectric layer 3 to form a liner layer of the second dielectric layer 30 (eg, a liner layer 1〇9, 32 and the plurality of clear layers outside the dielectric layer 32, refer to Fig. 24, in an isotropic 彳Φ

102去除，使第二介電層勺入/又刻製程將晶圓表面之介電層 數襯墊層）得以突出於基電層3卜領介電層32以及複 子植入製程，以進行整個晶圓井區J 其次，請合併參㈣25Α圖=電極21。 118於突出之第二介電層3 W，形成一間隙壁結構 之溝渠係一圓柱狀之溝渠，° ;較佳實施例t，由於本發明 為-圓柱狀結構，則環;於晶圓表面之第二介電層30 化石夕層料圓表面後，再:====係可經由沉積-氮 之俯視圖及職圖。圖’分別為铸體元件 之第二介電層30為勤//幕狀=5^18以及如於晶圓外 於晶圓表面上，形成—突出幕之部分基材10，以 結構係包含雜_壁結構其中，該突出圓柱狀 =份上電極（此處所示為第二ίΐΓ2ί電容器20 24)、以及環狀間隙壁結 ::層及部份第一導電層 50包含一第一部份51鱼一 娘狀結構50。環狀結構 30,而且該下源/汲極料係^^ ^其至少包圍第二介電層 部區域内。實際上，環狀巧、=:構5G中第—部份51之-下 狀結構％係由_基材1〇而形成，因此 16 1309076 其與基材1G係具有—連續 〃 在之溝渠之側壁向上延伸。 且該連續表面係沿電容器20所 接著，於形成一播Μ _ 行-離子摻雜餘於部分於概結構50之表面後，進 電晶體40之啟始。钱1衣狀結構50 ’以調整後續形成之垂直 係將離子摻雜於^!狀社構1，此調整電晶體工作之製程， 119 如 圓表面。襯墊層 晶圓表面，介電層12G 後’沉積—介電層12G覆蓋整個 接著，化學機械研磨法使晶==牛間電性隔離之用， 露出部分環狀結構50之内^壁。^除第·^電層3〇，以裸 :土;= :第-部份51之-上部區域，= 有，=内於上源7汲極42與下源二 30相鄰、。有通道Q 43，而該通道區43係與剩餘之第二介電層 電29圖’去除晶圓上之圖案化光阻層12卜形成-介 石夕i。接面曰° 2層122,，但不限於，例如：氮化 二得者，/儿積多晶矽層123於介電層122上，並 之凹陷。之後，再以化學機械研磨製程將整個晶圓平坦化Γ =閱第30圖’以下將進行垂直電晶體4G閘極 Ϊ之ΐΐ’於_表面形成一圖案化光阻層124 ’以作為酬字ί w尾增122下方之介電層120。承上所述，於前述侧 17 1309076 晶矽層123亦將同時地被少 iC過程中’部分裸露之多 ⑵第層31二：^案化光阻層124、裸露之多晶梦層 結構5〇之下源之Λ化層跑接近環狀102 removing, so that the second dielectric layer is scooped in and engraved to expose the dielectric layer pad layer on the surface of the wafer to the base layer 3 and the dielectric layer 32 and the complex implant process for performing The entire wafer well area J Next, please merge the reference (4) 25 Α map = electrode 21. 118, in the protruding second dielectric layer 3 W, forming a trench structure, a cylindrical trench, a preferred embodiment t, since the present invention is a cylindrical structure, the ring; on the wafer surface After the second dielectric layer 30 is formed on the round surface of the fossil layer, then: ==== can be through the deposition-nitrogen top view and job map. Figure 2 is a portion of the substrate 10 of the second dielectric layer 30 of the cast component, which is diligent//curtain=5^18 and formed on the wafer surface as a wafer, and is comprised of a structural system. a hetero-wall structure in which the protruding columnar portion is the upper electrode (herein shown as the second electrode 20 24), and the annular spacer layer: the layer and a portion of the first conductive layer 50 comprise a first portion 51 fish a mother-like structure 50. The annular structure 30, and the lower source/drain material system, at least surrounds the second dielectric layer region. In fact, the ring-shaped, =: 5G-part 51--the lower structure % is formed by the _substrate 1 ,, so 16 1309076 has a continuous 与 with the substrate 1G 〃 The side walls extend upward. And the continuous surface is followed by the capacitor 20, and after the formation of a seeding-row-ion doping portion is partially formed on the surface of the general structure 50, the start of the transistor 40. The money 1 garment structure 50' is doped to adjust the subsequently formed vertical system to dope the ions into the structure 1, which adjusts the working process of the transistor, such as a circular surface. The pad layer is on the surface of the wafer, and the dielectric layer 12G is deposited. The dielectric layer 12G covers the entire surface. Next, the chemical mechanical polishing method causes the crystal to be electrically isolated from the cattle to expose the inner wall of the partial annular structure 50. ^ In addition to the first ^ electric layer 3 〇, to bare: soil; =: the first part of the 51 - upper area, = yes, = inside the upper source 7 pole 42 and the next source two 30. There is a channel Q 43, and the channel region 43 is connected to the remaining second dielectric layer 29 to remove the patterned photoresist layer 12 on the wafer. The junction layer 2 2 layer 122, but is not limited to, for example, a nitrided oxide layer, or a polycrystalline germanium layer 123 on the dielectric layer 122, and recessed. After that, the entire wafer is planarized by a chemical mechanical polishing process. 阅 Figure 30 below, a vertical transistor 4G gate is formed, and a patterned photoresist layer 124 is formed on the surface of the vertical photoresist. The dielectric layer 120 under the 127 is increased. As described above, in the aforementioned side 17 1309076, the germanium layer 123 will also be simultaneously reduced by a part of the iC process (2) the first layer 31 2: the photoresist layer 124, the exposed polycrystalline dream layer structure 5 The sputum layer of the source runs close to the ring

Sit 層— 將進-步被部份移除。 挪之多晶石夕層123與介電層122 結構5(Γ外4之;^塾部份之氧化層12G後’將裸露於環狀 方式去除Si之犧牲^^9；^=方式去除，再以賴刻 隙去除部份該多晶石夕層，以形成一問極多 Ϊ-直^ J42外’而相鄰於該下源/細、該通道區43與該上源/汲 保該; ^^==用以協助定義閘極結 1309076 請參閱第34圖’以等向性濕侧製 線60外之該多晶石夕層412，以形成最終之閑於=述字元 述之製程較佳者細-氫氧化狀侧溶 ^、中’前 下進行去除多於閘極多晶销412之步驟。接著刻環境 熱氧化製程後，沉積-介電層126覆蓋整個^面進f巧 126可為’但不限於，例如氧化層 卜亥;I電層 晶圓表面平坦化。* I似化于機械研磨之方式將該 以下將進行一形成位元線7〇之製程。請參 巧化光阻層127 ’作輕刻位元線接觸之罩幕。亦二= 層V別餘刻去除溝渠電容器2〇上方之介電芦 人上用5亥罩幕 以及多晶矽層123，以裸露出原溝1〇6中曰第 y : 122、 成-位元線接觸128。 丨電層30，並形 接著，請參閱第36圖，於去除光阻圖案後，以 方式，位元線接觸128側壁上之殘留物質，例如4 = 程而存在於溝渠觸侧壁上之氧化㈣、氮化^ = ^衣 其次，形成字元線於覆蓋該第二介電層3〇。 $曰° !先：=以71，位元線接觸=:= 上筏者，再以化學軋相沉積法沉積金屬鎢層712 3 :接i回蝕刻去除部份之金屬鎢，使其與氧化矽層二 一=之#刻製程以及沉積欽/氮化欽層則、 702 4製私，形成一位元線7〇連接該位元線接觸128，以 達，電性串接該上源/藤之目的，並完成如第 之半導體元件。 ⑦U2圖所不 ^說明者，前狀溝渠電容結構僅為朗本發明之一 二’m際並^僅限於此’其他*同之溝渠電容結構亦可作為i私 ^適當實施雜。熟知此項技藝者，可於了解 了 ^ 19 1309076 ^述貫轭例僅為例示性說明本發明之原理及功效，而非用於 發明。任何熟於此項技#之人士均可在不違背本發明之技 =理及精神的情況下，對上述實施例進行修改及變化。因此， 土明之權利保護範圍應如後述之申請專利範圍所列。 【圖式簡單說明】 第1圖顯示本發明具垂直電晶體之一半導體元件之示意圖； 第2圖顯示本發明具垂直電晶體之一半導體元件之示g圖:Sit layer - the step is partially removed. The structure of the polysilicon layer 123 and the dielectric layer 122 is removed (the outer layer 4; the oxide layer 12G of the portion) is removed from the sacrificial method of removing the Si in a ring-like manner; Then, a portion of the polycrystalline layer is removed by a crevice to form a plurality of Ϊ-straight- J42 outer' adjacent to the lower source/thin, the channel region 43 and the upper source/protection ^^== to assist in defining the gate junction 1309076. See Figure 34, 'The polycrystalline layer 412 outside the isotropic wet side line 60 to form the final idle = description of the character Preferably, the process is a step of removing the more than the gate polycrystalline pin 412 by the fine-hydrogenated side dissolution and the middle portion. After the encapsulation of the ambient thermal oxidation process, the deposition-dielectric layer 126 covers the entire surface. Qiao 126 can be 'but not limited to, for example, oxide layer Bu Hai; I electric layer wafer surface flattening. * I like mechanical grinding method will be followed by a process of forming bit line 7 。. Please refer to The photoresist layer 127' is used as a mask for light-bit line contact. Also, the layer V is removed from the trench capacitor. The dielectric layer on the top of the cellar is covered with a 5 hai mask and a polysilicon layer 123. Exposing the original groove 1〇6, the middle y: 122, the formation-bit line contact 128. The electric layer 30, and then the shape, please refer to the figure 36, after removing the photoresist pattern, in the way, the bit line contact The residual material on the sidewalls of 128, for example, 4 = oxidized on the sidewalls of the trench (4), nitrided = ^, followed by the formation of word lines overlying the second dielectric layer 3 曰 ° ! First: = 71, bit line contact =: = upper, then chemical metallization deposition of metal tungsten layer 712 3: etch back part of the metal tungsten to make it with the yttrium oxide layer = #刻制程 and deposition Qin / nitride layer, 702 4 private, forming a meta-line 7〇 connected to the bit line contact 128, in order to electrically connect the source / vine purpose, And complete the semiconductor components such as the first. 7U2 figure does not explain, the front trench capacitance structure is only one of the two inventions of the invention and is limited to this 'other * the same trench capacitance structure can also be used as i private ^ </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; It is not intended to be used in the invention. Any person skilled in the art can modify and change the above embodiments without departing from the spirit and spirit of the present invention. Therefore, the scope of protection of the rights of the land should be as follows. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1 is a schematic view showing a semiconductor device having a vertical transistor of the present invention; and Fig. 2 is a view showing a semiconductor device having a vertical transistor of the present invention:

第3A圖至第3C圖顯示本發明4F2記憶體元件之示意^ ;， 第4A圖至第4C圖顯示本發明3.5F2記憶體元件之示*意圖； 第5A圖至第5D圖顯示本發明2F2記憶體元件之示意、圖；以 第6圖至第36圖顯示本發明製造一半導體元件之示意圖。3A to 3C are diagrams showing the 4F2 memory element of the present invention; FIGS. 4A to 4C are diagrams showing the 3.5F2 memory element of the present invention; 5A to 5D are diagrams showing the 2F2 of the present invention; BRIEF DESCRIPTION OF THE DRAWINGS FIG. 6 to FIG. 36 are views showing the manufacture of a semiconductor device of the present invention.

【主要元件符號說明】 10 :基材 21 :下電極 23 :第一介電層 25 :第二導電層 31 :氧化層 40 :垂直電晶體 42 :上源/沒極 44 :下源/汲極 51 :第一部分 60 :字元線 62 :氮化鎢層 70 :位元線 102 :氮化矽層 103 :硼矽玻璃層 20 :電容器 22 :上電極 24:第一導電層 30 :第二介電層 32 :氧化層 41 :閘極結構 43 :通道區 50 :環狀結構 52 :第二部份 61 :氣化鈦層 63 :金屬鹤層 71 :位元線接觸 104 :圖案化光阻層 20 1309076[Main component symbol description] 10: Substrate 21: Lower electrode 23: First dielectric layer 25: Second conductive layer 31: Oxide layer 40: Vertical transistor 42: Upper source/dipole 44: Lower source/bungee 51: first portion 60: word line 62: tungsten nitride layer 70: bit line 102: tantalum nitride layer 103: borosilicate glass layer 20: capacitor 22: upper electrode 24: first conductive layer 30: second Electrical layer 32: oxide layer 41: gate structure 43: channel region 50: annular structure 52: second portion 61: vaporized titanium layer 63: metal crane layer 71: bit line contact 104: patterned photoresist layer 20 1309076

105 :抗反光層 107 : ASG 層 109 :襯氧化層 111 :襯氮化矽層 113 :鈦/氮化鈦層 115 :光阻層 117 :光阻層 119 :氮化矽層 121 :光阻層 123 :多晶矽層 125 :閘極淺溝渠結構 127 :光阻層 211 :離子摻雜區域 241 :氮化鈦層 251 :氮化鈦層 411 :閘極介電層 701 :鈦層/氮化鈦層 711 :鈦層/氮化鈦層 106 :溝渠 108 :光阻層 110 :多晶矽層 112 :犧牲氧化層 114 :襯氮化矽層 116 :領氮化矽層 118 :氮化矽間隙壁結構 120 :氧化層 122 :氮化矽層 124 :光阻層 126 :氧化層 128 :位元線接觸 212 :導電層 242 :多晶矽層 252 :多晶矽層 412 :閘極 702 :金屬鶴層 712 :金屬鶴層 21105: anti-reflective layer 107: ASG layer 109: lining oxide layer 111: lining tantalum nitride layer 113: titanium/titanium nitride layer 115: photoresist layer 117: photoresist layer 119: tantalum nitride layer 121: photoresist layer 123 : polysilicon layer 125 : gate shallow trench structure 127 : photoresist layer 211 : ion doped region 241 : titanium nitride layer 251 : titanium nitride layer 411 : gate dielectric layer 701 : titanium layer / titanium nitride layer 711: Titanium layer/titanium nitride layer 106: trench 108: photoresist layer 110: polysilicon layer 112: sacrificial oxide layer 114: tantalum nitride layer 116: collar tantalum nitride layer 118: tantalum nitride spacer structure 120: Oxide layer 122: tantalum nitride layer 124: photoresist layer 126: oxide layer 128: bit line contact 212: conductive layer 242: polysilicon layer 252: polysilicon layer 412: gate 702: metal layer 712: metal layer 21

Claims (1)

1309076 十、申請專利範圍： 1. 一種半導體元件，包含： 一基材； -^電容H，位於該基材中，包含—上電極、 電層、及一下電極； 弟 器二介電層’位於該溝渠電容器上方，覆蓋該溝渠電容 一垂直電晶體’包含-閘極結構、—上源/汲極、 ’其中’該下彡織極係與該上電極接觸並i »亥基材相連，该通道區係位於該上源/汲極與該下、、 間，且位於該閘極結構與該第二介電層之間。'、峰t 2. 如請求項1所述之半導體元件，其中該溝渠係一圓環狀溝渠。 3. 如請求項1或2所述之半導體元件，其中該上電極係包含相接 觸之-第-導電層及一第二導電層，該第一介電層係介於該第 一導電層與該下電極之間，且該下源/汲極係與該第二導電層接 觸。 曰 4. 如請求項1或2所述之半導體元件，其中該上源/汲極、通道區 以及^源/汲極係位於一連續表面上，且該連續表面係沿該溝渠 電容器所在之溝渠之側壁向上延伸。 5. 如請求項4所述之半導體元件，其中該連續表面係實質上環繞 該溝渠電容器所在溝渠側壁周長之2/3或更低。 6. 如请求項4所述之半導體元件，其中該連續表面具一 50至300埃。 7. 如請求項6所述之半導體元件，其中該厚度為1〇〇至2〇〇埃。 1309076 8.如請求項1所述之半導體树，其係-記憶體。 9·如《月求項1所述之半導體元 (DRAM)。 ，、你動慼^機存取記憶體 10. -種包含-妒半導體 ，請求…之半導』4==陣= 陣列具-第一行列方向舆一第二行歹 陣其中該 正交於該第一行列方向，^^ # μ弟—仃列方向係 隔2個最小微影單:白且上^ 點上； Λ導體疋件僅出現於陣列之交會 複數個平行子元線，其中各該字元 向上f亥半導體元件之該閘極結構；以及、亥第一行列方 複數個平行位元線，其中各該位 向上各該半導體树之該上源/汲極。雜料二行列方 U. 一種半導體元件陣列之積體電路元件，包含. 列，其中該陣列具一第一=5匕排巧為-跳褀棋盤陣 方向，該等行列兩兩交;、各呈向二; 體元最小微影單位’且各該半導 向上’其_字元線係連接該第-行列方 Π工合邊牛導體兀件之該閘極結構；以及 方向複元?，其中各該位元線係正交於該第一行列 署·^了予70線相交於該字元線所連接之一半導體元件 之位置，輕無半導體树之該上源/汲極。 12. -種=一 2F2半導體元件陣列之積體電路元件，包含： 陣列ί ^請=^之半導體元件，排列為一陣列，其中該 早幻/、第—仃列方向、一第二行列方向、一第三行列方向與 1309076 了第四行列方向，該第一行列方向正交於該第二行列 =該第三行列方向間具45。夾角，該第三行列方 ^列且各該半導體元件做現於該第—行列方向^ 第—仃列方向上之交會點上，該第一行列方向上盥該第二二 列方向上相鄰交會點係實質上相隔V2個最小微影單位&quot;；一仃 ，數個平行字元線’其中各該字元_連_第三行 向上各該半導體元件之該閘極結構；以及 魯 複數個平行位元線，其中各該位元線係連接該第四 向上各該半導體元件之該上源/汲極。 方 13· 一種製造半導體元件之方法，該方法包含： (a) 提供一基材，該基材中包含一溝渠； (b) 形成一電容器結構於該溝渠中，該電容器結構係包含一 :電極、-第-導電層、及―介電層位於該 電層之間； 、茨弟V (e)形成一下源/汲極於該溝渠外且鄰近該第一導 基材中； a (Φ形成一第二導電層，與該第一導電層接觸而形成一上 極’且該第二導電層係與該下源/汲極接觸； (e) 形成一第二介電層覆蓋該上電極； (f) 去除部分該基材，以形成—環狀結構，該環狀結構係至 圍该第二介電層，且該下源/汲極係位於該環狀結構之—下 部區域中； (g) 去除部分該第二介電層，露出該環狀結構之一上部區 域， (=)形成-上源/没極於該上部區域，其中，該上源級極係 ，於该下源/沒極上方，且於該上源/汲極與下源/汲極之間係存 在一通道區；以及 電層縣結構，⑽触通道11相鄰且位於該第二介 3 1309076 14. 如請求項13所述之方法，其中該下源/汲極係一源極，該上源/ 汲極係一汲極。 15. 如請求項13所述之方法，其中於步驟⑴之後，另包含形成一 字元線，與該閘極結構接觸。 16. 如請求項13所述之方法，其中於步驟⑴之後，另包含形成一 位元線，覆蓋該第二介電層，且與該上源/汲極接觸。1309076 X. Patent application scope: 1. A semiconductor component comprising: a substrate; - a capacitor H, located in the substrate, comprising - an upper electrode, an electrical layer, and a lower electrode; Above the trench capacitor, covering the trench capacitor - a vertical transistor 'including a gate structure, - an upper source / a drain, 'where the lower ridge is in contact with the upper electrode and is connected to the substrate The channel region is located between the upper source/drain and the lower, and between the gate structure and the second dielectric layer. The semiconductor component of claim 1, wherein the trench is an annular trench. 3. The semiconductor device of claim 1 or 2, wherein the upper electrode layer comprises a contact-first conductive layer and a second conductive layer, the first dielectric layer being interposed between the first conductive layer and The lower electrode/drain is in contact with the second conductive layer. The semiconductor device of claim 1 or 2, wherein the upper source/drain, the channel region, and the source/drain are on a continuous surface, and the continuous surface is along a trench in which the trench capacitor is located The side walls extend upward. 5. The semiconductor component of claim 4, wherein the continuous surface is substantially 2/3 or less of the perimeter of the sidewall of the trench where the trench capacitor is located. 6. The semiconductor device of claim 4, wherein the continuous surface has a range of 50 to 300 angstroms. 7. The semiconductor device according to claim 6, wherein the thickness is from 1 Å to 2 Å. 1309076. The semiconductor tree of claim 1, which is a memory. 9. The semiconductor element (DRAM) as described in the monthly claim 1. ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The direction of the first row and column, ^^ #μ弟-仃 column direction is separated by 2 smallest lithography sheets: white and upper ^ points; Λ conductor elements only appear in the array of intersections of multiple parallel sub-elements, each of which The character element is up to the gate structure of the semiconductor device; and the first row of the plurality of parallel bit lines, wherein each of the bits is upward of the upper source/drain of the semiconductor tree. Two rows and columns of miscellaneous materials U. An integrated circuit component of a semiconductor device array, comprising: a column, wherein the array has a first = 5 匕 row - a flea checkerboard array direction, the rows and columns are two and two; Oriented to the second; the smallest lithographic unit of the voxel and each of the semi-guided 'the _ character line is connected to the gate structure of the first-row row of the side-behind bovine conductor element; and the direction recovery element, wherein Each of the bit lines is orthogonal to the first row and the 70 lines intersect at a position of one of the semiconductor elements connected to the word line, and the upper source/drain of the semiconductor tree is light. 12. An integral circuit element of a 2F2 semiconductor device array, comprising: an array of semiconductor elements arranged in an array, wherein the early illusion/, the first 仃 column direction, and the second row direction a third row and column direction and 1309076 have a fourth row and column direction, and the first row and column direction is orthogonal to the second row and column = the third row and column direction has a 45. An angle between the third row and the semiconductor elements and the intersection of the semiconductor elements in the direction of the first row and the column, the first row and the column are adjacent to each other in the second column direction The intersection point is substantially separated by V2 minimum lithography units &quot;; one, a plurality of parallel word lines 'where each of the characters_connected_third line up the gate structure of each of the semiconductor elements; and the complex number And a parallel bit line, wherein each of the bit lines is connected to the upper source/drain of the fourth upper semiconductor element. A method of fabricating a semiconductor device, the method comprising: (a) providing a substrate comprising a trench; (b) forming a capacitor structure in the trench, the capacitor structure comprising: an electrode a - a first conductive layer, and a dielectric layer is located between the electrical layers; a Z-V (e) forms a source/drain outside the trench and adjacent to the first conductive substrate; a (Φ formation a second conductive layer is in contact with the first conductive layer to form an upper pole ′ and the second conductive layer is in contact with the lower source/drain; (e) forming a second dielectric layer covering the upper electrode; (f) removing a portion of the substrate to form a ring-shaped structure surrounding the second dielectric layer, and the lower source/drainage system is located in a lower region of the annular structure; g) removing a portion of the second dielectric layer to expose an upper region of the annular structure, (=) forming-upper source/not exceeding the upper region, wherein the upper source level is at the source/ Above the pole, and there is a passage zone between the upper source/drain and the lower source/drain; and the electric layer county structure, (10) The method of claim 13, wherein the lower source/drain is a source, and the upper source/drain is a drain. The method of claim 13, wherein after the step (1), further comprising forming a word line in contact with the gate structure. 16. The method of claim 13, wherein after the step (1), further comprising forming a A bit line covering the second dielectric layer and in contact with the upper source/drain.