Claims (1)
1308789 十、申請專利範圍： 1. 一種嵌埋有晶片之承載板結構，包括： ^ 一鋁載板，該鋁載板之表面以氧化法形成有至少一 氧化鋁層，並具有至少一開口； 「晶片，該晶片係嵌埋於該開口中，並具有一主動 面，複數個電極墊係配置於該晶片之主動面；以及 至少-線路增層結構，該線路增層結構係配置於該 =载板表面、該晶片之主動面、與該電極塾之表面，其 中，錢路增層結構至少具有_對應於該電極墊之一導 電結構’且至少一該導電結構電性連接於該電極塾。 社構W申請專利範圍第1項所述之歲埋有晶片之承載板 ’該銘載板之上表面與下表面各形成有-該氧 15 20 圍第2項所述之嵌埋有晶片之承載板 、。冓〃中，該乳化銘層係利用陽極氧化法形成。 4. 如申請專利範圍第丨項所述之嵌埋有晶片之 〜構，其中，該等電極墊係為鋁墊或銅墊。 5. 如巾請專利範圍^項所述之心有晶片之承载板 n，該氧化鋁載板與該晶片之間填充有-環氧樹 曰，以固定該晶片於該氡化鋁載板之該開口中。 6‘如申請專利範圍第1項所述之嵌埋有晶片 板結構，：中，該氧》奴鄱缸 之承栽 "、中Μ仙載板與該晶片之間填充有 層材料’以固定該晶片於該氧化銘載板之該開口,中。^ 17 1308789 纯構I//請專利範圍第1項所述之嵌埋有晶片之承载板 其中，該線路增層結構係包括有—介電層介電層、 /置於該介電層介電層上之線路層、以及至少— ^結構，且至少一該導電結構穿過該介電層介電層以 線路層電性連接至該介電層介電層下方之線路層:電 8.如申請專利項所述之嵌埋有w 結構，其中，該線路增層結構 10 層形成有開口以供設置焊編tr谭層，防焊 接。 又置㈣凸塊並與線路增層結構電性導 括：9.—㈣埋有晶片之承餘之製造方法，其步驟包 (A) 提供一鋁載板； (B) 氧化該鋁載板’使該鋁栽 15 化鋁層； 呂載板之表面形成有至少一氧 (C) 於該|呂載板形成一開口； 中，(Γ:，、曰:片散入並固定於該氧化銘載板之該開口 ▲該阳片之主動面具有複數個電極墊；以及 20 表面形)成/氧化紹載板、該晶片之主動面、與該電極塾之 線路增層結構，其中，該線路增層結構至 八、有冑應於該電極塾之導電結構， 構電性連接於該電極墊。 ^忒V電結 18 !3〇8789 ,/0·如巾請專利_第9項所述之喪埋有晶片之承載板 ，其中，於步驟(Β)中，該氧化鋁層係利用陽極 之請翻範㈣9項所述之嵌埋有晶片之承載板 製仏方法’其中，於步驟⑻中，該銘載板之上表 表面各形成有一該氡化層。 〃、 之二如法申請範圍第9項所述之散埋有晶片之承載板 上方法’其中，於步驟⑼中’該等電極塾係為銘塾或 10 15 20 之製請/利範圍第9項所述之㈣有晶片之承載板 之門^中，於步驟⑼中’該氧化銘载板與該晶片 之;環氧樹脂層’以固定該晶片於該氧化-載板 板二:範圍第9項所述之篏埋有晶片之承載 片之門埴η於步驟(d)中，該氧化銘载板與該晶 板之；開介電層材料’以固定該晶片於該氧化紹載 之製^第9項所述之㈣有晶片之承载板 層結構係;括;:步:該步驟⑻中’形成該至少-線路增 於該氧化紹載板、該晶片之主動面、與該 介介電層介電層’且使該介電層介電層形成複數個 於該晶片之該電極墊位置； 介電層開口係對應 19 1308789 •» 於該介電層介電層及該介電層介電層開口表面形成一 晶種層； 於該晶種層表面形成一阻層，使該阻層形成複數個阻 層開口，其中，至少一阻層開口係對應至該晶片之該電極 5 墊之位置； 於該複數個阻層開口電鍍一層電鍍金屬層；以及 移除該晶種層與該阻層，其中該電鍍金屬層至少包含 有一線路層及一導電結構。 Φ 16.如申請專利範圍第15項所述之嵌埋有晶片之承載 10 板之製造方法，其中，該介電層介電層係至少一選自由 ABF(Ajinomoto Build-up Film)、雙順丁 酸二酸酿亞胺 /三氮 啡（BT，Bismaleimide triazine)、聯二苯環 丁二稀 (benzocylobutene ; BCB)、液晶聚合物（Liquid Crystal Polymer)、聚亞酿胺（Polyimide ; PI)、聚乙烯醚 15 (Poly(phenylene ether))、 聚四 It 乙烯（Poly (tetra-fluoroethylene))、芳香尼龍（Aramide)、環氧樹脂以及 ^ 玻璃纖維之材質組成之群組。 17.如申請專利範圍第15項所述之嵌埋有晶片之承載 板之製造方法，其中，該電鍍金屬層係為銅、錫、鎳、鉻、 20 把、欽、錫/錯或其合金。 201308789 X. Patent application scope: 1. A carrier board structure embedded with a wafer, comprising: an aluminum carrier board having a surface formed by oxidation forming at least one aluminum oxide layer and having at least one opening; a wafer, the wafer is embedded in the opening, and has an active surface, a plurality of electrode pads are disposed on the active surface of the wafer; and at least a line build-up structure, the line build-up structure is disposed at the = a surface of the carrier, an active surface of the wafer, and a surface of the electrode, wherein the credit enhancement structure has at least one conductive structure corresponding to the electrode pad and at least one of the conductive structures is electrically connected to the electrode The fabric W applies for the wafer-bearing carrier plate of the first aspect of the patent application, and the upper surface and the lower surface of the inscription carrier are each formed with the embedded wafer described in item 2 of the oxygen 15 20 In the carrier plate, the emulsified layer is formed by anodization. 4. The embedded structure of the wafer is as described in the scope of the patent application, wherein the electrode pads are aluminum pads. Or copper pad. The core of the patent item has a carrier board n for the wafer, and the alumina carrier board and the wafer are filled with an epoxy tree raft to fix the wafer in the opening of the aluminum halide carrier. 'The embedded wafer structure as described in claim 1 of the patent scope, wherein: the carrier of the oxygen slave cylinder", the carrier of the Zhongyuxian carrier and the wafer is filled with a layer material to fix The wafer is in the opening of the oxidized inscription board, and is in the form of a wafer-embedded carrier board as described in claim 1, wherein the line build-up structure includes a dielectric layer, a wiring layer disposed on the dielectric layer of the dielectric layer, and at least a structure, and at least one of the conductive structures is electrically connected to the dielectric layer through the dielectric layer a circuit layer under the dielectric layer of the dielectric layer: electricity 8. The embedded w structure is as described in the patent application, wherein the 10 layers of the line build-up structure are formed with openings for providing a soldering tan layer, anti-welding The (4) bumps are also electrically connected to the line build-up structure: 9. (4) Fabrication of the buried chip Method, the step package (A) provides an aluminum carrier plate; (B) oxidizes the aluminum carrier plate to make the aluminum layer 15 aluminum layer; the surface of the ruthenium plate is formed with at least one oxygen (C) in the Forming an opening; in the middle, (Γ:, 曰: the sheet is scattered and fixed to the opening of the oxidized inscription board ▲ the active surface of the positive sheet has a plurality of electrode pads; and 20 surface shape) The carrier board, the active surface of the wafer, and the line build-up structure of the electrode ,, wherein the line build-up structure is connected to the conductive pad of the electrode ,, and is electrically connected to the electrode pad.忒V electric junction 18 !3〇8789, /0·, as described in the patent _ ninth item, the carrier board of the buried wafer, wherein in the step (Β), the aluminum oxide layer utilizes the anode The method for manufacturing a carrier plate embedded with a wafer according to the above-mentioned item (4), wherein in the step (8), the surface of the surface of the inscription plate is formed with a vaporization layer. 〃, 之 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 如 散 散 散 散 散 散 散 散 散 散 散 散 散 散 散 散 散 散 散 散 散 散In the case of the (4) wafer carrier board, in the step (9), the oxide layer is bonded to the wafer; the epoxy layer is used to fix the wafer to the oxidation-carrier board 2: In the step (d), the etched imprinting plate and the crystal plate are opened; the dielectric layer material is opened to fix the wafer in the oxidized load. (4) a carrier layer structure of the wafer according to item 9; comprising: step: in the step (8), 'forming the at least-line is added to the oxide carrier, the active surface of the wafer, and the Dielectric layer dielectric layer 'and dielectric layer of the dielectric layer forming a plurality of locations on the electrode pad of the wafer; dielectric layer opening corresponding to the dielectric layer of the dielectric layer and the dielectric layer a seed layer is formed on the opening surface of the dielectric layer; a resist layer is formed on the surface of the seed layer, so that the resist layer forms a plurality of resistors a layer opening, wherein at least one resist opening corresponds to a position of the electrode 5 pad of the wafer; plating a layer of a plating metal on the plurality of resist layers; and removing the seed layer and the resist layer, wherein The electroplated metal layer includes at least one wiring layer and a conductive structure. Φ 16. The method for manufacturing a wafer-laden carrier 10 according to claim 15, wherein the dielectric layer is at least one selected from the group consisting of ABF (Ajinomoto Build-up Film) and Butyric acid diamine (Bismaleimide triazine), benzocylobutene (BCB), liquid crystal polymer (Liquid Crystal Polymer), polyimide (Polyimide; PI), A group consisting of Poly(phenylene ether), Poly (tetra-fluoroethylene), Aramide, epoxy, and glass fiber. 17. The method of manufacturing a wafer-embedded carrier plate according to claim 15, wherein the plated metal layer is copper, tin, nickel, chromium, 20, chin, tin/wrong or alloy thereof. . 20