TWI308786B - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
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- TWI308786B TWI308786B TW095106568A TW95106568A TWI308786B TW I308786 B TWI308786 B TW I308786B TW 095106568 A TW095106568 A TW 095106568A TW 95106568 A TW95106568 A TW 95106568A TW I308786 B TWI308786 B TW I308786B
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- E—FIXED CONSTRUCTIONS
- E06—DOORS, WINDOWS, SHUTTERS, OR ROLLER BLINDS IN GENERAL; LADDERS
- E06B—FIXED OR MOVABLE CLOSURES FOR OPENINGS IN BUILDINGS, VEHICLES, FENCES OR LIKE ENCLOSURES IN GENERAL, e.g. DOORS, WINDOWS, BLINDS, GATES
- E06B9/00—Screening or protective devices for wall or similar openings, with or without operating or securing mechanisms; Closures of similar construction
- E06B9/24—Screens or other constructions affording protection against light, especially against sunshine; Similar screens for privacy or appearance; Slat blinds
- E06B9/40—Roller blinds
- E06B9/42—Parts or details of roller blinds, e.g. suspension devices, blind boxes
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- Engineering & Computer Science (AREA)
- Structural Engineering (AREA)
- Architecture (AREA)
- Civil Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Description
1308786 令7.年力2 If丨1308786 Order 7. Annual strength 2 If丨
九、發明說明： 【發明所屬之技術領域】 本發明涉及製造半導體元件的方法；並且更具體地，涉 及在閘極圖案之間形成接觸塞的方法。 【先前技術】 隨著半導體技術的改進，在晶片上形成圖案的圖案化 ' 技術也已逐漸得到改進。最近的圖案化技術已能夠在晶片 ' 上形成80 nm以下的圖案。在能夠圖案化80 nm以下的半導 ^ 體技術中，產生了關於形成接觸塞的區域的限制。特別地， 穩定地形成設置在閘極圖案之間的接觸塞極其困難。在 此，閘極圖案組成半導體元件的電晶體。 半導體元件中的閘極圖案包括閘極絕緣層、閘極電極 和閘極硬掩模，並按順序次序堆疊。在此’間隔物形成於 閘極圖案的側壁上。側壁間隔物提供閘極電極和相鄰傳導 層之間的電絕緣。此外，側壁間隔物在用於形成接觸塞的 接觸孔形成過程期間用做蝕刻停止層。 ® 隨著半導體技術的改進，更多元件集成爲單個半導體 元件。因而，組成半導體元件的每一圖案的尺寸已減小。 特別地，閘極圖案的尺寸以及閘極圖案之間的間隔距離已 減小。然而，閘極圖案的側壁絕緣層’即側壁間隔物，通 常需要維持特定厚度以具有上述的絕緣效果並用做蝕刻停 止層。 因此，在閘極圖案之間穩定地形成接觸塞極其困難， 因爲閘極圖案之間的間隔距離已經減小而側壁絕緣層的所 1308786 “年ΰ A: :π修(更)正替換頁 需厚度仍維持。例如，儘管在以傳統的80 nm的半導體技術 技術製造的元件中所要求的側壁絕緣層通常需要以範圍從 大約280A到大約300A的幾乎均勻的厚度來形成，閘極圖 案之間的間隔距離卻連續減小。 閘極圖案之間的間隔距離的減小導致用於形成閘極圖 案之間的接觸塞的接觸孔內部的高寬比增加。因此，在隨 後技術期間難以完全掩埋接觸孔內部的層間絕緣層。 第1圖是說明製造半導體元件的傳統方法的橫截面視 ’圖。 如第1圖所示，閘極圖案形成於基板1 1上。在此，閘 極圖案的每一個包括按順序次序形成的閘極絕緣層1 2、閘 極電極13和聞極硬掩模14。 關於單個間極圖案形成方法的細節在下文敍述。間極 絕緣層1 2形成於基板1 1上。然後，閘極電極1 3和閘極硬 掩模1 4順序地形成於聞極絕緣層1 2上。隨後，儘管未加以 說明，光刻膠圖案形成於閘極硬掩模1 4上以形成閘極圖 B 案。在使用光刻膠圖案作爲蝕刻掩模來蝕刻閘極硬掩模1 4 後，移除光刻膠圖案。此外，使用閘極硬掩模1 4作爲蝕刻 掩模在一個技術中圖案化閘極電極1 3和閘極絕緣層1 2。 隨後，用於閘極側壁間隔物的緩衝氧化物層1 5形成於 閘極圖案上，所述閘極圖案的每一個包括閘極絕緣層1 2、 閘極電極1 3和閘極硬掩模1 4。第一氮化物層1 6形成於緩 衝氧化物層1 5上。在此，第一氮化物層1 6用做第一閘極間 隔物。接著，形成第二氮化物層1 7。在此，第二氮化物層 1308786 1 7用做第二間隔物。 此外，通過幹蝕刻技術選擇性地移除緩衝氧化物層 1 5、第一氮化物層1 6以及第二氮化物層1 7，使得間隔物只 保留在閘極圖案的側壁上。 在此，間隔物用做閘極圖案的閘極電極和相鄰傳導層 之間的絕緣。詳細地，形成氮化物層以在用於形成閘極圖 案之間的接觸塞的接觸孔形成技術中保護單個閘極圖案。 即，氮化物層在接觸孔蝕刻技術期間用做蝕刻阻擋，所述 蝕刻技術移除掩埋在閘極圖案之間的絕緣層。在此，兩次 形成並圖案化氮化物層，因爲由於氮化物層的形成特性， 一次難於獲得所希望的厚度。 而且，當製造半導體元件時，兩次形成氮化物層以改 進包括閘極圖案的金屬氧化物半導體（MOS )電晶體的特 性。半導體元件的一個工作特性是洩漏電流特性。當MOS 電晶體的洩漏電流特性最大程度減小時，工作特性得以改 進。通過在包括MOS電晶體的閘極圖案的側壁上形成特定 厚度的氮化物層，MOS電晶體的洩漏電流特性可得到改 進。因而，在閘極圖案的側壁上所形成的氮化物層以足夠 大的厚度形成，以改進MOS電晶體的洩漏電流特性。 而且，使用閘極圖案作爲離子注入阻擋，執行高濃度 離子注入技術以形成源/汲區1 8和1 8 A。在此，源/汲區1 8 A 代表輕度摻雜的汲（LDD)區。 接著，氧化物系的層間絕緣層1 9形成於以上得到的基 板結構上。 1308786 9义修(更)正替換頁 在此，使用氧化物系的絕緣層形成層間絕緣層1 9。氧 化物系的絕緣層可由硼矽酸鹽玻璃（B S G )層、硼磷矽酸鹽 玻璃（BPSG)層、磷矽酸鹽玻璃（PSG)層、原矽酸四乙酯 (TEOS )層、高密度等離子體（HDP )氧化物層、玻璃上 旋塗（SOG)層以及預平坦化層（APL)組成。同樣，無機 或有機的低K電介質層可代替氧化物系的層而使用。 隨後，執行化學機械拋光（CMP )技術或毯式回蝕刻 (blanket etch-back)技術以平坦化層間絕緣層19，從而暴 t 露閘極圖案的閘極硬掩模1 4的頂部。然後，儘管未示出， 硬掩模形成於平坦化的層間絕緣層1 9上。 此外，執行蝕刻技術以形成接觸孔20，所述蝕刻技術 使用硬掩模作爲蝕刻掩模來暴露基板1 1在閛極圖案之間的 部分。 上述製造半導體元件的傳統方法通常顯示如下所述的 局限性。 隨著半導體製造技術的改進，更多元件集成爲單個半 > 導體元件，因而，閘極圖案之間的間隔距離逐漸減小。然 而，形成於每一閘極圖案的側壁上的間隔物通常需要維持 特定厚度以減少包括閘極圖案的電晶體的特性退化。 因而，隨著聞極圖案之間的間隔距離由於提高的集成 度而減小，蝕刻技術中用於在帶有間隔物的閘極圖案之間 形成接觸孔的裕度（m a r g i η)也逐漸減小。 當製造80 nm以下的半導體元件時，通常難以在閘極 圖案之間穩定地形成接觸孔和接觸塞而同時維持閘極間隔 1308786[Technical Field] The present invention relates to a method of manufacturing a semiconductor element; and more particularly, to a method of forming a contact plug between gate patterns. [Prior Art] With the improvement of semiconductor technology, the patterning technique for forming patterns on a wafer has also been gradually improved. Recent patterning techniques have been able to form patterns below 80 nm on the wafer'. In the semi-conducting technique capable of patterning below 80 nm, a limitation is imposed on the region in which the contact plug is formed. In particular, it is extremely difficult to stably form the contact plugs disposed between the gate patterns. Here, the gate pattern constitutes a transistor of a semiconductor element. The gate pattern in the semiconductor element includes a gate insulating layer, a gate electrode, and a gate hard mask, and is stacked in order. Here, the spacer is formed on the sidewall of the gate pattern. The sidewall spacers provide electrical isolation between the gate electrode and the adjacent conductive layer. Further, the sidewall spacers are used as an etch stop layer during the contact hole forming process for forming the contact plug. ® As semiconductor technology improves, more components are integrated into a single semiconductor component. Thus, the size of each pattern constituting the semiconductor element has been reduced. In particular, the size of the gate pattern and the separation distance between the gate patterns have been reduced. However, the sidewall insulating layer of the gate pattern, i.e., the sidewall spacer, is usually required to maintain a specific thickness to have the above-described insulating effect and to be used as an etch stop layer. Therefore, it is extremely difficult to stably form the contact plug between the gate patterns because the separation distance between the gate patterns has been reduced and the 1308786 of the sidewall insulating layer "year ΰ A: : π repair (more) is required to replace the page The thickness is still maintained. For example, although the sidewall insulating layers required in components fabricated in conventional 80 nm semiconductor technology typically need to be formed with an almost uniform thickness ranging from about 280 A to about 300 A, between the gate patterns. The separation distance is continuously decreased. The decrease in the separation distance between the gate patterns leads to an increase in the aspect ratio of the inside of the contact holes for forming the contact plugs between the gate patterns. Therefore, it is difficult to completely bury them in the subsequent technology. An interlayer insulating layer inside the contact hole. Fig. 1 is a cross-sectional view showing a conventional method of manufacturing a semiconductor device. As shown in Fig. 1, a gate pattern is formed on a substrate 11. Here, a gate pattern is formed. Each of the gate insulating layer 2, the gate electrode 13, and the smear hard mask 14 are formed in a sequential order. Details of the method of forming a single interpole pattern are described below. A layer 12 is formed on the substrate 11. Then, a gate electrode 13 and a gate hard mask 14 are sequentially formed on the gate insulating layer 12. Subsequently, although not illustrated, a photoresist pattern is formed on The gate hard mask 14 is formed to form a gate pattern B. After the gate hard mask 14 is etched using the photoresist pattern as an etch mask, the photoresist pattern is removed. Further, the gate is hard. The mask 14 is used as an etch mask to pattern the gate electrode 13 and the gate insulating layer 12 in one technique. Subsequently, a buffer oxide layer 15 for the gate sidewall spacer is formed on the gate pattern, Each of the gate patterns includes a gate insulating layer 12.2, a gate electrode 13 and a gate hard mask 14. The first nitride layer 16 is formed on the buffer oxide layer 15. Here, The first nitride layer 16 is used as the first gate spacer. Next, the second nitride layer 17 is formed. Here, the second nitride layer 1308786 1 7 is used as the second spacer. The technique selectively removes the buffer oxide layer 15, the first nitride layer 16 and the second nitride layer 17 such that the spacers are only protected On the sidewall of the gate pattern. Here, the spacer serves as insulation between the gate electrode of the gate pattern and the adjacent conductive layer. In detail, a nitride layer is formed to be used between the gate patterns for forming The contact plug formation technique of the contact plug protects a single gate pattern. That is, the nitride layer is used as an etch stop during the contact hole etch technique, which removes the insulating layer buried between the gate patterns. The nitride layer is formed and patterned twice because it is difficult to obtain a desired thickness at a time due to the formation characteristics of the nitride layer. Moreover, when a semiconductor element is fabricated, a nitride layer is formed twice to improve metal oxidation including a gate pattern. Characteristics of a semiconductor (MOS) transistor. One operating characteristic of a semiconductor device is leakage current characteristics. When the leakage current characteristics of the MOS transistor are minimized, the operational characteristics are improved. The leakage current characteristics of the MOS transistor can be improved by forming a nitride layer of a specific thickness on the sidewall of the gate pattern including the MOS transistor. Thus, the nitride layer formed on the sidewall of the gate pattern is formed with a sufficiently large thickness to improve the leakage current characteristics of the MOS transistor. Moreover, using a gate pattern as an ion implantation barrier, a high concentration ion implantation technique is performed to form source/deuterium regions 18 and 18 A. Here, the source/deuterium region 18 A represents a lightly doped germanium (LDD) region. Next, an oxide-based interlayer insulating layer 19 is formed on the substrate structure obtained above. 1308786 9 Revision (More) Positive Replacement Page Here, an interlayer insulating layer 19 is formed using an oxide-based insulating layer. The oxide-based insulating layer may be a borosilicate glass (BSG) layer, a borophosphonite glass (BPSG) layer, a phosphosilicate glass (PSG) layer, a tetraethyl orthosilicate (TEOS) layer, and a high layer. A density plasma (HDP) oxide layer, a spin on glass (SOG) layer, and a pre-planarization layer (APL). Similarly, an inorganic or organic low-k dielectric layer can be used in place of the oxide-based layer. Subsequently, a chemical mechanical polishing (CMP) technique or a blanket etch-back technique is performed to planarize the interlayer insulating layer 19, thereby exposing the top of the gate hard mask 14 of the gate pattern. Then, although not shown, a hard mask is formed on the planarized interlayer insulating layer 19. In addition, an etching technique is performed to form contact holes 20 that expose a portion of the substrate 11 between the drain patterns using a hard mask as an etch mask. The above conventional methods of manufacturing semiconductor elements generally exhibit the limitations described below. As semiconductor manufacturing techniques improve, more components are integrated into a single half > conductor element, and thus, the separation distance between the gate patterns is gradually reduced. However, the spacers formed on the sidewalls of each gate pattern generally need to maintain a certain thickness to reduce the characteristic degradation of the transistor including the gate pattern. Thus, as the separation distance between the gate patterns is reduced due to increased integration, the margin (margi η) for forming contact holes between the gate patterns with spacers in the etching technique is also gradually reduced. small. When manufacturing semiconductor elements of 80 nm or less, it is generally difficult to stably form contact holes and contact plugs between gate patterns while maintaining gate spacing 1308786
物的必要厚度。 形成於閘極圖案之間的接觸塞通常是半導體元件中極 其基本的傳導連接單元。如果半導體元件製造成具有不良 的接觸塞，則元件幾乎不可能穩定地工作。 【發明內容】 因此，本發明的一個目的是提供製造半導體元件的方 ' 法，所述方法能夠確保形成於閘極圖案之間的接觸孔的開 - 口裕度和間隙塡充裕度。 ® 根據本發明的一方面，提供了一種製造半導體元件的 方法，包括：在基板上形成至少兩個閘極圖案；在包括閘 極圖案的整個基板結構上形成第一側壁層；在第一側壁層 上形成絕緣層；選擇性地移除所述閘極圖案之間的絕緣 層，以形成部分地暴露第一側壁層的接觸孔；在由接觸孔 暴露的第一側壁層上形成第二側壁層；以及移除設置在接 觸孔底部的第一和第二側壁層，以暴露基板在閘極圖案之 間的所選部分。 # 根據本發明的另一方面，提供了一種製造半導體元件 的方法，包括：在基板上形成至少兩個閘極圖案；在所述 閘極圖案的側壁上形成第一間隔物；在所述閘極圖案上形 成絕緣層；選擇性地移除所述閘極圖案之間的絕緣層以形 成接觸孔，所述接觸孔暴露基板在所述閘極圖案之間的部 分；在由接觸孔暴露的第一間隔物和基板的部分上形成間 隔物層；以及移除設置在接觸孔底部的間隔物層，以在第 一間隔物上形成第二間隔物。 1308786 根據本發明的又一方面，提供了一種製造半導體元件 的方法，包括：在基板上形成至少兩個閘極圖案；在包括 所述閘極圖案的整個基板結構上形成第一側壁層；在第一 側壁層上形成輔助側壁層；在輔助側壁層上形成絕緣層； 選擇性地移除所述閘極圖案之間的絕緣層’以形成部分地 暴露輔助側壁層的接觸孔；在由接觸孔暴露的輔助側壁層 上形成第二側壁層；以及移除設置在接觸孔底部的第一側 壁層、輔助側壁層和第二側壁層，以暴露基板在閘極圖案 之間的部分。 根據本發明的再一方面，提供了一種製造半導體元件 的方法，包括：在基板上形成至少兩個閘極圖案；在所述 閘極圖案的側壁上形成第一間隔物；在第一間隔物上形成 輔助間隔物；在所述閘極圖案上形成絕緣層；移除在所述 閘極圖案之間的絕緣層以形成接觸孔，所述接觸孔暴露基 板在所述閘極圖案之間的部分；在接觸孔的內部上形成間 隔物層；以及移除設置在接觸孔底部的間隔物層，以在輔 助間隔物上形成第二間隔物。 【實施方式】 根據本發明的一個實施例的製造半導體元件的方法， 包括：在基板上形成至少兩個聞極圖案；在包括閘極圖案 的整個基板結構上形成第一側壁層；在第一側壁層上形成 絕緣層；選擇性地移除所述閘極圖案之間的絕緣層，以形 成部分地暴露第一側壁層的接觸孔；在由接觸孔暴露的第 一側壁層上形成第二側壁層；以及移除設置在接觸孔底部 1308786 的 第 -- 和 第 二 側 壁 層 以 所 公BB 部 分 〇 根 據 本 發 明 的 另 一 實 包 括 在 基 板 上 形 成 至 少 的 側 壁 上 形 成 第 — 間 隔 物 層 t ίΒΒ m 擇 性 地 移 除 所 述 閘 孔 > 所 述 接 觸 孔 暴 露 基 板 由 接 觸 孔 暴 露 的 第 一 間 隔 層 > 以 及 移 除 設 置 在 接 觸 隔 物 上 形 成 第 二 間 隔 物 0 根 據 本 發 明 的 又 — 實 包 括 在 包 括 閘 極 圖 案 的 層 > 在 第 •-- 側 壁 層 上 形 成 成 絕 緣 層 » 選 擇 性 地 移 除 形 成 部 分 地 暴 露 輔 助 側 壁 輔助側壁層上形成第二側 部的第一側壁層、輔助側 在閘極圖案之間的部分。 根據本發明的再一實 包括：在基板上形成至少 的側壁上形成第一間隔物 物；在所述閘極圖案上形 之間的絕緣層以形成接觸 閘極圖案之間的部分；在 暴露基板在所述閘極圖案之間的 施例的製造半導體元件的方法， 兩個閘極圖案；在所述閘極圖案 ;在所述閘極圖案上形成絕緣 極圖案之間的絕緣層以形成接觸 在所述閘極圖案之間的部分；在 物和基板的部分上形成間隔物 孔底部的間隔物層，以在第一間 施例的製造半導體元件的方法， 整個基板結構上形成第一側壁 輔助側壁層；在輔助側壁層上形 所述閘極圖案之間的絕緣層，以 層的接觸孔；在由接觸孔暴露的 壁層；以及移除設置在接觸孔底 壁層和第二側壁層，以暴露基板 施例的製造半導體元件的方法， 兩個閘極圖案；在所述閘極圖案 ;在第一間隔物上形成輔助間隔 成絕緣層；移除在所述閘極圖案 孔，所述接觸孔暴露基板在所述 接觸孔的內部上形成間隔物層； -11- 1308786 ，7.钟H日修(更)正替換頁 ~ """""" 1 " ......11 I丨 I I — 以及移除設置在接觸孔底部的間隔物層，以在輔助間隔物 上形成第二間隔物。 在下文中’將參考附圖提供對本發明的某些實施例的 詳細描述。 第2A圖到第2C圖是說明根據本發明的第一實施例的 製造半導體元件的方法的橫截面視圖。 參考第2A圖，在基板21上形成了多個閘極圖案。閘 ' 極圖案的每一個通過以順序次序堆疊閘極絕緣層22、閘極 ® 電極層2 3和閘極硬掩模2 4而形成。 在關於形成閘極圖案的更多細節中，閘極絕緣層2 2形 成於基板2 1上。閘極電極層23和閘極硬掩模24順序地形 成於聞極絕緣層22上。儘管未加以說明，光刻膠圖案形成 於閘極硬掩模24上。使用光刻膠圖案作爲蝕刻掩模來蝕刻 閘極硬掩模24，然後移除光刻膠圖案。使用硬掩模24作爲 鈾刻掩模通過一個蝕刻技術將閘極電極層23和閛極絕緣層 2 2圖案化。 # 使用閘極圖案作爲離子注入阻擋來執行高度摻雜的離 子注入技術，從而形成多個源/汲區2 8。 氧化物系的層25和第一氮化物系的層26順序地形成於 閘極圖案上。氧化物系的層2 5可以是緩衝氧化物層。氧化 物系的層25和第一氮化物系的層可用做第一閘極間隔物。 對第一氮化物系的層26來說’第一氮化物系的層26 的厚度通過考慮其在隨後的技術以及輕度摻雜的汲（LD D ) 區形成期間作爲蝕刻停止層的角色來確定。在此’第一氮 1308786 .…:： — r._ ： 化物系的層26可以範圍從大約50A到大約250A的厚度形 成。優選地’第一氮化物系的層26的厚度範圍從大約80A 到大約1 2 0 A。The necessary thickness of the object. The contact plug formed between the gate patterns is typically a very basic conductive connection unit in the semiconductor component. If the semiconductor element is fabricated to have a poor contact plug, it is almost impossible for the element to operate stably. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor device which is capable of ensuring an opening margin and a gap margin of a contact hole formed between gate patterns. In accordance with an aspect of the present invention, a method of fabricating a semiconductor device includes: forming at least two gate patterns on a substrate; forming a first sidewall layer over the entire substrate structure including the gate pattern; Forming an insulating layer on the layer; selectively removing the insulating layer between the gate patterns to form a contact hole partially exposing the first sidewall layer; forming a second sidewall on the first sidewall layer exposed by the contact hole a layer; and removing the first and second sidewall layers disposed at the bottom of the contact hole to expose selected portions of the substrate between the gate patterns. According to another aspect of the present invention, there is provided a method of fabricating a semiconductor device, comprising: forming at least two gate patterns on a substrate; forming a first spacer on a sidewall of the gate pattern; Forming an insulating layer on the pole pattern; selectively removing an insulating layer between the gate patterns to form a contact hole, the contact hole exposing a portion of the substrate between the gate patterns; and being exposed by the contact hole A spacer layer is formed on a portion of the first spacer and the substrate; and a spacer layer disposed at a bottom of the contact hole is removed to form a second spacer on the first spacer. 1308786 According to still another aspect of the present invention, a method of fabricating a semiconductor device includes: forming at least two gate patterns on a substrate; forming a first sidewall layer over the entire substrate structure including the gate pattern; Forming an auxiliary sidewall layer on the first sidewall layer; forming an insulating layer on the auxiliary sidewall layer; selectively removing the insulating layer between the gate patterns to form a contact hole partially exposing the auxiliary sidewall layer; Forming a second sidewall layer on the exposed sidewall layer of the hole; and removing the first sidewall layer, the auxiliary sidewall layer, and the second sidewall layer disposed at the bottom of the contact hole to expose a portion of the substrate between the gate patterns. According to still another aspect of the present invention, a method of fabricating a semiconductor device, comprising: forming at least two gate patterns on a substrate; forming a first spacer on a sidewall of the gate pattern; and forming a first spacer on the sidewall Forming an auxiliary spacer thereon; forming an insulating layer on the gate pattern; removing an insulating layer between the gate patterns to form a contact hole, the contact hole exposing a substrate between the gate patterns a portion; forming a spacer layer on the inside of the contact hole; and removing the spacer layer disposed at the bottom of the contact hole to form a second spacer on the auxiliary spacer. [Embodiment] A method of fabricating a semiconductor device according to an embodiment of the present invention includes: forming at least two smear patterns on a substrate; forming a first sidewall layer on an entire substrate structure including a gate pattern; Forming an insulating layer on the sidewall layer; selectively removing the insulating layer between the gate patterns to form a contact hole partially exposing the first sidewall layer; forming a second on the first sidewall layer exposed by the contact hole a sidewall layer; and removing the first and second sidewall layers disposed at the bottom 1308786 of the contact hole to form a first spacer layer on the substrate, at least the sidewalls formed on the substrate择 择 selectively removing the gate hole > the contact hole exposing the first spacer layer exposed by the contact hole of the substrate > and removing the second spacer formed on the contact spacer to form a second spacer 0 according to the present invention — actually included in the layer including the gate pattern> in the - shaped upper side wall layer so as insulating layer >> selectively displacing the first side wall layer of the second side portion, the secondary-side portion between the gate pattern is formed on the partition to expose the auxiliary side wall of the auxiliary side wall layer other forming portion. According to still another aspect of the present invention, a first spacer is formed on at least a sidewall formed on a substrate; an insulating layer is formed on the gate pattern to form a portion between the contact gate patterns; a method of fabricating a semiconductor device between the gate patterns of the substrate, two gate patterns; in the gate pattern; forming an insulating layer between the insulating pattern on the gate pattern to form Contacting a portion between the gate patterns; forming a spacer layer at the bottom of the spacer hole on the portion of the object and the substrate to form a first method on the entire substrate structure in the first embodiment of the method of fabricating the semiconductor device a sidewall auxiliary sidewall layer; an insulating layer between the gate patterns on the auxiliary sidewall layer, a contact hole of the layer; a wall layer exposed by the contact hole; and a layer disposed on the bottom layer of the contact hole and the second layer a sidewall layer, in a method of exposing a substrate for fabricating a semiconductor device, two gate patterns; in the gate pattern; forming an auxiliary spacer on the first spacer to form an insulating layer; removing the gate pattern a hole, the contact hole exposing the substrate to form a spacer layer on the inside of the contact hole; -11- 1308786, 7. clock H repair (more) is replacing the page ~ """""" 1 " ... 11 I丨II - and removing the spacer layer disposed at the bottom of the contact hole to form a second spacer on the auxiliary spacer. In the following, a detailed description of some embodiments of the invention will be provided with reference to the accompanying drawings. 2A to 2C are cross-sectional views illustrating a method of manufacturing a semiconductor element in accordance with a first embodiment of the present invention. Referring to FIG. 2A, a plurality of gate patterns are formed on the substrate 21. Each of the gate 'pole patterns is formed by stacking the gate insulating layer 22, the gate electrode layer 23, and the gate hard mask 24 in a sequential order. In more detail regarding the formation of the gate pattern, the gate insulating layer 22 is formed on the substrate 21. The gate electrode layer 23 and the gate hard mask 24 are sequentially formed on the gate insulating layer 22. Although not illustrated, a photoresist pattern is formed on the gate hard mask 24. The gate hard mask 24 is etched using the photoresist pattern as an etch mask, and then the photoresist pattern is removed. The gate electrode layer 23 and the gate insulating layer 2 2 are patterned by an etching technique using the hard mask 24 as an uranium engraving mask. # Using a gate pattern as an ion implantation barrier to perform a highly doped ion implantation technique to form a plurality of source/deuterium regions 28. The oxide-based layer 25 and the first nitride-based layer 26 are sequentially formed on the gate pattern. The oxide layer 25 can be a buffer oxide layer. The layer 25 of the oxide system and the layer of the first nitride system can be used as the first gate spacer. For the first nitride-based layer 26, the thickness of the 'first nitride-based layer 26' serves as an etch stop layer by considering its subsequent technique and the formation of a lightly doped ytterbium (LD D ) region. determine. Here, the layer 14 of the first nitrogen 1308786 ....:: - r._ : compound system may be formed to a thickness ranging from about 50 A to about 250 A. Preferably, the thickness of layer 14 of the first nitride system ranges from about 80 A to about 1 20 A.
接著’通過使用閘極圖案作爲離子注入阻擋來執行LDD 離子注入技術而形成多個LDD區28A。形成層間絕緣層29 以掩埋閘極圖案。層間絕緣層2 9包括氧化物系的絕緣層。 例如，氧化物系的絕緣層可以是從由硼矽酸鹽玻璃（B s G ) 層、硼磷矽酸鹽玻璃（BPSG)層、磷矽酸鹽玻璃（psG)層、 原砂酸四乙酯（TEOS)層、高密度等離子體（HDP)氧化物 層、玻璃上旋塗（SOG)層以及預平坦化層（APL)組成的 組中所選擇的一個。除氧化物系的絕緣層以外，也可以使 用無機或有機的低K電介質層。 儘管未加以說明’光刻膠圖案形成於層間絕緣層29上 以在閘極圖案之間形成接觸孔。因爲要形成的接觸孔是自 對準接觸，光刻膠圖案的寬度要大於接觸孔。Next, a plurality of LDD regions 28A are formed by performing an LDD ion implantation technique using a gate pattern as an ion implantation barrier. An interlayer insulating layer 29 is formed to bury the gate pattern. The interlayer insulating layer 29 includes an oxide-based insulating layer. For example, the oxide-based insulating layer may be from a borosilicate glass (B s G ) layer, a borophosphonite glass (BPSG) layer, a phosphosilicate glass (psG) layer, orthosilicate tetraethylate One selected from the group consisting of a TEOS layer, a high density plasma (HDP) oxide layer, a glass spin on coating (SOG) layer, and a pre-planarization layer (APL). In addition to the oxide-based insulating layer, an inorganic or organic low-k dielectric layer can also be used. Although not illustrated, a photoresist pattern is formed on the interlayer insulating layer 29 to form contact holes between the gate patterns. Since the contact holes to be formed are self-aligned contacts, the width of the photoresist pattern is larger than that of the contact holes.
使用光刻膠圖案作爲蝕刻阻擋來選擇性地移除層間絕 緣層2 9 ’從而形成第一接觸孔3丨。利用氧化物系的材料和 氮化物系的材料具有蝕刻選擇性的特性來實現對層間絕緣 層29的餓刻。層間絕緣層29可利用從CxFy族選擇的氣體 來蝕刻’其中代表原子比的X和y範圍從大約1到大約1 〇。 例如’基於CxFy的氣體可從由C4F6、C5F8、（^F8及C3F3組成 的組中選擇。此時，第一氮化物系的層26用做蝕刻停止層。 如所示的’在第一接觸孔3丨形成之後暴露了第一氮化 物系的層26的部分。儘管光刻膠圖案形成爲寬度大於接觸 1308786 97钟.摩1日敝)正雜頁 孔，但由於形成於閘極圖案上並用做餓刻停止層的第一氮 化物系的層26，可能形成具有所需寬度的接觸孔。 更詳細地，由於第一接觸孔3 1在第一氮化物系的層26 通過一個技術以單層形成的狀態下形成，形成第一接觸孔 31的技術在閘極圖案之間的距離比由傳統方法可實現的距 離寬的狀態下執行。 ' 儘管未加以說明，輔助的氮化物系的層可形成於第一 ' 氮化物系的層2 6上。輔助的氮化物系的層比第一氮化物系 ^ 的層26或將隨後形成的第二氮化物系的層更薄地形成。例 如輔助的氮化物系的層的厚度可以在從大約5 0 A到大約 1 5 0 A的範圍。在層間絕緣層2 9包括B P S G的情況下，輔助 的氮化物系的層起到減少在熱技術期間注入到源/汲區28 上的雜質（例如硼）擴散到基板2 1中的作用。換句話說， 輔助的氮化物系的層起到輔助間隔物的作用。 參考第2B圖，第二氮化物系的層30形成於第一接觸 孔31上。第二氮化物系的層30用做第二間隔物。 • 在此，第二氮化物系的層30的厚度通過考慮以下事實 來確定：第二氮化物系的層3 0和在用做形成接觸孔3 1的蝕 刻阻擋後所保留的第一氮化物系的層26的總厚度大於至少 不允許閘極圖案暴露的特定値。 此外，第二氮化物系的層30的厚度通過考慮以下事實 來確定：包括閘極圖案的金屬氧化物半導體（MOS )電晶體 的洩漏電流特性確定第二氮化物系的層30和在用做形成接 觸孔3 1的蝕刻阻擋後所保留的第一氮化物系的層2 6的總厚 -14- 1308786 97,梅.11日修(更)正替換頁 度。 參考第2C圖’執行餽刻技術以移除設置在第一接觸孔 31底部的氧化物系的層25、第一氮化物系的層26以及第二 氮化物系的層3 0。相應地，在閘極圖案的側壁上形成了多 個閘極間隔物。閘極間隔物的每一個包括圖案化的第二氮 化物系的層30A、圖案化的第一氮化物系的層26A和圖案化 的基於緩衝氧化物的層25A。然後，第二接觸孔32打開。 如上所述，首先以氧化物系的層和氮化物系的層的雙 結構形成第一閘極間隔物。然後，在閘極圖案之間形成接 觸孔’並利用另一個氮化物系的層，其後形成第二閘極間 隔物。因而，當接觸孔形成時閛極圖案之間的距離變得較 寬。相應地，接觸孔的高寬比大大改進，且因此隨後的技 術可更容易地執行。 由於閘極圖案之間的接觸孔的高寬比的減少，閘極圖 案之間的接觸孔的開口裕度大大增加。此外，由於減少的 高寬比，當接觸孔以層間絕緣層塡充時，間隙塡充裕度也 增加。相應地，接觸孔能在大約8 0 n m以下的半導體元件中 穩定地形成於閘極圖案之間。 本發明的第一實施例與任何特定類型的半導體元件無 關，並可利用氧化物系的層（例如氧化矽層）和氮化物系 的層（例如氮化矽層）的堆疊結構作爲閘極間隔物而應用 於各種類型的半導體元件。 第3 A圖到第3 E圖是說明根據本發明的第二實施例的 製造半導體元件的方法的橫截面視圖。 1308786 如第3 A圖所示，多個閘極圖案1 1 4形成於提供有元件 絕緣層（未示出）和阱（未示出）的基板1 1 0上。閘極圖案 1 1 4的每一個通過順序地堆疊閘極絕緣層111、閘極電極層 1 1 2和閘極硬掩模1 1 3而形成。閘極絕緣層U 1包括典型的 氧化物系的層如氧化矽層。閘極電極層1 1 2通過使用從由傳 導性多晶矽、鎢（W )、氮化鎢（WN )、矽化鎢（WSh )及 其組合組成的組中所選擇的一個來形成。在此，X代表砂對 鎢的原子比，且爲正數。此外，閘極硬掩模1 1 3在用於在閘 極圖案層之間形成接觸塞的隨後的蝕刻技術期間起到保護 閘極電極層1 1 2的作用。 相應地，爲了在閘極圖案之間形成接觸塞，使用了具 有與氮化物層不同的蝕刻選擇性的材料。例如，在使用氧 化物系的層作爲絕緣層的情況下，可使用氮化物系的材料 如氮化砂（SiN)或氧氮化砂（SiON)作爲閘極硬掩模113。 在使用基於聚合物的低K電介質層的情況下，使用氧化物 系的材料作爲硬掩模1 1 3。 儘管未加以說明，執行離子注入技術以便在基板1 1 0 在閘極圖案1 1 4之間的特定區域形成源/汲結區。 接著，選擇性的氧化物層（未示出）和氧化物系的層 1 1 5 (例如緩衝氧化物層）形成於閘極圖案π 4和基板1 1 〇 上。第一氮化物系的層1 1 6形成於氧化物系的層1 1 5上。氧 化物系的層1 1 5和第一氮化物系的層1 1 6用做第一間隔物。 第一氮化物系的層1 1 6以範圍從大約5 0 A到大約2 5 0 A的厚 度形成。優選地’第一氮化物系的層1 1 6的厚度範圍從大約 1308786 年月::日修(更)正替換頁 120A到大約250A。 儘管未加以說明，光刻膠層形成於第一氮化物系的層 116上，且然後光刻膠圖案117通過執行使用光掩模（未示 出）的曝光技術及顯影技術而形成。 利用光刻膠圖案1 1 7作爲蝕刻掩模來執行第一蝕刻技 術118,從而移除閘極圖案114之間的第一氮化物系的層116 -和基於緩衝氧化物的層1 1 5。結果，形成了開口 1 1 9 (如接 觸孔），所述開口暴露基板1 1 0在閘極圖案1 1 4之間的部分。 B 基板區的暴露部分可爲源/汲結區。在此，使用從由C x F x、 CHF3、Ar、〇2和CO組成的組中所選擇的一種氣體來執行第 一蝕刻技術1 1 8，其中代表原子比的X和y範圍從大約1到 大約1 0。 儘管未加以說明，輔助的氮化物系的層可形成於第一 氮化物系的層1 1 6上。輔助的氮化物系的層比第一氮化物系 的層116或將隨後形成的第二氮化物系的層更薄地形成。例 如，輔助的氮化物系的層的厚度範圍可從大約50A到大約 ί 1 5 0 A。優選地，輔助的氮化物系的層的厚度範圍從大約8 0 A 到大約1 2 0 A。在層間絕緣層1 2 0包括B P S G的情況下，輔 助的氮化物系的層起到減少在熱技術期間注入到源/汲結區 上的雜質（例如硼）擴散到基板2 1中的作用。換句話說， 輔助的氮化物系的層起到輔助間隔物的作用。 參考第3 B圖，執行剝離技術，以移除光刻膠圖案丨丨7。 形成層間絕緣層1 2 0以掩埋閘極圖案1 1 4。在此，層間絕緣 層1 2 0包括氧化物系的材料如氧化矽。例如，層間絕緣層The interlayer insulating layer 2 9 ' is selectively removed using the photoresist pattern as an etch barrier to form the first contact hole 3 丨. The etching of the interlayer insulating layer 29 is achieved by using an oxide-based material and a nitride-based material having characteristics of etching selectivity. The interlayer insulating layer 29 may be etched using a gas selected from the CxFy family. wherein X and y representing atomic ratios range from about 1 to about 1 Å. For example, a CxFy-based gas can be selected from the group consisting of C4F6, C5F8, (^F8, and C3F3. At this time, the first nitride-based layer 26 is used as an etch stop layer. As shown in the 'first contact The portion of the first nitride-based layer 26 is exposed after the formation of the holes 3. Although the photoresist pattern is formed to have a width greater than that of the contact 1308786, which is formed by the gate pattern, it is formed on the gate pattern. Also used as the first nitride layer 26 of the hungry stop layer, it is possible to form contact holes having a desired width. In more detail, since the first contact hole 31 is formed in a state in which the first nitride-based layer 26 is formed in a single layer by a technique, the technique of forming the first contact hole 31 is a distance ratio between the gate patterns. The conventional method can be implemented with a wide range of states. 'Although not illustrated, an auxiliary nitride-based layer may be formed on the first 'nitride-based layer 26. The layer of the auxiliary nitride system is formed thinner than the layer 26 of the first nitride system or the layer of the second nitride system to be subsequently formed. For example, the thickness of the layer of the auxiliary nitride system may range from about 50 A to about 150 A. In the case where the interlayer insulating layer 29 includes B P S G , the auxiliary nitride-based layer functions to reduce diffusion of impurities (e.g., boron) implanted into the source/german region 28 during the thermal technique into the substrate 2 1 . In other words, the auxiliary nitride layer acts as an auxiliary spacer. Referring to Fig. 2B, a layer 25 of a second nitride system is formed on the first contact hole 31. The second nitride layer 30 serves as a second spacer. • Here, the thickness of the second nitride-based layer 30 is determined by considering the fact that the second nitride-based layer 30 and the first nitride remaining after being used as an etch barrier for forming the contact hole 31 The total thickness of the layer 26 is greater than the specific flaw that at least does not allow the gate pattern to be exposed. Further, the thickness of the second nitride-based layer 30 is determined by considering the fact that the leakage current characteristic of the metal oxide semiconductor (MOS) transistor including the gate pattern determines the layer 30 of the second nitride system and is used as The total thickness of the first nitride-based layer 26 remaining after the etch stop of the contact hole 31 is formed is -1,308,786,97, and the fine is replaced by the page. The engraving technique is performed with reference to Fig. 2C to remove the oxide-based layer 25, the first nitride-based layer 26, and the second nitride-based layer 30 provided at the bottom of the first contact hole 31. Accordingly, a plurality of gate spacers are formed on the sidewalls of the gate pattern. Each of the gate spacers includes a patterned second nitride based layer 30A, a patterned first nitride based layer 26A, and a patterned buffer oxide based layer 25A. Then, the second contact hole 32 is opened. As described above, the first gate spacer is first formed by a double structure of an oxide-based layer and a nitride-based layer. Then, a contact hole ' is formed between the gate patterns and a layer of another nitride system is utilized, after which a second gate spacer is formed. Thus, the distance between the drain patterns becomes wider when the contact holes are formed. Accordingly, the aspect ratio of the contact hole is greatly improved, and thus the subsequent technique can be performed more easily. Due to the reduction in the aspect ratio of the contact holes between the gate patterns, the opening margin of the contact holes between the gate patterns is greatly increased. In addition, due to the reduced aspect ratio, when the contact holes are filled with the interlayer insulating layer, the gap filling margin is also increased. Accordingly, the contact holes can be stably formed between the gate patterns in the semiconductor element of about 80 n or less. The first embodiment of the present invention is independent of any particular type of semiconductor element, and may utilize a stacked structure of an oxide-based layer (e.g., a hafnium oxide layer) and a nitride-based layer (e.g., a tantalum nitride layer) as a gate spacer. It is applied to various types of semiconductor elements. 3A to 3E are cross-sectional views illustrating a method of manufacturing a semiconductor element in accordance with a second embodiment of the present invention. 1308786 As shown in Fig. 3A, a plurality of gate patterns 1 14 are formed on a substrate 110 provided with an element insulating layer (not shown) and a well (not shown). Each of the gate patterns 1 1 4 is formed by sequentially stacking the gate insulating layer 111, the gate electrode layer 112, and the gate hard mask 113. The gate insulating layer U 1 includes a typical oxide-based layer such as a hafnium oxide layer. The gate electrode layer 112 is formed by using one selected from the group consisting of conductive polysilicon, tungsten (W), tungsten nitride (WN), tungsten telluride (WSh), and combinations thereof. Here, X represents the atomic ratio of sand to tungsten and is a positive number. In addition, the gate hard mask 1 13 functions to protect the gate electrode layer 112 during the subsequent etching technique for forming contact plugs between the gate pattern layers. Accordingly, in order to form a contact plug between the gate patterns, a material having an etching selectivity different from that of the nitride layer is used. For example, in the case where an oxide-based layer is used as the insulating layer, a nitride-based material such as silicon nitride (SiN) or oxynitride sand (SiON) may be used as the gate hard mask 113. In the case of using a polymer-based low-k dielectric layer, an oxide-based material is used as the hard mask 1 13 . Although not illustrated, an ion implantation technique is performed to form a source/junction region in a specific region between the gate electrodes 1 1 4 of the substrate 1 10 . Next, a selective oxide layer (not shown) and an oxide-based layer 1 15 (e.g., a buffer oxide layer) are formed on the gate pattern π 4 and the substrate 1 1 。. The first nitride-based layer 1 16 is formed on the oxide-based layer 115. The oxide layer 1 15 and the first nitride layer 1 16 are used as the first spacer. The first nitride-based layer 1 16 is formed with a thickness ranging from about 50 A to about 250 A. Preferably, the thickness of the layer 1 16 of the 'first nitride system ranges from about 1308786 month:: day repair (more) replacement page 120A to about 250A. Although not illustrated, a photoresist layer is formed on the first nitride-based layer 116, and then the photoresist pattern 117 is formed by performing an exposure technique and a development technique using a photomask (not shown). The first etching technique 118 is performed using the photoresist pattern 117 as an etch mask, thereby removing the first nitride-based layer 116 - and the buffer oxide-based layer 1 15 between the gate patterns 114. As a result, an opening 1 1 9 (e.g., a contact hole) is formed which exposes a portion of the substrate 1 10 between the gate patterns 1 1 4 . The exposed portion of the B substrate region can be a source/junction region. Here, the first etching technique 1 1 8 is performed using a gas selected from the group consisting of C x F x, CHF3, Ar, 〇 2, and CO, wherein the X and y representing the atomic ratio ranges from about 1 To about 10. Although not illustrated, an auxiliary nitride-based layer may be formed on the first nitride-based layer 116. The layer of the auxiliary nitride system is formed thinner than the layer 116 of the first nitride system or the layer of the second nitride system to be subsequently formed. For example, the thickness of the layer of auxiliary nitride system can range from about 50 A to about 355 mA. Preferably, the thickness of the layer of auxiliary nitride system ranges from about 80 A to about 1 20 A. In the case where the interlayer insulating layer 120 includes B P S G , the auxiliary nitride-based layer functions to reduce diffusion of impurities (e.g., boron) implanted into the source/germination region during the thermal technique into the substrate 2 1 . In other words, the auxiliary nitride layer acts as an auxiliary spacer. Referring to Figure 3B, a lift-off technique is performed to remove the photoresist pattern 丨丨7. An interlayer insulating layer 120 is formed to bury the gate pattern 1 1 4 . Here, the interlayer insulating layer 120 includes an oxide-based material such as ruthenium oxide. For example, interlayer insulation
1308786 120是從由高密度等離子體（HDP)氧化物層、硼磷矽酸鹽 玻璃（BPSG)層、磷矽酸鹽玻璃（PSG)層、等離子體增強 的原矽酸四乙酯（PETEOS )層、等離子體增強的化學氣相 沉積（PECVD )層、未摻雜的矽酸鹽玻璃（USG )層、氟化 矽酸鹽玻璃（FSG )層、碳摻雜的氧化物（CDO )層、有機 矽酸鹽玻璃（0 S G )層及其組合組成的組中所選擇的一個。 參考第3 C圖，儘管未加以說明，光刻膠層形成於層間 絕緣層1 20上。然後，執行使用光掩模（未示出）的曝光技 術及顯影技術以形成光刻膠圖案1 2 1。 利用光刻膠圖案1 2 1作爲蝕刻掩模來執行第二蝕刻技 術1 22，以蝕刻層間絕緣層1 20。特別地，執行第二蝕刻技 術以暴露基板1 1 0在閘極圖案1 1 4之間的部分。結果，形成 暴露上述源/汲結區（未示出）的另一個開口 1 23 (例如接 觸孔）。在此，使用從CXFX族中所選擇的氣體來執行第二蝕 刻技術122，其中代表原子比的X和y範圍從大約1到大約 10。例如，CxFx 族氣體可包括 C4F6、C5F8、OFdt] C3F3。在 第二蝕刻技術1 22期間，第一氮化物系的層1 1 6起到保護閘 極圖案1 1 4的作用。 此外，第二蝕刻技術122可使用硬掩模。例如，儘管未 加以說明，硬掩模可包括氮化物系的材料、無定形碳或多 晶矽，並使用光刻膠圖案1 2 1形成，所述光刻膠圖案1 2 1 隨後經由剝離技術來移除。然後，可使用硬掩模的保留部 分作爲蝕刻阻擋來執行第二蝕刻技術1 22。 參考圖3 D，通過執行剝離技術移除光刻膠圖案1 2 1。 -18- 1308786 ?。年乐im修(更)正替換頁 第二氮化物系的層1 25形成於圖案化的層間絕緣層1 20上。 在第二氮化物系的層125上執行化學機械拋光（CMP)技 術，以使第二氮化物系的層i 25僅保留在另一開口 1 23內部 (即圖案化的層間絕緣層1 20的側壁）。第二氮化物系的層 125用做第二間隔物。 第二氮化物系的層125的厚度通過考慮以下事實來確 定：第二氮化物系的層125和第一氮化物系的層116的總厚 度大於至少不允許閘極圖案1 1 4暴露的特定値。 此外，第二氮化物系的層1 2 5的厚度通過考慮以下事實 來確定：包括閘極圖案114的金屬氧化物半導體（MOS )電 晶體的洩漏電流特性確定第二氮化物系的層1 2 5和在用做 形成開口 1 1 9和1 23的蝕刻阻擋後所保留的第一氮化物系的 層1 1 6的總厚度。在第二實施例中說明了：通過使層間絕緣 層120處於第一氮化物系的層1 16和第二氮化物系的層125 之間而形成遠離第一氮化物系的層1 1 6的第二氮化物系的 層125。然而’仍然可能形成與第一·氮化物系的層116相接 觸的第二氮化物系的層1 2 5。 參考第3E圖’執行鈾刻技術以移除設置在另一開口 i 23 底部的第二氮化物系的層125。結果，基板1 1〇在閘極圖案 114之間的部分被暴露，限定了進一步的開口 127 (例如， 接觸孔）。儘管未示出’傳導材料塡充進一步的開口 127(例 如，接觸孔），從而形成接觸塞。 第4圖是掃描電子顯微（SEM)的顯微照片，說明根據 本發明的第二實施例的由接觸孔形成技術所形成的接觸孔 -19-1308786 120 is from a high density plasma (HDP) oxide layer, a borophosphonate glass (BPSG) layer, a phosphonate glass (PSG) layer, plasma enhanced tetraethyl orthosilicate (PETEOS) a layer, a plasma enhanced chemical vapor deposition (PECVD) layer, an undoped tellurite glass (USG) layer, a fluorided telluride glass (FSG) layer, a carbon doped oxide (CDO) layer, One selected from the group consisting of organic tellurite glass (0 SG ) layers and combinations thereof. Referring to Fig. 3C, although not illustrated, a photoresist layer is formed on the interlayer insulating layer 120. Then, an exposure technique and a development technique using a photomask (not shown) are performed to form a photoresist pattern 112. A second etching technique 222 is performed using the photoresist pattern 112 as an etch mask to etch the interlayer insulating layer 120. Specifically, a second etching technique is performed to expose a portion of the substrate 110 between the gate patterns 1 1 4 . As a result, another opening 1 23 (e.g., a contact hole) exposing the above source/junction region (not shown) is formed. Here, the second etching technique 122 is performed using a gas selected from the CXFX family, wherein X and y representing atomic ratios range from about 1 to about 10. For example, the CxFx family gas may include C4F6, C5F8, OFdt] C3F3. During the second etching technique 1 22, the first nitride-based layer 1 16 functions to protect the gate pattern 1 1 4 . Additionally, the second etch technique 122 can use a hard mask. For example, although not illustrated, the hard mask may include a nitride-based material, amorphous carbon, or polysilicon, and is formed using a photoresist pattern 1 2 1 , which is then transferred via a lift-off technique. except. The second etch technique 1 22 can then be performed using the remaining portion of the hard mask as an etch barrier. Referring to FIG. 3D, the photoresist pattern 1 21 is removed by performing a lift-off technique. -18- 1308786 ? The first layer of the second nitride system is formed on the patterned interlayer insulating layer 120. A chemical mechanical polishing (CMP) technique is performed on the second nitride-based layer 125 such that the second nitride-based layer i 25 remains only inside the other opening 1 23 (ie, the patterned interlayer insulating layer 120) Side wall). The second nitride layer 125 is used as the second spacer. The thickness of the second nitride-based layer 125 is determined by considering the fact that the total thickness of the second nitride-based layer 125 and the first nitride-based layer 116 is greater than the specificity at which the gate pattern 1 1 4 is not allowed to be exposed. value. Further, the thickness of the layer 1 2 5 of the second nitride system is determined by considering the fact that the leakage current characteristic of the metal oxide semiconductor (MOS) transistor including the gate pattern 114 determines the layer 1 2 of the second nitride system. 5 and the total thickness of the first nitride-based layer 1 16 retained after the etch stop used to form the openings 1 1 9 and 1 23 is used. In the second embodiment, it is explained that the interlayer insulating layer 120 is formed between the first nitride-based layer 1 16 and the second nitride-based layer 125 to form the layer 1 16 away from the first nitride system. A second nitride layer 125. However, it is still possible to form a layer 1 25 of a second nitride system that is in contact with the first nitride-based layer 116. The uranium engraving technique is performed with reference to Fig. 3E' to remove the layer 125 of the second nitride system disposed at the bottom of the other opening i23. As a result, the portion of the substrate 1 1 之间 between the gate patterns 114 is exposed, defining a further opening 127 (e.g., a contact hole). Although the conductive material is not shown to fill further openings 127 (e.g., contact holes), contact plugs are formed. Figure 4 is a photomicrograph of a scanning electron microscope (SEM) illustrating a contact hole formed by a contact hole forming technique according to a second embodiment of the present invention.
I 1308786 區域。 如所述，根據第二實施例所形成的接觸孔的區域W 2大 約是5 3 nm。與大約是24 nm的傳統接觸孔的區域相比，根 據弟一實施例的接觸孔的區域W 2增加了大約1 9 n m。因此， 接觸孔的高寬比也增加。如前所述，傳統接觸孔的高寬比 爲1 6 · 3比1。相對地，根據第二實施例的接觸孔的高寬比 大約爲8.6比1。 在本發明的示範性實施例的基礎上，在第一氮化物系 的層形成後形成打開源/汲區的接觸孔。然後，形成塡充於 接觸孔內的層間絕緣層。結果，增加了用於形成接觸孔的 裕度，導致比傳統接觸孔寬的接觸孔的形成。該事實顯示 層間絕緣層的間隙塡充裕度得到保證。 更具體地，在傳統方法中，層間絕緣層在第一氮化物 和第二氮化物層形成之後形成，所述第一氮化物和第二氮 化物層分別用做第一和第二閘極間隔物。因而，閘極圖案 之間的距離是不夠的，引起層間絕緣層的間隙塡充裕度的 減小。然而，根據本發明的示範性實施例，層間絕緣層在 第一氮化物系的層形成之後形成，所述第一氮化物系的層 用做第一閘極間隔物。結果，閘極圖案之間的距離增加。 因而，可保證層間絕緣層的間隙塡充裕度。保證間隙塡充 裕度顯示接觸孔的高寬比可減小。相應地，較少可能發生 接觸孔未打開或不正確地打開的事件。 如上所述。接觸孔的高寬比可通過順序的步驟改進。 首先，以氧化物系的層（例如緩衝氧化物層）和氮化物系 -20 -I 1308786 area. As described, the region W 2 of the contact hole formed according to the second embodiment is about 5 3 nm. The area W 2 of the contact hole according to the embodiment of the present invention is increased by about 1 19 nm as compared with the area of the conventional contact hole of about 24 nm. Therefore, the aspect ratio of the contact hole also increases. As described above, the conventional contact hole has an aspect ratio of 1 6 · 3 to 1. In contrast, the contact hole according to the second embodiment has an aspect ratio of about 8.6 to 1. On the basis of an exemplary embodiment of the present invention, a contact hole for opening the source/deuterium region is formed after the layer of the first nitride system is formed. Then, an interlayer insulating layer which is filled in the contact hole is formed. As a result, the margin for forming the contact holes is increased, resulting in the formation of contact holes wider than the conventional contact holes. This fact shows that the gap margin of the interlayer insulating layer is secured. More specifically, in the conventional method, an interlayer insulating layer is formed after the first nitride and the second nitride layer are formed, and the first nitride and the second nitride layer are used as the first and second gate intervals, respectively. Things. Therefore, the distance between the gate patterns is insufficient, causing a decrease in the gap margin of the interlayer insulating layer. However, according to an exemplary embodiment of the present invention, the interlayer insulating layer is formed after the formation of the layer of the first nitride system, and the layer of the first nitride system is used as the first gate spacer. As a result, the distance between the gate patterns increases. Therefore, the gap margin of the interlayer insulating layer can be ensured. It is ensured that the gap filling margin shows that the aspect ratio of the contact hole can be reduced. Accordingly, an event in which the contact hole is not opened or opened incorrectly is less likely to occur. As mentioned above. The aspect ratio of the contact holes can be improved by sequential steps. First, an oxide-based layer (such as a buffer oxide layer) and a nitride system -20 -
1308786 ί物。然後， 3隔物的另一 技術裕度也 ;觸（SAC)方 以下的元件中 $少能夠提供 、2005 年 6 ί勺韓國專利申 KR ’合於此。 ^明，對本領 :權利要求所 :各種變化和 以下結合附 ，其中： 法的橫截面視 第一實施例的 的層（例如氮化矽層）的雙層來形成閘極間PI 形成連接塞接觸的蝕刻技術。形成用做閘極間 個氮化物系的層。通過改進接觸孔的高寬比， 可得到改進。 因爲高寬比的減少，可增加使用自對準接 法打開氧化物系的層的裕度。結果，在80 nm 可保證足夠的開口裕度。同另外，高寬比的淘 改進層間絕緣層的間隙塡充裕度的效果。1308786 ί物. Then, another technical margin of the 3 spacers is also available; less than the components below the touch (SAC) side can be provided. In 2005, 6 Korean scoops of Korean patents KR' are included. ^明,对本本: Claims: various changes and the following combination, wherein: the cross section of the method depends on the double layer of the layer of the first embodiment (for example, a layer of tantalum nitride) to form a gate inter-gate PI to form a connection plug Contact etching technique. A layer used as a nitride system between the gates is formed. Improvements can be made by improving the aspect ratio of the contact holes. Because of the reduction in aspect ratio, the margin of opening the oxide system layer using self-aligned bonding can be increased. As a result, a sufficient opening margin is ensured at 80 nm. In addition, the aspect ratio of the effect of improving the gap filling margin of the interlayer insulating layer.
本申請包含涉及分別在2005年2月28日 月15日和2006年2月21提交於韓國專利局E 請 No. KR 2005-0016845 、 KR 2005-0051372 和 2006-00 1 6820的主題，其全部內容通過引用結 儘管已相對於某些優選實施例描述了本湧 域的技術人員顯而易見的是，在不背離如以τ 限定的本發明的精神和範圍的情況下，可進朽 修改。 【圖式簡單說明】 本發明的上述及其它的目的和特徵將參： 圖給出的優選實施例的描述而得到更好地理库 第1圖是說明製造半導體元件的傳統方 圖； 第2A圖到第2C圖是說明根據本發明的 製造半導體元件的方法的橫截面視圖； 第3Α圖到第3Ε圖是說明根據本發明的第二實施例的 1308786 Ί — 製造半導體元件的方法的橫截面視圖；以及 第4圖是掃描電子顯微（SEM )的顯微照片，說明根據 本發明的第二實施例的通過使用連接塞接觸（landing plug c ο n t a c t )形成技術所形成的接觸孔區域。 【主要元件符號說明】This application contains the subject matter that was submitted to the Korean Patent Office E, No. KR 2005-0016845, KR 2005-0051372, and 2006-00 1 6820, respectively, on February 15, 2005, February 15, 2005, and February 21, 2006, respectively. It is apparent to those skilled in the art that the present invention has been described with respect to certain preferred embodiments, without departing from the spirit and scope of the invention as defined by τ. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects and features of the present invention will become better in the description of the preferred embodiments of the present invention. FIG. 1 is a conventional diagram illustrating the fabrication of semiconductor components; 2C is a cross-sectional view illustrating a method of fabricating a semiconductor device in accordance with the present invention; FIGS. 3D through 3D are cross-sectional views illustrating a method of fabricating a semiconductor device in accordance with a second embodiment of the present invention. And FIG. 4 is a photomicrograph of a scanning electron microscope (SEM) illustrating a contact hole region formed by a landing plug c ο ntact formation technique according to a second embodiment of the present invention. [Main component symbol description]
11 基 板 12 閘 極 絕 緣 層 13 閘 極 電 極 14 閘 極 硬 掩 膜 15 緩 衝 氧 化 物 層 16 第 —- 氮 化 物 層 17 第 二 氮 化 物 層 18 源 / 汲 區 1 8A 輕 度 摻 雜 的 汲 區 19 氧 化 物 的 層 間 絕緣層 20 接 觸 孔 21 基 板 22 閘 極 絕 緣 層 23 閘 極 電 極 層 24 閘 極 硬 掩 膜 25 氧 化 物 系 的 層 26 氮 化 物 的 層 28 源 /汲區 28A 輕 度 摻 雜 的 汲 區 -22 -11 substrate 12 gate insulating layer 13 gate electrode 14 gate hard mask 15 buffer oxide layer 16 first - nitride layer 17 second nitride layer 18 source / germanium region 1 8A lightly doped germanium region 19 Oxide interlayer insulating layer 20 Contact hole 21 Substrate 22 Gate insulating layer 23 Gate electrode layer 24 Gate hard mask 25 Oxide-based layer 26 Nitride layer 28 Source/汲 region 28A Lightly doped germanium District-22 -
層間絕緣層 第二氮化物系的層 第一接觸孔 第二接觸孔 基板 閘極絕緣層 閘極電極層 閘極硬掩膜 閘極圖案 氧化物的層 第一氮化物系的層 光蝕刻圖案 第一蝕刻技術 接觸孔 層間絕緣層 光蝕刻圖案 接觸孔 第二氮化物系的層 開口 接觸孔的區域 -23 -Interlayer insulating layer second nitride-based layer first contact hole second contact hole substrate gate insulating layer gate electrode layer gate hard mask gate pattern oxide layer first nitride-based layer photo-etching pattern An etching technique contact hole interlayer insulating layer photo-etching pattern contact hole second nitride-based layer opening contact hole region -23 -
Claims (1)
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| KR20050016845 | 2005-02-28 | ||
| KR20050051372 | 2005-06-15 | ||
| KR1020060016820A KR100717812B1 (en) | 2005-02-28 | 2006-02-21 | Method for manufacturing semiconductor device |
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| TW200731470A TW200731470A (en) | 2007-08-16 |
| TWI308786B true TWI308786B (en) | 2009-04-11 |
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| KR (1) | KR100717812B1 (en) |
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| CN102810478B (en) * | 2011-05-31 | 2015-03-11 | 中芯国际集成电路制造(上海)有限公司 | Forming method for transistor |
| KR102160017B1 (en) | 2013-11-18 | 2020-09-25 | 한국전자통신연구원 | Glass appratus using eyesignt-based virtual screen |
| CN110349908B (en) * | 2018-04-03 | 2022-11-04 | 华邦电子股份有限公司 | Self-aligned contact structure and method for forming the same |
| TWI643277B (en) | 2018-04-03 | 2018-12-01 | 華邦電子股份有限公司 | Self-aligned contact and method forming the same |
| US11417749B2 (en) * | 2019-06-14 | 2022-08-16 | Taiwan Semiconductor Manufacturing Company Limited | Semiconductor arrangement with airgap and method of forming |
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| KR100541369B1 (en) * | 2003-06-30 | 2006-01-11 | 주식회사 하이닉스반도체 | Method of forming interconnection line for semiconductor device |
| KR20060023004A (en) * | 2004-09-08 | 2006-03-13 | 주식회사 하이닉스반도체 | Forming method of contact plug in semiconductor device |
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| KR20060095465A (en) | 2006-08-31 |
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