TWI307961B - - Google Patents
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- TWI307961B TWI307961B TW92134005A TW92134005A TWI307961B TW I307961 B TWI307961 B TW I307961B TW 92134005 A TW92134005 A TW 92134005A TW 92134005 A TW92134005 A TW 92134005A TW I307961 B TWI307961 B TW I307961B
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1307961 五、發明說明(1) 發明所屬之技術領域: 一本發明有關於一種液晶顯示器之薄膜電晶體陣列基板 技術,特別有關一種多閘極結構之薄膜電晶體及其製作方 法。 先前技術: 液明顯示器(1 iquid cry sta 1 d i spl ay,以下簡稱 LCD)之薄膜電晶體(thin f丨lm transist〇r,以下簡稱 TFT)疋用來作為晝素之開關元件,一般可區分成非晶矽 TFT>與多晶石夕TFT兩種型式。由於多晶石夕TFT的載子遷移率 較高、驅動電路之積集度較佳、漏電流較小,故多晶矽 TFT較常應用在向操作速度的電路中。但是,多晶矽之 開啟(on)與關閉(off)狀態下的電流很大,且鄰近汲極區 域之空乏區内會產生一大的電場,因此材料缺陷以及穿遂 效應所產生的能隙極易使汲極區域内之電子與空乏區之電 洞結合,則於關閉狀態下易發生漏電流(leakage current)的問題。為了有效改善漏電流的現象,目前技術 係於閘極與汲極之間製作一未摻雜之間隔區域(und〇ped offset region)或一輕摻雜汲極(Hghtiy doped drain, LDD)區域’用來降低没極接面處(drain juncti〇n)的電 %。此外,更將多晶石夕T F T設計為多閘極(m u 11 i - g a t e)結 構’例如:雙閘極(dual - gate)結構,可以進一步減緩漏 電流現象。 請參閱第1 A〜1 C圖,其顯示習知第一種雙閘極結構之 0773-9592CIPT»F(Nl);P92031;che r ry.ptd 第6頁 1307961 五、發明說明(2) 多晶石夕T F T製程的剖面示意圖。首先,如第1 a圖所示,— 玻璃基板1 0上包含有一緩衝層1 2以及一多晶矽層丨4,並進 行一蝴離子佈植(B+ i〇n impiantati〇n)製程16用以調、整、 晶體之臨界電壓(threshold voltage)。然後,如第1B圖、 所示’依序製作一閘極絕緣層丨8以及分隔之一第一開極^ 20 I、一第二閘極層2〇丨丨。而後進行一輕摻雜離子佈^直制曰 程2 2 ’利用第一閘極層2 〇丨以及第二閘極層2 〇丨丨作為罩衣 幕,於第一閘極層2 0 I以及第二閘極層2 0 I I周圍之多曰曰 層14内形成一N-摻雜區域14a。後續,如第1(:圖所示阳= 行沉積、微影與蝕刻製程以形成一光阻層24,使其、 一閘極層2〇I以及第二閘極層20丨丨之間隙處的N_摻y 14a。最後進行一重摻雜離子佈植製程26,利用光阻:域 2一4、第-閘極層201以及第二閘極層2〇11作為罩幕,二 一閘極層201以及第二閘極層2〇11之外側周圍的n 域14a成為兩個…摻雜區域丨“、HD。如此一 ϋ隹& 24覆蓋之Ν-摻雜區域14a係成為一 LDDH且層 ::係分別 =2〇1以及第二閑極層…j覆蓋之未摻雜區域心-14 C2則成為兩個通道區域。 一 1 上述製程較易達成黃光之精準性與電性之對P # 卻無法在筮一 托a 〇 » "、电丨王I對%性’但 閘極層2 0 I以及第二閘極層2 〇 I I之爭 側的源/汲極區域附近形成L 取外圍兩 TFT的結構必須犧鉍門从,、 口此上迷多晶矽 h± 牲開啟(〇1°電流以提高[叩區域之由$ 抗來抑制漏電流’況且此結構之漏電流仍過大==1307961 V. INSTRUCTION DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention: The present invention relates to a thin film transistor array substrate technology for a liquid crystal display, and more particularly to a thin film transistor having a multi-gate structure and a method of fabricating the same. The prior art: a thin film transistor (hereinafter referred to as TFT) of a liquid display (1) is used as a switching element of a halogen element. It is divided into two types: amorphous 矽 TFT> and polycrystalline shi TFT. Since the polycrystalline silicon TFT has a higher carrier mobility, a better integration of the driving circuit, and a smaller leakage current, the polycrystalline germanium TFT is more commonly used in a circuit for operating speed. However, the current in the on (on) and off (off) states of the polysilicon is large, and a large electric field is generated in the depletion region adjacent to the drain region, so that the material gap and the energy gap generated by the piercing effect are extremely easy. When the electrons in the drain region are combined with the holes in the depletion region, the leakage current is liable to occur in the off state. In order to effectively improve the leakage current phenomenon, the current technology is to form an undoped offset region or a lightly doped drain (LDD) region between the gate and the drain. Used to reduce the electricity % of the drain juncti〇n. In addition, the polycrystalline stone T F T is designed as a multi-gate (m u 11 i - g a t e) structure, for example, a dual-gate structure, which can further alleviate the leakage current phenomenon. Please refer to the figure 1A~1 C, which shows the first type of double gate structure of 0773-9592CIPT»F(Nl); P92031; che r ry.ptd page 6 1307961 V. Description of invention (2) Schematic diagram of the spar ray TFT process. First, as shown in FIG. 1a, the glass substrate 10 includes a buffer layer 12 and a polysilicon layer 4, and is subjected to a process of bionic ion implantation (B+i〇n impiantati〇n) 16 for adjustment. , the whole, the threshold voltage of the crystal. Then, as shown in FIG. 1B, a gate insulating layer 8 is sequentially formed, and one of the first open electrodes 20 1 and the second gate layer 2 is separated. Then, a lightly doped ion cloth is used to make a straight process 2 2 ' using the first gate layer 2 〇丨 and the second gate layer 2 〇丨丨 as a hood, on the first gate layer 2 0 I and An N-doped region 14a is formed in the multi-turn layer 14 around the second gate layer 2 0 II. Subsequently, as shown in FIG. 1 : a positive deposition, lithography and etching process to form a photoresist layer 24, such as a gate layer 2〇I and a second gate layer 20丨丨N_doped y 14a. Finally, a heavily doped ion implantation process 26 is performed, using photoresist: domain 2 - 4, first gate layer 201 and second gate layer 2 〇 11 as a mask, two gates The n-domain 14a around the outer side of the layer 201 and the second gate layer 2〇11 becomes two...doped regions 丨", HD. Thus, the Ν-doped region 14a covered by the ϋ隹& 24 becomes an LDDH and Layer:: respectively = 2 〇 1 and the second idle layer ... j covered undoped region heart - 14 C2 becomes two channel regions. 1 The above process is easier to achieve the accuracy and electrical properties of yellow light P # 却 can not form L in the vicinity of the source/dual region of the dispute side of the 筮一托 a 〇» & The structure of the two external TFTs must be sacrificed from the gate, and the polysilicon 矽h± is turned on (the current of 〇1° is increased to improve the leakage current of the region Too big ==
0773-9592CIPIW(Nl) ;P92031 ;cherry .ptd_ 第7頁0773-9592CIPIW(Nl) ;P92031 ;cherry .ptd_ Page 7
彌MS 1307961MS MS1307961
請參閱第ID圖,其翔千羽土结 _ ^ ε.Τϋτ A1 ··、貝不S知弟二種雙閘極結構之多晶 矽TFT製程的剖面示意圖。笛一 ^ 口 弟一種製作方式大致與上述第 程相同,相同之處於此省略敘述,…處在於光 :層—=之圖案設計。當完成上述第ία〜iBm示之步驟後, 圖所示,進行沉冑、微影與蝕刻製程以形成-第- 篦! „241以及一第一光阻層2411 ’使第-光阻層241覆蓋 甲極層2GI及其周圍之—部份N_#雜區域i4a,並使第 層2411覆蓋第二閘極層2GII及其周圍之-部份N-摻 ^域14a。最後進行一重摻雜離子佈植製程26,利用第 一光阻層241、第二光阻層2411、帛—閘極層2()1以及第二 閑極層20 I I作為罩幕,使第一閘極層2〇 I以及第二閘極層 2 0 I I之外側周圍的N摻雜區域丨4 a成為三個N+摻雜區域 14S、14D、US/D。如此一來,被第一光阻層241、第二光 阻層2411覆蓋之N摻雜區域14\、14^、14^、14〜係成為 四個LDD區域,N+摻雜區域143、UD、14S/D係分別成為一 源極區域、一汲極區域以及一共用源/汲極區域,而被第 一閘極層201以及第二閘極層2〇1丨覆蓋之未摻雜區域HCi、 1 4 C2則是成為兩個通道區域。 上述製私可於第一、第二閘極層2〇1、2〇11之外圍與 内部的多晶係層14内製作LDD區域,故可有效抑制漏電 流。但是’受限於曝光技術之對準誤差(ph〇t〇 misal ignment) ’不易控制四個n -摻雜區域148丨、14〜、 1 4 a;5、1 4 的長度對稱性’且會發生l j) d區域之位置偏移現Please refer to the ID diagram for a schematic diagram of the polycrystalline 矽TFT process of the two-gate structure of the Xiangqian soil knot _ ^ ε.Τϋτ A1 ····贝不 S知弟. The method of making a flute is basically the same as that of the above-mentioned process, and the similarities are omitted here. The light is in the design of the layer:==. After the steps of the above ία~iBm are completed, as shown in the figure, the deposition, lithography and etching processes are performed to form - - 篦! „ 241 and a first photoresist layer 2411 ′ such that the first photoresist layer 241 covers the first layer N_# impurity region i4a of the electrode layer 2GI and its surroundings, and the first layer 2411 covers the second gate layer 2GII and The surrounding - part of the N-doped field 14a. Finally, a heavily doped ion implantation process 26 is performed, using the first photoresist layer 241, the second photoresist layer 2411, the gate layer 2 () 1 and the second The idle layer 20 II serves as a mask such that the first gate layer 2〇I and the N-doped region 丨4 a around the outer side of the second gate layer 2 0 II become three N+ doped regions 14S, 14D, US In this way, the N-doped regions 14\, 14^, 14^, 14~ covered by the first photoresist layer 241 and the second photoresist layer 2411 become four LDD regions, and the N+ doping region 143 , UD, 14S/D are respectively a source region, a drain region, and a common source/drain region, and are undoped by the first gate layer 201 and the second gate layer 2〇1丨. The regions HCi and 1 4 C2 are two channel regions. The LDO region can be formed in the periphery of the first and second gate layers 2〇1 and 2〇11 and the polycrystalline layer 14 inside. Can effectively suppress leakage Flow. But 'restricted by the exposure technique's alignment error (ph〇t〇misal ignment) 'difficult to control the four n-doped regions 148丨, 14~, 1 4 a; 5, 1 4 length symmetry' And the positional offset of the lj) d region will occur.
0773-9592CIPTW(Nl);P92031;cherry.ptd 第8頁 !3〇7961 ---- 五、發明說明(4) —一 象,進而導致雷曰JBil ---- 备令t 展日9體呈現電性上的不對稱性、制 產率低的問題。 製程複雜、 發明内容: 有4監於此,太狀 夕夕n +發明的目的就在於提供一插夕 側ί 作方法,可於每-個間極/二极結構0773-9592CIPTW(Nl);P92031;cherry.ptd Page 8!3〇7961 ---- V. Invention description (4) - Image, which leads to Thunder JBil ---- Preparation order t The problem of electrical asymmetry and low yield is presented. The process is complicated, and the content of the invention: There are 4 supervisors here, too, the purpose of the invention is to provide a method of inserting the side of the eve, which can be used in each of the interpole/diode structures.
且可免M 性。 < 問通,並達到LDD區域的 电成, 食度對稱 電曰二、成古^目❸’本發明提供-種多閘朽* 摻雜區域以及一第:二1.:第-輕摻雜區域;!,溥骐 側;一第-通道區域以及-第成於該第-ί ::形成於該第二摻雜區域以及:二通道區域,: 該第-通道區域以及:第五輕摻雜區域,係^之外側; 重摻雜區域以及一第二:通道區域之外側;、^別形成於 輕摻雜區域以及該第:± ^雜區域,係分別形士及一第一 緣層係形成於該有致芦^參雜區*之夕卜側。」^該第四 ί該有效層之第-心區域且=:-中央C 有效層之第四輕摻雜區域]第一遮蔽區域,^係覆 ;有效層之第二輕掺雜區域心第二遮蔽區域;;ί該 於该有效層上’且包含有::-問極絕緣層:覆蓋 之第二通道區域;一 中央區域,係覆$ ^係形成 第一遮蔽區域,係覆該有致層 _____ 益该有效j® ~政層之第And can be exempted from M. < Query, and reach the electrical formation of the LDD region, the symmetry of the food symmetry, the second generation of the ancient ^ ❸ 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本Miscellaneous area;! a first channel region and a first region formed in the second doped region and a second channel region, the first channel region and the fifth lightly doped region, The outer side of the system; the heavily doped region and a second: the outer side of the channel region; the other is formed in the lightly doped region and the first: ± ^ region, respectively, the shape of the shape and a first edge layer formed in This has the side of the lusheng area*. ^The fourth ί the first-heart region of the active layer and =: - the fourth lightly doped region of the central C active layer] the first masking region, the ^-covering; the second lightly doped region of the active layer The second shielding area;; ί on the active layer 'and includes: - - the pole insulating layer: covering the second channel region; a central region, the system covering the ^ ^ system to form the first shielding region, covering the Layer __ benefit the effective j® ~ political layer
0773- C D E -9592CIPWF(N1) ;P92031 ;cherry .ptd 1307961 五、發明說明(5) 三輕摻雜區域;以及一第二遮蔽區域,係覆蓋該有效層之 第五輕摻雜區域。一第一閘極層,係形成於該第一閘極絕 緣層上,且覆蓋該第一閘極絕緣層之中央區域。一第二閘 極層,係形成於該第二閘極絕緣層上,且覆蓋該第二閘極 絕緣層之中央區域。 為達成上述目的,本發明提供一種多閘極結構之薄膜 電晶體的製作方法,其包括下列步驟。依序形成一有效 層、一絕緣層以及一導電層於一基底上。進行一钱刻製 程,將該導電層定義為一第一閘極層以及一第二閘極層’ 並將該絕緣層定義為一第一閘極絕緣層以及一第二閘極絕 緣層。該第一閘極絕緣層包含有一中央區域、一第一遮蔽 區域形成於該中央區域之一側、以及一第二遮蔽區域形成 於該中央區域之另一側。該第一閘極層係覆蓋該第一閘極 絕緣層之中央區域。該第二閘極絕緣層包含有一中央區 域、一第一遮蔽區域形成於該中央區域之一側、以及一第 二遮蔽區域形成於該中央區域之另一側。該第二閘極層係 覆蓋該第二閘極絕緣層之中央區域。該第一閘極絕緣層之 第二遮蔽區域係鄰近於該第二閘極絕緣層之第一遮蔽區 域,且該第一閘極絕緣層之第二遮蔽區域與該第二閘極絕 緣層之第一遮蔽區域之間隙處係暴露下方之該有效層。進 行一輕摻雜離子佈植製程,於該有效層中形成複數個具有 不同摻雜濃度之區域:一第一區域與一第二區域係為一未 摻雜區域,且分別形成於該第一閘極絕緣層之中央區域與 該第二閘極絕緣層之中央區域的下方;一第三區域與一第0773- C D E -9592CIPWF(N1) ; P92031 ;cherry .ptd 1307961 V. Description of the invention (5) A three-lightly doped region; and a second masking region covering a fifth lightly doped region of the active layer. A first gate layer is formed on the first gate insulating layer and covers a central region of the first gate insulating layer. A second gate layer is formed on the second gate insulating layer and covers a central region of the second gate insulating layer. In order to achieve the above object, the present invention provides a method of fabricating a thin film transistor having a multi-gate structure, which comprises the following steps. An effective layer, an insulating layer and a conductive layer are sequentially formed on a substrate. The conductive layer is defined as a first gate layer and a second gate layer ′ and the insulating layer is defined as a first gate insulating layer and a second gate insulating layer. The first gate insulating layer includes a central region, a first shielding region is formed on one side of the central region, and a second shielding region is formed on the other side of the central region. The first gate layer covers a central region of the first gate insulating layer. The second gate insulating layer includes a central region, a first shielding region is formed on one side of the central region, and a second shielding region is formed on the other side of the central region. The second gate layer covers a central region of the second gate insulating layer. The second shielding region of the first gate insulating layer is adjacent to the first shielding region of the second gate insulating layer, and the second shielding region of the first gate insulating layer and the second gate insulating layer The gap between the first masking regions exposes the active layer below. Performing a lightly doped ion implantation process, forming a plurality of regions having different doping concentrations in the active layer: a first region and a second region are an undoped region, and are respectively formed in the first region a central region of the gate insulating layer and a lower portion of the central region of the second gate insulating layer; a third region and a first
0773-9592CIPTWF(Nl);P92031jcherry .ptd 第10頁 1307961 五、發明說明(6) 四區域係為一具有第一摻 成於該第一閘極絕緣層之 域的下方;一第五區域與 濃度輕摻雜區域,且分別 一遮蔽區域與該第二遮蔽 具有第二摻雜滚度之輕摻 緣層之第一遮蔽區域的外 摻雜濃度之輕摻雜區域, 一遮蔽區域的外側;一第 之輕摻雜區域’且形成於 域與該第二閘極絕緣層之 光阻層,以覆蓋該該第一 弟一閘極絕緣層之第·一遮 域。進行一重摻雜離子佈 五區域成為一具有第三摻 七區域與該第八區域成為 雜濃度之輕 該第—遮蔽 一第六區域 形成於該第 區域的下方 雜區域,且 側;—第八 且形成於該 九區域係為 s亥第一閘極 第一遮蔽區 閘極絕緣層 蔽區域及其 植製程,以 雜濃度之輕 一重摻雜區 摻雜區域’ 區域與該第 係為一具有 二閘極絕緣 ;一第七區 形成於s亥第 區域係為一 第二閘極絕 一具有第二 絕緣層之第 域的間隙處 之第二遮蔽 間隙處之該 使該第三區 摻雜區域, 域0 且分別形 二遮蔽區 第一摻雜 層之該第 域係為一 一閘極絕 具有第二 緣層之第 摻雜濃度 二遮蔽區 。形成一 區域、該 第九區 域與該第 並使該第 實施方式: 本發明提出一種多閘極結構之多晶@TFT及其製作方 法’利用閘極絕緣層之暴露於閘極層兩側之遮蔽區域作為 離子佈植製程的罩幕,則可同時達成LDD區域以及源/汲極 區域之製作。如此可於每一個閘極層之周圍兩側均製作一 LDD區域’以使多晶矽打τ具有極低之漏電流,且可免去黃 光對準之問題’並達到LDD區域的長度對稱性。0773-9592CIPTWF(Nl); P92031jcherry.ptd Page 10 1307961 V. Description of the invention (6) The four-region is a region having a first domain doped in the first gate insulating layer; a fifth region and concentration a lightly doped region, and a lightly doped region of the first doped region of the first masking region of the lightly doped edge layer having the second doping tempering, respectively, and a second outer region; The lightly doped region is formed on the photoresist layer of the second gate insulating layer to cover the first mask of the first gate-first insulating layer. Performing a heavily doped ion cloth five-region to have a third doped seven region and the eighth region becomes a light concentration. The first-masking sixth region is formed in a lower impurity region of the first region, and the side; And forming the nine regions as the first gate of the first gate of the first gate region, and the implantation process, and the doping region of the lightly doped region with the impurity concentration is the same as the first system The second gate is formed in the shai region, and the second gate is a second gate, and the second shielding gap at the gap of the second insulating layer is used to dope the third region. The region, the domain 0 and the second doping region of the first doped layer are respectively a first doping layer having a second doping layer and a second doping region. Forming a region, the ninth region, and the first embodiment: The present invention provides a polygate @TFT having a multi-gate structure and a method for fabricating the same by using a gate insulating layer exposed to both sides of the gate layer As a mask for the ion implantation process, the masked area can simultaneously produce the LDD region and the source/drain region. Thus, an LDD region can be formed on both sides of each gate layer so that the polysilicon τ has a very low leakage current, and the problem of yellow light alignment can be eliminated, and the length symmetry of the LDD region is achieved.
0773-9592CIPnvF(Nl);P92031;cherry.ptd 第11頁 1307961 五、發明說明(7) ,^讓本發明之上述和其他目的、特徵、和 心特舉一雙閉極結構之多晶石夕TFT作為 貫把例並配合所附圖示,作詳細說明如下: [第一實施例] 梅&二二?第2 A〜2 E圖,其顯示本發明第一實施例之雔n 極、,。構=夕晶矽TFT的製作方法的剖面示意圖。-閘 π床:你’如第2八圖所示,提供一基底30,並於基底30上 作—緩衝層32以及-有效層34。基底30之較佳者土 二ί =緣基底’例如:破璃基底。緩衝層32之較佳:為 ::於二層〇 :例ΐ :氧化矽層,其目的為幫助有效層3 4 :成:=3〇上。有效層34之較佳者為一半導體石夕 如η夕^夕層。為了調整電晶體之臨界電壓Uhreshold V〇1叩6),可進行一爛或碟離子佈植(B+ 〇r P ion implantation)製程 〇 然後,如第2 B圖所千,> + 層36以及一導電声38。絕上序於有效層34上沉積-絕緣 -氣化矽層、一氮氧化矽之較佳者》-氧化矽層、 之較佳者為-金屬層或—多 =且々¥電層38 光阻作為罩幕以進行乾蝕 . π用口茶化之 為-第-閑極層381以及1第將導電層38定義成 ^ , 4m ^9Γ ® - 第一開極層3811的圖案。繼 :=2。圖所不,進行電漿蝕 應性離子蝕刻,可使用—呈右人¥ y g; ^ ^ 氣體,於導電層38的餘刻=及含氯氣體之混合 表〗過&中將含氣氣體之流量逐漸調0773-9592CIPnvF(Nl);P92031;cherry.ptd Page 11 1307961 V. INSTRUCTIONS (7), Having the above and other objects, features, and characteristics of the present invention, a double-closed structure of polycrystalline stone The TFT is described in detail as an example and is accompanied by the accompanying drawings, and is described in detail as follows: [First Embodiment] Mei &22; 2A to 2E, which shows the 雔n pole of the first embodiment of the present invention, ,. A schematic cross-sectional view of a method of fabricating a TFT. - Gate π bed: You're providing a substrate 30 as shown in Figure 2, and a buffer layer 32 and an active layer 34 on the substrate 30. The preferred substrate 30 is a soil substrate, such as a glass substrate. Preferably, the buffer layer 32 is: :: in the second layer: Example: a layer of yttrium oxide, the purpose of which is to help the effective layer 3 4 : into: = 3 〇. The preferred layer of the active layer 34 is a semiconductor layer such as a layer of n. In order to adjust the threshold voltage Uhreshold V〇1叩6) of the transistor, a B+ 〇r P ion implantation process can be performed, and then, as shown in Fig. 2B, > + layer 36 and A conductive sound 38. Preferably, the upper layer is deposited on the active layer 34 - the insulating - gasified tantalum layer, the preferred one of the niobium oxynitride - the tantalum oxide layer, preferably the - metal layer or - more = and the electric layer 38 light The resistance is used as a mask for dry etching. The π is made into a -first-electrode layer 381 and the first conductive layer 38 is defined as a pattern of ^, 4m ^ 9 Γ ® - first open layer 3811. Following :=2. If the figure is not, the plasma etching should be performed, and it can be used - the right person ¥ yg; ^ ^ gas, the remaining layer of the conductive layer 38 and the mixed table of the chlorine gas Gradually adjusted traffic
0773-9592CIFTWF(Nl);P92031;cherry.ptd 605 第12頁 1307961 五、發明說明(8) --- 整至極大(甚至是僅使用含氣氣體作為蝕刻反應氣體),待 I虫刻至絕緣層36時再同時通入氧氣或加大氧氣流量,同時 可蝕刻再度露出之第一、第二閘極層3 8工、3 8丨I輪廓,則 可將第一、第二閘極層38I、3811製作成為一上窄下寬的 梯形,並可使絕緣層3 6成為兩個分隔之第一、第二閘極絕 緣層4 0、4 2。後續將圖案化之光阻移除。 對於第一閘極絕緣層4〇而言,其包含有一中央區域 40a、一第一遮蔽區域401^以及一第二遮蔽區域4〇b2。中央 區域40a係被第一閘極層381之底部覆蓋,第一、第二遮蔽 區域40b、4〇b2係分別暴露於第一間極層381之底部兩侧, 且第一閘極絕緣層4 0係暴露有效層3 4之一預定源/汲極區 域。較佳者為,第一遮蔽區域4〇bi之橫向長度%為〇. i # m〜2·0μπι ’第二遮蔽區域4〇b2之橫向長度界2為〇.1 〜2_0 # m。依據電路設計需求,可以適當調整%、%之長度及其 對稱性。 對於弟二閘極絕緣層4 2而言,其包含有一中央區域 42a、一第一遮蔽區域42 h以及一第二遮蔽區域42 b2,中央 區域4 2 a係被第二閘極層3 8 I I之底部覆蓋,第一、第二遮 蔽區域42b]、42 b2係分別暴露於第二閘極層38 I I之底部兩 i側’且第二閘極絕緣層4 2係暴露有效層34之一預定源/汲 極區域。較佳者為’第一遮蔽區域42 b!之橫向長度匕為0.1 /zm〜2.0/zm,第二遮蔽區域42b2之橫向長度〇2為0.1//111〜2. 0 μ m。依據電路設計需求,可以適當調整Di、D2之長度及 其對稱性,並可調整%、W2、D,、D2之對稱性。較佳者為:0773-9592CIFTWF(Nl);P92031;cherry.ptd 605 Page 12 1307961 V. Description of invention (8) --- To the extreme (even using only gas containing gas as etching reaction gas), to be insected to the insulation At the same time, the layer 36 can simultaneously pass oxygen or increase the oxygen flow rate, and at the same time, the first and second gate layers can be etched to expose the first and second gate layers, and the first and second gate layers 38I can be used. 3811 is formed into a trapezoid having a narrow upper and a lower width, and the insulating layer 36 can be made into two first and second gate insulating layers 40 and 42. The patterned photoresist is subsequently removed. For the first gate insulating layer 4, it includes a central region 40a, a first shielding region 401^, and a second shielding region 4〇b2. The central region 40a is covered by the bottom of the first gate layer 381, and the first and second shielding regions 40b, 4b2 are respectively exposed on both sides of the bottom of the first interlayer 381, and the first gate insulating layer 4 The 0 system exposes one of the predetermined source/drain regions of the active layer 34. Preferably, the lateral length % of the first masking region 4〇bi is 〇. i #m~2·0μπι ′ The lateral length boundary 2 of the second masking region 4〇b2 is 〇.1 〜2_0 # m. According to the circuit design requirements, the length of %, % and its symmetry can be adjusted appropriately. For the second gate insulating layer 42, it comprises a central region 42a, a first shielding region 42 h and a second shielding region 42 b2, and the central region 4 2 a is the second gate layer 3 8 II Covered by the bottom, the first and second shielding regions 42b], 42b2 are respectively exposed to the bottom two sides i of the second gate layer 38 II and the second gate insulating layer 42 is exposed to one of the active layers 34 Source/bungee area. Preferably, the lateral length 匕 of the first shielding area 42 b! is 0.1 /zm to 2.0 / zm, and the lateral length 〇2 of the second shielding area 42b2 is 0.1 / / 111 ~ 2. 0 μ m. According to the circuit design requirements, the lengths of Di and D2 and their symmetry can be adjusted appropriately, and the symmetry of %, W2, D, and D2 can be adjusted. The better one is:
0773-9592CIPTWF(Nl);P92031;cherry.ptd 第13頁 13079610773-9592CIPTWF(Nl);P92031;cherry.ptd Page 13 1307961
五、發明說明(9) wi=D2,〇 此外’第一閘極絕緣層4 0之第二遮蔽區域4 〇 h係相鄰 於第二閘極絕緣層42之第一遮蔽區域42N,且第二遮蔽區 域40b2與第一遮蔽區域42bi之間隙處係暴露下方之有效層° 3 4 .第 閘極纟巴緣層4 0之第一遮蔽區域4 0 b2的外側係暴露 下方之有效層34 ’第二閘極絕緣層42之第二遮蔽區域22t) 的外側係暴露下方之有效層34。 — 2 接著,如第2 D圖所示,進行一輕摻雜離子佈植製程 44,利用第一、第二閘極層38 ϊ、38丨〗、第一閘極絕緣層 40之遮蔽區域40 b!、4 ΟΝ、第二閘極絕緣層42之遮蔽區域 421^、42bz作為罩幕’則可於有效層34中形成多個具有不 同摻雜濃度的區域。第一、第二區域341、342乃為未摻雜 區域’且相對應形成於中央區域4〇a、42a的下方。第二、 第四區域343、344乃為一 N ——摻雜區域,且相對應形成於 第一閘極絕緣層4 0之第一、第二遮蔽區域4 〇 h、4 0 b2的下 方。第五、第六區域345、346乃為一 N--摻雜區域,且相 對應形成於第二閘極絕緣層42之第一、第二遮蔽區域 42 b!、42 b>2的下方。第七區域347乃為一 N -摻雜區域,係暴 露於第一閘極絕緣層40之第一遮蔽區域4Ob!的外側。第'八' 區域3 4 8乃為一 N _摻雜區域,係暴露於第二閘極絕緣層4 2 之第二遮蔽區域42b2的外側。第九區域349乃為一N-捧雜區 域’係暴露於第一閘極絕緣層4 0之第二遮蔽區域4 〇 b2 ‘第^ 二閘極絕緣層42之第一遮蔽區域42b!的間隙處。值得丨主音 的是,由於第一閘極絕緣層40之遮蔽區域40、、4Gb 、: 2 弟V. Description of the invention (9) wi=D2, 〇 further, the second shielding region 4 〇h of the first gate insulating layer 40 is adjacent to the first shielding region 42N of the second gate insulating layer 42, and The gap between the second shielding area 40b2 and the first shielding area 42bi is exposed to the lower effective layer. The outer side of the first shielding area 40b of the second gate edge layer 40 is exposed to the lower effective layer 34'. The outer side of the second masking region 22t) of the second gate insulating layer 42 exposes the underlying active layer 34. 2, then, as shown in FIG. 2D, a lightly doped ion implantation process 44 is performed, using the first and second gate layers 38, 38, and the masking region 40 of the first gate insulating layer 40. b!, 4 ΟΝ, the shielding regions 421^, 42bz of the second gate insulating layer 42 as a mask' can form a plurality of regions having different doping concentrations in the active layer 34. The first and second regions 341, 342 are undoped regions 'and are correspondingly formed below the central regions 4a, 42a. The second and fourth regions 343 and 344 are an N-doped region, and are correspondingly formed under the first and second shielding regions 4 〇 h, 4 0 b2 of the first gate insulating layer 40. The fifth and sixth regions 345, 346 are an N-doped region, and are correspondingly formed under the first and second shielding regions 42 b!, 42 b > 2 of the second gate insulating layer 42. The seventh region 347 is an N-doped region exposed outside the first shielding region 4Ob! of the first gate insulating layer 40. The 'eight' region 3 4 8 is an N-doped region exposed to the outside of the second masking region 42b2 of the second gate insulating layer 42. The ninth region 349 is an N-doping region ′ that is exposed to the gap of the first shielding region 42b! of the second shielding region 4 〇b2 'the second gate insulating layer 42 of the first gate insulating layer 40 At the office. It is worthy of the main sound, because the shielding area of the first gate insulating layer 40, 4Gb,: 2 brother
1307961 五、發明說明(10) 閘極絕緣層42之遮蔽區域42b 42b係用為輕 =程“之罩幕,因此第三、第四區域343、3“雜二 ^五:第六區域345、34 6之邊緣乃實質上對齊於第_、第 一遮蔽區域42^、42bz的邊緣。此外,藉由調整輕摻雜離 ,佈植製程4 4之加速電壓與劑量,可以控制第三、第四、 第五、第六區域343、344、345、346的濃度,以使其成為 摻^雜區域或是濃度極小之間隔區域(〇f fset regi()n): ,、取後,如第2E圖所示,進行沉積、微影與蝕刻製程以 y成一光阻層46,使其覆蓋第一閘極絕緣層4〇之第二遮蔽 區域4〇b2、第二閘極絕緣層42之第一遮蔽區域42h及其間 隙處之第九區域34 9。繼續,進行一重摻雜離子佈植^程 48,利用光阻層46、第一、第二閘極層38I、3811、第一 閘極絕緣層40之第一遮蔽區域40 bi、第二閘極絕緣層42之 第二遮蔽區域42b2作為罩幕,可以增加有效層34之第三區 ,343、第六區域346、第七區域347、第八區域348之摻雜 濃度。如此一來,第三、第四區域343、344成為一N—摻雜 區域,第七區域347成為一N+摻雜區域,第八區域34 8乃為 一 N+摻雜區域。 ’ 、由上述可知,第七區域347、第八區域348為『摻雜區 域,係用作為一源極區域與一汲極區域;第三區域343、 第六區域346為N -摻雜區域,係用作為雙閘極結構之外圍 的LDD區域;第四區域344、第五區域345為計—摻雜區域, 係用作為雙閘極結構之内部的LDD區域;第九區域349為^1307961 V. INSTRUCTION OF THE INVENTION (10) The shielding region 42b 42b of the gate insulating layer 42 is used as a mask for the light=process, so the third and fourth regions 343 and 3 are “different and five: sixth region 345, The edges of 34 6 are substantially aligned with the edges of the first and first masking regions 42^, 42bz. In addition, by adjusting the light doping distance, the accelerating voltage and the dose of the implantation process 44, the concentrations of the third, fourth, fifth, and sixth regions 343, 344, 345, and 346 can be controlled to be blended. ^ impurity region or a very small interval region (〇f fset regi () n): , after taking, as shown in Figure 2E, deposition, lithography and etching process to y into a photoresist layer 46, so that The second shielding region 4〇b2 of the first gate insulating layer 4, the first shielding region 42h of the second gate insulating layer 42 and the ninth region 34 9 at the gap thereof are covered. Continuing, a heavily doped ion implantation process 48 is performed, using the photoresist layer 46, the first and second gate layers 38I, 3811, the first shielding region 40 bi of the first gate insulating layer 40, and the second gate. The second shielding region 42b2 of the insulating layer 42 serves as a mask to increase the doping concentration of the third region 343, the sixth region 346, the seventh region 347, and the eighth region 348 of the active layer 34. As a result, the third and fourth regions 343, 344 become an N-doped region, the seventh region 347 becomes an N+ doped region, and the eighth region 348 is an N+ doped region. As can be seen from the above, the seventh region 347 and the eighth region 348 are "doped regions, which are used as a source region and a drain region; and the third region 343 and the sixth region 346 are N-doped regions. The LDD region is used as the periphery of the double gate structure; the fourth region 344 and the fifth region 345 are the doped regions, which are used as the LDD region inside the double gate structure; the ninth region 349 is ^
1307961 圖式簡單說明 第1 A〜1 C圖顯示習知第一種雙閘極結構之多晶矽TFT製 程的剖面示意圖。 第1 D圖顯示習知第二種雙閘極結構之多晶矽TFT製程 的剖面示意圖。 第2 A〜2E圖顯示本發明第一實施例之雙閘極結構之多 晶矽TFT的製作方法的剖面示意圖。 第3圖顯示本發明第二實施例之雙閘極結構之多晶矽 TFT的剖面示意圖。 符號說明: 習知技4标 玻璃基板〜10 ; 緩衝層〜12 ; 多晶矽層〜1 4 ; N -摻雜區域〜1 4 a、1 4 a!、1 4 a2、1 4 a3、1 4 a4 ; N+ 摻雜區域〜14S、14D、14S/D ; 未摻雜區域〜14(^、14C2 ; 硼離子佈植製程〜16 ; 閘極絕緣層〜1 8 ; 閘極層〜2 0 ; 第一閘極層〜2 0 I ; 第二閘極層〜2 0 I I ; 輕摻雜離子佈植製程〜2 2 ; 光阻層〜24、241、2411 ; 重摻雜離子佈植製程〜26。 本發明技術1307961 BRIEF DESCRIPTION OF THE DRAWINGS The first embodiment of FIGS. 1A to 1C shows a schematic cross-sectional view of a conventional polysilicon TFT process of the first double gate structure. Fig. 1D is a schematic cross-sectional view showing a conventional polysilicon TFT process of the second double gate structure. 2A to 2E are cross-sectional views showing a method of fabricating a polysilicon TFT having a double gate structure according to a first embodiment of the present invention. Fig. 3 is a cross-sectional view showing a polysilicon TFT of a double gate structure according to a second embodiment of the present invention. DESCRIPTION OF REFERENCE NUMERALS: conventional technique 4 standard glass substrate ~10; buffer layer ~12; polycrystalline germanium layer ~1 4 ; N -doped region ~1 4 a,1 4 a!,1 4 a2,1 4 a3,1 4 a4 N+ doped region ~14S, 14D, 14S/D; undoped region ~14 (^, 14C2; boron ion implantation process ~16; gate insulating layer ~1 8; gate layer ~20; first Gate layer ~ 2 0 I; second gate layer ~ 2 0 II ; lightly doped ion implantation process ~ 2 2 ; photoresist layer ~ 24, 241, 2411; heavily doped ion implantation process ~ 26. Invention technology
〇773-9592CIPTWF(Nl);P92031;cherry.ptd 第19頁 1307961 圖式簡單說明 基底〜3 0 ; 緩衝層〜3 2 ; 有效層〜3 4 ; 區域〜341 ' 342 '343 '344 '345 '346 '347 '348 ' 349 ; 絕緣層〜3 6 ; 第一閘極層〜3 8 I ; 第一閘極絕緣層〜4 0 中央區域〜40a ; 第二遮蔽區域〜40b2 延伸區域〜40c ; 中央區域〜42a ; 第二遮蔽區域〜42 b2 延伸區域〜42c ; 光阻層〜4 6 ; 導電層〜38 ; 第二閘極層〜3 8 I I ; 第一遮蔽區域〜401^ ; 第二閘極絕緣層〜4 2 ; 第一遮蔽區域〜421^ ; 輕摻雜離子佈植製程〜44 ; 重摻雜離子佈植製程〜4 8。〇773-9592CIPTWF(Nl);P92031;cherry.ptd Page 19 1307961 Schematic description of the substrate ~3 0; buffer layer ~3 2 ; effective layer ~3 4 ; area ~341 ' 342 '343 '344 '345 ' 346 '347 '348 ' 349 ; Insulation layer ~ 3 6 ; First gate layer ~ 3 8 I ; First gate insulating layer ~ 4 0 Central area ~ 40a ; Second masking area ~ 40b2 Extended area ~ 40c ; Area ~42a; second masking area ~42 b2 extension area ~42c; photoresist layer ~4 6 ; conductive layer ~38; second gate layer ~3 8 II; first masking area ~401^; second gate Insulation layer ~ 4 2 ; first masking area ~ 421 ^ ; lightly doped ion implantation process ~ 44; heavy doping ion implantation process ~ 4 8 .
0773-9592CIPTW(Nl) ;P92031 ;cherry .ptd 第20頁0773-9592CIPTW(Nl) ;P92031 ;cherry .ptd第20页
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JP2004132507A JP4101787B2 (en) | 2003-04-28 | 2004-04-28 | Multi-gate thin film transistor and method of manufacturing the same |
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US8890165B2 (en) | 2009-11-13 | 2014-11-18 | Samsung Display Co., Ltd. | Method of forming polycrystalline silicon layer, thin film transistor, organic light emitting diode display device having the same, and methods of fabricating the same |
US9035311B2 (en) | 2009-03-03 | 2015-05-19 | Samsung Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
US9117798B2 (en) | 2009-03-27 | 2015-08-25 | Samsung Display Co., Ltd. | Thin film transistor, method of fabricating the same and organic light emitting diode display device including the same |
TWI548039B (en) * | 2015-03-17 | 2016-09-01 | 力晶科技股份有限公司 | Method for fabricating semiconductor device |
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US9035311B2 (en) | 2009-03-03 | 2015-05-19 | Samsung Display Co., Ltd. | Organic light emitting diode display device and method of fabricating the same |
US9117798B2 (en) | 2009-03-27 | 2015-08-25 | Samsung Display Co., Ltd. | Thin film transistor, method of fabricating the same and organic light emitting diode display device including the same |
TWI578541B (en) * | 2009-03-27 | 2017-04-11 | 三星顯示器有限公司 | Thin film transistor, method of fabricating the same and organic light emitting diode display device including the same |
US8890165B2 (en) | 2009-11-13 | 2014-11-18 | Samsung Display Co., Ltd. | Method of forming polycrystalline silicon layer, thin film transistor, organic light emitting diode display device having the same, and methods of fabricating the same |
TWI548039B (en) * | 2015-03-17 | 2016-09-01 | 力晶科技股份有限公司 | Method for fabricating semiconductor device |
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