1305982 a) 玖、發明說明： 先前技術 本發明係關於無線數位通訊系統，特別是本發明係關於 無線TD-CDMA通訊接收器内用於分碼、擾碼和通道回應的 迴旋之方法和裝置，以計算系統傳送矩陣係數p 在像是由第三代夥伴計劃（Third Generation Partnership Project ’ 3GPP)所規定的TD_CDMA系統内之通訊期間，基地 台和使用者設備（UE)之間的每一信號脈衝都會以化分成時 槽的方式沿著訊框結構發送和接收。圖i顯示包含位於兩資 料符號叢集之間一預定中置碼的通訊脈衝時槽結構，尤其 是為了通道評估目的由基地台指派至UE的結構β中置碼資 訊的特徵在於有許多月碼，其中Tc代表片碼期間而k為中 置碼長度。在接收器内運作的濾波器會將前置碼片碼轉換 成由實體和虚數成分構成的通道回應，因為tD_cdma系統 允許將許多UE指派至相同時槽，每個都有獨一的展頻碼以 及附加的展頻因數，來分辨彼此的^£中置碑通道代表。擾 瑪附加至信號上以分辨出基地台彼此，藉此避免基地台内 部干擾’這有可能發生於在雨鄰近基地台範圍内時。 在無線傳送通過發射器與接收器之間的空間時，信號干 擾以及外部雜訊影響會讓接收到的信號不同於原始狀態。 因此，在通訊系統内’發展出一套對於特定基地台和UE來 說獨一的已知系統傳輪特性之代表非常有用。在3GPP系統 内’為此使用了係數值的系統傳輸矩陣A以及/或其複合 (-3) (-3)1305982 接合調換ΑΗβ將接收到的信號供應至系統傳輸矩陣係數是 一種方式，可以從所接收受到外部影馨的信號中取得原始 信號資料。 發明内容 本發明提供一種資料處理的裝置和方法，其特別適用於 分碼、擾碼和通道回應的結合迴旋，以架構出***傳送係 數矩陣，而仍舊能夠維持和在分別執行每一迴旋時相同之 電路大小和執行時間。 本發明包含特別是處理一系列雙元素資料值％至像 是複數代表）的裝置和方法，其中整數1)1從丨到％的資料值Vm 對應至具有N位元二進位值的第一元素和第二元素， 其中N為正偶整數，來產生一系列資料值v、至V、，其中每 一整數P從1至y的資料值¥、對應至第一元素A，p和第二元素 B’P。較好是，一系列資料值％至^代表具有#展頻因數（其 中Μ為整數並且2msN)的通訊信號之通道反應值□在這種案 例中’N位元二進位值代表隨複通訊信號的通道碼值，並且 系列資料值^、至y’y代表一列系統傳輪矩陣值，N較好是 2的乘方β 在此提供第一元素位移暫存器反〗和第二元素位移暫存器 汉2 ’每個暫存器Rl、R2都具有一系列Ν位置ci，每個整數i 都從1至N，每個暫存器r〗、r2都分別隨附第一元素加法器 電路A1，1、A1>2，以及第二元素加法器電路A21、A2,2。 每個加法器電路都具有一系列N/2選擇性可控制輸入ik， 每個整數k從1至N/2。每個加法器電路輸入都和不同的暫存 器位置叙合，來接收其實料。透過隨附個別暫存器位置的 1305982 控制位元可控制每侗&A Α J母個加法器電路輪入，其中控制位元會集 體回應N位元二進伤推 ^ A ^ 值β每一隨附暫存器rr的位置Ci之控制 位元Bi和隨附暫存装兑以，_ . 仔器Ri的位置Ci之控制位元B〗相同，其中每 -整數!從1至N，如此根據控制位元之值，輸入會接收來自 其耦。位置的資料’當成接收的資料之值或反向值。每個 加法器電路都具有—^ ^ ^ ^ 輸入，用於輸出其個別可控制輸入所 接收的值總合β 較好疋第元素加法器電路All和暫存器及丨輕合，如此 輸入ik接收來自暫存器位置C2k·】的資料，其中每個整數^ 從1至赠。第二元素加法器電路A2，!和暫存器R一合，如此 輪入接收來自暫存器位置C2k的資料’其中每個整數 至N/2〇第一元素加法器電路A"和暫存器心耦合，如此輸 入1k接收來自暫存器位置C21c的資料，其中每個整數!至 N’2。第二元素加法器電路Ay和暫存器i耦合，如此輸入 L接收來自暫存器位置cnq的資料，其中每個整數^^從】至 N/2。 第一元素結合器電路耦合至第一元素加法器電路An、 a1>2的輸ώ，用於輪出處理值v，p的第一元素值A、。第二元 素結合器電路耦合至第二元素加法器電路Au、Α22的輸 出’用於輪出處理值V’p的第一元素值Β，ρβ 暫存器Rr、R][可操作將其個別位置的資料位移，並接收 新的資料而產生下一個處理值V，p + 1。較好是，暫存器Ri、 I可操作來將個別位置Ci-i至位置Ci的資料位移，其中每個 整數i從2至N，並在位置C1内接收新資料而產生下一個處理 值0 8 (-0 1305982 較妤是，所提供的控制電路可根據通訊（對應至 資料值串列)的展顏因數，操作來控制暫存器和 電 路。控制電路可操作來依序將一系列資料值％至、（跟 系列N]零值）輸入至暫存器⑽次，以產生^ x V，,至V，y，其中^Χ+Ν]，每一 貧种值 Α糸統傳輪矩陣值《 當2 <贿，控制電路可操作來選擇性啟動和關閉加法器電 路的輸入，如此每次一系列資料值％至、輪入暫存器内， 來自每一暫存器不同2M輪入集合就會致動，而其他加法器 輸入則關閉。 較好是’暫存器1和112為每個位置具有？位元的赚置型 (Ν’，用於透過迴旋移動通道回應。在多工器内，將使 用以金字塔方式連接的最佳最少數量加法器來執行代碼之 增質，以簡化構造'㈣包含從二進位表示至複雜表示而 當成整個方法-部分的通道碼轉換’如此可從裝置内消除 不必要的加法器》 精通此技術的人士從下列說明中就可了解到其他目的和 優點β 實施方式 慮下將參考附圓説明較佳具體實施例，其中相同的號碼 代表相同的元素。 請參閱圖2Α和2Β，其中分別說明電路圖1〇〇和2〇〇，用於 執行TD-CDMA時槽隨附的一系列實質和虚數通道回應片碼 值之迴旋。通道回應值區分成實質部分和虚數部分 CRI。電路100會處理實質通道回應CRR,而電路2〇〇則處理 虛數通道回應CRI。 1305982 (〇) 在圖2A内’暫存器Rr較好是職暫存器，可接收通道回 應CRR的實數部分。暫存器及汉的每個位置以（㈣至μ)每個位 置具有F位tc ,其中F為選取的資料位元大小，較好是。 對應至較佳通道碼大小的位置數目前在内指定為^， 並且較好是數字2的乘冪。實數成分電路⑽包含複數個元 素A1-A14,每一加法器元素都具有兩輸入一輪出（為該兩輪 入的合）的加法器。加法器元素人卜^^較好如圓4内所說明來 設定。加法器元素A9-A14較好是簡單加法器。 力法器元素Al、A2、A3、A4接收來自暫存器^^奇數位置 的輸入，鼓在其輸入對上執行加法或減法。類似地，加法 器兀素A5、A6、A7和A8耦合至暫存器Rr，以在通道回應值 上執行加法或減法，但是只在暫存器^^的偶數位置上運 集β來說，加法器元素AH4、A9-A11形成一個加法器 樹枝狀電路，具有由元素A1-A4定義的輸入以及元素A11定 義的輪出β類似地，加法器元素A5_A8、A12-A14形成第二 加法器樹枝狀電路。加法器樹枝狀電路的隨附暫存器r_r， '十算出自由暫存器Rr所處理的CRR值之處理值虚數部分。 用來當成控制信號，具有位元cc〇至CC15的通道碼（^會 輸入至加法器元素入1至A卜二進位通道碼根據個別控制位 元控制加法·器元素Ai至人§執行加法或滅法，較好是當通道 碼cc位元時為加法並且當通道碼CC位元=1時為減法。 圖4說月輪入加法器元素人^具有一個加法器A〗，以及兩個 、補裝置TCI、TC2之較佳構造。輸入CRR1和CRR3接收 暫存器第二和第四位置C1、C3内含的實數通道回應值， 由二的互補裝置TCI、TC2來處理D利用加法器A1，加總二的 10 1305982 (Ο 互補裝置TCI、TC2的输入，而達成CCR值加法或減法"這 兩互補裝置TCI、TC2利用將值或其二的互補傳遞至加法器 • 人1’ ’以便在輸入值上操作》16位元通道碼控制信號CC的第 二位元CC1利用二的互補裝置TC1執行操作判斷，而通道碼 的第四位元CC3則利用二的互補裝置TC2執行操作的判斷。 請參閱圖2A，加法器A9執行由A1和A2執行的加總之粂 總。類似地，加法器A10執行A3總合和A4總合的加總，加 法器A12執行A5總合和A6總合的加總，並且加法器A13將A7 和A8加在一起。加法器All利用將A9和A10的總合加起來以 產生輸出AC，就是實數通道回應值的實數部分e輸出 jAD(實數通道回應值的虚數部分）為加法器a14所產生的加 總’就是加法器A12和A13的輸岀加總。 如圖2B内所示的處理電路2〇〇構造類似於圊2A内所示的 電路100。不遇，也移暫存器Ri接收通道回應的虚數部分 CRI。加法器元素A15至A28對應於加法器元素，產 生具有兩隨附加法器樹枝狀電路的暫存器兒厂圈犯内所示 電路200的加法器樹枝狀電路之兩輸出為圖2人内所適用於 電路1〇〇的相反，其中對應至實數部份顯示當成輪出；61)的值 來自暫存HR!的偶數位置’並且對應至虚數輸出jBC的值為 暫存器Rz奇數位置的最後總合。關轸偶數和奇數暫存器位 置的實數和虚數輸&之組態可完全反向，並獲得一樣的結 果。尤其疋，以圖2A和2B内交換的暫存器心和心來說，輪 出AC和jBC#自於偶數暫存器位置並且輸出扣和則得 自於奇數暫存器位置。 雖然圖2A和2B的暫存器已經各自用16位置來代表，依照 11 (2) 1305982 本發明的通道回應值之迴旋通常可使用具有2N暫存器位置 的暫存器來達·成，並且結合所有據此設定的多或少加法 器’以執行偶數和奇數暫存器位置上的加總。 電路100和200的四個輸出值AC、BD、j AD和jBC代表乘法 運算的實數和虚數部分，如方程式1内所示： AH=(A+jB)*(C+jD)方程式 1 其中A通道回應的實數部分，b為通道回應的虚數部分，並 且其中C對應至通道碼CC的位元Cl、C3、C5、C7、C9、C11、 C13、C15，D對應至通道碼的位元 c〇、C2、C4、C6、C8、C10、 C12、C14。每個通道碼位元代表純實數或純虚數之值。因 此’加法器樹枝狀電路可連線至暫存器^和Ri的所有奇數 或所有偶數位置。依照本發明用於判斷哪個通道碼位元為 實數或虛數所使用的加法器樹枝狀消除了乘法器的需求， 乘法器會消耗較多的硬髏空間。 如圖3内所示，提供額外電路來結合電路1〇〇、200的加法 器樹枝狀產生用於架構系統傳輸係數矩陣複合連接調換 AH的係數值（對應至實數和虛數輸出值）。減法器si隨附於 電路100的輸出Αα及電路2〇〇的輸出以減去已處理的 實數通道回應信號的實數部分以及虛數通道回應信號的實 數部分加法器Α29隨附於電路200的輸出jBC以及電路100 的輸出jAD’以將已處理的虛數通道回應信號的虛數部分以 及只數通道回應信號的虛數部分相加。然後將加法器A29 產生的加總傳遞過用於虛數輸出的二的互補裝置丁。3,而產 生A矩陣的複合撞么士。+丄_ 連心在本發明的其他具趙實施例内，已將 裝置TC3省略，因此.哞阁< 囚此允許圖2A ' 2丑和3的電路產生 12 (3) (3)1305982 其在CDMA信號的處理中也非常有用。 較好是，通道碼CC為方程式2所示16位元長擾碼s和修改 過的16位元展頻瑪SCM之互斥（x〇r)運算，所建立的,μ位元 長二進位數》 CC=S XOR SCM 方程式 2 若要產生16位元SCM，利用重複展頻碼Sc的第一 SF位數， 直到產生16位无值來修改展頻碼SC，其中SF為展頻因數 值。例如，對於展頻碼因數SF8以及展頻碼SC=0011 1111 〇〇〇〇 1010來說，修改過的展頻碼SCM=0011 1111 OOii mi即是sc 的前八個位數重複了兩次。以此方式建構的通道碼提供了 通道重複CR值、展頻碼SC和擾碼S迴旋所需的裝置。通道 碼CC在迴旋處理期間仍舊固定，因為展頻因數SF和擾碼s 設定用於已處理的特定UE /基地台通訊。藉由結合所有操作 (即是擾碼和展頻碼結合）取代在個別處理階段内分別執 行’如此就可省略乘法器。在所公铈的設計中可將加法器 所需的數量最佳化》 16位元通道碼CC會當成控制信號連續呈現給圖2Α的第一 階加法器元素Α1至Α8以及囷2Β的加法器元素Α15至Α22，用 於判斷輪入加法器的值在加總之前是否無效或仍舊相同。 如上提及，每一加法器都受到通道碼位元（用輸入加法器的 暫時位置來修正）控制。例如，加法器Α1受到通道碼位元cci 和CC3的控制，如圖2Α内所是對應於暫存器rr的位置ci和 C3 » 此外’電路1〇〇、2〇〇和加法器樹枝狀電路的運算都受到展 頻因數SF的控制。在較佳具體實施例内，其中使用16位置 13 (4) (4)1305982 暫存器’展頻因數的可能值為1、2、4、8或16。每组通道回 應CR要由每一電路1〇〇、200執行的完整處理週期數量取決 於關係16/SF，例如對於展頻因數SF=16而言，處理電路1〇〇、 200會操作CR值一個週期，對於SF=4則處理4次（16/4)。 暫存器一開始在所有位置上都為零值，一旦開始週期處 理’第一°^值會初次輸入位置C0並且每一位置Ci(值=0)的 内容會往右移動-個位置。暫存器Rr的位置CO接收實數成 分’並且暫存器Ri的位置C0則接收虚數成分。複合係數值 根摟暫存器值計算並從圖3的結合電路輸出，並如上述選擇 性控制加法器樹枝狀。然後再次位移暫存器位置的值，如 此暫存器位置Ci中i>i接收來自暫存器位置ci-1的值，並且 下一個CR值輪入位置c〇，分別用於每一暫存器rr、。然 後在週期期間處理會重複至整组CR值都依序輸入位置 C0-C15。當整組的所有CR值都已經輸入，處理會繼續將零 值輪入位置C0和每個依序位置，直到最後一個cr值移出位 置C15»因此’對於CR組N值而言，在每個運算週期都有：K+15 輸出值。一般而言’在系統用X暫存器位置設定之處，運算 週期會從一组N值產生N+(X-1)輸出值。 在每個處理週期輸入加法器樹枝狀電路的作用輸入數等 於16/SF ’當CR值處理超過一次，即是SF?tl6，則每一週期 會啟用不同的輪入紕。對於展頻因數SF=8而言，第一運算 週期由通道碼CC0至CC7的前八位元所控制。如此，圖2A的 加法器元素Al、A2、A5、A6和圖2B的加法器元素A15、A16、 A19和A20會啟用來接收來自位置C0至C7之值。在此第一運 算期間，所有剩餘輸入若接收零值也會運作" 14 (5) (5)1305982 在第二週期期間》加法器元素A3、A4、A7、A8和A17、 A18、A21、A22的輪入都會啟用，以接收來自暫存器“和 Ri的資料並且取消其他加法器樹枝狀輸入。對於展頻因數 SF=2而言，作用輸入較好是第一週期來自暫存器位置c〇、 Cl、第二週期來自C2、C3，如此最後第八週期就為ci4,C15。 圖2A和2B的轉換器1〇1產生回應至展頻因數SF的啟用信號 E’據此控制來自暫存器“和心的加法器元素輸入之啟用。 囷5顯示尺寸HxW的系統傳輪係數矩陣AH的方塊圖，其中 H=16為根據通訊***的較佳最大可能向量數D為了填滿矩 陣的十六列，將再通道環應順序上執行十六次運算週期， 每一運算週期都由通道碼控制，以判斷AH矩陣上一列向量 之值。對於一系列N值其中N=57而言，每一矩陣列包含W=72 值，如此會處理該系列直到最後一個N值通過最後一個暫存 器位置。N、W和Η可根據特定通訊系統而改變。 在3GPP内，標準資源單元RU由展頻因數SF所定義。展頻 因數SF代表特定RU的每位元月碼數，或位元率》因此，具 有展頻因數SF = 8的RU其位元率為具有展頻因數SF=16的RU 之兩倍。如此，如圖5的列7和8内所示，矩陣AH的一列用於 展頻因數為16的每一 RU，如此只需要一個通道回應值設定 過暫存器尺汉和！^的處理週期》展頻因數等於8的RU需要兩 個處理週期，因此佔用矩陣的兩列。對於展頻因數等於4 而言，RU佔用矩陣的4列用於通過四個通道回應。類似地， 展頻因數等於2的RU佔用8列，並且展頻因數等於1的RU佔 用全部16列》該系統設計成若佔用15列，將以展頻因數等 於16執行RU的最终運算。否則，矩陣的最後一列會填滿零， 15 1305982 ⑹ 個矩陣列内。類似 下的列，***會用 因為其他任何展頻因數都無法填入〜 地’對於其他所有組合而言，當佔用剩 適當的展頻因數容納^ 如圖5内所示’對於展頻因數16而言， 起陣的所有列都填 入計算過的迴旋結果係數值。對於其 丹他所有展頻因數面 言，由於啟用信號E控制加法器樹枝狀輪 、 在矩陣列一端 或兩端上會產生連續零的區@，而在處理期間強迫選擇的 零值。例如，對於展頻因數SF = 8而言，因為只啟用暫存器 前8位置隨附的輪入，所以列〗的最後8個值為零，並且在第 一操作週期的最後8週期包含零值。類似地，因為位置⑶ 至C7隨附的加法器樹枝狀輸入未啟用，並 社第二通過的 頭8處理反覆時位置C8至C15具有零值，則矩陣（隨附第二處 理遇期結果）内列2的前8值為零。 圖6顧示在展頻因數SF=1的加法器元素上啟用信號£的效 果。在通道回應的第一通過期間，因為受到啟用信號E的控 制，從位置C1至C15的加法器樹枝狀輸入並未啟用，所以加 法器元素A5和A19只會處理來自位置CO的輸入a在第二通過 期間’當只有暫存器位置C15提供啟用的輪入给加法器，則 來自暫存器位置C1的輸入提供單獨輪入至加法器樹故狀等 等，直到第十六週期。 雖然已經藉由參考某些特定具體實施例來說明部分本發 明，這些細節用於指示而非限制。精通此技術的人士就能 了解，在不悖離此處說明的本發明精神和領域之下，可對 結構以及操作模式方面可進行許多修改。 圖式簡單說明 16 1305982 ⑺ 圖1顯示一包含多重片碼的中置碼之時槽結構，本發明運 作其上。 圖2A顯示用於將通道回應的實數部分迴旋的裝置。 圖2B顯示用於將通道回應的虛數部分迴旋的裝置。 圖3顯示用於將圖2A和圖2B裝置的輸出加總，以產生用於 建構系統傳輸係數矩陣的實數和虛數輸出之裝置。 圖4顯示顯示用於圖2A和圖2B的加法器樹枝狀輸入之較 隹電路。 圖5顯示系統傳輸矩陣複合連結調換AH的尺寸。 圖6顯示展頻因數1的系統傳輸矩陣複合連結調換AH之尺 寸。 100 200 Α1Ά14 Rr CC CC0至 CC15 TC1 TC2 AC JAD Ri A15-A281305982 a) 发明, DESCRIPTION OF THE INVENTION: BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to wireless digital communication systems, and more particularly to a method and apparatus for rounding, scrambling, and channel response in a wireless TD-CDMA communication receiver, Transmitting the matrix coefficient p in the computing system. During the communication in the TD_CDMA system as defined by the Third Generation Partnership Project (3GPP), each signal pulse between the base station and the user equipment (UE) It will be sent and received along the frame structure in a manner that is divided into time slots. Figure i shows a communication pulse slot structure comprising a predetermined midamble between two data symbol clusters, in particular a structure assigned to the UE by the base station for channel estimation purposes. The beta midamble information is characterized by a plurality of monthly codes. Where Tc represents the chip code period and k is the midamble length. A filter operating in the receiver converts the preamble chip code into a channel response consisting of both physical and imaginary components, since the tD_cdma system allows many UEs to be assigned to the same time slot, each with a unique spread spectrum. The code and the additional spreading factor are used to distinguish each other's membrane channel representation. The scrambling is attached to the signal to distinguish the base stations from each other, thereby avoiding internal interference in the base station. This may occur when the rain is in the vicinity of the base station. When wirelessly transmitting through the space between the transmitter and the receiver, signal interference and external noise effects can cause the received signal to differ from the original state. Therefore, it is useful to develop a representative set of known system pass characteristics for a particular base station and UE within the communication system. In the 3GPP system, the system transmission matrix A and/or its composite (-3) (-3) 1305982 splicing ΑΗβ using the coefficient value for this purpose is a way to supply the received signal to the system transmission matrix coefficient. The original signal data is obtained from the signal received by the external image. SUMMARY OF THE INVENTION The present invention provides an apparatus and method for data processing, which is particularly suitable for combining a convolution of a code division, a scrambling code, and a channel response to construct a system transmission coefficient matrix while still being able to maintain and be the same when performing each convolution separately. Circuit size and execution time. The invention comprises, in particular, a device and method for processing a series of two-element data values % to, for example, a complex representation, wherein an integer 1)1 from 丨 to % of a data value Vm corresponds to a first element having an N-bit binary value And a second element, wherein N is a positive even integer, to generate a series of data values v, to V, wherein each integer P has a data value from 1 to y, and corresponds to the first element A, p and the second element B'P. Preferably, a series of data values % to ^ represent a channel response value of a communication signal having a #spreading factor (where Μ is an integer and 2 msN). In this case, the 'N bit binary value represents a complex communication signal. The channel code value, and the series data value ^, to y'y represents a column of the system transfer matrix value, N is preferably the power of 2 β here provides the first element displacement register reverse and the second element displacement存汉汉 2 'Each register Rl, R2 has a series of Ν position ci, each integer i is from 1 to N, and each register r 〗 and r2 are respectively accompanied by the first element adder circuit A1, 1, A1 > 2, and second element adder circuits A21, A2, 2. Each adder circuit has a series of N/2 selectable controllable inputs ik, each integer k being from 1 to N/2. Each adder circuit input is summed with a different register location to receive the actual material. Each of the 侗 &A Α J parent adder circuit is controlled by the 1305982 control bit with the location of the individual register, wherein the control bit will collectively respond to the N-bit binary injection. A ^ value β per The control bit Bi of the position Ci accompanying the register rr and the accompanying temporary storage are the same as the control bit B of the position Ci of the child Ri, wherein each integer is from 1 to N, Thus, depending on the value of the control bit, the input will be received from its coupling. The location data 'as the value of the received data or the reverse value. Each adder circuit has a -^ ^ ^ ^ input for outputting the sum of the values received by its individual controllable inputs. Preferably, the first element adder circuit All and the register and the buffer are lightly coupled, so input ik Receive data from the scratchpad location C2k·], where each integer ^ is from 1 to the gift. The second element adder circuit A2, ! and the register R are combined, so that the data from the register position C2k is received in turn, wherein each integer to N/2 〇 first element adder circuit A" and temporary storage The heart is coupled such that input 1k receives data from register location C21c, where each integer! to N'2. The second element adder circuit Ay is coupled to the register i such that the input L receives data from the register location cnq, wherein each integer ^^ is from n to N/2. The first element combiner circuit is coupled to the input of the first element adder circuit An, a1 > 2 for rounding out the first element value A of the processed value v, p. The second element combiner circuit is coupled to the output of the second element adder circuit Au, Α22, the first element value 轮 used to rotate the processed value V'p, ρβ register Rr, R] [operably individualized The position of the data is shifted and a new data is received to produce the next processed value V, p + 1. Preferably, the registers Ri, I are operable to shift the data of the individual positions Ci-i to the position Ci, wherein each integer i ranges from 2 to N and receives new data in position C1 to produce the next processed value 0 8 (-0 1305982) Furthermore, the control circuit provided can operate to control the register and the circuit according to the display factor of the communication (corresponding to the data value string). The control circuit can be operated to sequentially sequence The data value % to, (with series N] zero value) is input to the scratchpad (10) times to generate ^ x V, to V, y, where ^Χ + Ν], each poor value Α糸 传Matrix value "When 2 < bribe, the control circuit is operable to selectively activate and deactivate the input of the adder circuit, so each time a series of data values are up to, in the register, different from each register 2M The rounding of the collection will be actuated, while the other adder inputs will be closed. Preferably, the 'storage registers 1 and 112 are earned by each bit with a bit (Ν' for responding through the whirling mobile channel. Within the multiplexer, the best minimum number of adders connected in a pyramid will be used to perform code increments. Qualitative, to simplify the construction '(4) contains from binary representation to complex representation as the entire method - part of the channel code conversion 'so can eliminate unnecessary adders from the device." Those skilled in the art can understand from the following description Other objects and advantages will be described with reference to the preferred embodiments in which the same reference numerals represent the same elements. Referring to Figures 2A and 2B, which illustrate circuit diagrams 1 and 2, respectively, The series of substantial and imaginary channels accompanying the slot in the TD-CDMA implementation are responsive to the chip value. The channel response value is divided into a substantial part and an imaginary part CRI. The circuit 100 processes the substantial channel response CRR, and the circuit 2〇 〇 Processing the imaginary channel response CRI. 1305982 (〇) In Figure 2A, the 'storage register Rr is better than the register, which can receive the real part of the channel response CRR. Each location of the register and the han ((4) To μ) each position has an F bit tc, where F is the selected data bit size, preferably. The number of positions corresponding to the preferred channel code size is specified as ^, and preferably the number 2 is multiplied. The real component circuit (10) includes a plurality of elements A1-A14, each of which has an adder of two inputs and one round (for the combination of the two rounds). The adder element is better as a circle 4 The setting is as described in the following. The adder elements A9-A14 are preferably simple adders. The force element elements A1, A2, A3, A4 receive the input from the odd position of the register, and the drum performs addition on its input pair. Or subtraction. Similarly, adder elements A5, A6, A7, and A8 are coupled to the register Rr to perform addition or subtraction on the channel response value, but only in the even position of the register ^^. In other words, adder elements AH4, A9-A11 form an adder dendritic circuit having an input defined by elements A1-A4 and a round-out β defined by element A11, similarly, adder elements A5_A8, A12-A14 form a second Adder dendritic circuit. The add-on register r_r of the adder dendrite, '10 calculates the imaginary part of the processed value of the CRR value processed by the free register Rr. Used as a control signal, the channel code with bits cc〇 to CC15 (^ will be input to the adder element into the 1 to A binary channel code according to the individual control bit control adder element Ai to the person § perform addition or The extinction method is preferably subtracted when the channel code cc bit is used and subtracted when the channel code CC bit = 1. Figure 4 shows that the moon wheel input adder element ^ has an adder A, and two, complement A preferred configuration of the devices TCI and TC2. The input CRR1 and CRR3 receive the real channel response values contained in the second and fourth positions C1 and C3 of the register, and the complementary devices TCI and TC2 of the second process D use the adder A1. Adding a total of 10 1305982 (Ο the input of the complementary device TCI, TC2, and achieving the CCR value addition or subtraction " the two complementary devices TCI, TC2 use the complement of the value or its two to the adder • person 1 ' ' The second bit CC1 of the 16-bit channel code control signal CC is operated on the input value, and the operation judgment is performed by the complementary device TC1 of the two, and the fourth bit CC3 of the channel code is judged by the operation of the complementary device TC2 of the two. Please refer to FIG. 2A, the adder A9 performs The sum of the totals performed by A1 and A2 is similar. Similarly, adder A10 performs the sum of A3 sum and A4 sum, adder A12 performs the sum of A5 sum and A6 sum, and adder A13 will A7 and A8 is added together. The adder All uses the sum of A9 and A10 to add the output AC, which is the real part of the real channel response value e output jAD (the imaginary part of the real channel response value) is generated by the adder a14 The summation 'is the sum of the adders A12 and A13. The processing circuit 2 shown in Fig. 2B is constructed similarly to the circuit 100 shown in Fig. 2A. Otherwise, the register Ri receiving channel is also shifted. The imaginary part of the response CRI. The adder elements A15 to A28 correspond to the adder element, producing two of the adder dendrites having the circuit 200 shown in the register with the add-on dendrite circuit The output is the opposite of that applied to circuit 1〇〇 in Figure 2, where the corresponding to the real part shows the round-out; the value of 61) comes from the even-numbered position of the temporary HR! and the value corresponding to the imaginary output jBC The last sum of the odd positions of the register Rz. The configuration of the real and imaginary inputs of the odd register location can be completely reversed and achieve the same result. In particular, the AC and the heart are exchanged in the register heart and heart exchanged in Figures 2A and 2B. And jBC# from the even register location and the output buckle is derived from the odd register location. Although the registers of Figures 2A and 2B have each been represented by 16 locations, the channel according to 11 (2) 1305982 The spin of the response value can typically be achieved using a scratchpad with a 2N scratchpad location, and in conjunction with all of the more or less adders set accordingly to perform summation at the even and odd register locations. The four output values AC, BD, j AD and jBC of circuits 100 and 200 represent the real and imaginary parts of the multiplication operation, as shown in Equation 1: AH = (A + jB) * (C + jD) Equation 1 The real part of the A channel response, b is the imaginary part of the channel response, and C corresponds to the bit code C1, C3, C5, C7, C9, C11, C13, C15, D of the channel code CC corresponding to the bit of the channel code Yuan c〇, C2, C4, C6, C8, C10, C12, C14. Each channel code bit represents the value of a pure real or pure imaginary number. Therefore, the adder dendrite can be wired to all odd or all even positions of the registers ^ and Ri. The adder dendron used to determine which channel code bit is a real or imaginary number in accordance with the present invention eliminates the need for a multiplier, and the multiplier consumes more hard space. As shown in Figure 3, additional circuitry is provided to combine the adder branches of the circuits 1, 200, 200 to produce coefficient values (corresponding to real and imaginary output values) for the architectural system transmission coefficient matrix composite connection swap AH. The subtractor si is supplied to the output Αα of the circuit 100 and the output of the circuit 2〇〇 to subtract the real part of the processed real channel response signal and the real part of the imaginary channel response signal. The adder Α29 is supplied to the output jBC of the circuit 200. And the output jAD' of the circuit 100 is added to add the imaginary part of the processed imaginary channel response signal and the imaginary part of the only number of channel response signals. The summation produced by adder A29 is then passed through the complementary device for the imaginary output. 3, and the composite of the A matrix produced a collision. + 丄 _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ It is also very useful in the processing of CDMA signals. Preferably, the channel code CC is a 16-bit long scrambling code s shown in Equation 2 and a modified 16-bit spread-spectrum SCM mutual exclusion (x〇r) operation, and the μ-bit long binary is established. Number CC=S XOR SCM Equation 2 To generate a 16-bit SCM, use the first SF digit of the repeated spreading code Sc until the 16-bit value is generated to modify the spreading code SC, where SF is the spread frequency factor . For example, for the spreading code factor SF8 and the spreading code SC=0011 1111 〇〇〇〇 1010, the modified spreading code SCM=0011 1111 OOii mi is the first eight digits of sc repeated twice. The channel code constructed in this way provides the means required for the channel repeating CR value, the spreading code SC, and the scrambling code S to be rotated. The channel code CC is still fixed during the whirling process because the spread factor SF and scrambling code s are set for the specific UE/base station communication that has been processed. By combining all operations (ie, scrambling code and spreading code combination) instead of performing separately in individual processing stages, the multiplier can be omitted. In the disclosed design, the number of adders required can be optimized. The 16-bit channel code CC is continuously presented as a control signal to the adder of the first-order adder elements Α1 to Α8 and 囷2Β of Fig. 2Α. The elements Α15 to Α22 are used to determine whether the value of the round-in adder is invalid or still the same before the summation. As mentioned above, each adder is controlled by the channel code bits (corrected by the temporary position of the input adder). For example, adder Α1 is controlled by channel code bits cci and CC3, as shown in Figure 2, corresponding to locations ci and C3 of register rr » In addition, 'circuits 1 〇〇, 2 〇〇 and adder dendrites The operations are all controlled by the spreading factor SF. In a preferred embodiment, the 16-position 13 (4) (4) 1305598 register register's possible value of the spreading factor is 1, 2, 4, 8, or 16. The number of complete processing cycles that each set of channel response CRs are to be executed by each circuit 1, 200 depends on the relationship 16/SF. For example, for the spreading factor SF=16, the processing circuits 1〇〇, 200 operate the CR value. One cycle is processed 4 times (16/4) for SF=4. The scratchpad initially has a zero value at all positions. Once the start cycle is processed, the first value will enter the position C0 for the first time and the content of each position Ci (value = 0) will move to the right - position. The position CO of the register Rr receives the real component 'and the position C0 of the register Ri receives the imaginary component. The composite coefficient value is calculated from the register value and output from the combined circuit of Fig. 3, and the adder is dendritic as described above. The value of the scratchpad position is then shifted again, such that i>i in the register position Ci receives the value from the register position ci-1, and the next CR value is taken into the position c〇 for each temporary storage Rr,. The processing then repeats during the cycle until the entire set of CR values are sequentially entered into positions C0-C15. When all CR values of the entire group have been entered, the process will continue to zero the value into position C0 and each sequential position until the last cr value moves out of position C15»so 'for CR group N values, in each The calculation cycle has: K+15 output value. In general, where the system is set with the X register location, the computation cycle produces an N+(X-1) output value from a set of N values. The number of input inputs to the adder daemon at each processing cycle is equal to 16/SF'. When the CR value is processed more than once, that is, SF?tl6, each cycle enables different roundings. For the spread spectrum factor SF = 8, the first operational period is controlled by the first octets of the channel codes CC0 to CC7. Thus, adder elements A1, A2, A5, A6 of FIG. 2A and adder elements A15, A16, A19, and A20 of FIG. 2B are enabled to receive values from positions C0 through C7. During this first operation, all remaining inputs will also operate if they receive a zero value " 14 (5) (5) 1305982 during the second period "Adder elements A3, A4, A7, A8 and A17, A18, A21, The wheeling of A22 is enabled to receive data from the register "and Ri" and cancel other adder dendritic inputs. For the spread factor SF=2, the input is preferably the first period from the register location. C〇, Cl, the second period is from C2, C3, so the last eighth period is ci4, C15. The converter 1〇1 of Fig. 2A and 2B generates an enable signal E' corresponding to the spread spectrum factor SF, according to which the control comes from The register of the register "and the input of the heart's adder element is enabled.囷5 shows a block diagram of the system transfer coefficient matrix AH of size HxW, where H=16 is the preferred maximum possible vector number D according to the communication system. In order to fill the sixteen columns of the matrix, the re-channel ring should be executed sequentially. The six-period operation cycle, each operation cycle is controlled by the channel code to determine the value of a column of vectors on the AH matrix. For a series of N values where N = 57, each matrix column contains a value of W = 72, which will process the series until the last N value passes the last register location. N, W, and Η can vary depending on the particular communication system. Within 3GPP, the standard resource unit RU is defined by the spreading factor SF. The spread spectrum factor SF represents the number of codes per month of a particular RU, or the bit rate. Therefore, an RU having a spread spectrum factor of SF = 8 has a bit rate twice that of a RU having a spread spectrum factor of SF=16. Thus, as shown in columns 7 and 8 of Figure 5, a column of matrix AH is used for each RU with a spread factor of 16, so that only one channel response value is required to set the scratchpad and the sum! The processing cycle of ^ is a RU with a spreading factor equal to 8 requiring two processing cycles, thus occupying two columns of the matrix. For a spread factor equal to 4, the 4 columns of the RU occupancy matrix are used to respond through four channels. Similarly, a RU with a spread factor of 2 occupies 8 columns, and a RU with a spread factor of 1 equals all 16 columns. The system is designed to take 15 columns and the final operation of the RU will be performed with a spread factor equal to 16. Otherwise, the last column of the matrix fills up with zero, 15 1305982 (6) matrix columns. Similar to the next column, the system will use any other spreading factor that cannot be filled in ~ ground' for all other combinations, when the appropriate spread-spectrum factor is occupied, as shown in Figure 5, for the spread spectrum factor of 16 In this case, all columns of the array are filled with the calculated value of the convolution result coefficient. For all of its spreading factor expressions, the enable signal E controls the adder dendritic wheel, creating a continuous zero zone @ at one or both ends of the matrix column, and forcing the selected zero value during processing. For example, for the spread factor SF = 8, the last 8 values of the column are zero and only zero is included in the last 8 cycles of the first operation cycle because only the roundings accompanying the first 8 positions of the scratchpad are enabled. value. Similarly, since the adder dendritic input accompanying positions (3) to C7 is not enabled, and the second pass of the header 8 is repeated, the positions C8 to C15 have zero values, then the matrix (with the second processing result) The first 8 values of the inner column 2 are zero. Figure 6 illustrates the effect of enabling the signal £ on the adder element with the spread factor SF=1. During the first pass of the channel response, the adder-like input from position C1 to C15 is not enabled because of the control of enable signal E, so adder elements A5 and A19 will only process input a from position CO. During the pass period 'When only the register position C15 provides the enabled round-in adder, the input from the register position C1 provides a separate round-up to the adder tree, etc. until the sixteenth cycle. Although the invention has been described with reference to certain specific embodiments, these details are intended to be Those skilled in the art will appreciate that many modifications can be made in the structure and mode of operation without departing from the spirit and scope of the invention described herein. BRIEF DESCRIPTION OF THE DRAWINGS 16 1305982 (7) FIG. 1 shows a time slot structure including a mid-code of a multi-chip code, to which the present invention operates. Figure 2A shows a device for swirling the real part of the channel response. Figure 2B shows the means for swirling the imaginary part of the channel response. Figure 3 shows the means for summing the outputs of the apparatus of Figures 2A and 2B to produce real and imaginary outputs for constructing a system of transmission coefficient matrices. Figure 4 shows a comparison circuit for the adder dendritic inputs of Figures 2A and 2B. Figure 5 shows the size of the system transfer matrix composite link swap AH. Figure 6 shows the system transfer matrix composite link of the spread factor of 1 to swap the size of AH. 100 200 Α1Ά14 Rr CC CC0 to CC15 TC1 TC2 AC JAD Ri A15-A28
BD 圖式代表符號說明 電路圖 電路圖 元素 暫存器 通道碼 位元 二的互補裝置 二的互補裝置 輸出 輸出 暫存器 元素 輸出 17 (8)1305982 jBC 101 輸出 轉換器 18BD schema representation symbol description circuit diagram circuit diagram element register register channel code bit 2 complementary device 2 complementary device output output register element output 17 (8)1305982 jBC 101 output converter 18