TWI305031B

TWI305031B - Complementary metal-oxide-semiconductor device and fabricating method thereof

Info

Publication number: TWI305031B
Application number: TW95134172A
Authority: TW
Inventors: Che Hung Liu; Po Lun Cheng; Chun An Lin; Li Yuen Tang; Hung Lin Shih; Ming Chi Fan; Hsien Liang Meng; Jih Shun Chiang
Original assignee: United Microelectronics Corp
Priority date: 2006-09-15
Filing date: 2006-09-15
Publication date: 2009-01-01
Also published as: TW200814233A

Description

^ w ^ ^»100-2005-0692 19042twf.doc/n 九、發明說明：【發明所屬之技術領域】本發明是有關於一種半導體元件及其形成方法，且特別疋有關於一種互補式金氧半導體元件及其製造方法。【先前技術】目剷，業界提出一種以石夕錯(SiGe)技術來製作金氧半電晶體的源極/汲極(S/D)區之方法，以增加電子和電洞的鲁遷移率(mobility) ’進而提高元件的效能。一般而δ，應用矽鍺(SiGe)技術來製作互補式金氧半^ w ^ ^»100-2005-0692 19042twf.doc/n IX. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device and a method of forming the same, and in particular to a complementary gold oxide Semiconductor component and method of manufacturing the same. [Prior Art] In the shovel, the industry proposed a method for fabricating the source/drain (S/D) region of a MOS transistor using SiGe technology to increase the electron mobility and hole mobility. (mobility) 'In turn, improve the performance of components. In general, δ, using 矽锗 (SiGe) technology to make complementary MOS

導體元件之方法是，先於基底上形成p型閘極結構以及N 型閘極結構，然後依序形成間隙壁與LDD。接著，於整個基底上覆蓋一層咼溫氧化層（HTO layer)。然後，以圖案化光阻層當做罩幕，移除PM〇s區域上方的部分高溫氧化層，而曝硌出PMOS區域中預形成源極/汲極區的基底表而於P型閘極結構及其側壁之間隙壁上保留有部分高溫氧化層，以達到保護閘極結構與間隙壁的功能。接著， • 移除此圖案化光阻層。之後，移除所裸露出的基底，以形成一溝渠。隨後，於溝渠中填入矽化鍺層，作為pM〇s的源極/汲極區。然而，在移除圖案化光阻層的步驟中、在形成1>]^〇8 區域之溝渠的步驟中，以及在接下來預進行的預清洗 (pre-clean)製程或預烘烤(pre_bake)製程的步驟中，會使得覆盍於P型閘極結構上之部分向溫氧化層被移除，甚至會移除掉NMOS區域之部分高溫氧化層，而曝露出p型間極 19042twf.doc/n I305(UL〇O5-O692 結構表面及NMOS區域之部分基底表面。因此，進行矽鍺製程，以於溝渠中填入矽化鍺層時，同時也會在所曝露出的基底表面與P型閘極結構頂部產生矽化鍺層，亦即是所謂的多晶矽凸塊(poly bump) ’其會嚴重影響製程的可靠度以及元件效能。此外，在一些美國專利上也有揭露關於上述提及之相關技術’例如US 6573172B1以及US 6858506B2。以上文獻皆為本案之參考資料。【發明内容】有鑑於此’本發明的目的就是在提供一種互補式金氧半導體元件的製造方法，能夠避免習知之多晶矽凸塊的產. 生，及其衍生的種種問題問題，且可提高製程的可靠度以及元件效能。本發明的另一目的是提供一種互補式金氧半導體元件的製造方法，同樣能夠避免習知之多晶石夕凸塊的產生，及其衍生的種種問題問題，且可提高製程的可靠度以及元件效能。本發明的又一目的是提供一種互補式金氧半導體元件同樣能夠避免習知之多晶碎凸塊的產生，及其衍生的種種問題問題’且可提高製程的可靠度以及元件效能。本發明的再一目的是提供一種互補式金氧半導體元件’同樣能夠避免習知之多晶矽凸塊的產生，及其衍生的種種問題問題，且可提高製程的可靠度以及元件效能。本發明提出一種互補式金氧半導體元件的製造方 nMCD-2005-0692 19042twf.doc/n 法。首先，提供一基底，此基底中具有一隔離結構，將基底區隔出第一主動區與第二主動區，且第一主動區已形成有一第一閘極結構、一第一間隙壁結構與一第一 LDD，第二主動區已形成有一第二閘極結構、一第二間隙壁結構與一第二LDD。然後，於基底上順應性地形成保護層，其中保護層為一含碳之氧-氮化物層。隨後，於第二主動區之保護層上形成光阻層。之後，以光阻層為罩幕，進行一蝕刻製程，以於第一閘極結構以及第一間隙壁結構上保留下部分的保護層，接著移除光阻層。然後，以保護層為罩幕，移除第一主動區之裸露出的部分基底，以於基底中形成溝渠。之後，於溝渠中填入磊晶材料層，作為第—導電型源極/汲極區，接著移除保護層。繼之，於第二主動區之基底中开>成摻雜區，作為第二導電型源極/汲極區。，依照本發明的實施例所述之互補式金氧半導體元件的製造方法，上述之含碳之氧_氮化物層例如是一雙第三丁基胺基魏(BTBAS)氧化層。雙第三丁基胺基魏氧化層的形成方法例如是一低壓化學氣相沈積法(LPCVD)。，依照本發明的實施例所述之互補式金氧半導體元件的製造方法’其中在溝渠形成後，更包括進行一清洗製程。依照本發明的實施例所述之互補式金氧半導體元件的製造方法，其中在進行清洗製程之前以及保護層形成之後，更包括對保護層進行一熱處理製程。上述之熱處理製程的溫度例如是介於750〜800°C之間，時間例如是介於3〇心至10分鐘之間’壓力例如是介於5〜50 torr之間，而熱 Ι3〇5·· 2005-0692 19042twf.doc/n 處理製程所使用之氣體例如是選自氦氣(He)、氖氣(Ne)、氣氣(Ar)、氣氣(Kr)、氛氣(Xe)及I氣所組合之族群其中一。依照本發明的實施例所述之互補式金氡半導體元件的製造方法，於摻雜區形成之後還包括進一步，在第二主動區之基底上方形成一應力層，順應性地覆蓋第二閘極結構、第二間隙壁結構以及摻雜區。在一實施例中，第一導電型源極/汲極區為P型源極/汲極區，則磊晶材料層為矽化鍺層，上述之應力層為一拉伸應力層。在另一實施例中，第一導電型源極/汲極區為N型源極/汲極區，則磊晶材料層為碳化⑪層，上狀應力層為—壓縮應力層。、、本發明另提出一種互補式金氧半導體元件的製造方 f首先’提供-基底’此基底中具有一隔離結構，將基 $ 第-主動區與第二主動區，且第—主動區已形成一閘極結構、一第一間隙壁結構與一第一 LDD，第一=動區已形成有—第二閘極結構、—第二間隙壁結構與声二D。隨後：於基底上順應性地形成-第-保護方層為—含碳之氧氮化物層。然後，於基 : 光阻層，覆蓋第二主動區之第-保護 tin阻層為罩幕，進彳卜__，_ 護層，接===上:留下部分的第-保 γϊ:主動區之裸露出的部分基底'以二= 成幕」第一溝渠。繼之，於第一溝一土纸⑽成作為-第-導電型源極/汲極區，^晶材料層，匕接耆，移除第一保護層。 8 1-2005-0692 19042twf.doc/n 之後’於基底上順應性地形成一第二保護層，其中第二保護層為含碳之氧-氮化物層。繼之，於基底上方形成一第二光阻層’覆蓋第一主動區之第二保護層。之後，以第二光阻層為罩幕’進行一蝕刻製程，以於第二閘極結構以及第二間隙壁結構上保留下部分的第二保護層，接著移除第二光阻層。然後’以第二保護層為罩幕，移除第二主動區之裸露出的部分基底，以於基底中形成一第二溝渠。隨後，於第一溝渠中填入一第二磊晶材料層，作為一第二導電型 ® 源極/汲極區。依照本發明的實施例所述之互補式金氧半導體元件的製造方法，上述之含碳之氧-氮化物層包括一雙第三丁基胺基矽烷氧化層。雙第三丁基胺基矽烷氧化層的形成方法例如是一低壓化學氣相沈積法。依照本發明的實施例所述之互補式金氧半導體元件的製造方法，其中在第一溝渠形成之後及/或第二溝渠形成之後，更包括進行一清洗製程。鲁依如本發明的實施例所述之互補式金氧半導體元件的製造方法，其中在進行清洗製程之前以及第―、第二保護層形成之後，更包括對第一、第二保護層進行一熱處理製程。上述之熱處理製程的溢度例如是介於〜之間，時間例如是介於30秒至10分鐘之間，壓力例如是介於f〜50 t〇rr之間，而熱處理製程所使用之氣體例如是選自氦氣(He)、氖氣(Ne)、氬氣(Ar)、氪氣(Kr)、氙氣(Xe)及氮氣所組合之族群其中一。 1-2005-0692 19042twf.doc/n 依照本發明的實施例所述之互補式金氧半導體元件的製造方法，上述之第—導電型源極/汲極區為p型源極/ ，極區’第二導電型源極/波極區為N型源極/汲極區，則第-蟲晶材料層切化鍺層’第二|晶材料層為碳化石夕厚。依照本發明的實施例所述之互補式金氧半導體元件的製造方法，上述之第—導電型源極/汲極區為N型源極/ ;及極區4一^笔型源極/汲極區為P型源極/汲極區，則The conductor element is formed by forming a p-type gate structure and an N-type gate structure on the substrate, and then sequentially forming the spacers and the LDD. Next, the entire substrate is covered with a layer of HTO layer. Then, the patterned photoresist layer is used as a mask to remove a portion of the high temperature oxide layer above the PM〇s region, and the base surface of the source/drain region pre-formed in the PMOS region is exposed to the P-type gate structure. A portion of the high temperature oxide layer remains on the spacers of the sidewalls thereof to protect the gate structure and the spacer. Next, • Remove the patterned photoresist layer. Thereafter, the exposed substrate is removed to form a trench. Subsequently, a bismuth telluride layer is filled in the trench as a source/drain region of pM〇s. However, in the step of removing the patterned photoresist layer, in the step of forming the trench of the region of 1>, and in the next pre-clean process or pre-baking (pre_bake) In the process step, the portion covered on the P-type gate structure is removed to the temperature oxide layer, and even a part of the high-temperature oxide layer of the NMOS region is removed, and the p-type inter-electrode is exposed to 19402 twf.doc /n I305 (UL〇O5-O692 part of the surface of the structure and the surface of the NMOS area. Therefore, the tantalum process is performed to fill the surface of the substrate and the P-type when the trench is filled with the tantalum layer. A bismuth telluride layer is formed on the top of the gate structure, which is a so-called poly bump. It can seriously affect the reliability of the process and the component performance. In addition, some related technologies mentioned above are also disclosed in some US patents. For example, US Pat. No. 6,573,172 B1 and US Pat. No. 6,858,506, B2. The above references are hereby incorporated by reference. It is possible to improve the reliability of the process and the performance of the device, and to improve the reliability of the process and the efficiency of the device. Another object of the present invention is to provide a method for fabricating a complementary MOS device. It is possible to avoid the occurrence of the conventional polycrystalline litter bumps and the problems of their derivatives, and to improve the reliability of the process and the performance of the components. It is still another object of the present invention to provide a complementary MOS device which can also be avoided. The production of conventional polycrystalline bumps, and the problems associated with them, can improve the reliability of the process and the performance of the device. A further object of the present invention is to provide a complementary MOS device that can also avoid the conventional The production of polycrystalline germanium bumps, and various problems arising therefrom, and the reliability of the process and the efficiency of the device can be improved. The invention provides a method for fabricating a complementary metal oxide semiconductor device, nMCD-2005-0692 19042 twf.doc/n. First, a substrate is provided, the substrate having an isolation structure separating the substrate from the first active region and the second An active region, and the first active region has been formed with a first gate structure, a first spacer structure and a first LDD, and the second active region has formed a second gate structure, a second spacer structure and a a second LDD. Then, a protective layer is formed conformally on the substrate, wherein the protective layer is a carbon-containing oxygen-nitride layer. Subsequently, a photoresist layer is formed on the protective layer of the second active region. The resist layer is a mask, and an etching process is performed to leave a lower protective layer on the first gate structure and the first spacer structure, and then the photoresist layer is removed. Then, the protective layer is used as a mask to remove A portion of the exposed portion of the first active region forms a trench in the substrate. Thereafter, a layer of epitaxial material is filled in the trench as a first-conductivity type source/drain region, and then the protective layer is removed. Then, a doped region is formed in the substrate of the second active region as a second conductivity type source/drain region. According to a method of fabricating a complementary MOS device according to an embodiment of the present invention, the carbon-containing oxygen-nitride layer is, for example, a double TBT-based oxide layer. The formation method of the bis-tert-butylamino-based Wei oxide layer is, for example, a low pressure chemical vapor deposition (LPCVD). A method of fabricating a complementary MOS device according to an embodiment of the present invention, wherein after the trench is formed, a cleaning process is further included. A method of fabricating a complementary MOS device according to an embodiment of the present invention, further comprising performing a heat treatment process on the protective layer before performing the cleaning process and after forming the protective layer. The temperature of the above heat treatment process is, for example, between 750 and 800 ° C, and the time is, for example, between 3 and 10 minutes. The pressure is, for example, between 5 and 50 torr, and the heat is 3〇5· · 2005-0692 19042twf.doc/n The gas used in the process is, for example, selected from the group consisting of helium (He), helium (Ne), gas (Ar), gas (Kr), atmosphere (Xe) and I. One of the ethnic groups combined with gas. The method for fabricating a complementary metal-germanium semiconductor device according to the embodiment of the present invention further includes forming a stress layer over the substrate of the second active region after the formation of the doped region, and conformingly covering the second gate Structure, second spacer structure, and doped region. In one embodiment, the first conductive source/drain region is a P-type source/drain region, and the epitaxial material layer is a germanium germanium layer, and the stress layer is a tensile stress layer. In another embodiment, the first conductivity type source/drain region is an N-type source/drain region, and the epitaxial material layer is carbonized 11 layers, and the upper stress layer is a compressive stress layer. Further, the present invention further provides a fabrication method of a complementary MOS device. First, a 'provide-substrate' has an isolation structure in the substrate, and a base-first active region and a second active region, and the first active region has Forming a gate structure, a first spacer structure and a first LDD, the first = active region has been formed with a second gate structure, a second spacer structure and an acoustic second D. Subsequently: a -protective square layer is formed on the substrate to be a carbon-containing oxynitride layer. Then, in the base: photoresist layer, covering the second active region, the first-protective tin resist layer is a mask, and the __, _ protective layer is connected, and === is left: the part of the first-protected γ ϊ: Part of the exposed base of the active area is 'two = curtains' first ditch. Then, in the first trench, a soil paper (10) is formed as a -first-conducting source/drain region, and a layer of germanium material is bonded to the first protective layer. 8 1-2005-0692 19042twf.doc/n Thereafter, a second protective layer is formed conformally on the substrate, wherein the second protective layer is a carbon-containing oxygen-nitride layer. Then, a second photoresist layer is formed over the substrate to cover the second protective layer of the first active region. Thereafter, an etching process is performed using the second photoresist layer as a mask to retain the lower portion of the second protective layer on the second gate structure and the second spacer structure, and then the second photoresist layer is removed. Then, the second protective layer is used as a mask to remove a portion of the exposed substrate of the second active region to form a second trench in the substrate. Subsequently, a second layer of epitaxial material is filled in the first trench as a second conductivity type source/drain region. According to a method of fabricating a complementary MOS device according to an embodiment of the present invention, the carbon-containing oxygen-nitride layer comprises a double-tert-butylaminodecane oxide layer. The method for forming the bis-tert-butylaminodecane oxide layer is, for example, a low pressure chemical vapor deposition method. A method of fabricating a complementary MOS device according to an embodiment of the invention, wherein after the first trench is formed and/or after the second trench is formed, a cleaning process is further included. The method for manufacturing a complementary MOS device according to the embodiment of the present invention, wherein before the cleaning process and after the forming of the first and second protective layers, the first and second protective layers are further included. Heat treatment process. The above-mentioned heat treatment process has an overflow of, for example, between 〜, for example, between 30 seconds and 10 minutes, and the pressure is, for example, between f and 50 t rr, and the gas used in the heat treatment process is, for example, It is one of a group selected from the group consisting of helium (He), helium (Ne), argon (Ar), helium (Kr), xenon (Xe) and nitrogen. 1-2005-0692 19042 twf.doc/n According to a method of fabricating a complementary MOS device according to an embodiment of the present invention, the first conductivity type source/drain region is a p-type source/polar region The second conductivity type source/wave region is an N-type source/drain region, and the first-crystal material layer is diced and the second material layer is carbonized. According to the manufacturing method of the complementary MOS device according to the embodiment of the present invention, the first-conducting source/drain region is an N-type source/; and the polar region 4-pen type source/汲The polar region is a P-type source/drain region, then

第一蟲晶材料層為碳化料H晶材料層為魏鍺層。依照本發明的實施例所述之互補式金氧半導體元曰的ΐ造方?，上述之第—偏移間隙壁與該第二偏移間隙壁皆是由-氧化層以及―氮化層所構成，其氧化層的材質ς 如是-高溫氧化材料或—含碳之氧遗化物材料。在一實 :]中’第-偏移間隙壁與第二偏移間隙壁的形成方法例：是一臨場沈積製程。依照本發明的實施例所述之互補式金The first smectic material layer is a carbonized material H crystal material layer is a Wei 锗 layer. According to the embodiment of the present invention, the complementary MOS transistor is fabricated, and the first offset spacer and the second offset spacer are both an oxide layer and a nitride layer. The material of the oxide layer is, for example, a high temperature oxidation material or a carbonaceous oxygen residue material. An example of the formation of the first-offset spacer and the second offset spacer in a real:] is a on-site deposition process. Complementary gold according to an embodiment of the invention

的製造方法，上述之第—間隙壁與第二間隙壁皆是由1 二氣化層、-氮化層以及―第二氧化層所構成，其第一、 ί二氧化層的材質例如是-高溫氧化材料或-含碳之氧_ 沾化，材料。在—實施例中，第—間隙壁與該第二間隙壁的形成方法例如是—臨場沈積製程。本^又提出—種互補式金氧半導體元件，其包括： ί—閘極結構、第二閘極結構、第―_壁結構、 LDD、第二n日日材料層以曰，、中，基底具有一第一主動區與一第二主動區，：D-2005-0692 19042twf.doc/n 且第一主動區與第二主動區之間以一隔離結構區隔。第一閘極結構配置於第一主動區之基底上，第二閘極結構配置於第二主動區之基底上，第一間隙壁結構配置於第一閘極結構之側壁，第二間隙壁結構配置於第二閘極結構之側壁。另外，第一 LDD配置於第一閘極結構側邊之基底中，第二LDD配置於第二閘極結構側邊之基底中。磊晶材料層配置於第一主動區之基底中，且位於第一 LDD侧邊，以作為一第一導電型源極/汲極區。保護層配置於第一閘極結構、第一間隙壁結構以及第一 LDD上，且覆蓋住第二主動區，其中保護層為一含碳之氧-氮化物層。依照本發明的實施例所述之互補式金氧半導體元件’上述之弟一導電型源極/波極區為P型源極Λ及極區’ 則遙晶材料層為吩化錯層。依照本發明的實施例所述之互補式金氧半導體元件，上述之第一導電型源極/汲極區為Ν型源極/汲極區，則蟲晶材料層為碳化碎層。依照本發明的實施例所述之互補式金氧半導體元件，上述之含碳之氧-氮化物層例如是一雙第三丁基胺基矽烷氧化層。本發明再提出一種互補式金氧半導體元件，其包括：基底、第一閘極結構、第二閘極結構、第一間隙壁結構、第二間隙壁結構、第一 LDD、第二LDD、第一磊晶材料層、第二磊晶材料層以及保護層。其中，基底具有一第一主動區與一第二主動區，且第一主動區與第二主動區之間 11 1305021 CD-2005-0692 19042twf.doc/n 1305021 CD-2005-0692 19042twf.doc/n 以从-隔離結構區隔。第一閘極結構配置於第一主動區之令基底上’第一閘極結構配置於第二主動區之該基底:，第一間隙壁結構配置於第一閘極結構之側壁，第二間隙壁結構配置於第二閘極結構之侧壁。另外，第一 LDD配置於第-閘極結構側邊之基底中，第二咖配置於第二間極結構側邊之基底中。第一磊晶材料層配置於第一主動區之基底中，且位於第一 LDD側邊，以作為一第一導電；源極/汲極區。第二蟲晶材料層配置於第二 '、In the manufacturing method, the first gap and the second spacer are composed of a gasification layer, a nitride layer and a second oxide layer, and the material of the first and second oxide layers is, for example, High temperature oxidizing material or - carbon containing oxygen _ smear, material. In an embodiment, the method of forming the first spacer and the second spacer is, for example, a field deposition process. A complementary MOS device is further provided, which comprises: ί—gate structure, second gate structure, __wall structure, LDD, second n-day material layer, 、, medium, base There is a first active area and a second active area, D-2005-0692 19042 twf.doc/n and the first active area and the second active area are separated by an isolation structure. The first gate structure is disposed on the substrate of the first active region, the second gate structure is disposed on the substrate of the second active region, the first spacer structure is disposed on the sidewall of the first gate structure, and the second spacer structure The sidewall is disposed on the sidewall of the second gate structure. In addition, the first LDD is disposed in the substrate on the side of the first gate structure, and the second LDD is disposed in the substrate on the side of the second gate structure. The epitaxial material layer is disposed in the substrate of the first active region and is located on the side of the first LDD to serve as a first conductivity type source/drain region. The protective layer is disposed on the first gate structure, the first spacer structure and the first LDD, and covers the second active region, wherein the protective layer is a carbon-containing oxygen-nitride layer. The complementary MOS device according to the embodiment of the present invention has a P-type source and a drain region, and the layer of the crystal material is a pheno-staggered layer. According to the complementary MOS device of the embodiment of the invention, the first conductivity type source/drain region is a Ν source/drain region, and the worm material layer is a carbonized layer. According to the complementary MOS device according to the embodiment of the present invention, the carbon-containing oxygen-nitride layer is, for example, a double-tert-butylaminodecane oxide layer. The present invention further provides a complementary MOS device, comprising: a substrate, a first gate structure, a second gate structure, a first spacer structure, a second spacer structure, a first LDD, a second LDD, and a first An epitaxial material layer, a second epitaxial material layer, and a protective layer. The substrate has a first active region and a second active region, and between the first active region and the second active region 11 1305021 CD-2005-0692 19042twf.doc/n 1305021 CD-2005-0692 19042twf.doc/ n is separated by a slave-isolation structure. The first gate structure is disposed on the substrate of the first active region. The first gate structure is disposed on the substrate of the second active region: the first spacer structure is disposed on the sidewall of the first gate structure, and the second gap is The wall structure is disposed on a sidewall of the second gate structure. In addition, the first LDD is disposed in the substrate on the side of the first gate structure, and the second coffee is disposed in the substrate on the side of the second interlayer structure. The first epitaxial material layer is disposed in the substrate of the first active region and located on the side of the first LDD to serve as a first conductive source/drain region. The second smectic material layer is disposed in the second ',

且位於第二LDD側邊，以作為一第一土泜TAnd located on the side of the second LDD to serve as a first soil T

區=護層配置於第二閘極結構、第二‘結US 倾層為一含碳件，朗狀互㈣錢半導體元第一^第—型源極/汲極區為P型源極/汲極區，材;1==為N型賴及極區,則第；晶 Π ’第二磊晶材料層為碳化矽層。件，上^所叙互補式金氧半導體元第二導電型源榀二原汲極區為N型源極/汲極區，晶材料層為碳化矽層，；為?型源極/汲極區’則第-屋依照本發明：實;=曰曰材料層為矽化鍺層。例如是—雙第爲:：述’上述之含碳之氧-氮化物層叉罘—丁基胺基矽烷氧化層。刻率’ ，保護層為一含碳之氧-氮化物層，复且右低飩因此在元件的製造過程中可避免保護4= 12 I30501L 005-0692 19042twf.doc/n 移除掉，而導致習知之多晶矽凸塊(poly bump)的產生，及其衍生的種種問題。另一方面，本發明之方法中所進行的熱處理製程，能夠使得保護層的密度更為敏密化，以降低保護層的蝕刻率，而更加有利於後續製程的進行。為讓本發明之上述和其他目的、特徵和優點能更明顯易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。【實施方式】圖1A至圖1H為依照本發明一實施例所繪示之互補式金氧半導體元件的製造方法之剖面示意圖。百先，請參照圖1A ,提供一基底100，基底1〇〇具有第一，動區102以及第二主動區1〇4，且第一主動區1〇2 以及第二主動區1〇4之間以隔離結構區隔。上述，隔離結構舰例如是淺溝渠隔離結構(STI)或其他合適之隔離結構。接著，第—絲區102以及第二主動區104之基底削上已分別形成有第—閘極結構1G8以及-第二閘極結 t二L中所I閘極結構⑽是由閘介電層1〇8a與閘與問導體層膽叫上述，第一問極結構二；：閘極結構110各構件的好哲命r^ 一禾一中具有通常知識者所周知述'領域參照圖1A’於第一閘極結構108以及 —偏移間隙壁114。其中，第一偏移間隙 13 19042twf. doc/nZone = sheath is disposed in the second gate structure, the second junction US tilt layer is a carbon-containing component, and the first-shaped source/drain region is the P-type source/ The bungee region, the material; 1 == is the N-type and the polar region, then the first; the crystalline germanium 'the second epitaxial material layer is the tantalum carbide layer. The second conductivity type source of the complementary MOS semiconductor element is an N-type source/drain region, and the crystalline material layer is a ruthenium carbide layer; The zone 'the first house' according to the invention: the real; = 曰曰 material layer is the bismuth telluride layer. For example, the double is: the above-mentioned carbon-containing oxygen-nitride layer fork-butylamine-based decane oxide layer. The engraving rate ', the protective layer is a carbon-containing oxygen-nitride layer, and the lower right 饨 is thus prevented from being protected during the manufacturing process of the component. 4= 12 I30501L 005-0692 19042twf.doc/n is removed, resulting in The production of poly-bumps and their various problems. On the other hand, the heat treatment process carried out in the method of the present invention can make the density of the protective layer more dense, thereby reducing the etching rate of the protective layer, and is more advantageous for the subsequent process. The above and other objects, features and advantages of the present invention will become more <RTIgt; 1A to 1H are schematic cross-sectional views showing a method of fabricating a complementary MOS device according to an embodiment of the invention. Referring to FIG. 1A, a substrate 100 is provided. The substrate 1 has a first moving region 102 and a second active region 1〇4, and the first active region 1〇2 and the second active region 1〇4 Separated by isolation structure. In the above, the isolation structure ship is, for example, a shallow trench isolation structure (STI) or other suitable isolation structure. Then, the base of the first wire region 102 and the second active region 104 are respectively formed with the first gate structure 1G8 and the second gate junction t2 L. The gate structure (10) is formed by the gate dielectric layer. 1〇8a and the gate and the conductor layer are called the above, the first question pole structure 2;: the gate structure 110 each member of the good philosophies r ^ one Wo one in the general knowledge is well known 'domain reference Figure 1A' The first gate structure 108 and the offset spacer 114 are provided. Wherein, the first offset gap 13 19042twf. doc/n

I305〇3^D-20〇5_〇692 壁丄12是由一氧化層⑽以及一氮化層112b所構成，第 =^間隙壁m是由-氧化層_以及—氮化層⑽ 冓成。鼠化層mb、mb的材質例如是氮化石夕，氧化層 a、114a的材質例如是高溫氧化材料。隨後，進行一摻 =程，以分別於第-閘極結構⑽以及第二閘極結構ιι〇側邊之^底1〇〇中形成第—LDD116以及第二lddu8。接著，請參照圖1B，於第一偏移間隙壁ιΐ2以及第二偏移間隙壁114之側壁分別形成第一間隙壁i 2〇以及第 =間隙壁122。其中，第—間隙壁⑽是由氧化層12加、氮化層120b以及氧化層丨施所構成，第二間隙壁i22是由氧化層122a、氮化層122b以及氧化層U2e所構成。氮化層騰’“勺材質例如是氮化矽’氧化層咖、·、 122a、122c的材質例如是高溫氧化材料。然後，請參照圖1C，於基底1〇〇上方形成保護層124, 順應性地覆蓋住第一閘極結構108、第一偏移間隙壁丨12、第一間隙壁120、第一 LDD116、第二閘極結構11〇、第二偏移間隙壁114、第二間隙壁122、第二LDD118以及隔離結構106。接著’於基底1〇〇上方形成一光阻層126，覆蓋第二主動區104之保護層124。其中’本發明的特徵是保護層124為含碳之氧_氮化物 (carbon-containing oxidenitride)層，其具有低蝕刻率。含破之氧-氮化物層可例如是雙第三丁基胺基破炫 (bis(tert-butylamino)silane)，BTBAS)氧化層，其是指以 BTBAS 為基礎之氧化層（BTBAS-based oxide)。BTBAS 氧 14 1305m '2005-0692 19042twf.doc/n 化層的形成方法例如是，進行一低壓化學氣相沈積製程 (LPCVD)，溫度約為5〇〜350 torr左右，溫度約為5〇〇〜75〇 °C左右’而通入之氣體包括BTBAS以及一氧化二氮 (N20)(或一氧化1(Ν0))。BTBAS係做為含碳之氧-氣化物層的矽與碳之氣體來源，而沁0(或N0)係做為含碳之氧_ 氮化物層的氮之氣體來源。在一實施例中，BTBAS與化0(或NO)的流量關係為BTBAS/N2〇(或NO)大於1/2。繼之，請參照圖1D，以光阻層126為罩幕，進行一非等向性蝕刻製程，以於第一閘極結構1〇8、第一偏移間隙壁112以及第一間隙壁12〇上保留下部分的保護層 124。之後’移除光阻層丨26。 θ 值得特別說明的是，本發明之保護層124為一含碳之氧-氮化物層，其具有低蝕刻率(l〇w etching rate)。因此，在移除光阻層126的步驟時，並不會移除掉第二主動區之部分保護層124,所以不會因曝露出部分基底表面，而導致衍生出種種問題。 # 在另一實施例中，第一、第二偏移間隙壁112、114 之氧化層112a、114a的材質亦可例如是與保護層的材質相同，其形成方法可例如是與保護層124的形成條件相同。第一、第二偏移間隙壁112、114的形成方法可例如是一臨場(in-situ)沈積製程。在又一實施例中’第一、第二間隙壁12〇、122之氧化層120a、120c' 122a、122c的材質亦可例如是與保護層 124的材質相同，其形成方法可例如是與保護層124的形 15 1305m -2005-0692 19042twf.doc/n 成條件相同。第-、第二間隙壁12G、122的形成方法如是一臨場沈積製程。之後，請參照圖1E，以保護層124為罩幕，移除第— 主動區102之裸露出的部分基底1〇〇，以於基底_令带 f-溝渠128。溝渠128的形成方法例如是進行—飯刻製程。同樣地，由於本發明之保護層124為一含碳之氧-氮^ 物層’其具有健刻率，此在雜部分基底⑽以 f渠128的步驟時’亦不會對保護層124造成影響。亦即疋’在軸溝渠128的步驟巾，並不會歸掉酿結構⑽ 頂部之部分保護層124，而曝露出閘極結構應的部面。 ^ 接耆’請參照圖1F，於溝渠128中填入遙晶材料居 130 ’作為第-導電型源桎/沒極區。在一實施例巾，於ς 入蟲晶材料層13G之前，通常會進行-清洗(ρ—)製程以，月潔溝渠128底部之基底1〇〇表面。同樣地，由於本發】之保€層124為-含碳之氧_氮化物層，其具有低钱刻率，因此在進行清洗製程的步驟時，亦不會對第一主動區收之保護層m造成影響。也就是說，並不會移除掉第 —主動區102之部分保護層124,而曝露出閘極結構1〇8 的部分表面。 _另外，在磊晶材料層130的形成步驟中，還包括會進行—預烘烤(pre-bake)步驟，以清除形成溝渠128後^ 的雜質。在上述實施例中’若第一導電型源極/汲極區為p型源 16 1305¾¾ CD-2005-0692 19042twf.doc/n 極/汲極區’則磊晶材料層130為矽化鍺(SiGe)層，其形成方法例如是選擇性遙晶成長(selective epitaxial growth， SEG)製程。更詳細而言，磊晶材料層13〇是含硼的矽化鍺 (SiGe)層，其可以是以臨場方式進行摻雜製程而形成，或是先形成石夕錯材料層後，再進行摻雜製程而形成。另一方面，若第一導電型源極/沒極區為N型源極/；；及極區’則磊晶材料層130為碳化矽(SiC)層。I305〇3^D-20〇5_〇692 The wall 12 is composed of an oxide layer (10) and a nitride layer 112b, and the first spacer m is composed of an oxide layer and a nitride layer (10). . The material of the mouse layers mb and mb is, for example, nitride nitride, and the material of the oxide layers a and 114a is, for example, a high-temperature oxidizing material. Subsequently, a doping process is performed to form the first-LDD 116 and the second lddu8 in the first gate of the first gate structure (10) and the second gate structure ιι. Next, referring to FIG. 1B, first spacers i 2 and first spacers 122 are formed on the sidewalls of the first offset spacers ι2 and the second offset spacers 114, respectively. The first spacer (10) is composed of an oxide layer 12, a nitride layer 120b, and an oxide layer. The second spacer i22 is composed of an oxide layer 122a, a nitride layer 122b, and an oxide layer U2e. The material of the nitride layer is, for example, a material of tantalum nitride oxide layer, 122a, 122c, for example, a high temperature oxidizing material. Then, referring to FIG. 1C, a protective layer 124 is formed over the substrate 1 ,. The first gate structure 108, the first offset gap wall 12, the first spacer 120, the first LDD 116, the second gate structure 11〇, the second offset spacer 114, and the second spacer are covered. 122. The second LDD 118 and the isolation structure 106. Then, a photoresist layer 126 is formed over the substrate 1 to cover the protective layer 124 of the second active region 104. The feature of the present invention is that the protective layer 124 is carbon-containing. a carbon-containing oxide nitride layer having a low etching rate. The broken oxygen-nitride layer may be, for example, bis (tert-butylamino) silane (BTBAS). An oxide layer, which is a BTBAS-based oxide layer. The formation method of the BTBAS oxygen 14 1305m '2005-0692 19042 twf.doc/n layer is, for example, a low pressure chemical vapor deposition process ( LPCVD), the temperature is about 5〇~350 torr, and the temperature is about 5 〇~75〇 °C' and the gas introduced includes BTBAS and nitrous oxide (N20) (or oxidized 1 (Ν0)). BTBAS is used as the carbon-containing oxygen-vapor layer of bismuth and carbon. The gas source, and 沁0 (or N0) is the gas source of nitrogen for the carbon-containing oxygen-nitride layer. In one embodiment, the flow relationship between BTBAS and 0 (or NO) is BTBAS/N2〇 ( Or NO) is greater than 1/2. Then, referring to FIG. 1D, using the photoresist layer 126 as a mask, an anisotropic etching process is performed to the first gate structure 1〇8 and the first offset gap. The lower portion of the protective layer 124 remains on the wall 112 and the first spacer 12. The photoresist layer 26 is then removed. θ It is particularly noted that the protective layer 124 of the present invention is a carbon-containing oxygen-nitride. a layer having a low etching rate. Therefore, in the step of removing the photoresist layer 126, part of the protective layer 124 of the second active region is not removed, so that it is not exposed Part of the surface of the substrate causes various problems to be derived. # In another embodiment, the materials of the oxide layers 112a, 114a of the first and second offset spacers 112, 114 may also be If it is the same as the material of the protective layer, the forming method thereof may be, for example, the same as the forming condition of the protective layer 124. The forming method of the first and second offset spacers 112, 114 may be, for example, an in-situ deposition process. In another embodiment, the material of the oxide layers 120a, 120c' 122a, 122c of the first and second spacers 12, 122 may be the same as the material of the protective layer 124, for example, The shape of the protective layer 124 is the same as the condition 15 1305m -2005-0692 19042twf.doc/n. The method of forming the first and second spacers 12G, 122 is a on-site deposition process. Thereafter, referring to FIG. 1E, the protective layer 124 is used as a mask to remove the exposed portion of the substrate 1 of the first active region 102, so as to be the substrate-and-band f-ditch 128. The method of forming the trench 128 is, for example, a cooking process. Similarly, since the protective layer 124 of the present invention is a carbon-containing oxygen-nitrogen layer, which has a robustness, this does not cause the protective layer 124 when the heterogeneous substrate (10) is in the step of the d-channel 128. influences. That is, the step towel in the shaft trench 128 does not return part of the protective layer 124 at the top of the brewing structure (10), but exposes the portion of the gate structure. ^ 接耆 Please refer to FIG. 1F. The trench 128 is filled with a remote crystal material 130 ′ as a first-conductivity source/no-polar region. In an embodiment of the towel, prior to the insertion of the layer 13G of the insecticidal material, a cleaning (p-) process is generally performed to expose the surface of the substrate at the bottom of the trench 128. Similarly, since the layer 124 of the present invention is a carbon-containing oxygen-nitride layer, which has a low cost, it does not protect the first active region during the cleaning process. Layer m has an effect. That is to say, part of the protective layer 124 of the first active region 102 is not removed, and a part of the surface of the gate structure 1〇8 is exposed. In addition, in the forming step of the epitaxial material layer 130, a pre-bake step is also performed to remove impurities which form the trench 128. In the above embodiment, 'if the first conductivity type source/drain region is a p-type source 16 13053⁄43⁄4 CD-2005-0692 19042 twf.doc/n pole/drain region', the epitaxial material layer 130 is bismuth telluride (SiGe) The layer is formed by, for example, a selective epitaxial growth (SEG) process. In more detail, the epitaxial material layer 13 is a boron-containing germanium telluride (SiGe) layer, which may be formed by a doping process in a field manner, or may be formed after the formation of a layer of stone-like material. The process is formed. On the other hand, if the first conductivity type source/potential region is an N-type source/; and a polar region', the epitaxial material layer 130 is a tantalum carbide (SiC) layer.

以下，說明本發明一實施例之互補式金氧半導體元件的結構。請再次參照圖1F ’本發明之元件包括：基底100、第一閘極結構108、第二閘極結構11()、第一偏移間隙壁 112、第二偏移間隙壁丨14、第一 LDDU6、第一間隙壁12〇、第二LDD118、第二間隙壁122、磊晶材料層13〇以及保護層124。其中，基底100具有一第一主動區1〇2Hereinafter, the structure of a complementary MOS device according to an embodiment of the present invention will be described. Referring again to FIG. 1F, the components of the present invention include: a substrate 100, a first gate structure 108, a second gate structure 11 (), a first offset spacer 112, a second offset gap wall 14, and a first The LDDU 6, the first spacer 12, the second LDD 118, the second spacer 122, the epitaxial material layer 13A, and the protective layer 124. Wherein, the substrate 100 has a first active area 1〇2

區104，且第一主動區1〇2與第二主動區1〇4之間以一隔離結構106區隔。第一閘極結構1〇8配置於第一主動區⑴2 之基底1〇〇上，第二閘極結構11〇配置於第二主動區1〇4 之基底1〇〇上。另外，第一偏移間隙壁112配置於第一閘極結構108之側壁，第二偏移間隙壁114配置於第二間極結構m之側壁。第-偏移間隙壁112是由—氧化層ii2a 以及-氮化層112b所構成，第二偏移間隙壁114是由化層ma以及一氮化層114b所構成。第一、第二偏移間隙壁112、114的氧化層112a、114a的材質例化材料或一含碳之氧-氮化物材料。 Γ"服乳 17 I30501L -2005-0692 19042twf.doc/n 第一 LDDl 16配置於第一閘極結構i〇8側邊之基底 100中。第一 LDD118配置於第二閘極結構11〇側邊之基底100中。另外，第一間隙壁120配置於第一偏移間隙壁 112之側壁，弟一間隙壁122配置於第二偏移間隙壁H4 之側壁’且位於部分第二LDD118上。其中，第—間隙壁 120是由一氧化層120a、一氮化層120b以及一氧化層12〇c 所構成’第一間隙壁122是由一氧化層122a、一氮化層122b 以及一氧化層122c所構成。第一、第二間隙壁12〇、122 的氧化層120a、120c、122a、122c的材質例如是高溫氧化材料或一含碳之氧-氮化物材料。磊晶材料層130配置於第一主動區1〇2之基底1〇〇中，且位於弟一 LDD116側邊，以作為第一導電型源極/ 汲極區。保護層12/!配置於第一閘極結構1〇8、第一偏移間隙壁122、第一間隙壁丨2〇以及第一 LDDU6上，且覆蓋住整個第一主動區1〇4。保護層124為含碳之氧_氮化物層，其例如是一雙第三丁基胺基矽烷氧化層。因為本發明之保護層為具有低敍刻率之含壤之氧氮化物層，因此在元件的製造過程中可避免保護層被不適當的移除，而導致習知之多晶矽凸塊(p〇lybump)的產生，^ 其衍生的種種問題。繼之，接續圖1F，在磊晶材料層130形成之後，還可繼續進行後續之製程。請參照圖1G，移除保護層124。之後，進行一#雜製程，於第二主動區1〇4之基底1〇〇中形成一摻雜區132 ’作為第二導電型源極/汲極區。 18 I3〇5〇3cl D-2005-0692 19042twf,doc/n 之後，請參照圖1H，於第二主動區1〇4形成應力層 134，順應性地覆盍第二閘極結構no、第二偏移間隙壁 114、第二間隙壁122以及摻雜區132。應力層134的材質例如是氮化矽或其他合適的應力材料，而其形成方法例如是化學氣相沈積法或其他適合的方法。在上述貫施例中’若第—導電型源極/汲極區為p型源極/汲極區，磊晶材料層13〇為矽化鍺(SiGe)層，則應力層 134為拉伸應力層。另—方面，若第—導電型源極/没極區為N型源極/沒極區’ i晶材料層13〇為碳化石夕⑸c)層，則應力層134為壓縮應力層。除此之外，本發明之方法還可在，形成保護層124的步驟之後’以及㈣渠⑶妨清洗製㈣㈣之前，進行-熱處理製程，以使得保護層124的密度更為敏密化，崎低保護層124的_率，而更加有利於後續製程的進。行上述之熱處理製程的條件例如&，溫度介於乃〇〜⑽〇 C之間，時間介於3〇秒至1〇分鐘之間，壓力介於5〜5〇 t⑽ S ^熱處理製程戶斤使用之氣體是選自氦氣_、氖氣其^魏(Αι·)、减(Κι·)、氣氣(Xe)及氮氣所組合之族群祕對保護層124進行-熱處理製程，可更加有驟Η呆摘124在光阻層的移除步驟、溝渠的形成步驟以及進行清洗製料步财被移除，而導致習知之多晶矽凸塊的產生，進而影響元件致能。在一較佳實施例中，以第―主"動區Η)2是Ρ型元件區 19 1305031 UMCD-2005-0692 19042twf.doc/n 及第-主動區104 S N型元件區為例，在第一主動區1〇2 保留下部分的保護層124及移除光阻層之後(如圖⑴所不）’進行上述之熱處理製程，除了可使保護層 124的密度 ^為缴魏’及降低保護層124的餘刻率之外，此熱處理製程還有利於應力轉換技術(伽ss t咖以a·)，且不會使元件性能退化。 f1 2A至圖2D依照本發明另一實施例所繪示之互補 φ ’金，半導體元件的製造方法之剖面示意圖。圖2A至圖 2,D疋接續圖1F後之流程剖面示意圖，在圖2A至圖2D中省略與圖1A至圖1F之相同構件的說明，且以相同標號表不。請參照圖2A，於移除保護層124之後，於基底1()〇上方形成保護層136,順應性地覆蓋住第一閘極結構應、第一偏移間隙壁112、第一間隙壁12〇、第一 LDDU6、第閘極、、’σ構11 〇、弟一偏移間隙壁114、第二間隙壁122、第了 LDD118、隔離結構1〇6以及蟲晶材料層13〇。其中， • 保護層136的材質及形成方法與保護層124的材質及形成方法相同。之後，於基底勘上方形成光阻層138，覆蓋第一主動區102之保護層136。 ’ ^然後，請參照圖2Β，以光阻層138為罩幕，進行一非等向性蝕刻製程，以於第二閘極結構11〇、第二偏移間隙壁114以及第二間隙壁122上保留下部分的保護層 136。之後’移除光阻層138。接著，請參照圖2C，以保護層136為罩幕，移除第 20 •2005-0692 19042twf.doc/n 一主動區104之裸i备出的部分基底100 ,以於基底100中形成一溝渠140。之後，請參照圖2D，於溝渠14〇中填入磊晶材料層 142，作為第一導電型源極/汲極區。在一實施例中，於填入此磊晶材料層142前，通常會進行一清洗製程以清潔溝渠140底部之基底1〇〇表面。另外，在磊晶材料層142的形成步驟中，還包括會進行—預烘烤(pre_bake)步驟，以清除形成溝渠140後所產生的雜質。上述實施例中，若第—導電型源極/汲極區為p型源極 /波極區’第二導電型源極/汲極區㈣型源極級極區，則蟲晶材料層130為魏錯層，蠢晶材料層142為碳化石夕層。相反地’右第-導電型源極/汲極區為N型源極級極區，型源極/汲極區為P型源極/汲極區，則磊晶材料層為石厌化石夕層，蟲晶材料層M2為石夕化鍺層。 η，是’入本發明之保護層136與保護層124材質相 3碳之氧_氮化物層，其具有低_率。因此， 128的于、ίΓ層Μ的步驟，移除部分基底100以形成溝渠清洗製底部之基底⑽表面進行 102之^ 步驟時’不會移除掉第一主動區 L影響製程可靠度以及树效能。之後。:、:發明之方法可在，形成保護層136的步驟熱處理^對= = = Τ製程的步驟之前，進行一低保護層Μ0的的密度更為緻密化，以降勺蝕划率，而更加有利於後續製程的進行。 I3〇5〇l 2005-0692 19042twf.doc/n 上述之熱處理製程的條件例如是，溫度介於75〇〜8〇〇〇c之間，時間介於30秒至10分鐘之間，壓力介於5〜5〇 t〇rr 之間，而熱處理製程所使狀氣體是選自氦氣㈣、氧氣 (Ne)、氬氣(Ar)、氪氣(Kr)、氙氣(Xe)及氮氣所組合之族群其中一。洋吕之，對保護層140進行一熱處理製程，可更加有助於避免保護層M0在光阻層的移除步驟、溝渠的形成步 «•驟以及進行清洗製程等步驟中被移除，而導致習知之多晶矽凸塊的產生，進而影響元件效能。在一較佳實施例中，以第—主動區1〇2是]^型元件區及第二主動區104是P型元件區為例，在第二主動區1〇4 保遠下σ卩分的保護層136及移除光阻層之後(如圖2B所示）’進行上述之熱處理製程，除了可使保護層124的密度更為緻密化，及降低保護層136的蝕刻率之外，此熱處理製程還有利於應力轉換技術，且不會使元件性能退化。一接下來，說明本發明另一實施例之互補式金氧半導體 • 元件的結構。請再次參照圖2D’本發明之元件包括：基底 100第閘極結構108、第二閘極結構11〇、第一偏移間隙壁112、第二偏移間隙壁114、第一 LDD116、第一間隙壁120、第二LDD118、第二間隙壁122、磊晶材料層13〇、磊晶材料層142以及保護層136。其中，磊晶材料層M2 配置於第二主動區1〇4之基底1〇〇中，且位於第：lddu8 側邊，以作為—第二導電型源極/汲極區。保護層136配置於第二閘極結構110、第二偏移間隙壁114、第二間隙壁 22 1305·— 19042twf.doc/n 122以及第二LDD118上，且覆蓋住整個第一主動區1〇2。其中，保護層136為一含碳之氧_氮化物層，其例如是一雙第三丁基胺基矽烷氧化層。综上所述，本發明之保護層為一含碳之氧_氮化物層，其具有低蝕刻率，因此在元件的製造過程中可避免保護層被不適當的移除掉，而導致習知之多晶矽凸塊(p〇ly bump) 的產生，及其衍生的種種問題。此外，本發明對保護層進 φ 仃二熱處理製程，可使保護層的密度更為緻密化，以降低保濩層的蝕刻率，而更加有利於後續製程的進行。雖然本發明已以較佳實施例揭露如上’然並並非用以任何熟習此技藝者，在不脫離本發明之精神一口粑圍内，當可作⑽之更動與卿，因此本發明之軏圍當視後附之ΐ請專利範圍所界定者為準。 ’、°又【圖式簡單說明】、圖1Α至圖1Η為依照本發明一實施例所繪式金氧半導體元件的製造方法之剖面示意圖。圖2Α至圖2D為依照本發明另一實施例所子式金氧半導體元件的製造方法之剖面示意圖。【主要元件符號說明】 :基底 102 :第一主動區 104 :第二主動區 106 :隔離結構 108:第一閘極結構 23 13050认 D-2005-0692 19042twf.doc/n 108a ' 110a :閘介電層 108b、110b :閘導體層 110 :第二閘極結構 112 :第一偏移間隙壁 112a、114a、120a、120c、122a、122c :氧化層 112b、114b、120b、122b :氮化層 114 :第二偏移間隙壁The region 104, and the first active region 1〇2 and the second active region 1〇4 are separated by a spacer structure 106. The first gate structure 1〇8 is disposed on the substrate 1〇〇 of the first active region (1)2, and the second gate structure 11〇 is disposed on the substrate 1〇〇 of the second active region 1〇4. In addition, the first offset spacer 112 is disposed on the sidewall of the first gate structure 108, and the second offset spacer 114 is disposed on the sidewall of the second interpole structure m. The first offset spacer 112 is composed of an oxide layer ii2a and a nitride layer 112b, and the second offset spacer 114 is composed of a layer ma and a nitride layer 114b. The material of the oxide layers 112a, 114a of the first and second offset spacers 112, 114 is exemplified by a material or a carbon-containing oxygen-nitride material. Γ"服乳 17 I30501L -2005-0692 19042twf.doc/n The first LDD1 16 is disposed in the substrate 100 on the side of the first gate structure i〇8. The first LDD 118 is disposed in the substrate 100 on the side of the second gate structure 11〇. In addition, the first spacer 120 is disposed on the sidewall of the first offset spacer 112, and the spacer 122 is disposed on the sidewall of the second offset spacer H4 and located on the portion of the second LDD 118. Wherein, the first spacer 120 is composed of an oxide layer 120a, a nitride layer 120b and an oxide layer 12〇c. The first spacer 122 is composed of an oxide layer 122a, a nitride layer 122b and an oxide layer. 122c is composed. The material of the oxide layers 120a, 120c, 122a, 122c of the first and second spacers 12, 122 is, for example, a high temperature oxidizing material or a carbon-containing oxygen-nitride material. The epitaxial material layer 130 is disposed in the substrate 1〇〇 of the first active region 1〇2 and is located on the side of the LDD 116 as the first conductive type source/drain region. The protective layer 12/! is disposed on the first gate structure 1〇8, the first offset spacer 122, the first spacer 丨2〇, and the first LDDU6, and covers the entire first active region 1〇4. The protective layer 124 is a carbon-containing oxygen-nitride layer which is, for example, a pair of a third butylaminodecane oxide layer. Since the protective layer of the present invention is a soil-containing oxynitride layer having a low characterization rate, the protective layer can be prevented from being improperly removed during the fabrication of the device, resulting in a conventional polycrystalline germanium bump (p〇lybump). The production of ^, its various problems. Next, following Fig. 1F, after the formation of the epitaxial material layer 130, the subsequent process can be continued. Referring to FIG. 1G, the protective layer 124 is removed. Thereafter, a doping process is performed to form a doped region 132' as a second conductivity type source/drain region in the substrate 1〇〇 of the second active region 1〇4. 18 I3〇5〇3cl D-2005-0692 19042twf, doc/n, please refer to FIG. 1H, forming a stress layer 134 in the second active region 1〇4, compliantly covering the second gate structure no, second The spacers 114, the second spacers 122, and the doped regions 132 are offset. The material of the stress layer 134 is, for example, tantalum nitride or other suitable stress material, and the formation method thereof is, for example, chemical vapor deposition or other suitable method. In the above embodiment, if the first-conducting source/drain region is a p-type source/drain region, and the epitaxial material layer 13 is a germanium telluride (SiGe) layer, the stress layer 134 is a tensile stress. Floor. On the other hand, if the first-conductivity-type source/no-polar region is an N-type source/no-polar region, and the i-crystalline material layer 13 is a carbonized carbide (5)c) layer, the stressor layer 134 is a compressive stress layer. In addition, the method of the present invention may also perform a heat treatment process after the step of forming the protective layer 124 and before the (4) canal (3) cleaning process (4) (4), so that the density of the protective layer 124 is more dense, The low protection layer 124 has a _ rate, which is more conducive to the subsequent process. The conditions of the above heat treatment process are, for example, &, the temperature is between 〇 ( (10) 〇 C, the time is between 3 〇 sec and 1 〇 minutes, and the pressure is between 5 〇 5 〇 t (10) S ^ heat treatment process The gas to be used is selected from the group consisting of helium gas, helium gas, Wei (Αι·), reduced (Κι·), gas (Xe) and nitrogen, and the protective layer 124 is subjected to a heat treatment process. The step of removing the photoresist layer 124, the step of forming the trench, and the step of cleaning the material are removed, resulting in the generation of conventional polycrystalline bumps, which in turn affects component enablement. In a preferred embodiment, the first main "moving area" 2 is a 元件-type element area 19 1305031 UMCD-2005-0692 19042 twf.doc/n and the first active area 104 SN type element area is taken as an example. The first active region 1〇2 retains the lower portion of the protective layer 124 and removes the photoresist layer (not shown in FIG. 1) to perform the heat treatment process described above, except that the density of the protective layer 124 can be reduced and reduced. In addition to the residual rate of the protective layer 124, this heat treatment process also facilitates the stress conversion technique (against) and does not degrade component performance. F1 2A to FIG. 2D are schematic cross-sectional views showing a method of fabricating a semiconductor device in accordance with another embodiment of the present invention. 2A to 2D, a cross-sectional view of the flow subsequent to Fig. 1F, and the same components as those of Figs. 1A to 1F are omitted in Figs. 2A to 2D, and are denoted by the same reference numerals. Referring to FIG. 2A, after the protective layer 124 is removed, a protective layer 136 is formed over the substrate 1(), compliantly covering the first gate structure, the first offset spacer 112, and the first spacer 12 〇, first LDDU 6, first gate, 'σ structure 11 〇, brother-offset spacer 114, second spacer 122, first LDD 118, isolation structure 1〇6, and layer of insecticidal material 13〇. The material and formation method of the protective layer 136 are the same as those of the protective layer 124. Thereafter, a photoresist layer 138 is formed over the substrate to cover the protective layer 136 of the first active region 102. Then, referring to FIG. 2A, an anisotropic etching process is performed with the photoresist layer 138 as a mask, so as to be the second gate structure 11〇, the second offset spacer 114, and the second spacer 122. The lower portion of the protective layer 136 is retained. The photoresist layer 138 is then removed. Next, referring to FIG. 2C, the protective layer 136 is used as a mask to remove a portion of the substrate 100 prepared by the bare surface of the active region 104 of the 20th, 2005-0692 19042 tw.doc/n to form a trench in the substrate 100. 140. Thereafter, referring to Fig. 2D, an epitaxial material layer 142 is filled in the trench 14 , as a first conductivity type source/drain region. In one embodiment, prior to filling the layer of epitaxial material 142, a cleaning process is typically performed to clean the surface of the substrate 1 at the bottom of the trench 140. In addition, in the step of forming the epitaxial material layer 142, a pre-bake step is performed to remove impurities generated after the trench 140 is formed. In the above embodiment, if the first conductivity type source/drain region is a p-type source/wave region 'second conductivity type source/drain region (four) type source-level polar region, the silicon oxide material layer 130 As the Wei dislocation layer, the stray material layer 142 is a carbonized stone layer. Conversely, the 'right-conducting source/drain region is the N-type source-level polar region, and the source/drain region is the P-type source/drain region, and the epitaxial material layer is the stone-analyzed stone The layer, the layer of the insect crystal material M2 is a layer of stone enamel. η is an oxygen-nitride layer of the protective layer 136 and the protective layer 124 of the present invention having a low _ rate. Therefore, the step of removing the portion of the substrate 100 to form the surface of the substrate (10) at the bottom of the trench cleaning is performed in the step of 102. The process does not remove the first active region L and affects the process reliability and the tree. efficacy. after that. :,: The method of the invention can be performed in the step of forming the protective layer 136 by heat-treating the === Τ process, and the density of a low-protection layer Μ0 is more densified to reduce the etching rate, and is more advantageous. In the subsequent process. I3〇5〇l 2005-0692 19042twf.doc/n The conditions of the above heat treatment process are, for example, a temperature between 75 〇 and 8 〇〇〇 c, a time between 30 seconds and 10 minutes, and a pressure between Between 5 and 5 〇t〇rr, and the heat treatment process is selected from the group consisting of helium (tetra), oxygen (Ne), argon (Ar), helium (Kr), helium (Xe) and nitrogen. One of the ethnic groups. Yang Luzhi, a heat treatment process on the protective layer 140 can further help to prevent the protective layer M0 from being removed in the steps of removing the photoresist layer, forming the trench, and performing the cleaning process. This leads to the generation of conventional polycrystalline germanium bumps, which in turn affects component performance. In a preferred embodiment, the first active region 1〇2 is a P-type device region, and the second active region 1〇4 is further protected by a σ-minute. After the protective layer 136 and the photoresist layer are removed (as shown in FIG. 2B), the heat treatment process described above is performed, except that the density of the protective layer 124 can be made more dense, and the etching rate of the protective layer 136 is lowered. The heat treatment process also facilitates stress conversion techniques without degrading component performance. Next, the structure of a complementary MOS semiconductor element of another embodiment of the present invention will be described. Referring again to FIG. 2D, the components of the present invention include: a substrate 100 gate structure 108, a second gate structure 11A, a first offset spacer 112, a second offset spacer 114, a first LDD 116, and a first The spacer 120, the second LDD 118, the second spacer 122, the epitaxial material layer 13A, the epitaxial material layer 142, and the protective layer 136. The epitaxial material layer M2 is disposed in the substrate 1〇〇 of the second active region 1〇4 and located at the side of the lddu8 to serve as the second conductivity type source/drain region. The protective layer 136 is disposed on the second gate structure 110, the second offset spacer 114, the second spacer 22 1305·-19042twf.doc/n 122, and the second LDD 118, and covers the entire first active region 1〇 2. Wherein, the protective layer 136 is a carbon-containing oxygen-nitride layer, which is, for example, a double-tert-butylaminodecane oxide layer. In summary, the protective layer of the present invention is a carbon-containing oxygen-nitride layer having a low etching rate, so that the protective layer can be prevented from being improperly removed during the manufacturing process of the device, resulting in a conventional The generation of polycrystalline germanium bumps and their various problems. In addition, the present invention can further improve the density of the protective layer by reducing the density of the protective layer by applying a heat treatment process to the protective layer, thereby reducing the etching rate of the protective layer and facilitating the subsequent process. Although the present invention has been disclosed in the preferred embodiments as described above, it is not intended to be used in any way, and the scope of the present invention may be made without departing from the spirit of the invention. The latter is subject to the definition of patent scope. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A to FIG. 1A are schematic cross-sectional views showing a method of fabricating a MOS device according to an embodiment of the present invention. 2A to 2D are schematic cross-sectional views showing a method of fabricating a sub-type MOS device according to another embodiment of the present invention. [Main component symbol description]: substrate 102: first active region 104: second active region 106: isolation structure 108: first gate structure 23 13050 recognizes D-2005-0692 19042twf.doc/n 108a '110a: sigma Electrical layer 108b, 110b: gate conductor layer 110: second gate structure 112: first offset spacers 112a, 114a, 120a, 120c, 122a, 122c: oxide layers 112b, 114b, 120b, 122b: nitride layer 114 : second offset spacer

116 :第一 LDD116: The first LDD

118 :第二 LDD 120 :第一間隙壁 122 :第二間隙壁 124、136 :保護層 126、138 :光阻層 128、140 :溝渠 130、142 :磊晶材料層 132 :摻雜區 134 :應力層 24118: second LDD 120: first spacer 122: second spacer 124, 136: protective layer 126, 138: photoresist layer 128, 140: trench 130, 142: epitaxial material layer 132: doped region 134: Stress layer 24

Claims

13050¾¾ »-2005-0692 19042twf.doc/n 十、申請專利範圍：種互補式金氧半導體元件的提供一基底’該基底中具有一法，匕括. 隔出一第一主動區與一第—主、’、°構，將該基底區成有一第一閘極結構、一第辟且該第—主動區已形 =二絲區已爾4::料：第-⑽，構與一第二LDD ; 弟一間隙壁結於該基底上順應性地形成_保護層 β 一含碳之氧-氮化物層； q "中该保護層為於該第二主動區之該倾層上以該光阻層為轉，崎—_ 先阻層；極結構以及該第-間隙壁結構 _^ ’以於該第-閘移除該光阻層； /、下。卩分的該保護層；以該保護層為罩幕，移除該第— 分該基底，以於讀基底中形成—溝渠.品之裸露出的部於該溝渠中填入-蟲晶材料層了作極/汲極區； 1卜马—弟—導電型源移除該保護層；以及於該第二主動區之該基底中形成一二導電型源極/汲極區。鸠&作為一第 2如申請專利範圍第μ所述之互補式金氧半件的製造方法，其中該含碳之梟务 " 基胺基石夕烧(BTBAS)氧化層。物層包括一雙第三丁 3.如申請專利範圍第2項所述之互補式金氧半導體元 25 'D-2005-0692 19042twf.doc/n 件的製造方法，其中該雙第三丁基胺基矽烷氧化層的形成方法包栝一低壓化學氣相沈積法(LPCVD)。 4. 如申請專利範圍第1項所述之互補式金氧半導體元件的製造方法，其中在該溝渠形成之後，更包括進行洗製程。 5. 如申請專利範圍第4項所述之互補式金氧半導體元130503⁄43⁄4 »-2005-0692 19042twf.doc/n X. Patent application scope: A complementary MOS device provides a substrate with a method in the substrate, including a first active region and a first The main, ', ° structure, the base region is formed into a first gate structure, a first and the first active region has been shaped = two wire region has been 4:: material: - (10), structure and a second LDD; a spacer layer is formed on the substrate to conformally form a protective layer β-carbon-containing oxygen-nitride layer; q " wherein the protective layer is on the tilt layer of the second active region The photoresist layer is a turn-on, a first-resistive layer; a pole structure and the first-gap structure _^' to remove the photoresist layer from the first gate; Separating the protective layer; removing the first layer from the substrate by using the protective layer as a mask to form a trench in the read substrate. The exposed portion of the product is filled in the trench - a layer of insect crystal material a pole/drain region; a Bu Ma-di-conducting source removes the protective layer; and a two-conducting source/drain region is formed in the substrate of the second active region.鸠 & a method for producing a complementary oxy-half half as described in the second application of the patent application, wherein the carbon-containing oxime " carbamazepine (BTBAS) oxide layer. The material layer comprises a pair of third butyl 3. The method for producing a complementary MOS semiconductor element 25 'D-2005-0692 19042 twf.doc/n according to claim 2, wherein the bis-tert-butyl group The method for forming an amine decane oxide layer is a low pressure chemical vapor deposition (LPCVD) method. 4. The method of fabricating a complementary MOS device according to claim 1, wherein after the trench is formed, a cleaning process is further included. 5. Complementary MOS semiconductor elements as described in claim 4

件的製造方法’其巾在進行該清洗製程之前以及該保護層形成之後，更包括對該保護層進行一熱處理製程。曰 6. 如申請翻_第5項所述之互補式錢半導體元件的製造方法’ #中該熱處理製程的溫度介於75〇〜之間。固弟！）項所述之互補式金氧半導體件的製造方法，其中賴處理製程的時間介於分鐘之間。 v王υThe manufacturing method of the article, wherein the towel is subjected to the cleaning process and after the protective layer is formed, further comprises a heat treatment process for the protective layer.曰 6. If the application method of the complementary money semiconductor element described in the above-mentioned item 5 is applied, the temperature of the heat treatment process is between 75 〇 and 〜. Gudi! The method of manufacturing a complementary oxy-metal device according to the item, wherein the time of the aging process is between minutes. v王υ

件的二；專::圍第5項所述之互補式金氧半導體元牛衣^ 〜中該熱處理製程的麗力介於5〜50 torr <間。件二二:專It圍第5項所述之互補式金氧半導體元該熱處理製频使狀氣體是選自氦所組合之族群其中=綠°、氮氣(Kr)、氤氣(Xe)及I氣元件的“方法々中圍於第二:所述之互補式金氧半導體於該第二形成之後，更包括：土氐上方形成一應力層，順應性 26 '-2005-0692 19042twf.doc/n 地覆蓋該第二閘極結構、該第二間隙壁結構以及該摻雜區。 11. 如申請專利範圍第10項所述之互補式金氧半導體元件的製造方法，其中該第一導電塑源極/汲極區為P型源極/没極區，則該磊晶材料層為石夕化錯層，該應力層為一拉伸應力層。 12. 如申請專利範圍第1〇項所述之互補式金氧半導體元件的製造方法’其中該第一導電型源極/汲極區為N型源極/汲極區’則該磊晶材料層為碳化矽層，該應力層為一壓縮應力層。 13_—種互補式金氧半導體元件的製造方法，包括：提供一基底，該基底中具有一隔離結構區，將該基底區隔出一第一主動區與一第二主動區，且該第一主動區已形成有一第一閘極結構、一第一間隙壁結構與一第一 LDD，該第二主動區已形成有一第二閘極結構、一隙壁結構與-第二LDD; 弟—間於該基底上順應性地形成一第一保護層，其中該第一保護層為一含碳之氧-氮化物層；於該基底上方形成一第一光阻層，覆蓋該第二主動區之該第一保護層；以該第一光阻層為罩幕，進行一蝕刻製程，以於該第一閘極結構以及該第一間隙壁結構上保留下部分的芎^ 一保護層；〇A 移除該第一光阻層；以該第一保護層為罩幕，移除該第一主動區之裸露出 27 ：D-2005-0692 19042twf.doc/n 的部分該基底，以於該基底中形成一第一溝渠；於該第一溝渠中填入一第一蠢晶材料層’作為一第— 導電型源極/汲極區；移除該第一保護層；於該基底上順應性地形成一第二保護層，其中該第二保護層為該含碳之氧-氮化物層；於該基底上方形成一第二光阻層，覆蓋該第—主動區之該第二保護層；Part 2: Special:: Complementary MOS semiconductor element described in Item 5 牛衣^ 〜 The heat treatment process of Lili is between 5~50 torr < Item 22: Complementary MOS semiconductor element according to Item 5 of the special It. The heat treatment frequency-making gas is selected from the group consisting of 氦, = green °, nitrogen (Kr), xenon (Xe) and The "method" of the I gas element is surrounded by the second: after the second formation of the complementary MOS semiconductor, the method further comprises: forming a stress layer above the soil, compliance 26 '-2005-0692 19042 twf.doc The second gate structure, the second spacer structure, and the doped region. The method of manufacturing the complementary MOS device according to claim 10, wherein the first conductive Where the plastic source/drain region is a P-type source/no-polar region, the epitaxial material layer is a Shixia dislocation layer, and the stress layer is a tensile stress layer. 12. As claimed in the first item In the method for fabricating a complementary MOS device, wherein the first conductivity type source/drain region is an N-type source/drain region, the epitaxial material layer is a tantalum carbide layer, and the stress layer is a compressive stress layer. 13_- A method of manufacturing a complementary MOS device, comprising: providing a substrate The substrate has an isolation structure region, the substrate region is separated from a first active region and a second active region, and the first active region has been formed with a first gate structure and a first spacer structure and a first LDD, the second active region has been formed with a second gate structure, a gap structure and a second LDD; a first protective layer is formed on the substrate in compliance, wherein the first The protective layer is a carbon-containing oxygen-nitride layer; a first photoresist layer is formed over the substrate to cover the first protective layer of the second active region; and the first photoresist layer is used as a mask An etching process for leaving a lower portion of the first gate structure and the first spacer structure; 〇A removing the first photoresist layer; using the first protective layer as a mask Removing a portion of the substrate of the first active region 27: D-2005-0692 19042 twf.doc/n to form a first trench in the substrate; filling a first trench in the first trench Asphalt material layer 'as a first - conductive source / bungee zone; remove the first guarantee a second protective layer is formed on the substrate, wherein the second protective layer is the carbon-containing oxygen-nitride layer; and a second photoresist layer is formed over the substrate to cover the first layer The second protective layer of the active area;

以該第二光阻層為罩幕，進行一蝕刻製程，以於該第二閘極結構以及該第二間隙壁結構上保留下部分的該保護層； ~ • ' w I — / 曰 y 以該第二保護層為罩幕，移除該第二主動區的部分該^底以於該基底中形成-第二溝渠；以及出於S亥第一溝渠中埴入—_石曰導電型源極/沒極區。' 4〜日日材· ’作為—第二Using the second photoresist layer as a mask, an etching process is performed to retain the lower portion of the protective layer on the second gate structure and the second spacer structure; ~ • ' w I — / 曰y The second protective layer is a mask, and a portion of the second active region is removed to form a second trench in the substrate; and a conductive source is inserted into the first trench of the Shai Extreme / no pole area. '4~日日材·' as - second

項所述之互補式金氧半導體之氧-鼠化物層包括一雙第： 14.如申請專利範圍第13 元件的製造方法，其中該含# 丁基胺基矽烷氧化層。反 15. 如申請專利範圍第μ 元件的製造方法，JL巾物#貞所奴互補式金乳半導體成方法包括-=基胺齡烧氧化層的形 16. 如申請專利範圍第' 元件的製造方法，苴令在項所述之互補式金氧半導體〃中在_~溝渠形成之後及/或該第二 28 1305031 UMCD-2005-0692 19042twf.doc/n 溝渠形成之後，更包括進行—清洗製程。 ,如申請專利範圍第16項所述之互補式金氧半導體 =件的製造方法’其中在進行該清洗製程之前以及該第 $1该第三保護層形成之後，更包括對該第―、該第二保護層進行一熱處理製程。 18.如中請專利範_ 17項所述之互補式金氧半導體 =的製造方法，其中該熱處理製程的溫度介於750〜800 C之間。 -丛19·如u利範圍第17項所述之互補式金氧半導體 =的製造方法’其中該熱處理製程的時間介於 10分鐘之間。 V 元件5月專利视圍第17項所述之互補式金氧半導體之門 ' 版1"方法’其中該熱處理製程的壓力介於5〜5〇t〇rr 之間。元Μ17項所述之賴核氧半導體兀件的製造方法，苴由兮也占, ^ ^ _ 〃、令該熱處理製程所使用之氣體是選自氣氯氣㈣、氮购、氣氣师^ 元件^之互補式金氧半導體極/汲極區，該第：導導電型源極/汲極區為p_ 泠电^·/原極/汲極區為N型源極/汲極 00 ’ Ί。弟一蟲晶材料層為石夕化錯層，該第二蟲晶材料層為碳化矽層。 23.如申請專利範圍第13項所述之互補式金氧半導體 29 1305031 UMCD-2005-0692 19042twf.doc/n 元件的製造方法’其中該第一導電型源極/汲極區為]^型源極/>及極區，該第二導電型源極/沒極區為p型源極/没極區，則該第一遙晶材料層為碳化石夕層，該第二蠢晶材料層為石夕化鍺層。 24.—種互補式金氧半導體元件，包括：一基底，該基底中具有一隔離結構，將該基底區隔出 —第一主動區與一第二主動區；The oxygen-mouse layer of the complementary oxymetallate described in the present invention comprises a double: 14. A method of producing a component of the thirteenth element of the patent application, wherein the #butylaminodecane oxide layer is contained. In the manufacturing method of the μ-component of the patent application scope, the method for forming a complementary gold-semiconductor semiconductor of the JL towel includes a shape of a -= amine-based burned oxide layer. The method further comprises: after the formation of the _~ trench in the complementary MOS semiconductor according to the item and/or after the formation of the second 28 1305031 UMCD-2005-0692 19042 twf.doc/n trench, further comprising performing a cleaning process . The method for manufacturing a complementary metal oxide semiconductor article according to claim 16 wherein the cleaning process and the formation of the third protective layer are further included. The second protective layer is subjected to a heat treatment process. 18. The method of manufacturing a complementary MOS semiconductor according to claim 17, wherein the temperature of the heat treatment process is between 750 and 800 C. - plex 19. A method of manufacturing a complementary MOS semiconductor as described in item 17 of the U.S. Patent. wherein the heat treatment process has a time of between 10 minutes. The V-element May patent is referred to in paragraph 17 of the complementary MOS gate 'version 1" method' wherein the pressure of the heat treatment process is between 5 and 5 〇t rr. The manufacturing method of the yttrium-oxygen semiconductor device described in the 17th item of Yuanxiao, 苴兮 also occupies, ^ ^ _ 〃, the gas used in the heat treatment process is selected from the group consisting of gas chlorine (4), nitrogen purchase, gas appliance ^ component ^Complementary MOS gate/drain region, the first: conductive source/drain region is p_ 泠 ^ ^ / original pole / drain region is N-type source / drain 00 ' Ί. The layer of the worm-like material is a Shixia dislocation layer, and the second layer of worm material is a layer of ruthenium carbide. 23. The method of manufacturing a complementary metal oxide semiconductor according to claim 13 of the invention, wherein the first conductive type source/drain region is a type a source/> and a polar region, wherein the second conductive source/drain region is a p-type source/no-polar region, and the first remote material layer is a carbonized stone layer, and the second amorphous material The layer is the Shixi Huayu layer. 24. A complementary MOS device, comprising: a substrate having an isolation structure in the substrate, separating the substrate from the first active region and a second active region;

一第一閘極結構，配置於該第一主動區之該基底上；一第二閘極結構，配置於該第二主動區之該基底上； -第-間隙壁結構’配置於該第—閘極結構之側壁； -第二間隙壁結構’配置於該第二閘極結構之側壁； -第- LDD ’配置於該第—閘極結構側邊之該基底中； -第二LDD，配置於該第二閘極結構側邊之該基底中； - -遙晶材料層’ S己置於該第—主動區之該基底中，且位於該第一 LDD側邊，以你丸够措不、 ^以作為一第一導電型源極/汲極區；以及 -保痩層’配置於該第—閘極結構、該第_間隙壁姓構以及該第-LDD上’且覆蓋住該第二主動區，盆中^ 保護層為一含碳之氧-氮化物層。 25.如申請專利範圍第24項所述之互補式金氧半導體二其曰亟/㈣為p型源極/波極區，貝J 5亥;5¾晶材料層為石夕化錯層。 30 1305m -2005-0692 19042twf.doc/n 26. 如申請專利範圍第24項所述之互補式金氧半導體元件’其中該弟一導電型源極及極區為N型源極/波極區’則該兹晶材料層為碳化石夕層。 27. 如申請專利範圍第24項所述之互補式金氧半導體元件，其中該含碳之氧-氮化物層包括一雙第三丁基胺基矽览氧化層。 28. —種互補式金氧半導體元件，包括：一基底，該基底中具有一隔離結構，將該基底區隔出一第一主動區與一第二主動區；一第一閘極結構，配置於該第一主動區之該基底上；一第二閘極結構，配置於該第二主動區之該基底上；一第一間隙壁結構，配置於該第一閘極結構之侧壁；一第二間隙壁結構，配置於該第二閘極結構之側壁；一第一 LDD，配置於該第一閘極結構側邊之該基底中；一第二LDD，配置於該第二閘極結構側邊之該基底中；一第一磊晶材料層，配置於該第一主動區之該基底中，且位於該第一 LDD側邊，以作為一第一導電型源極/ >及極區，一第二磊晶材料層，配置於該第二主動區之該基底中，且位於該第二LDD側邊，以作為一第二導電型源極/ >及極區，以及一保護層，配置於該第二閘極結構、該第二間隙壁結 31 13050^1 D-2005-0692 19042twf.doc/n 構以及該第二LDD上’且覆蓋住該第—主動區，A 保護層為一含碳之氧-氮化物層。 '、ΌΛ —29·如申請專利範圍第28項所述之互補式金氧兀件，其中該第一導電型源極/汲極區為ρ型源極/汲極區，該第二導電型源極/汲極區為Ν型源極/汲極區，則該第— 磊晶材料層為矽化鍺層，該第二磊晶材料層為碳化矽層。 30. 如申請專利範圍第28項所述之互補式金氧半導體兀件’其中該第一導電型源極/汲極區為Ν型源極/汲極區’該第二導電型源極/汲極區為Ρ型源極/汲極區，則該第一磊晶材料層為碳化矽層，該第二磊晶材料層為矽化鍺層。 31. 如申請專利範圍第28項所述之互補式金氧半導體元件，其中該含碳之氧_氮化物層包栝一雙第三丁基胺基矽炫*氧化層。a first gate structure disposed on the substrate of the first active region; a second gate structure disposed on the substrate of the second active region; - a first spacer structure disposed on the first a sidewall of the gate structure; - a second spacer structure disposed on a sidewall of the second gate structure; - a first - LDD ' disposed in the substrate on a side of the first gate structure; - a second LDD, configured In the substrate on the side of the second gate structure; - a layer of the remote crystal material 'S has been placed in the substrate of the first active region, and located on the side of the first LDD, And ^ as a first conductivity type source/drain region; and - a protection layer 'disposed on the first gate structure, the first spacer wall structure and the first-LDD' and covering the first In the active region, the protective layer in the basin is a carbon-containing oxygen-nitride layer. 25. The complementary MOS semiconductor according to claim 24, wherein the bismuth/(iv) is a p-type source/wave region, the shell J 5 hai; and the 53⁄4 crystal material layer is a shixi fault layer. 30 1305m -2005-0692 19042twf.doc/n 26. Complementary MOS device according to claim 24, wherein the source and the polarity of the source are N-type source/wave regions 'The layer of the crystalline material is a carbonized stone layer. 27. The conjugated MOS device of claim 24, wherein the carbon-containing oxygen-nitride layer comprises a pair of a third butylamine-based oxide layer. 28. A complementary MOS device, comprising: a substrate having an isolation structure, the substrate being separated from a first active region and a second active region; a first gate structure, configured On the substrate of the first active region; a second gate structure disposed on the substrate of the second active region; a first spacer structure disposed on the sidewall of the first gate structure; a second spacer structure disposed on the sidewall of the second gate structure; a first LDD disposed in the substrate on a side of the first gate structure; a second LDD disposed on the second gate structure a first layer of epitaxial material disposed in the substrate of the first active region and located at a side of the first LDD as a first conductivity type source/gt; a second epitaxial material layer disposed in the substrate of the second active region and located on the side of the second LDD to serve as a second conductivity type source/gt; and a polar region, and a protection a layer disposed on the second gate structure, the second spacer wall junction 31 13050^1 D -2005-0692 19042 twf.doc/n and the second LDD' and covering the first active region, the A protective layer is a carbon-containing oxygen-nitride layer. '''''''''''''' The source/drain region is a germanium source/drain region, and the first epitaxial material layer is a germanium telluride layer, and the second epitaxial material layer is a tantalum carbide layer. 30. The complementary MOS device according to claim 28, wherein the first conductivity type source/drain region is a 源 source/drain region, the second conductivity source/ The drain region is a germanium source/drain region, and the first epitaxial material layer is a tantalum carbide layer, and the second epitaxial material layer is a tantalum germanium layer. 31. The conjugated MOS device of claim 28, wherein the carbon-containing oxynitride layer comprises a pair of a third butylamine fluorene oxide layer.

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