1299905 九、發明說明： 【發明所屬之技術領域】 本發明關於一種液晶顯示裝置的製造方法，尤其是關於一種在頂 端閘極型多晶矽互補金屬氧化物半導體(CM0S)製程中使用繞射 曝光(diffraction exp〇sure)製造液晶顯示裝置的方法。 【先前技術】 近年來’液晶顯示裝置由於具有耗能低、便於攜帶和高附加 馨值的特點已經被視為下一代高科技顯示裝置的核心產品。液晶顯 示裝置包含位於薄膜電晶體(TFT)所在的陣列基板與彩色濾光基 板之_液晶層’其透過液晶分子的光學異向性產生的折射顯示 影像。 ‘、、 目前使用中的主動矩陣型液晶顯示器(AM-LCD)包含陣列形 式的賴和畫素電極。主動㈣魏晶顯解析度高， 顯示運動畫_能力強。薄膜電晶體中主要使用岐氫化的非晶 ®石夕(a-Si · Η)’因為它能用低溫製程和廉價的絕緣基板製造。然而， 氫化後的非晶石夕具有不規則的原子排列，因此石夕與石夕之間的連接 ’鍵減而且疋不穩定連接(danglingbond)。當絲照或加載磁場時 .非曰曰石夕可轉化成準穩定態（职以_血此_)。因而，當薄膜電晶 體裝置中使_晶料，需要考慮其穩定性的問題。而且，由於 非㈣㈣效遷㈣罐l*m2/V*S)，因此無法細在驅動電 路上。 近來，業界正在研究開發使用多晶石夕薄膜電晶體的液晶顯示 1299905 置由於夕曰曰石夕的場效遷移率比非晶石夕大應至2〇〇倍，因此 D ‘《速度也更丨夬對溫度和光的穩定性也較好。而且，多晶石夕還 有一個優點，即驅動電路可形成在同-塊基板上。 以下將依照_詳細描述先前技術使用多晶赠造液晶顯示 裝置的薄膜電晶體的方法。 第1麵㈣先雜卿成具有鶴桃驗晶顯示裝置的 示意圖。 如第1圖所示’驅動電路5和畫素部份3形成在絕緣的基板工 上。晝素部份3位於絕緣的基板}的中央。而且晝素部份3的兩 侧分別形成有垂直相交的閘極驅動電路5a和資料驅動電路％。在 晝素部份3中’與雕縣電路&相連接的複數制極線7和與 資料驅動電路5b相連接的複數條資料線9彼此交叉。相鄰的開極 線7和資料、線9限定的晝素區域p中還形成有晝素電極1〇。而且， 每條閘極線7和資料線9的奴歧形成有與晝素電極1()相連接 的薄膜電晶體丁。 閘極驅動電路5a和資料驅動電路5b分別與外部信號輸入終 端12連接。閘極驅動電路5a和資料驅動電路5b可控制透過外部 信號輸入終端12輸入的外部信號，接著藉由閘極線7和資料線9 向晝素部份3提供顯示控制信號和資料信號。 以互補金屬氧化物半導體(CM0S)結構作為反向器的薄膜電 晶體(圖未示)形成在驅動電路内，以令閘極驅動電路5a和資料驅 1299905 動=鳴蝴觸當·。峨爾導體結構 可』在驅動電路#的需要快速信號處理_膜電晶體中。互補 金屬氧化物半導體結構中的p型和n型半導體由互補方法進行電 ΛBACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a liquid crystal display device, and more particularly to a method of using diffraction in a top gate gate type polysilicon germanium complementary metal oxide semiconductor (CMOS) process. Exp〇sure) A method of manufacturing a liquid crystal display device. [Prior Art] In recent years, the liquid crystal display device has been regarded as a core product of the next-generation high-tech display device because of its low energy consumption, portability, and high added value. The liquid crystal display device includes a refractive display image which is generated by the optical anisotropy of the liquid crystal molecules in the array substrate on which the thin film transistor (TFT) is located and the liquid crystal layer of the color filter substrate. ‘,, the active matrix liquid crystal display (AM-LCD) currently in use includes an array of ray and pixel electrodes. Active (four) Wei Jingxian's high resolution, showing sports painting _ strong ability. In the thin film transistor, yttrium-hydrogenated amorphous ® a-Si · Η is used because it can be fabricated using a low-temperature process and an inexpensive insulating substrate. However, the hydrogenated amorphous rock has an irregular atomic arrangement, so the connection between the stone eve and the stone eve is reduced and the dangling bond is unstable. When the silk is shot or the magnetic field is loaded, the non-stone can be converted into a quasi-stable state (the job is _ blood this _). Therefore, when the film is made in a thin film transistor device, it is necessary to consider the problem of stability. Moreover, since it is not (four) (four) effective (four) tank l * m2 / V * S), it cannot be fine on the drive circuit. Recently, the industry is researching and developing liquid crystal display 12299905 using polycrystalline silicon thin film transistor. Since the field effect mobility of Xi Xi Shi Xi is 2 times larger than that of amorphous stone, D '"speed is also more丨夬 is also good for temperature and light stability. Moreover, polycrystalline stone has an advantage that the driving circuit can be formed on the same-block substrate. A method of using a polycrystalline crystal film of a liquid crystal display device in the prior art will be described in detail below in accordance with _. The first side (four) of the first miscellaneous into a schematic diagram of the crane peach crystal display device. As shown in Fig. 1, the drive circuit 5 and the pixel portion 3 are formed on an insulating substrate. The halogen portion 3 is located at the center of the insulating substrate}. Further, on both sides of the halogen portion 3, a gate driving circuit 5a and a data driving circuit % which are perpendicularly intersected are formed. In the elementary part 3, the complex electrode line 7 connected to the sculpt circuit & and the plurality of data lines 9 connected to the data drive circuit 5b cross each other. A halogen electrode 1〇 is also formed in the adjacent open region 7 and the halogen region p defined by the data and line 9. Further, each of the gate line 7 and the data line 9 is formed with a thin film transistor D which is connected to the halogen electrode 1 (). The gate drive circuit 5a and the data drive circuit 5b are connected to the external signal input terminal 12, respectively. The gate driving circuit 5a and the data driving circuit 5b can control an external signal input through the external signal input terminal 12, and then supply the display control signal and the data signal to the pixel portion 3 through the gate line 7 and the data line 9. A thin film transistor (not shown) having a complementary metal oxide semiconductor (CMOS) structure as an inverter is formed in the driving circuit so that the gate driving circuit 5a and the data drive 1299905 are turned on. The 导体el conductor structure can be used in the drive circuit# for fast signal processing _ membrane transistors. Complementary metal oxide semiconductor structures in which p-type and n-type semiconductors are electrically operated by complementary methods
性控制以控制流經的電流。 ，補金屬減<物半導體結構的驅動電路的N型薄膜電晶體和 P型錢電晶體、以及陣瓶板的畫素部份關關元件都將依照第 2圖進恤述。第2騎㈣先前技術晝素部份的卿元件及具有 互補金屬氧化物轉體結構的驅動電路的薄膜電晶體的剖面圖。 如第2圖所示’在先前技術晝素部份的開關元件工中，由域 絕緣材料如二減雜成賴铺Μ軸在紐a㈣整個表面 上。半導體層30軸械衝層25上，咖_ 45形成在半導 體層30上。 間極50形成在閘極絕緣層45上，中間絕緣層70形成在閘極 5〇上。用於接解導體層㈣轉體層输⑽、现形成在 間極絕緣層45和中間絕緣層7G。分別與半導體層接觸孔7如、现 連接的源極8Ga和汲極8Gb形成在中間絕緣層％上，且二者與閑 極50間隔有預設距離。 、 包含汲極接觸孔95的鈍化層90形成在汲極上，與汲極 8〇b透過汲極接觸孔95連接的晝素電極97形成在鈍化層9〇上。 位於閘極絕緣層45的較低位置的半導體層3〇的與間極％對 應的部份為主動層3〇a，位於酿絕緣層Μ的較低位置的半導體 1299905 層30的與源極80a和汲極接觸的部份為n型推賴，以形成 η型歐姆接觸層30c。η-型摻雜的輕摻雜汲極(_層通形成在 主動層施與η型歐姆接觸層撕之間。輕摻驗極層通為低 濃度摻雜以散佈熱载子，以防止電流泄漏和開啟電流的損失。 而且’具有互補金屬氧化物半導體結構的薄膜電晶體的通路 層、歐姆層、輕摻雜汲極層、閘極和源極/汲極的製程都與晝素 部份的開關元件的通路層、歐姆層、輕推雜汲極層、閉極和源極 /没極的抛_。驅動電路中的具有金屬氧化物半導體結 構的薄膜電晶體包含第-薄膜電晶體區域η，第二薄膜電晶體區 域Π、包含n+型摻雜的η型半導體層％，以及包括ρ+型推雜 型半導體層40的第三薄膜電晶體區域皿。. η型半賴邱㈣轉體層初錄形成有預設間隔的緩 衝層25的透明絕緣的基板2〇上，閘極絕緣層必形成在n型半導 體層奸Ρ型半導體層40的整個表面。閘極55、⑻形成在閑極 絕緣層45上。 包含半導體層接觸孔75a、75b、77a和77b的中間絕緣層％ 位於形成有閘極55、6G的基板的整個表面上。源極仏、^和 汲極跳、87b形成在中間絕緣層7G上，其分财過半導體層^ 觸孔75a、75b、77a和77b與n型半導體層35和p型半導體層奶 相接觸。 曰 位於閘極絕緣層45的較低處的n型半導體層％的與鬧極义 1299905 W為主動層3Ga ’位於触絕緣層45的較低處的n型半 導體層35的與源極83a和沒極咖接觸的部份為η+接雜型的η型 歐姆接觸層说。η-_的輕摻雜汲極_層说形成在主動 層35a與n型歐姆接觸層35c之間。 在P型半導體層40 t，電洞即载子。因此，與n型薄膜電晶 體相比’細失和咖露不大。所以無嶋輕細及極層。 位於閘極絕緣層45的較低處的半導體層4〇的與閑極6〇對應的部 份為主動層他，其外圍區域為P型歐姆接觸層撕。 _以下將依照第3圖及第4A圖至第犯圖描述先前技術液晶顯 不褒置的㈣電路部份中具有互補金屬氧化物轉體結構的薄膜 電晶體以及畫素部份的糊裝置的製造方法。Sexual control to control the current flowing through. The N-type thin film transistor and the P-type money transistor of the driving circuit of the metal-reduced semiconductor structure and the pixel-parting components of the array plate will be described in accordance with FIG. A second section (four) a cross-sectional view of a thin film transistor of a prior art element and a thin film transistor having a driving circuit of a complementary metal oxide rotating structure. As shown in Fig. 2, in the switching element of the prior art element, the domain insulating material, such as the second insulating material, is placed on the entire surface of the new a (four). On the semiconductor layer 30, the ceramic layer 45 is formed on the semiconductor layer 30. The interpole 50 is formed on the gate insulating layer 45, and the intermediate insulating layer 70 is formed on the gate 5?. It is used to connect the conductor layer (4) to the transfer layer (10), which is now formed in the interpole insulating layer 45 and the intermediate insulating layer 7G. The source 8Ga and the drain 8Gb, which are respectively connected to the semiconductor layer contact hole 7, for example, are formed on the intermediate insulating layer %, and are spaced apart from the idler 50 by a predetermined distance. A passivation layer 90 including a drain contact hole 95 is formed on the drain, and a halogen electrode 97 connected to the drain electrode 95 via the drain contact hole 95 is formed on the passivation layer 9A. The portion of the semiconductor layer 3 位于 located at the lower position of the gate insulating layer 45 corresponding to the interpole portion is the active layer 3 〇 a, the lower portion of the semiconductor insulating layer Μ at the lower position of the semiconductor 1299905 layer 30 and the source 80a The portion in contact with the drain is an n-type push-up to form an n-type ohmic contact layer 30c. Η-type doped lightly doped drain (the layer is formed between the active layer and the n-type ohmic contact layer. The lightly doped layer is doped at a low concentration to spread the hot carrier to prevent current Leakage and turn-on current loss. Also, the process of the via layer, the ohmic layer, the lightly doped drain layer, the gate and the source/drain of the thin film transistor with a complementary metal oxide semiconductor structure is related to the halogen component. The via layer of the switching element, the ohmic layer, the napped heterodymium layer, the closed-pole and the source/no-pole throwing _. The thin film transistor having the metal oxide semiconductor structure in the driving circuit includes the first-thin film transistor region η, a second thin film transistor region Π, an n-type doped n-type semiconductor layer%, and a third thin film transistor region plate including the ρ+-type push-type semiconductor layer 40. η-type semi-Lai Qiu (four) turn The bulk layer is formed on the transparent insulating substrate 2 on which the buffer layer 25 of the predetermined interval is formed, and the gate insulating layer is formed on the entire surface of the n-type semiconductor layer of the sinusoidal semiconductor layer 40. The gates 55 and (8) are formed in the idle state. On the pole insulating layer 45. The semiconductor layer contact holes 75a, 75 are included. The intermediate insulating layer % of b, 77a and 77b is located on the entire surface of the substrate on which the gates 55, 6G are formed. The source 仏, 汲 and 汲 跳, 87b are formed on the intermediate insulating layer 7G, which is divided into semiconductor layers ^ The contact holes 75a, 75b, 77a, and 77b are in contact with the n-type semiconductor layer 35 and the p-type semiconductor layer milk. 曰 The n-type semiconductor layer at the lower portion of the gate insulating layer 45 is 与 义 1 1299905 W The active layer 3Ga' is located at the lower portion of the n-type semiconductor layer 35 of the contact insulating layer 45, and the portion of the n-type semiconductor layer 35 that is in contact with the source 83a and the ruthenium is n-type ohmic contact layer of the n+-doped type. η-_ The lightly doped drain _ layer is formed between the active layer 35a and the n-type ohmic contact layer 35c. In the P-type semiconductor layer 40 t, the hole is a carrier. Therefore, compared with the n-type thin film transistor, the fine loss It is not too thin, so it is light and thin. The portion of the semiconductor layer 4 at the lower portion of the gate insulating layer 45 corresponding to the idle pole 6〇 is the active layer, and its peripheral region is P. Type ohmic contact layer tearing. _ The following description will be made in the (4) circuit part of the prior art liquid crystal display according to FIG. 3 and FIG. 4A to the first drawing. A method of manufacturing a thin film transistor of a metal oxide-transferred structure and a paste device of a pixel portion.
、第3騎^先前技術液晶顯轉置巾鶴電路部份的具有 互補金屬氧化物半導體結構的薄膜電晶體及頂端閘極結構的晝素 部份的開關元件的製造方法中光罩製程的流程圖。第4A圖至第 妞圖所示分別為先前技術驅動電路部份的具有互補金屬氧化物 半導體結構的薄膜電晶體及晝素部份的開關元件的製程的剖面 如第3騎示’先前技術製造液晶顯示裝置之薄膜電晶體的 方法包含製造基板上的轉體層的第—光罩製程㈣，在半導體 層上形成驅動電路部份和晝素部份的閘極的第二光罩製程製程 ⑽），在驅動部份和細卩份醉導體層的—側選擇性= 10 1299905 雜η型雜質的第二光罩製程(⑽），在驅動電路部份的半導體層的 另-側選擇性地摻雜p+型雜質的第四光罩製程㈣），用於形成暴 露雜質所處的半導體層的源極/汲極接觸孔的第五光罩製程 (S50)，在源極/汲極接觸孔處形成源極和汲極的第六光罩製程 (S60)，在包含源極和汲極的基板的整個表面上的鈍化層上形成接 觸孔的第七光罩餘_，及在鈍化層啸觸孔處形成晝素電極 的第八光罩製程(S80)。 以下將結合第4A圖至第4H圖描述透過上述八次光軍製程製 造先前技術液晶顯示裝置的薄膜電晶體的方法。 、 如第4A圖所示’將如二氧化石夕的無機絕緣娜冗積在透明絕 緣的基板2G的整個表面上，以形成緩衝| 25。接著將非晶石夕卜 si沉積在包含形成有緩衝層25的基板2G的整個表面。然後使非 晶石夕a-Si脫氫，並透過雷射結晶贼後的非晶石夕卜&使之結曰 成多晶梦。 接著，透過第-光罩製程S10將多晶石夕層形成圖案以形成半 導體層30、35和40 〇 如第狃圖所示，將氧化石夕沉積在形成有半導體層％％和 40的基板20的整値表面上，以形成閘極絕緣層45。 然後，將如_0)的金屬材料沉積在閉極絕緣層4 :二光罩製_在其上形成_ 5G、55和6g。=、 55和仰作為«透鱗子賴纽錢板2q岐麵面上進行 11 1299905 雜極轉雜製程。位时素部份和補電路部份的閑 Γ:5和60下方的主動層施，和*無_^^^ 而輕細及極層3〇b、现和鄕進行η-型摻雜製程。 本如弟^圖所示，將光隱沉積在，雜型基板20的整個 义面上’亚猎由$三光罩S3〇形成光阻圖案.光阻圖案a不僅 用於遮㈣―__域卜第二__域II的閑極 5〇、55 於遮蔽從具有預設間__ 5G、55的兩侧延伸的 閘極絕緣層45的頂部。而g μ ^ 賴‘而且，細_63不僅可完全遮蔽間極 =用於遮咖動電路部份的ρ型第三薄膜電晶體區賴的 半導體層40對應部份的閘極絕緣層45。 接著，在形成有光阻圖案62、63的基板Μ的整個表面上透 =^度離子進行__。未被光_ _遮蔽 體層透過0摻雜製程形成n型歐姆接觸層撕、奴。第 賴電日日體區域I、第二薄膜電晶體區域π中由於閘極％％ =在而未咖讎輸和__細彻層㈣ ^了主動綠、祝，絲祕、㈣ _n型推雜部份形成了輕摻雜汲極層30b、35b。 弟4D圖所不，將光阻沉積在形成有^型歐姆接觸層撕、 ‘Γ板Μ的整個表面上’接著，用於_極5〇、55和間極 ^層45 _半繼3G、％對應細_圖㈣透過第四 先罩衣㈣成在猶電財做為第—元魏域之第二薄膜電晶體 12 1299905 =1和_份之第—薄膜電_域1内。但是，在閘極絕 、、曰t驅動電路中做為第二元件區域之第三薄膜電晶體區域m t P型半導體層4G對應的部份沒有形成光阻圖案。 曰^著if過噴射^農度離子進行p+摻雜製程。在第三薄膜電 晶體區域111_ ’ _極6_蔽絲進行p+摻雜製程的 半‘體層4〇域了主動層他，進行p+摻雜製程的部份半導體層 4〇心成了 p型歐姆接觸層4〇c。接著移除光阻圖案。 如第犯圖所示’將如聊或_的無機絕緣材料沉積在形 成有P型歐姆接觸層4〇c的基板2〇的整個表面，以形成中間絕緣 層7〇。接著透過第五光罩製程將中間絕緣層7〇和閑極絕緣層衫 起钱刻以形成用於將部份歐姆接_ 3〇c、攻 '输暴露在外 的半導_接觸孔 73a、73b、75a、75b、77a、77b。 如第4F圖所示，在形成有半導體層接觸孔73a、73b、75a、 75b、77a、77b的中間絕緣層7〇上依次沉積鉬⑽〇)和敛化銘 (AINd)接著’透過第六光罩製程進行整體钱刻，以开)成透過半 導體層接觸孔73a、73b、75a、75b、77a、77b與歐姆接觸層30c、 35c、4〇C 連接的源極 8〇a、83a、87a 和汲極 8〇b、83b、87b。 如第4G圖所不，將氮化矽(siNx)沉積在形成有源極8〇a、83a、 87a和汲極80b、83b、87b的基板2〇上，接著進行熱氫化製程。 然後’透過第七光罩製程在基板2〇上形成具有汲極接觸孔95的 鈍化層90 〇 13 1299905 ==的步鱗舰減程，但由___ 胰電曰曰體相關，因此將對其進行簡述。 圖所示，將氧化銦錫(ΙΤ〇)沉9# 第Α崎鄉恤 孔95與雜9〇b連接的晝素電極97。 及其二在!含集成驅動電路的液晶顯示裝置的開關元件 阻‘、14進行八次光罩製程。由於光罩製程包含光 曝光和顯影製程，製程次數多，因此增加了成本並且製 ^目峨。因此，降低了價格的競爭力和生 細失物加，料，麵_結構的 、日日體衣釦中，當形成半導體層 使一摻__接觸層消失。、&於過賴刻易 【發明内容】 次數二?明的主要目的在於提供一種可縮減製程 瓤 射曝光製造㈣顯科置之_電晶體龄法。μ使用繞 薄膜=體明所揭露之-種液晶顯示裝置之 層，基板包含晝素部份和基板的整録面上職半導體 元件，,_路部份内 導體層的獅魏、帛_雜獅；^== 14 1299905 的半‘體層進仃第二雜質摻雜；在基板的整個表面上形成導電 曰並將導電層與半導體層—同形成圖案，以分卿成第一、第 #第_7〇件的雜區域、汲祕域和絲區域；在基板的整個 …表面上形成閘極絕緣層；在閘極絕緣層上形成第_、第二和第三 .7L件的閘極，在基板的整個表面上形成純化層；形成用於暴露晝 素部份的細娜_孔；及在慧層上形錢過錄接觸孔 與汲極相連接的晝素電極。 、本發明所揭露之-種液晶顯示裝置之薄膜電晶體的製造方 法，其包含在基㈣整個表面上形成半導體層，基板包含晝素部 份和驅動電路部份，畫素部份_成有第—元件，驅動電路部份 内开v成有第一和第二疋件；在第一元件的半導體層上、第二元件 整體及第三元件的閘極形成區域上形成第一光阻圖案；藉由第一 光二圖案作為光罩對第三树的半導體層進行第—雜質推雜；移 •除弟-光阻圖案並在第—元件的閘極形成區域、第二元件的間極 域區域及部分第三元件上形成第二光阻圖案；藉由第二光阻圖 •案作為光罩對第-和第二树的半導體層進行第二雜質推雜；在 基板的翻表面職導電層和光阻層，織透魏射曝光部份钱 刻光阻層以形成第三光阻圖案；藉由第三光阻圖案作為光罩將導 電層與半導體層一同形成圖案以定義汲極和源極區域及主動區 域；钱刻位於第-、第二和第三元件的通路區域的繞射曝光後的 弟三光阻·以暴露導電層；藉由第三光阻圖案作為光罩侧導 1299905 電層以形成第-、第二和第三元件的汲極和源極；移除第三光阻 圖案，、然後梅_絲上糊極糊；㈣極絕緣^ 上形成閘極導電層，錢在閘極導電層上形成第四光阻圖案；^ 由第四光阻圖案作為解賴該閘極導電層，以形成第―、第二 和第二7G件的難；移除第四光_案，然後在基板的整個表面 上形成鈍化層；在鈍化層上形成第五光關案，然後藉由第五光 阻圖案作為光罩蝴舰層以暴露第-元件的源極或汲極；移除 弟五光阻®案’紐在鈍化層上形成透魏極層，翻電極係與 第-元件的源極歧極相連接；及在透鴨極層上形成第六光阻 圖案，紐藉由該第六光闕案作為光罩侧該透明雜層以形 成晝素電極。 本發明所揭露之一種液晶顯示裝置的製造方法，其包含使用 至多六次光罩製程在基板的畫素區域形成第一薄膜電晶體，在基 板的驅動電路區域形成第二薄膜電晶體和第三薄膜電晶體；及形 成第一、第二和第三薄膜電晶體的製程包含將半導體層及位於其 上的導電層一同形成圖案，以形成第一、第二和第三薄膜電晶體 的源極、汲極和主動區域。 有關本發明的特徵與實作，茲配合圖式作最佳實施例詳細說 明如下。 【實施方式】 以下將依照附圖詳細描述本發明的實施例。 16 1299905 第5騎不為本發明製造具有頂端閘極結構的晝素部份的開 =件Μ及製造驅動f路部份的具有互補金屬氧化物半導體結構 八=膜電日日體的方法中光罩製程的流程圖。第Μ圖至第张圖所 為本1月衣仏晝素部份的開關元件以及製造驅動電路部份 、具有^補金屬氧化物半導體結構的薄膜電晶體的剖面圖。 •第圖所不，本剌製造液晶顯示裝置之薄膜電晶體的方The third process is a process for manufacturing a photomask process in a method of manufacturing a thin-film transistor having a complementary metal oxide semiconductor structure and a halogen-emitting portion of a top gate structure in a liquid crystal display Figure. 4A to FIG. 2 are cross-sectional views showing a process of manufacturing a thin film transistor having a complementary metal oxide semiconductor structure and a switching element of a halogen portion in a prior art driving circuit portion, respectively, as shown in FIG. The method for manufacturing a thin film transistor of a liquid crystal display device comprises a first photomask process (four) for manufacturing a swivel layer on a substrate, and a second photomask manufacturing process for forming a driver circuit portion and a gate portion of the halogen portion on the semiconductor layer (10) The second mask process ((10)) of the side-selectivity = 10 1299905 hetero-n-type impurity in the driving portion and the fine-grained drunk conductor layer is selectively doped on the other side of the semiconductor layer of the driving circuit portion The fourth mask process (four) of the hetero-p+ type impurity, the fifth mask process (S50) for forming the source/drain contact hole of the semiconductor layer where the impurity is exposed, at the source/drain contact hole a sixth mask process (S60) for forming a source and a drain, forming a seventh mask of the contact hole on the passivation layer on the entire surface of the substrate including the source and the drain, and squeaking in the passivation layer The eighth mask process for forming a halogen electrode at the hole (S80) . A method of manufacturing a thin film transistor of a prior art liquid crystal display device through the above-described eight-time optical process will be described below in conjunction with Figs. 4A to 4H. As shown in Fig. 4A, the inorganic insulating material such as silica dioxide is accumulated on the entire surface of the transparent insulating substrate 2G to form a buffer |25. Then, an amorphous stone is deposited on the entire surface including the substrate 2G on which the buffer layer 25 is formed. Then, the amorphous a-Si is dehydrogenated, and the amorphous austenite & Next, the polycrystalline layer is patterned by the first photomask process S10 to form the semiconductor layers 30, 35, and 40. As shown in the second figure, the oxidized oxide is deposited on the substrate on which the semiconductor layers %% and 40 are formed. The entire surface of the 20 is formed to form a gate insulating layer 45. Then, a metal material such as _0) is deposited on the closed-electrode insulating layer 4: a reticle _ on which _5G, 55, and 6g are formed. =, 55 and Yang as the "Through the scales Lai New money board 2q 岐 face to carry out 11 1299905 heteropolar conversion process. The idle time of the bit-time component and the complementary circuit part: the active layer application under 5 and 60, and *no_^^^ and the light-thin and the polar layer 3〇b, the current and the 鄕-type doping process . As shown in the figure, the light is deposited on the entire surface of the hetero-substrate 20, and the photoresist pattern is formed by the $3 mask S3. The photoresist pattern a is not only used to cover (4) - __ domain The idle poles 5, 55 of the second __ domain II are shielded from the top of the gate insulating layer 45 extending from both sides having the preset spaces __ 5G, 55. And g μ ^ 赖 ‘and, fine _63 can not only completely obscure the interpole = the gate insulating layer 45 of the corresponding portion of the semiconductor layer 40 of the p-type third thin film transistor region for the occlusion circuit portion. Next, __ is performed on the entire surface of the substrate on which the photoresist patterns 62, 63 are formed. The n-type ohmic contact layer is not torn by the light _ _ shielding body layer through the 0 doping process. The first solar region I and the second thin film transistor region π are due to the gate %% = not in the glutinous and __ fine layer (four) ^ active green, wish, silk secret, (four) _n type push The impurity portion forms lightly doped gate layers 30b, 35b. In the 4D diagram, the photoresist is deposited on the entire surface of the ohmic contact layer formed by the ohmic contact layer, and then used for the _ pole 5 〇, 55 and the interpolar layer 45 _ semi-continuous 3G, % corresponds to the fine_figure (4) through the fourth first cover (four) into the second thin film transistor 12 1299905 =1 and the first part of the thin film electric _ domain 1. However, the photoresist pattern is not formed in the portion corresponding to the third thin film transistor region m t P type semiconductor layer 4G in the gate region and the 曰t driving circuit.曰^ If the over-spray ^ agricultural ion is used for the p + doping process. In the third thin film transistor region 111_'_pole 6_clear wire, the p+ doping process is performed on the semi-body layer 4, and the active layer is formed. The portion of the semiconductor layer 4 subjected to the p+ doping process becomes p-type ohmic. Contact layer 4〇c. The photoresist pattern is then removed. The inorganic insulating material such as Talk or _ is deposited on the entire surface of the substrate 2A having the P-type ohmic contact layer 4〇c as shown in the figure to form the intermediate insulating layer 7〇. Then, the intermediate insulating layer 7 and the dummy insulating layer are etched through the fifth mask process to form semi-conductive contact holes 73a, 73b for exposing a part of the ohmic junctions. , 75a, 75b, 77a, 77b. As shown in FIG. 4F, molybdenum (10) 依次 is sequentially deposited on the intermediate insulating layer 7〇 on which the semiconductor layer contact holes 73a, 73b, 75a, 75b, 77a, and 77b are formed, and AINd is then transmitted through the sixth The mask process is entirely engraved to open the source 8A, 83a, 87a connected to the ohmic contact layers 30c, 35c, 4C through the semiconductor layer contact holes 73a, 73b, 75a, 75b, 77a, 77b. And bungee 8〇b, 83b, 87b. As shown in Fig. 4G, tantalum nitride (siNx) is deposited on the substrate 2A on which the source electrodes 8a, 83a, 87a and the drain electrodes 80b, 83b, 87b are formed, followed by a thermal hydrogenation process. Then, through the seventh mask process, a passivation layer 90 〇13 1299905 == having a gate contact hole 95 is formed on the substrate 2, but the step is reduced by the ___ pancreatic body, so it will be It is briefly described. As shown in the figure, the indium oxide tin (yttrium) sinks 9#, the Α 乡 乡 乡 乡 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 95 And the second is in the switching element of the liquid crystal display device including the integrated driving circuit, and the reticle process is performed eight times. Since the photomask process includes a photoexposure and development process, the number of processes is large, thereby increasing the cost and making it possible. Therefore, the competitiveness of the price and the loss of the material, the material, the surface structure, the day and the body, and the formation of the semiconductor layer cause the disappearance of the __ contact layer. , & 过 赖 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 【 μ uses a layer of a liquid crystal display device disclosed by a film, which comprises a halogen component and a semiconductor component of the substrate, and a lion-like, inner-conductor layer of the inner conductor layer Lion; ^== 14 1299905 The semi-th body layer is doped with a second impurity; a conductive erbium is formed on the entire surface of the substrate, and the conductive layer and the semiconductor layer are patterned together to form a first and a _7 the impurity region, the 汲 secret region and the silk region; forming a gate insulating layer on the entire surface of the substrate; forming gates of the first, second and third .7L members on the gate insulating layer, Forming a purification layer on the entire surface of the substrate; forming a fine-hole for exposing the moiré portion; and forming a halogen electrode on the surface of the layer on which the contact hole is connected to the drain. The method for fabricating a thin film transistor of a liquid crystal display device according to the present invention comprises forming a semiconductor layer on the entire surface of the substrate (four), the substrate comprising a halogen portion and a driving circuit portion, and the pixel portion is formed a first component, the driving circuit portion is internally formed with the first and second germanium members; and the first photoresist pattern is formed on the semiconductor layer of the first component, the gate forming region of the second component and the third component Performing a first-impurity impurity on the semiconductor layer of the third tree by using the first photo-two pattern as a mask; shifting the dipole-resist pattern and forming the region of the gate of the first element and the interpole region of the second element Forming a second photoresist pattern on the region and a portion of the third component; performing second impurity doping on the semiconductor layers of the first and second trees by using the second photoresist pattern as a mask; conducting electrical conductivity on the flip surface of the substrate a layer and a photoresist layer, which are etched through the surface of the photoresist to form a third photoresist pattern; the third photoresist pattern is used as a mask to form a pattern together with the semiconductor layer to define a drain and a source Polar region and active region; money engraved Diffraction of the exposed regions of the via regions of the first, second and third elements to expose the conductive layer; by means of the third photoresist pattern as the reticle side guide 1299905 electrical layer to form the first and second a drain and a source of the third component; removing the third photoresist pattern, and then paste the paste on the plum-silver; (4) forming a gate conductive layer on the pole insulator ^, forming a fourth light on the gate conductive layer a resist pattern; the fourth photoresist pattern is used as a solution for dissolving the gate conductive layer to form the first, second, and second 7G members; the fourth light is removed, and then formed on the entire surface of the substrate a passivation layer; forming a fifth photo-cut on the passivation layer, and then exposing the source or the drain of the first component by using the fifth photoresist pattern as a photomask layer; removing the dipole photoresist® case Forming a transparent layer on the passivation layer, the flip electrode is connected to the source of the first element; and forming a sixth photoresist pattern on the penetrating layer, the sixth light is used as the light The transparent layer is covered on the cover side to form a halogen electrode. A method of fabricating a liquid crystal display device according to the present invention includes forming a first thin film transistor in a pixel region of a substrate using at most six mask processes, forming a second thin film transistor in a driving circuit region of the substrate, and third a thin film transistor; and a process for forming the first, second, and third thin film transistors, comprising patterning the semiconductor layer and the conductive layer thereon to form a source of the first, second, and third thin film transistors , bungee and active areas. The features and implementations of the present invention are described in detail with reference to the preferred embodiments. [Embodiment] Hereinafter, embodiments of the present invention will be described in detail in accordance with the accompanying drawings. 16 1299905 The fifth rider does not manufacture the open part of the halogen component having the top gate structure of the present invention and the method of fabricating the f-portion portion having the complementary metal oxide semiconductor structure VIII = film electric solar body Flow chart of the mask process. The first to the first figures are cross-sectional views of the switching element of the kiwi fraction in January and the thin film transistor having the metal oxide semiconductor structure. • The figure is not, the side of the film transistor that manufactures the liquid crystal display device
》匕含第—至第六鮮製程。第_光罩製輝糊於在書素部份 1的+導體層上以及驅動電路部份中做為第二元件區域之第三薄 膜電晶體區域in中的部份半導體層上摻雜p+型雜質；第二光罩製 私(S120)用於在驅動電路部份中做為第―元件區域之第二薄膜電 晶體區域II中的部份半導體層上摻雜n+型㈣，第三光罩製程 酬用於透過使嶋曝光將源極/觸域和湖域形成 圖案，、第四光罩製__於形成閘極，第五光罩製卿_》 contains the first to the sixth fresh process. The photomask is doped with a p+ type on a portion of the semiconductor layer in the third thin film transistor region in the second conductor region on the +conductor layer of the pixel portion 1 and the driver circuit portion Impurity; second mask manufacturing (S120) for doping n+ type (four) on a portion of the semiconductor layer in the second thin film transistor region II of the first element region in the driver circuit portion, the third mask The process is used to pattern the source/contact and the lake by exposing the ,, and the fourth mask is used to form the gate, the fifth mask is _
於形成畫她她，第六爾卿_於形成透過晝素電 極接觸孔與汲純域連接的晝素電極。 以下將依照第 製造液晶顯示裝置 法0 6A圖至第6K圖描述本發明透過六次光罩製程 的驅動電路部份和晝素部份㈣_晶體的方 第圖所Τ，將减絕緣材料如二氧切(蜗)沉積在透 明絕緣的基板m的整個表面上，以形成緩衝層125。將非晶石夕a —S1沉積在形成有緩衝層125的基板m的整個表面上。然後進 1299905 行非晶雜絲程，接著崎職後神晶⑽射結晶製程，以 將非晶梦層結晶為多晶碎層130。 如第6B圖所示，將第一光阻層沉積在多曰曰曰石夕芦 過第-光罩製程sno選擇性地將其形成圖案，^成用於吳露= 份多晶石M uo的第-光阻圖案135。在進行第—_程· 化，第一光阻圖案135仍殘留在晝素部份 區域!、_路部份的所有第二薄膜電 =: 份的第三薄膜電晶體區域m的間極形成區域上Μ和驅動電路部 接著，透過第35作為鮮，對驅動電路部份 膜電晶體區域m的多晶石夕層130進+ ρ弟一厚 -光阻圖案135。 然後移除第 如第冗_示，將第二光阻層崎在多晶 光罩製程㈣將第二光阻層形成用於^ 3〇的第二光關請。紅光_馳可她^曰曰 的所有p型第：薄膜電曰邦枝m β Γ遮蚊驅動電路部份 區域Μ 晝素_的第—_電曰俨 =的閘極形成區域，以及驅動電路部份的η型第二=:體 區域II的閘極形成區域。 —顧電曰曰體 接著，以第二光阻圖案14〇作為光對曰 型雜質摻雜。 、阳曰130進行η+ 如第奶圖所示，透過灰化製程一定 裳 140，並對多晶石夕層⑽進行η-型雜予度的弟一光阻圖案 ^貝_以形成輕摻雜紐區 18 1299905 域。接著移除灰化後的第二光阻圖案14〇a。 如第6E圖所示，在雜質摻雜製程後，將源極/雜導電層 W5沉積在基板12〇的整個表面上。 接著’將第二光阻層沉積在導電層145上。町透過使用繞射 圖案光罩的第三光罩製程8130部份侧第三光阻層，卩定義主動 區域和源極/祕區域，進而形成第三光阻圖案15()。當使用繞射 圖案作為光罩曝S第三光阻層時，繞射曝光後的第三光阻並未被 凡全曝光，因而在後續的顯影製程中僅對被曝光預設厚度進行顯 影。就是說，繞射曝光並未完全曝光第三光阻，而只是部份曝光， 足是因為繞射圖案曝光區域的光傳輸率小於完全曝光的光阻部份 的光傳輸率。 因而，如第6E圖所示，當對繞射曝光後的第三光阻進行顯影 日才’與未曝光的光阻相比，僅有預設厚度的光阻被顯影。就是說， 在繞射曝光過程中，第-、第二和第三元件的通路區域的曝光程 度大於源極和汲極區域。 如第6F圖所示，導電層145和多晶矽層13〇均以第三光阻圖 案150作為光罩被選擇性地蝕刻，以定義源極/汲極區域和主動 區域。 如第6G圖所示，透過灰化製程移除一定厚度的第三光阻圖案 150，以暴露導電層145頂部的中央部份。 如第6H圖所示，使用灰化後的第三光阻圖案15〇a (參照第 19 1299905 6G圖）作為光罩選擇性地移除導電層145，以形成晝素部份的第 -源極/汲極155a、155b ’和鶴電路部份㈣二源極A及極 臟、160b ’以及驅動電路部份的第三源極/汲極脑、π%。 接著移除灰化後的第三光阻圖案15〇a。 如第61圖所示’可將二氧化石夕si〇2沉積在基板的整個表面上 以形成閘極絕緣層17G，此時的基板包含晝素部份的第—源極/沒 極155a、l55b和驅動電路部份的第二源極力及極施、祕，以 及驅動電路部份的第三源極/汲極⑽、祕。接著對閘極絕緣 層’進行活化，可將如翻(M〇)、銘(A1)、敛化銘(a腕）' 絡⑼、 ,u)或鵁W沉積在閘極絕緣層17〇上，並將第四光阻層沉積在 導電材料上。可透過第四光罩製程S140選擇性地移除第四光阻 層，以形成用於定義閘極的第四光阻圖案(圖未示）。 一、，苐61圖所示，可透過第四光阻圖案(圖未示)作為光罩將導 電材料形朗案，以形成閘極Π5、18G和185。接著，移除第四 光阻圖案(圖未示）。 如第6J圖所示，將絕緣材料沉積在包含閘極175、180和185 、板的整個表面上，以形成鈍化層190。絕緣材料可包令^一 種或多種域材料，如二氧切(SiQ2)或統⑨(SiNx)，和/或-3、夕種有機材料，如苯並環丁稀或壓克力樹 月曰。接著，對鈍化層190進行熱氮化製程。 二、:後’在鈍化層190上沉積第五光阻層，並透過第五光罩製 20 1299905 程S150選擇性地移除第五光阻層，以形成用於定義連接沒極和晝 素電極的接觸孔的第五光阻圖案(圖未示）。 如第6K圖所示，可透過第五光阻圖案(圖未示)作為光罩選擇 性地移除鈍化層⑽和位於其下方_極絕緣層m，以形成用於 暴露晝素部份的第—難155b的鈍化層接觸孔193。紐，移除 第五光阻圖案(圖未示）。 、In the formation of painting her, the sixth erqing _ in the formation of a halogen electrode connected to the 汲 pure domain through the contact hole of the halogen element. Hereinafter, the driving circuit portion of the six-pass mask process and the pixel portion (four)_crystal of the present invention will be described in accordance with the method of manufacturing the liquid crystal display device from 6A to 6K, and the insulating material such as the insulating material will be A dioxant (worm) is deposited on the entire surface of the transparent insulating substrate m to form a buffer layer 125. Amorphous stone a-S1 is deposited on the entire surface of the substrate m on which the buffer layer 125 is formed. Then, 1299905 rows of amorphous wires are processed, and then the post-Shenzhen Shenjing (10) crystallization process is performed to crystallize the amorphous dream layer into the polycrystalline layer 130. As shown in FIG. 6B, the first photoresist layer is deposited on the multi-small shovel through the first-mask process sno to selectively pattern it, and is used for Wu Lu = part of the polycrystalline stone M uo The first photoresist pattern 135. In the first process, the first photoresist pattern 135 remains in the partial region of the halogen! All the second thin films of the _ road portion are electrically formed: the intermediate electrode of the third thin film transistor region m is formed. The upper region and the driving circuit portion are then passed through the 35th as a fresh, and the polysilicon layer 130 of the driving circuit portion of the film transistor region m is etched into a thick-resist pattern 135. Then, as shown in the second redundancy mode, the second photoresist layer is formed in the polycrystalline mask process (4) to form the second photoresist layer for the second light gate. Red light _ Chi can be all her p-type: thin film electric 曰 枝 m m β Γ Γ 驱动 驱动 驱动 驱动 驱动 驱动 _ _ _ 第 的 第 的 的 _ _ _ _ _ _ _ _ _ _ _ _ _ _ 的 的Part of the n-type second =: the gate formation region of the body region II. —Electric Electrode Next, the second photoresist pattern 14 is used as a light doping impurity for the ytterbium type impurity. , Yangshuo 130 for η+ as shown in the milk map, through the ashing process must be 140, and the polycrystalline stone layer (10) η-type hybrid degree of the first photoresist pattern Miscellaneous New Area 18 1299905 domain. The ashed second photoresist pattern 14〇a is then removed. As shown in Fig. 6E, after the impurity doping process, the source/heteroconductive layer W5 is deposited on the entire surface of the substrate 12A. Next, a second photoresist layer is deposited on the conductive layer 145. The mura defines a active region and a source/secret region by using a third mask process 8130 side-side third photoresist layer using a diffractive pattern mask to form a third photoresist pattern 15(). When the diffractive pattern is used as the reticle exposure S third photoresist layer, the third photoresist after the diffractive exposure is not fully exposed, and thus only the exposed preset thickness is developed in the subsequent development process. That is to say, the diffractive exposure does not completely expose the third photoresist, but only a partial exposure, because the optical transmission rate of the exposed portion of the diffraction pattern is smaller than that of the fully exposed photoresist portion. Thus, as shown in Fig. 6E, when the third photoresist after the diffraction exposure is developed, only the photoresist of a predetermined thickness is developed as compared with the unexposed photoresist. That is, during the diffraction exposure, the path areas of the first, second, and third elements are exposed to a greater extent than the source and drain regions. As shown in Fig. 6F, the conductive layer 145 and the polysilicon layer 13 are selectively etched using the third photoresist pattern 150 as a mask to define the source/drain regions and the active regions. As shown in Fig. 6G, a third photoresist pattern 150 of a certain thickness is removed by an ashing process to expose a central portion of the top of the conductive layer 145. As shown in FIG. 6H, the etched third photoresist pattern 15A (refer to FIG. 19 1299905 6G) is used as a photomask to selectively remove the conductive layer 145 to form a first source of the halogen portion. The pole/bungee 155a, 155b' and the crane circuit part (4) the two source A and the extremely dirty, 160b' and the third source/drain brain of the drive circuit portion, π%. The ashed third photoresist pattern 15〇a is then removed. As shown in FIG. 61, 'the oxidized stone Xixi 2 can be deposited on the entire surface of the substrate to form the gate insulating layer 17G, and the substrate at this time includes the first source/drain 155a of the halogen portion, L55b and the second source of the driver circuit and the extreme source, the secret, and the third source/drain (10) of the driver circuit. Then, the gate insulating layer 'is activated, and can be deposited on the gate insulating layer 17〇, such as 翻 (M〇), Ming (A1), 聚化铭(a wrist) '(9), u) or 鵁W. And depositing a fourth photoresist layer on the conductive material. The fourth photoresist layer can be selectively removed through the fourth mask process S140 to form a fourth photoresist pattern (not shown) for defining the gate. First, as shown in Fig. 61, the conductive material can be shaped as a mask through a fourth photoresist pattern (not shown) to form gate electrodes 5, 18G and 185. Next, the fourth photoresist pattern (not shown) is removed. As shown in Fig. 6J, an insulating material is deposited on the entire surface including the gates 175, 180, and 185, the plate to form a passivation layer 190. The insulating material may be used to make one or more domain materials, such as bismuth (SiQ2) or stellite (SiNx), and/or -3, organic materials such as benzocyclobutene or acrylic tree . Next, the passivation layer 190 is subjected to a thermal nitridation process. Second, the following: a fifth photoresist layer is deposited on the passivation layer 190, and the fifth photoresist layer is selectively removed through the fifth mask 201299905, S150 to form a connection for defining the junction and the halogen. A fifth photoresist pattern of the contact hole of the electrode (not shown). As shown in FIG. 6K, the passivation layer (10) and the underlying insulating layer m are selectively removed as a mask through a fifth photoresist pattern (not shown) to form a portion for exposing the element. The passivation layer of the first-difficult 155b contact hole 193. New, remove the fifth photoresist pattern (not shown). ,
接下來可將如氧化銦錫(ITO)或氧化鋅錫(IZO)的透明導電材 料沉積在形成有純化層携的基板12σ的整個表面上。可將第六 光阻層沉積在氧化銦錫層上，並透過第六光罩製程_將盆形成 第六光阻圖案(圖未示)，並以第六光阻圖案(圖未示)作為光罩選擇 性地移除氧化銦錫層，以形成與第—汲極155b連接的晝素電極 195。此後，移除第六光阻圖案(圖未示）。 第7A圖至第7K圖所不為本發明另一實施例之製造晝素部份 的開關7L件以及製造驅動電路部份的具有互補金屬氧化物半導 結構的薄膜電晶體的方法的剖面圖。 、* 7Α圖所不’將如二氧切Si02的無觀緣材料沉稽 透明絕緣的基板220的整個表面上，以形成緩衝層奶。將非晶 卜&沉積在形成有緩衝層225的基板22〇的整個表面上。^ 了的脫氣製程。舆第—實施例不同的是 在脫虱製錢立即進行非㈣魏結晶触。 如第7B圖所示’將第一先阻層沉積在非晶石夕層230上，並』 1299905 過第-光單製程咖選 份非晶矽層230 ^^成圖案’以形成用於暴露部 時，第—235。在進行第一光罩製程_ 區域留在晝素部份的所有第—_電晶體 二，部份的所有第二薄膜電晶體區域π和驅動電二 弟-相電晶髓區域m的閘極形成區域上。 ° 型第先阻圖案235作為先罩’_電路部份的p 然後移除第-光阻圖案235。 雜 料冗_示，將第二光阻層沉積在物層现 2trr纖㈣：_咖蝴部份物層 的所右弟7?阻圖案240。第二光阻圖案240可遮蔽驅動電路部份 膜電晶體區域m、畫素區域的第—薄 區域工的閘極形成區域，以及驅動電路部份的n型第二薄膜電= f或11的·形成區域。可使用第二光阻圖案作為光^非 晶發層230進行n+型雜質摻雜。 如第7D圖所示，透過灰化製程姓刻一定厚度的第二光阻圖案 240 ’亚對非晶石夕層23〇進行n-型雜質摻雜以形成輕接雜汲極區 域。接著移除灰化後的第二光_案織，並透過雷射結晶製程 將非晶石夕層230結晶為多晶石夕層。 如第7E目所示’在雜質摻雜製程後，將源極力及極導電層 245沉積在基板22〇的整個表面上。接著，將第三光阻沉積在導電 22 1299905 層245上，並透過使用繞射圖案光罩的第三光罩製程姓刻部 份第三光阻，以定義主動區域和源極/汲極區域，進而形成第三 光阻圖案250。當使用繞射圖案作為光罩曝光第三光阻時，繞射曝 光後的苐二光阻並未被元全曝光’在後續的顯影製程中也僅對已 曝光的預設厚度進行顯影。就是說，繞射曝光後的第三光阻並未 被完全曝光，而只是被部份曝光，這是因為繞射圖案曝光區域的 光傳輸率小於完全曝光的光阻部份的光傳輸率。因而，如第7E圖 所示，當對繞射曝光後的第三光阻進行顯影時，與未曝光的光阻 相比，僅有預設厚度的光阻被顯影。就是說，在繞射曝光過程中， 第一、第二和第三元件的通路區域的曝光程度大於源極和汲極區 域。 如第7F圖所示，導電層245和多晶矽層230a均透過第三光 阻圖案250作為光罩被選擇性地钕刻，以定義源極/汲極區域和 主動區域。 如第7G圖所示，透過灰化製程移除一定厚度的第三光阻圖案 25〇，以暴露導電層245頂部的中央部份。 如第7H圖所*，透過灰化後的第三光關案織（參照第 冗圖）作為光罩選擇性地移除導電層μ5，以形成晝素部份的第 一源極/汲極255a ' 255b，和驅動電路部份的第二源極/汲極 a、260b，以及驅動電路部份的第三源極/汲極2孤、2娜。 接著，移除第三光阻250a。 23 1299905 如第π圖所示’可將如二氧化石夕Si〇2的絕緣層沉積在基板 220的整個表面上以形成閘極絕緣層27〇，此時的基板创包含苎 素部份的第i極/_55a、255b，和_路部份的第二二 極/錄2⑹a、26Gb，以及鶴電路部份的第三源極/汲極施、 265b。與第-實施例不同’本實施例中形成_絕緣層挪後不 立即進行活化製程。 接著，將如鉬陶、雖!）、歛化銘(A1Nd)、絡(Cr)、銅(cu) 或鶴(w爾電金屬沉積在閘極絕緣層27〇上，並將第四光阻層沉 積在導電材料上。可透過細光罩製程⑽選擇性地移除第四光 阻，以形成用於定義閘極的第四光阻圖案(圖未示）。 如第π圖所示，可透過第四光阻圖案(圖未示)作為光罩將導 電材料形成圖案，以形成閑極275、28〇和285。接著，移除第四 光阻圖案(圖未示）。 如第7J圖所示，將絕緣材料沉積在包含閘極275、28〇和285 的基板220的整個表面上，以形成鈍化層29〇。絕緣材料可包含一 種或多種無機材料如二氧化矽(Si〇2)或氮化矽(SiNx)，和/或一種 或多種有機材料如苯並環丁烯(Benz〇cycl〇butene)或壓克力樹脂。 接著，對鈍化層290進行熱氫化製程。 然後’在鈍化層290上沉積第五光阻層，並透過第五光罩製 程S150選擇性地移除第五光阻層，以形成用於定義連接汲極和晝 素電極的接觸孔的第五光阻圖案(圖未示)。 24 1299905 如第7K圖所不，可透過第五光阻圖案(圖未示)作為光罩選擇 =私除鈍化層’和位於其下方的_絕緣層27q，以形成用於 =路旦素精的第一沒極255b的純化層接觸孔观。然後，移除 第五光阻圖案(圖未示）。 、、接下來可將如氧化錮錫(IT〇试氧化鋅錫(IZ〇)的透明導電材 料/儿積在鈍化層’上的純化層接觸孔別形成區域。可將第六 光阻沉積在祕_層上，錢過第六鮮製㈣60形成第六光 阻圖_未示）。料六光_細未稱為鮮選擇性地移除 乳化銦錫層，以形成連·—汲極挪的畫素雜B。此後， 移除第六光阻圖案(圖未示）。 第8A圖至第8K圖所示為本發明另一實施例之製造晝素部份 的開關兀件以及製造驅動電路部份的具有互補金屬氧化物半導體 、、Ό構的薄膜電晶體的方法的剖面圖。 如第8Α圖所示，將無機絕緣體如二氧化石夕(沉積 絕緣的基板卿整個表面上，以形成緩衝層奶。將非晶石夕a_ SU冗積在形成有緩衝層325的基板32〇的整個表面上。然後進行 非晶石夕的脫氫製程，但脫氫製程後不立即進行非晶石爾射結晶 製程。 如第8B圖所示，將第一光阻層沉積在非晶石夕層330上，並透 過^光罩製程sn鳴性地將其形成_，以形成用於暴露部 伤非晶梦層330的第-光阻圖案335。在進行第—光罩製程卿 25 1299905 時，第—光㈣案切仍殘留在畫素部 第 师、驅動電路部份的所有第二薄膜 二•電晶體 份的第三薄膜電晶體區域in的閉極形成區域上。嘴動電路部 接著’以第-光阻圖案335作為光罩，對 型第三_晶體 路=的p 後移除第-光阻圖案335。 雜貝摻雜。然 所示’將第二光阻層沉積在非晶梦層现上 透過弟一光罩製程Sl2〇將第— 者 f 1 軸用於暴露部份非晶石夕声 330的弟二光阻圖案340。第二光阻圖請可遮蔽驅動電路4: 的所有Ρ型第三薄膜電晶體區域瓜、畫素區域的第 區域1的閘極形顧爾鶴魏獅哺：_3 _的__區域，’陳紐__作為== 非晶矽層330進行n+型雜質摻雜。 口如第8D圖所示，移除第二光阻圖案34〇，並進行雷射結晶製 程以將非晶矽層330結晶為多晶矽層。 如第8E圖所示，在雷射結晶製程後，將源極力及極導電層 345沉積在基板320的整個表面上。沉積第三光阻層在導電層泌 上’並透過使用繞射圖案光罩的第三光罩製程⑽細部份第三 光阻，以定義主動區域和源極/汲極區域，進而形成第三光阻圖 案35〇。當使用繞賴案作為光罩曝光第三光阻時，繞射曝光後的 第三光阻並未被完全曝光’在__影製程巾僅對已曝光的預 26 1299905 吞又厗度進仃顯影。就是說，繞 Η 、兀射曝先的弟三光阻並未完全曝光， 而只疋部份曝光，這是因為縝 %于圖木曝光區域的光傳輸率小於完 全曝光的光阻部份的光傳輪率。— 旱口而，如弟8Ε圖所示，當對繞射 曝光後的弟三光阻進行顯旦^ 士 '、、、心寸/、未曝光的光阻相比，僅有預設 〔旱度的光阻被顯影。就是說，在繞射曝光過程中，第…第二和 第三兀件的通路區域的曝光程度大於源極和祕區域。 如第8F圖所示，導電層祕和多晶石夕層3施均以第三光阻 圖案350作為光罩被選摆峰从 ^早I擇地烟，以定義源極/汲極區域和主 動區域。 如第犯圖所示，透過灰化製程移除一定厚度的第三光阻圖案 350以暴4導電層345頂部的中央部份。 如第8Η圖所不’使用灰化後的第三光阻圖案(參照第 犯圖）作為光罩選擇性地移除導電層345，以形成畫素部份的第 -源極/没極355a、355b，和驅動電路部份的第二源極/汲極 360a、36Gb，以及驅動電路部份的第三源極/汲極施、獅。 然後移除第三光阻圖案350a。 如第81圖所不’可將如二氧化梦Si〇2絕緣層沉積在基板娜 的整個表面上以形成陳絕緣層37()，此時的基板挪包含晝素部 份的第-源極/汲極355a、355b，和驅動電路部份的第二源極/ 沒極360a、鳩，以及驅動電路部份的第三源極力及極麻、 365b t成閘極絕緣層370後並不立即進行閘極、絕緣層37〇的活 27 1299905 化製程。 將如_。)、_)、鈥化__、鉻⑼、鋼㈣或鶴㈤ 的導電金屬沉積在閘極絕緣層37〇上，並將第四光阻層沉積在導 電材料上。可透過第四光罩製程灿〇選擇性地移除第四光阻層， 以形成用於絲_的第四細_(縣示）。可透過細光關 案(圖未示)作為光罩將導電材料形成圖案，以形成閘極375、380 、接著私除第四光阻圖案(圖未示）。透過間極375、38〇、 385作為光罩對多曰曰曰石夕層施進行n型雜質摻雜，以形成自動配 向的輕摻雜汲極區域387。 第8J圖所示，將絕緣材料沉積在包含閘極3⑽和3% 的基板320的整個表面上，以形成鈍化層·。絕緣材料可包含一 種或多種域材料，如二氧切卿2)或統梦(SiNx) ，和/或一 種或多種有機材料，如苯並環丁烯(Ben·———或壓克力樹 脂。接著，對鈍化層39〇進行熱氫化製程。 後，在鈍化層390上沉積第五光阻層，並透過第五光罩製 転Sl5〇選擇性地移除第五光阻層，以形成用於定義連接沒極和畫 素電極的接觸孔的第五光阻圖案(圖未示）。 如第8K圖所示，可透過第五光阻圖案(圖未示)作為光罩選擇 f生地私除鈍化層39〇和位於其下方的閘極絕緣層37〇,以形成用於 恭路旦素邛知的第一汲極355b的鈍化層接觸孔。然後，移除 第五光阻圖案(圖未示）。 28 1299905 、；接下來可將如氧化銦錫(ITO)或氧化鋅錫(IZO)的透明導電材 π L積在鈍化層390的鈍化層接觸孔393區域上。可將第六光阻 二知在氧化鱗層上，並透過第六光罩製程§ι㈣彡成第六光阻 θ卞(圖未不）。以第六光阻圖案(圖未示)作為光罩選擇性地移除氧 化銦錫層，以形成與第一汲極通連接的晝素電極395。此後， 移除第六光阻圖案(圖未示）。 如上所述，在本發明製造液晶顯示裝置的薄膜電晶體的方法 中’透過繞射曝光而侧主動區域和源極力及極區域，並藉由光 =灰化製_成轉雜祕相及省緣層_程，將先 讀術的八次群製雜減為六次鮮製程，縮減了製程次數。 =本發咖祕之較姆_縣如上，然其並非用以限 : 任何熟1相像技藝者，在不聰本發明之精神和範圍 :可作麵之更動與潤飾，因此本發权專·護範圍須視 本說明書_之中請專·_界定者騎。、 【圖式簡單說明】 驅動電路的液晶顯示裝 置的示意 第1圖為先前技術形成具有 圖； 第2圖為先前技術畫素部份的開關元件及具有 〆 物+導體結構的驅動電路的薄膜電晶體的剖面圖.〃乳化 第3圖為先前技賴_裝置中驅動電路部份的具有互補 29 1299905 第圖至第4H圖分別為先前技術驅動電路部份的具右 氧編繼綱軸關元件 程的剖面圖 補 的製 弟5、圖為本發日嶋具有頂端_罐的晝素部份的開關元 件以及製造驅動電路部份的 補金屬虱化物+導體結構的薄 膜電晶體的方法中光罩製程的流程圖； 霉1潯 *第从嶋⑽竭本侧造晝素部份的簡元件以 及衣造驅動電路部份的具有互補金屬氧化物半導體 晶體的剖賴； 电 第7A圖至第7K圖分別為本發明另一實施例之製造書素部份 的開關元件以及製造驅_路部份的具有互補金屬氧化物半導體 結構的薄膜電晶體的方法的剖面圖；及 _ 第8Α圖至第8Κ圖分別為本發明另一實施例之製造晝素部份 的開關元件以及製造驅動電路部份的具有互補金屬氧化物半導體 結構的薄膜電晶體的方法的剖面圖。 【主要元件符號說明】 卜 20、120、220、320 3 基板 晝素部分 驅動電路 30 5 1299905Next, a transparent conductive material such as indium tin oxide (ITO) or zinc tin oxide (IZO) may be deposited on the entire surface of the substrate 12? on which the purification layer is formed. The sixth photoresist layer may be deposited on the indium tin oxide layer and passed through the sixth mask process to form a sixth photoresist pattern (not shown) and a sixth photoresist pattern (not shown). The photomask selectively removes the indium tin oxide layer to form a halogen electrode 195 connected to the first drain 155b. Thereafter, the sixth photoresist pattern (not shown) is removed. 7A to 7K are cross-sectional views showing a method of manufacturing a halogen portion of a switch 7L and a method of manufacturing a driving circuit portion of a thin film transistor having a complementary metal oxide semiconductor structure according to another embodiment of the present invention. . , * 7 Α 所 ’ 将 ’ ’ 如 Si Si 02 Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si Si 。 。 。 。 。 。 。 。 。 。 。 。 An amorphous wafer & is deposited on the entire surface of the substrate 22 on which the buffer layer 225 is formed. ^ The degassing process. The difference between the first and the first embodiment is that the non-fourth crystallization touch is immediately carried out in the production of dislocation. As shown in FIG. 7B, 'the first first resist layer is deposited on the amorphous slab layer 230, and the 1299905 is over-patterned to form an amorphous enamel layer 230' to form a pattern for exposure. Ministry Department, No. -235. In the first mask process _ region, all the first------the second crystal-crystal region, the portion of all the second thin-film transistor region π and the gate of the electro-secondary-phase electromorphic region m Formed on the area. The ° type first resistance pattern 235 serves as the p of the first mask '_circuit portion and then removes the first photoresist pattern 235. The cumbersome material indicates that the second photoresist layer is deposited on the object layer 2trr fiber (4): the right side of the layer of the material layer. The second photoresist pattern 240 can shield the portion of the film transistor region of the driver circuit, the gate formation region of the first thin region of the pixel region, and the n-type second film of the driver circuit portion = f or 11 · Form an area. The n + -type impurity doping may be performed using the second photoresist pattern as the optical non-crystal layer 230. As shown in Fig. 7D, the second photoresist pattern 240' of a certain thickness is etched through the ashing process to submerge the amorphous enamel layer 23' to form a light-bonded drain region. Next, the ashed second light is removed, and the amorphous glazed layer 230 is crystallized into a polycrystalline layer by a laser crystallization process. As shown in Fig. 7E, after the impurity doping process, source and electrode conductive layers 245 are deposited on the entire surface of the substrate 22A. Next, a third photoresist is deposited on the conductive layer 12 1299905 layer 245, and a third portion of the third photoresist is processed through the third mask process using the diffraction pattern mask to define the active region and the source/drain regions. Further, a third photoresist pattern 250 is formed. When the diffractive pattern is used as the reticle to expose the third photoresist, the diffractive bismuth resist is not fully exposed by exposure. In the subsequent development process, only the exposed preset thickness is developed. That is, the third photoresist after the diffraction exposure is not completely exposed, but is partially exposed because the light transmission rate of the exposed portion of the diffraction pattern is smaller than the light transmission rate of the photoresist portion of the full exposure. Thus, as shown in Fig. 7E, when the third photoresist after the diffraction exposure is developed, only the photoresist of a predetermined thickness is developed as compared with the unexposed photoresist. That is, during the diffraction exposure, the path areas of the first, second, and third elements are exposed to a greater extent than the source and drain regions. As shown in Fig. 7F, the conductive layer 245 and the polysilicon layer 230a are selectively etched through the third photoresist pattern 250 as a mask to define a source/drain region and an active region. As shown in Fig. 7G, a third photoresist pattern 25A of a certain thickness is removed through the ashing process to expose the central portion of the top of the conductive layer 245. As shown in FIG. 7H, the conductive layer μ5 is selectively removed as a mask by the ashed third light-cut (refer to the redundancy diagram) to form the first source/drain of the halogen portion 255a '255b, and the second source/drain a, 260b of the driver circuit portion, and the third source/drain 2 of the driver circuit portion are 2, 2 nano. Next, the third photoresist 250a is removed. 23 1299905 As shown in FIG. π, an insulating layer such as SiO 2 may be deposited on the entire surface of the substrate 220 to form a gate insulating layer 27, at which time the substrate includes a halogen portion. The i-th pole/_55a, 255b, and the second diode/record 2(6)a, 26Gb of the _road portion, and the third source/drain gate 265b of the crane circuit portion. Unlike the first embodiment, the activation process is not immediately performed after the formation of the insulating layer in the present embodiment. Next, a molybdenum ceramic, although!), acupuncture (A1Nd), a complex (Cr), a copper (cu) or a crane (wur metal is deposited on the gate insulating layer 27〇, and the fourth photoresist a layer is deposited on the conductive material. The fourth photoresist is selectively removed through the thin mask process (10) to form a fourth photoresist pattern (not shown) for defining the gate. As shown in FIG. The conductive material may be patterned by using a fourth photoresist pattern (not shown) as a photomask to form the idle electrodes 275, 28A and 285. Then, the fourth photoresist pattern (not shown) is removed. As shown, an insulating material is deposited over the entire surface of the substrate 220 including the gates 275, 28A and 285 to form a passivation layer 29. The insulating material may comprise one or more inorganic materials such as hafnium oxide (Si〇2). Or yttrium nitride (SiNx), and/or one or more organic materials such as benzocyclobutene or acryl resin. Next, the passivation layer 290 is subjected to a thermal hydrogenation process. A fifth photoresist layer is deposited on the passivation layer 290, and the fifth photoresist layer is selectively removed through the fifth mask process S150 to form a definition The fifth photoresist pattern (not shown) of the contact hole of the drain electrode and the halogen electrode. 24 1299905 As shown in Fig. 7K, the fifth photoresist pattern (not shown) can be used as a mask selection = private The passivation layer 'and the underlying insulating layer 27q are formed to form a purification layer contact hole view for the first gate 255b of the phlo sulphate. Then, the fifth photoresist pattern (not shown) is removed. Then, a purification layer such as a tantalum tin oxide (IT 〇 氧化 氧化 的 的 的 的 / / / / 在 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 接触 纯化 纯化 纯化 纯化 纯化 纯化 纯化 纯化 纯化 纯化 纯化 纯化On the secret _ layer, the money is over the sixth fresh system (four) 60 to form the sixth photoresist pattern _ not shown. The material six light _ fine is not known to freshly selectively remove the emulsified indium tin layer to form a joint · 汲 挪The picture is abbreviated B. Thereafter, the sixth photoresist pattern (not shown) is removed. Figures 8A to 8K illustrate a switch element for manufacturing a halogen component and manufacturing drive according to another embodiment of the present invention. A cross-sectional view of a method of a circuit portion having a complementary metal oxide semiconductor, a thin film transistor, as shown in Fig. 8 Such as a dioxide stone (depositing the insulating substrate on the entire surface to form a buffer layer of milk. Amorphous austenite a_SU is accumulated on the entire surface of the substrate 32 formed with the buffer layer 325. Then amorphous The dehydrogenation process, but the amorphous stone crystallization process is not performed immediately after the dehydrogenation process. As shown in Fig. 8B, the first photoresist layer is deposited on the amorphous layer 330 and passed through the mask. The process sn is formed into a sensation to form a first photoresist pattern 335 for exposing the portion of the amorphous dream layer 330. When the first photomask process 25 1299905 is performed, the first light (four) case remains. In the closed-form formation region of the third thin film transistor region in of the second thin film two-electrode portion of the pixel portion of the pixel portion. The nozzle circuit portion then removes the first photoresist pattern 335 by using the first photoresist pattern 335 as a photomask and the third type _ crystal path = p. Miscellaneous doping. However, the deposition of the second photoresist layer on the amorphous layer is now used to expose the second photoresist pattern of the amorphous Aussie 330 through the reticle process Sl2. 340. The second photoresist diagram may be shielded from all of the 第三-type third thin-film transistor regions of the drive circuit 4: the gate of the region 1 of the pixel region, the gate-shaped Gu Erhe Wei Shi, the __ region of the _3 _, ' Chen New__ is doped with n+ type impurity as the == amorphous germanium layer 330. As shown in Fig. 8D, the second photoresist pattern 34 is removed, and a laser crystallization process is performed to crystallize the amorphous germanium layer 330 into a polysilicon layer. As shown in Fig. 8E, after the laser crystallization process, source and electrode conductive layers 345 are deposited on the entire surface of the substrate 320. Depositing a third photoresist layer on the conductive layer and transmitting a third portion of the third photoresist through the third mask process (10) of the diffraction pattern mask to define an active region and a source/drain region, thereby forming a The three photoresist pattern is 35 〇. When the third photoresist is exposed as a reticle, the third photoresist after the diffractive exposure is not fully exposed. development. That is to say, the three photoresists of the Η and 兀 exposures are not fully exposed, but only part of the exposure, because 缜% of the light in the exposed area of the wood is less than the light of the fully exposed photoresist. Transfer rate. — The dry mouth, as shown in the figure of the 8th, when the diffraction of the third light resisted by the diffractive exposure is compared with the light resistance of the sensation, ',, and/or unexposed, only the preset [dryness] The photoresist is developed. That is, during the diffraction exposure, the passage areas of the second and third members are exposed to a greater extent than the source and the secret areas. As shown in FIG. 8F, both the conductive layer and the polycrystalline layer 3 are selected as the reticle with the third photoresist pattern 350 as the reticle, and the source/drain region is defined. Active area. As shown in the first figure, a third photoresist pattern 350 of a certain thickness is removed by the ashing process to blast the central portion of the top of the conductive layer 345. As shown in FIG. 8 , the third photoresist pattern (refer to the first map) after ashing is used as a mask to selectively remove the conductive layer 345 to form the first source/drain 355a of the pixel portion. 355b, and the second source/drain electrodes 360a, 36Gb of the driver circuit portion, and the third source/drain electrode of the driver circuit portion. The third photoresist pattern 350a is then removed. As shown in FIG. 81, an insulating layer such as a SiO2 insulating layer can be deposited on the entire surface of the substrate to form an insulating layer 37 (), and the substrate is transferred to the first source of the halogen portion. / bungee 355a, 355b, and the second source/dot pole 360a, 鸠 of the driver circuit portion, and the third source force and the pole of the driver circuit portion, 365b t become the gate insulating layer 370 is not immediately The process of the gate and the insulating layer 37〇 is carried out. Will be like _. The conductive metal of _), 鈥___, chrome (9), steel (four) or crane (five) is deposited on the gate insulating layer 37, and the fourth photoresist layer is deposited on the conductive material. The fourth photoresist layer can be selectively removed through the fourth photomask process to form a fourth thinner (counter) for the wire. The conductive material may be patterned as a photomask by a fine light (not shown) to form gates 375, 380, and then a fourth photoresist pattern (not shown). An n-type impurity doping is applied to the polysilicon layer through the interpoles 375, 38A, and 385 as a mask to form an auto-aligned lightly doped drain region 387. As shown in Fig. 8J, an insulating material is deposited on the entire surface of the substrate 320 including the gate 3 (10) and 3% to form a passivation layer. The insulating material may comprise one or more domain materials such as dioxin 2) or SiNx, and/or one or more organic materials such as benzocyclobutene (Ben·- or acrylic resin) Then, the passivation layer 39 is subjected to a thermal hydrogenation process. Thereafter, a fifth photoresist layer is deposited on the passivation layer 390, and the fifth photoresist layer is selectively removed through the fifth mask to form a fifth photoresist layer. a fifth photoresist pattern (not shown) for defining a contact hole connecting the electrodeless electrode and the pixel electrode. As shown in FIG. 8K, the fifth photoresist pattern (not shown) can be used as a mask to select a habitat. The passivation layer 39A and the gate insulating layer 37〇 underneath are privately formed to form a passivation layer contact hole for the first drain 355b known as the gongluan. Then, the fifth photoresist pattern is removed ( 28 1299905; Next, a transparent conductive material such as indium tin oxide (ITO) or zinc tin oxide (IZO) may be accumulated on the passivation layer contact hole 393 of the passivation layer 390. Six photoresists are known to be on the oxidized scale layer, and through the sixth mask process §ι (4) into a sixth photoresist θ 卞 (not shown). A resist pattern (not shown) selectively removes the indium tin oxide layer as a photomask to form a halogen electrode 395 that is connected to the first drain. Thereafter, the sixth photoresist pattern (not shown) is removed. As described above, in the method for manufacturing a thin film transistor of a liquid crystal display device of the present invention, 'the side active region and the source and the polar region are transmitted through the diffraction exposure, and the light is reduced by the light=ashing process. The edge layer _ Cheng, the first reading of the eight-time group system is reduced to six fresh processes, reducing the number of processes. = The secret of the hair _ _ county as above, but it is not limited to: Any cooked 1 like Artists, in the spirit and scope of the invention: can be used for face-to-face changes and retouching, so the scope of this special rights and protection must be based on this manual _ special _ defined by the ride., [Simple description Fig. 1 is a schematic view showing a prior art of a liquid crystal display device of a driving circuit. Fig. 2 is a cross-sectional view showing a switching element of a prior art pixel portion and a thin film transistor having a driving circuit of a material + conductor structure. 〃Emulsification Figure 3 shows the part of the driver circuit in the previous technology Complementary 29 1299905 Fig. 4th to Fig. 4H respectively show the cross-sectional view of the part of the prior art drive circuit with the right oxime relay axis component path. A flow chart process for a portion of the switching element and a method for fabricating a thin film transistor of a metal-filled germanide + conductor structure for a driver circuit portion; a mold 1 浔 第 10 (10) The simplified element and the complementary metal oxide semiconductor crystal of the manufacturing circuit portion; the electric 7A to 7K are respectively the switching element for manufacturing the pixel portion and the manufacturing drive according to another embodiment of the present invention. a cross-sectional view of a method of forming a thin film transistor having a complementary metal oxide semiconductor structure; and FIGS. 8 to 8 are respectively a switching element for fabricating a halogen component according to another embodiment of the present invention and manufacturing thereof A cross-sectional view of a method of driving a portion of a thin film transistor having a complementary metal oxide semiconductor structure. [Description of main component symbols] Bu 20, 120, 220, 320 3 Substrate Alizarin part Drive circuit 30 5 1299905
5a 閘極驅動電路 5b 資料驅動電路 7 閘極線 9 資料線 10、97、195、295、395 晝素電極 P 晝素區域 T 薄膜電晶體 12 外部信號輸入終端 30、35、40 半導體層 25、125、225、325 緩衝層 30b、35b、40b 輕摻雜没極層 30c、35c、40c 歐姆接觸層 30a、35a、40a 主動層 62、63、65 光阻圖案 45、170、270、370 閘極絕緣層 50、55、60、175、180、185、275 、280、285、375、380、385 閘極 70 中間絕緣層 90b 没極 73a、73b、75a、75b、77a、77b 半導體層接觸孔 80a、83a、87a 源極 31 12999055a gate drive circuit 5b data drive circuit 7 gate line 9 data line 10, 97, 195, 295, 395 pixel electrode P halogen region T thin film transistor 12 external signal input terminal 30, 35, 40 semiconductor layer 25, 125, 225, 325 buffer layer 30b, 35b, 40b lightly doped gate layer 30c, 35c, 40c ohmic contact layer 30a, 35a, 40a active layer 62, 63, 65 photoresist pattern 45, 170, 270, 370 gate Insulating layer 50, 55, 60, 175, 180, 185, 275, 280, 285, 375, 380, 385 Gate 70 Intermediate insulating layer 90b No poles 73a, 73b, 75a, 75b, 77a, 77b Semiconductor layer contact hole 80a , 83a, 87a source 31 1299905
80b、83b、87b 没極 155a、155b、255a、255b、355a、355b 第一源極/汲極 160a、160b、260a、260b、360a、360b 第二源極/汲極 165a、165b、265a、265b、365a、365b 第三源極/;及極 90、190、290、390 鈍化層 95 汲極接觸孔 130、230a、330a 多晶秒層 135、235、335 第一光阻圖案 140、140a、240、240a、340 第二光阻圖案 145、245、345 導電層 150、150a、250、250a、350、350a 第三光阻圖案 193、293、393 鈍化層接觸孔 230、330 非晶秒層 387 輕摻雜汲極區域 I 弟'一薄膜電晶體區域 Π 第二薄膜電晶體區域 m 弟二薄膜電晶體區域 S10 第一光罩製程(形成半導體層) S20 第二光罩製程製程(形成閘極) S30 第三光罩製程(n+型摻雜） 32 129990580b, 83b, 87b poleless 155a, 155b, 255a, 255b, 355a, 355b first source/drain 160a, 160b, 260a, 260b, 360a, 360b second source/drain 165a, 165b, 265a, 265b , 365a, 365b third source/; and pole 90, 190, 290, 390 passivation layer 95 drain contact hole 130, 230a, 330a polymorph layer 135, 235, 335 first photoresist pattern 140, 140a, 240 240a, 340 second photoresist pattern 145, 245, 345 conductive layer 150, 150a, 250, 250a, 350, 350a third photoresist pattern 193, 293, 393 passivation layer contact hole 230, 330 amorphous second layer 387 light Doping the drain region I, a thin film transistor region, the second thin film transistor region, m, the second thin film transistor region, S10, the first mask process (forming the semiconductor layer), S20, the second mask process (forming the gate) S30 third mask process (n+ type doping) 32 1299905
S40 第四光罩製程(p+型摻雜） S50 第五光罩製程(形成源極/汲極接觸） S60 第六光罩製程(形成源極和汲極） S70 第七光罩製程(形成鈍化層接觸） S80 第八光罩製程(形成晝素電極） S110 第一光罩製程(P+型摻雜） S120 第二光罩製程(n+型摻雜） S130 第三光罩製程(形成源極/>及極區域和主動區域) S140 第四光罩製程(形成閘極） S150 第五光罩製程(形成晝素接觸） S160 第六光罩製程（形成晝素電極）S40 Fourth mask process (p+ doping) S50 Fifth mask process (formation of source/drain contact) S60 Sixth mask process (formation of source and drain) S70 Seventh mask process (formation passivation) Layer contact) S80 Eighth mask process (formation of halogen electrode) S110 First mask process (P+ type doping) S120 Second mask process (n+ type doping) S130 Third mask process (formation source / > and polar region and active region) S140 Fourth mask process (formation of gate) S150 Fifth mask process (formation of halogen contact) S160 Sixth mask process (formation of halogen electrodes)
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