TWI297500B - Multi-level-cell programming methods of non-volatile memories - Google Patents

Description

1297500 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種電子資料儲存襄 上MLC)記舰裡-㈣姉叫元時__作壽命的方 【先前技術】 (EEPROM) 為主之電子可程式可抹除非揮發技 應麟許多現代贿上。快閃記㈣設計成可以單獨程 體單元陣列。快閃記憶體内的感測放大器係用 制裡疋、1二=發性纖體内之=#料或數值。在典型的感測機 狀嫌鮮㈣魏係m制放大器與 ^多記憶體單元結構可以用來作為邱簡職快閃記憶體。 電，來越小，以電荷捕捉介電層為主之記憶體單元結 =製程簡單崎來越受到青睞。記_單元結構藉由捕捉電 =、1站捉介電層内，例如氮化销内的方式來儲存資料。當負電 =、捉時’魏、體單元之起始輯會增加。記,It鮮元之起始 電壓2藉由從電荷捕捉層移除負電荷的方式來降低。 請參考第一圖，其係繪示一種傳統多單元程式化方法100，該 法係依序％式化具四個位元之氮化物捕捉記憶體單元的流程 圖三方法100依序進行氮化物捕捉記憶體單元之程式化：一開始 進行位階1之程式化（步驟11G)，接著進行位階II之程式化（步 =Uf) ’接著進行位階ΙΠ之程式化（步驟13〇)。氮化物捕捉記 憶體單元之順序程式化可能造成互補位元擾亂（或第二位元效1297500 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an electronic data storage device (MLC) in a ship--(four) squeaking time __ for the life of the [previous technique] (EEPROM) The electronically programmable can be wiped out unless there is a lot of modern bribes. The flash (4) is designed to be a separate array of process cells. The sense amplifier in the flash memory system is used in the system, or in the body of the hair body. In the typical sensing machine, the four-dimensional amplifier and the multi-memory unit structure can be used as the Qiu job flash memory. The smaller the electricity is, the more the memory cell layer is dominated by the charge trapping dielectric layer. The simpler the process, the more popular it is. The cell structure is stored by capturing electricity =, 1 station captures the dielectric layer, such as within the nitride pin. When the negative power =, catching the 'Wei, the beginning of the body unit will increase. It is noted that the initial voltage of the Itian element is reduced by removing the negative charge from the charge trapping layer. Please refer to the first figure, which illustrates a conventional multi-unit stylization method 100, which sequentially performs a flow chart of a four-bit nitride-capturing memory cell. Stylization of the capture memory unit: Initialization of the level 1 (step 11G), followed by the programming of the level II (step = Uf) 'following the stylization of the level (step 13). The sequential stylization of nitride capture memory cells may cause complementary bit disturb (or second bit effect)

Chinese_Macronix-P940126 031406 1297500 應）’由於高邊界位移的影響而縮小讀取範圍之線寬。此缺點請進 一步對應第二圖之說明如後。 弟一圖係繪示說明氮化物捕捉記憶體單元内不同起始電壓位 〜 階之順序程式化的圖式200。圖式200裡，在抹除後之最初為位階 0 210。在第一步驟裡，進行位階I之程式化（步驟22〇)，顯示起 始電壓分佈225。第二步驟裡，進行位階I[之程式化（步驟23〇)， 顯示一起始電壓分佈235。第三步驟裡，進行位階m之程式化 24^，顯示一起始電壓分佈245。每個程式順序會造成較低Vt位階 ^高邊界移動。在位階II程式化230之後，較低為較低Vt位階之 擊高邊界移到右邊，如225-2所示。標記227代表位階j程式 化220時較低vt位階之高邊界位移量。在位階Ιη程式化24〇之 後，位階I程式化時較低vt位階之高邊界移到右邊，如225_3所 示，而位階π程式化時較低vt位階之高邊界移到右邊，如235_2 所示。標記AVt2 237表示位階II程式化230時較低％位階之言 邊界移動量。 同 ^對於一較高的Vt位階而言，會造成互補位元擾亂而引發較大 的範圍損失。結果，最高邊界，H區域247，會產生對Vt移動量 擊^AVtO，Λνη及△VG)的主要影響。讀取速度因為每個位 程式化順序皆由一被抹除Vt區域開始而變得較慢。 i因此，需要一種多重位階單元程式化方法，可降低或消除一記 憶體陣列裡一或多個氮化物捕捉記憶體單元之較低Vt位階的高邊 界移動。 。從 【發明内容】 本發明係提供一種改變氮化物捕捉記憶體單元之多位元單元 内多重位階單元程式侧序之_方法，其降低朗除程式化步 驟之間的起始電壓移動，同時避免抑制因互補位元擾亂所引起之 6 Chinese—Macr〇niX-P94〇i26—〇31. 1297500 作壽命。本發明氮化物捕捉材料記憶體單元之一適當 實施=為S0N0S單元。在—第—具體實施例裡，本發明係依下 列順序，式化具四個位元之多重位元單元_多重位階單元··程 ΐ化Γ第三★程式化位階（位階m)，程式化一第一程式化位階（位 階I)及-第二程式化位階（位階n)至位階T，及從第一程式化 位階程式化第二程式化位階。在—第二具體實施例裡，本發明係 依下列順序程式化具四個位元之多重位元單元_多重位階單 兀·程式化-第三程式化位階（位階m)，程式化一第二程式化位 階（位階II)，及程式化一第一程式化位階（位階工）。 0 一廣義而言，一具四個位元之氮化物捕捉記憶體單元的多重位元 單元内夕重彳靖單元程式化方法包括··在氮化物捕捉記憶體單元 内程式化-赠In，該靖ln之程式化具有—第三祕電壓位 Psb，在位階III程式化後，在氮化物捕捉記顏單元㈣行位階H 之程式化，位階π之程式化具有一第二起始電壓位階；及在位階 II程式化後，在氮化物捕捉記憶體單元内進行位階z之程式化，位 階^之程式化具有一第一起始電壓位階；其中第三起始電壓位階高Chinese_Macronix-P940126 031406 1297500 should) reduce the line width of the read range due to the influence of high boundary displacement. Please refer to the description of the second figure as further below. Figure 1 shows a stylized diagram 200 illustrating the different starting voltage levels in the nitride capture memory cell. In the equation 200, the level is initially 0 210 after erasing. In the first step, the staging of level I is performed (step 22A), and the starting voltage distribution 225 is displayed. In the second step, the level I is programmed (step 23A) to display a starting voltage distribution 235. In the third step, the stylization of the level m is performed, and an initial voltage distribution 245 is displayed. Each program sequence causes a lower Vt level ^ high boundary shift. After the level II is programmed 230, the lower high boundary of the lower Vt level shifts to the right, as shown in 225-2. The mark 227 represents the high boundary shift amount of the lower vt level when the step j is programmed 220. After the level Ιη is programmed to be 24〇, the high-order boundary of the lower vt level moves to the right when the level I is programmed, as shown in 225_3, and the high-order boundary of the lower vt level moves to the right when the level π is programmed, such as 235_2 Show. The mark AVt2 237 indicates the amount of boundary shift of the lower % level when the level II is programmed 230. For a higher Vt level, it will cause the complementary bit to be disturbed and cause a large range loss. As a result, the highest boundary, H region 247, has a major influence on the Vt moving amount hits AVtO, Λνη, and ΔVG. The read speed is slower because each bit stylized order begins with an erased Vt region. Therefore, there is a need for a multi-level cell stylization method that reduces or eliminates the high boundary shift of the lower Vt level of one or more nitride trapping memory cells in a memory array. . SUMMARY OF THE INVENTION The present invention provides a method for changing a multi-level cell program side sequence in a multi-bit cell of a nitride-capturing memory cell, which reduces the initial voltage shift between the staging steps while avoiding Suppresses the 6 Chinese-Macr〇niX-P94〇i26-〇31. 1297500 caused by the interference of the complementary bits. One of the nitride trapping material memory cells of the present invention is suitably implemented = is a SONOS unit. In the first embodiment, the present invention digitizes a multi-bit unit having four bits in the following order: a multi-level unit, a program, a third, a programmed level (level m), a program A first stylized level (level I) and a second stylized level (level n) to a level T, and a second stylized level from the first stylized level. In the second embodiment, the present invention is to program a multi-bit unit with four bits in the following order: multi-level order 程式 stylized - third stylized level (level m), stylized one The second stylized level (level II), and the stylized first stylized level (level work). 0 In a broad sense, a four-bit nitride-capture memory cell unit of a multi-bit cell inner-harmonic unit stylized method includes: - stylized in a nitride trap memory unit - a gift, The stylization of the Jing ln has the third secret voltage level Psb. After the programming of the level III, the stylization of the level H of the nitride capture unit (4), the stylization of the level π has a second starting voltage level. And after the programming of the level II, the programming of the level z is performed in the nitride trap memory unit, the programming of the level ^ has a first starting voltage level; wherein the third starting voltage level is high

於第二起始電壓位階，且第二起始電壓位階高於第一起始電壓位 階。 有利地，本發明因互補位元狀態之相互作用而產生一較快程式 化速度。本發明也有利地抑制由於互補位元擾亂造成的讀取範圍 損失。 以下係詳細說明本發明之結構與方法。本發明内容說明章節目 的並非在於定義本發明。本發明係由申請專利範圍所定義。舉凡 本發明之實施例、特徵、觀點及優點等將可透過下列說明申請專 利範圍及所附圖式獲得充分瞭解。 7 Chinese_Macronix-P940126_031406 1297500 【實施方式】 請參考第三A圖，其係繪示一種具二個位元之氮化物捕捉記 ， 憶體元件300内多重位元單元(MBC)的結構剖面圖。一第一位元， 位元A 310，係位於氮化物捕捉記憶體元件3〇〇之左側上，而第 二位元B 320則位於氮化物捕捉記憶體元件3〇〇之右侧上。氮化 物儲存單元結構300係由利用位元線n+植入330及一位元線n+ 植入332於p型基板334上的方式製得。通道336從位元線n+植 入330之右側延伸到位元線n+植入332之左侧。氧化物-氮化物_ 氧化物介電層338具有一被一氮化矽層342覆蓋之底部二氧化矽 籲層340，其中氮化矽層342被一上二氧化矽層344覆蓋。矽化鎢 (WSL)及多晶石夕導電閘極結構（例如由多晶石夕及石夕化鶴所構成） 348覆蓋上二氧化石夕層344。位元線氧化物346位於位元線n+植入 332，WSi及多晶矽348之間。 請參考第三B圖，其係繪示利用通道熱電子程式化技術進行 程式化之氮化物儲存單元的簡化操作剖面視圖35〇。當位元〗352 進行程式化時，汲極區域356定義於右側上，並連接阻障層擴散 N+(BD N+)358，而源極364則定義於左侧，並連接阻障層擴散 _ N+ 366。、另一方面’阻障層擴散N+ 366連接作為虛擬接地％的 源極區域364。汲極及源極區域之認定與操作可利用虛擬接地Vs 進行父換’使得當位元I進行程式化時汲極區域位於右側而源極區 域位於左#卜當位元II進行程式化岐極區域位於左側而源極區 域位於右侧。程式化期間電子364係儲存於一氮化物層（％师7〇 之内。 至於在既疋讀體單元面積内增加氮化物捕捉記憶體元件· 推度的技術，請參考第四圖，其繚示之圖形4⑻為一種利用分開 起始電壓位階之雜方式達到位元總數從二她元增加到四個位 兀之多重位階單元。在- MLC實施時，第一程式化位階（位階〇) 8 Chinese_Macronix-P940126 031406 1297500 410，-第二程式化位階（位階υ 42〇，一第三程式化位階（位 階II) 430 ’及一第四程式化位階（位階Ιπ)内之程式化位階（或 、起始電壓位階）分別由二進位數格式u，〇1，1〇及〇〇表示。在 另一 MLC實施時，程式化電壓位階分別由二進位數格式u，〇1， 00及10表示。在又- MLC實施時，程式電壓位階係以二進位數 格式U ’ 10，00及01表示。熟習此項技藝者應暸解起始電壓位 階定義不限於此三個實施例，而其他起始電壓位階定義亦可用於 本發明，卻不脫離本發明之精神範缚。 、 為了在多重位元單元氮化物記憶體單元内建立一多重位階單 齡元，第五圖所示之氮化物捕捉記憶體單元500内左侧及右側上的 每個位元具有二個vt位階，使得氮化物捕捉記憶體單元500有效 地包含四個位元。氮化物捕捉記憶體單元500之左側包含位元J 510及位元II520，而氮化物捕捉記憶體單元500之右側則包含位 元III530及位元4 540。換言之，氮化物捕捉記憶體單元5〇〇在左 側上具有二個位元，位元I 510及位元Π 52〇，而右侧上具有二個 位元，位元III530及位元4 540。熟習此項技藝者應瞭解可施加額 外的Vt位階給氮化物捕捉記憶體單元5〇〇内每個位元，以為每個 ，氮化物捕捉記憶體單元5〇〇產生8個，16個或更多個位元。 第六圖為圖式600，其係繪示氮化物捕捉記憶體單元5〇〇左側 與右侧之間的互補位元擾亂（或第二位元效應）。由於左侧上二個 位元其中一個（位元1510或位元1152〇)與氮化物捕捉記憶體單 元500内二個位元其中一個（位元11153〇或位元4540)之間的相 互作用’起始電壓將依互補位元狀態而受到影響。在多重位元單 元氮化物捕捉記憶體單元5〇〇内，左侧上二個位元之一（位元151〇 或位元II 520)及右侧上二個位元（位元m 530或位元4 54〇)之 一落入L1區域610内，亦即落入低vt區域内。在一實施例裡， 假設位元1510與位元in 530落入L1區域610。起始電壓Vt，位 9 Chinese Macronix-P940126 031406 1297500 二=ΐ升到L2區域_，如果位元ΠΙ 530被程式化至高vt 白品品5、630 ’即使位元j 51〇未被程式化。起始電壓％的移動 .ίΓ係指—互補位元擾。互補位元擾亂造成互補較低Vt (或被 ，抹除vt) ^的類似程式化行為。vt範圍係指一起始電錄離， 亦即施加於字猶崎記麵單元可取成械對應參^電 流之被抹除狀態的最小電壓。 ^式化多重位階單元之二個優先考慮因素為程式化速度及讀 取範圍。互齡元航係域改善氮化物捕捉記憶體單元之程式 化速度有關。另-影響氮化物捕捉記憶體單元之程式化速度的因 素則為當附近位元具有高起始電壓vt時。例如，位元m 530之程 式化速度可能較快，如果位元1510具有高起始電壓vt狀態。 第七圖係綠示-種提高多重位階單元程式化速度而同時抑制 因互補位元擾亂所引起之讀取範圍的方法的圖式7〇〇。圖7⑽顯示 依下列順序進行程式化：⑴進行位階ΙΠ之程式化；⑵進行位 階I之程式化，及將位階II程式化成位階J，及（3 )從位階J程 式化位階π。一開始，氮化物捕捉記憶體單元5〇〇在位階〇71〇操 作時被抹除。步驟1不是開始在位階〗進行程式化，而是氮化物捕 ⑩捉纪憶體單元5⑻被程式化成位階III720。步驟2時，在730裡， 氮化物捕捉記憶體單元500被程式化至位階〗，也將位階π程式化 至位階I。步驟3時，在740裡，氮化物捕捉記憶體單元5〇〇從位 階I被程式化至位階II。 在第一具體實施例裡，位階I位元程式化速度提升的理由有 二。首先，就第一方法的程式化順序而言，程式化速度較快如果 附近位元為位階III且具有高Vt。換言之，如果位元j 510 (左側） 具有高Vt狀態，則位元III 530之程式化將更快。其次由位階Ιπ 程式化互補位元擾所產生，其中一些位元的初始點不是來自被 抹除狀態，而是來自第七圖所示之Β區域725 (而非第二圖所示 10At a second starting voltage level, and the second starting voltage level is higher than the first starting voltage level. Advantageously, the present invention produces a faster stylized speed due to the interaction of complementary bit states. The present invention also advantageously suppresses loss of read range due to complementary bit disturb. The structure and method of the present invention are described in detail below. The description of the present invention is not intended to define the present invention. The invention is defined by the scope of the patent application. The embodiments, features, aspects, and advantages of the present invention will be fully understood from the following description. 7 Chinese_Macronix-P940126_031406 1297500 [Embodiment] Please refer to FIG. 3A, which is a cross-sectional view showing a structure of a multi-bit cell (MBC) in a body element 300 with a nitride capture of two bits. A first bit, bit A 310, is located on the left side of the nitride capture memory element 3, and a second bit B 320 is located on the right side of the nitride capture memory element 3. The nitride memory cell structure 300 is fabricated by implanting 332 on the p-type substrate 334 using a bit line n+ implant 330 and a bit line n+. Channel 336 extends from the right side of bit line n+ implant 330 to the left side of bit line n+ implant 332. The oxide-nitride-oxide dielectric layer 338 has a bottom cerium oxide layer 340 covered by a tantalum nitride layer 342, wherein the tantalum nitride layer 342 is covered by an upper ruthenium dioxide layer 344. The tungsten carbide (WSL) and polycrystalline lithosphere conductive gate structures (for example, composed of polycrystalline shi and Xi Xihua) 348 cover the upper layer of SiO2. The bit line oxide 346 is located between the bit line n+ implant 332, WSi and polysilicon 348. Please refer to Figure 3B, which shows a simplified operational cross-sectional view of a nitride storage unit programmed with channel thermal electronic stylization techniques. When bit 352 is programmed, the drain region 356 is defined on the right side and connected to the barrier diffusion N+(BD N+) 358, while the source 364 is defined on the left side and connected to the barrier diffusion _ N+ 366. On the other hand, the barrier diffusion N+ 366 is connected as the source region 364 of the virtual ground %. The identification and operation of the drain and source regions can be performed by using the virtual ground Vs for parental replacement. 'When the bit I is programmed, the drain region is on the right side and the source region is on the left side. The area is on the left and the source is on the right. During the stylization period, the electrons 364 are stored in a nitride layer (% of the masters. For the technique of adding nitride capture memory components and pushing in the area of the read unit), please refer to the fourth figure. Figure 4(8) shows a multi-level cell with a total number of bits increasing from two to four bits using a different way of separating the starting voltage levels. In the implementation of MLC, the first stylized level (level) 8 8 Chinese_Macronix-P940126 031406 1297500 410, - the second stylized level (levels υ 42 〇, a third stylized level (level II) 430 ' and a fourth stylized level (level Ι π) within the stylized level (or, The starting voltage levels are represented by the binary format u, 〇1, 1〇 and 分别, respectively. In another MLC implementation, the stylized voltage levels are represented by the binary format u, 〇1, 00 and 10, respectively. In the case of the MLC implementation, the program voltage level is expressed in the binary format U ' 10, 00 and 01. Those skilled in the art should understand that the starting voltage level definition is not limited to the three embodiments, and other starting voltages. Level definition The invention is used without departing from the spirit of the invention. In order to establish a multi-level single-age element in a multi-bit cell nitride memory cell, the nitride-capturing memory cell 500 shown in FIG. Each bit on the left and right sides has two vt steps, such that the nitride capture memory cell 500 effectively contains four bits. The left side of the nitride capture memory cell 500 includes bit J 510 and the bit II520, and the right side of the nitride trap memory unit 500 includes a bit III 530 and a bit 4 540. In other words, the nitride trap memory unit 5 具有 has two bits on the left side, the bit I 510 and the bit Π 52〇, and there are two bits on the right side, bit III 530 and bit 4 540. Those skilled in the art should understand that an additional Vt level can be applied to each bit in the nitride capture memory cell 5 Yuan, thinking that each, nitride capture memory cell 5 〇〇 produces 8, 16 or more bits. The sixth figure is a diagram 600, which shows the nitride capture memory unit 5 〇〇 left side Complementary bit disturbing with the right side (or Second bit effect). One of the two bits on the left side (bit 1510 or bit 1152〇) and one of the two bits in the nitride capture memory cell 500 (bit 11153〇 or bit) 4540) The interaction 'the starting voltage will be affected by the complementary bit state. Within the multi-bit cell nitride trapping memory cell 5〇〇, one of the two bits on the left side (bit 151 One of the two bits (bit m 530 or bit 4 54 〇) on the right side and the second bit (bit m 530 or bit 4 54 〇) falls within the L1 region 610, that is, falls into the low vt region. In an embodiment It is assumed that the bit 1510 and the bit in 530 fall into the L1 region 610. Starting voltage Vt, bit 9 Chinese Macronix-P940126 031406 1297500 Two = ascending to L2 area _, if bit ΠΙ 530 is programmed to high vt white goods 5, 630 ' even if bit j 51 is not programmed. The movement of the starting voltage %. Γ refers to the complementary bit disturb. Complementary bit disturbing results in a similar stylized behavior of complementary lower Vt (or by, wiping vt)^. The vt range refers to a starting electrical recording, that is, the minimum voltage applied to the word erased state of the word yakisaki recording unit. The two priority factors for the multi-level cell are the stylized speed and read range. It is related to the stylized speed of improving the nitride trapping memory unit in the mutual ageing system. Another factor affecting the stylized speed of the nitride trap memory cell is when nearby bits have a high starting voltage vt. For example, the programming speed of bit m 530 may be faster if bit 1510 has a high starting voltage vt state. The seventh figure is a diagram showing the method of increasing the stylized speed of the multi-level unit while suppressing the read range caused by the complementary bit disturb. Figure 7 (10) shows the stylization in the following order: (1) stylization of the level ΙΠ; (2) stylization of the level I, and stylization of the level II into the level J, and (3) programming the level π from the level J. Initially, the nitride trapping memory cell 5 is erased during the level 〇71〇 operation. Step 1 is not to start stylizing in the level, but the nitride capture unit 5 (8) is programmed into the level III720. In step 2, in 730, the nitride capture memory cell 500 is programmed to a level, and the level π is also programmed to level I. In step 3, at 740, the nitride capture memory cell 5 is programmed from level I to level II. In the first embodiment, there are two reasons for the stylized speed increase of the level I bit. First, in terms of the stylized order of the first method, the stylization speed is faster if the nearby bit is level III and has a high Vt. In other words, if bit j 510 (left side) has a high Vt state, the stylization of bit III 530 will be faster. Secondly, it is generated by the level Ιπ stylized complementary bit disturb, some of which are not from the erased state, but from the Β region 725 shown in the seventh figure (instead of the second figure 10)

Chinese_Macronix-P940126 031406 ：S) 1297500 ，A區域215) ’即轉換至較高Vt區域。換言之，互補位元擾亂 係用以辅助程式化。 、，位階^之程式化速度在第一方法裡獲得提升，其原因有二。 首先’在第-方法的程式化順序裡，程式化速度將更快如果附近 ，元非位階III即位階！，二者皆為高Vt。換言之，如果位元151〇 ^侧）具有南vt狀態，則位元冚530(右側)之程式化將更快。 其-人，饭疋位階II之程式化也在位階〗程式化狀態時進行，則最 終位階II程式化躺—些位元的初始點絲自第七圖所示之c區 域735 ’而非第六圖所示之a區域215。 口第一方法也維持讀取範圍的操作時間。第二圖所示之讀取範圍 損失^\Vt2 237被消除，第二圖所示之227也明顯受到抑制， 因為第一方法的第一順序乃為進行佩bin72〇之程式化。如第七 ，所示’ AVtl 744小於第二圖所示之Ανι：1 227，因為AVtl % 又到HI區域750影響而非來自H區域752。參數之起 始電壓移動也獲得改善，因為在第一方法中位階m目標根據較緊 湊的位階I及位階II讀取範圍而降低。 ’、 第八®係為-種以相反順序提高多重位階單元程式化速度而 同日守抑制因互補位元擾亂所引起之讀取窗的方法的圖式_。圖 800所示之第二方法採用逆向程式化順序：⑴程式化位階m; 程式化位階II及⑶程式化位階Jf。圖_所示之第二方法 或消除位階I處的小讀取範圍損失Avu。 - 一開始，氮化物捕捉記憶體單元500在位階〇 _賴 被抹除狀態。科在位階！開始進行程式，而是步驟〗裡，氮 捕捉記憶體，元500被程式化至位階m 82〇。步驟2裡，氮化物 捕捉記憶體單元5GG被程式化至位階^謂。步驟 捉記憶體單元500被程式化至位階84〇。 虱化物捕 在圖_所示第二方法之逆向程式化順序裡，附近位元（互補 11Chinese_Macronix-P940126 031406 :S) 1297500, A area 215) ' is switched to the higher Vt area. In other words, the complementary bit disturb is used to aid in stylization. The stylized speed of the level ^ is improved in the first method for two reasons. First of all, in the stylized order of the first method, the stylization speed will be faster. If nearby, the meta-level III is the level! Both are high Vt. In other words, if the bit 151 〇 ^ side has a south vt state, the stylization of the bit 冚 530 (right side) will be faster. The -man, the stylization of the rice cooker level II is also carried out in the stylized state of the level, and the final level II is programmed to lie - the initial point of some bits is from the c area 735 ' shown in the seventh figure instead of the first The a area 215 shown in the six figures. The first method of the mouth also maintains the operating time of the read range. The read range loss ^\Vt2 237 shown in the second figure is eliminated, and the 227 shown in the second figure is also significantly suppressed because the first order of the first method is to perform the stylization of the bin 72. As shown in the seventh, 'AVtl 744 is smaller than Ανι:1 227 shown in the second figure because AVtl% is in turn affected by the HI area 750 instead of the H area 752. The initial voltage shift of the parameters is also improved because the level m target is reduced in the first method according to the tighter level I and the level II read range. ', the eighth® is a pattern of a method of increasing the stylized speed of the multi-level unit in the reverse order and suppressing the reading window caused by the scramble of the complementary bit. The second method shown in Figure 800 uses a reverse stylized sequence: (1) the stylized level m; the stylized level II and (3) the stylized level Jf. The second method shown in Figure _ or eliminates the small read range loss Avu at level I. - Initially, the nitride trap memory cell 500 is erased in the level 〇 _ _ Branch in the ranks! Start the program, but in the step, the nitrogen captures the memory and the element 500 is programmed to the level m 82〇. In step 2, the nitride trap memory unit 5GG is programmed to the level. Step The capture memory unit 500 is programmed to a level 84〇. Telluride trapping in the reverse stylized sequence of the second method shown in Figure _, nearby bits (complement 11

Chinese^Macronix-P940126_031406 1297500 位元）的不必要效應在完成較低位階位元程式化後將被程式至較 南位階，除了不需要被程式化之已抹除位元區域外。例如，位階 ,11830之程式化完成後，不需要考慮到附近位元是否稍後將被程式 , 化成較咼位階（亦即位階III)，如互補位元擾亂所引起者，因為位 階111/20已經被程式化了。因此，相對於習知方法而言。圖8〇〇 所示第二方法之逆向程式化順序可降低或消除Avtl&Avt2讀取 範圍損失。 請參考第九圖，其係繪示第一及第二具體實施例裡多重位元單 元内多重位階單元之程式化流程的流程圖。雖然第七圖所示第一 鲁具體實施例之程式化方法及第八圖所示第二具體實施例之程式化 方法可以分別實施，但是記麵陣狀程式化行為因為電流泵的 有限能力而希望以數個程式化單元組合實施。通常，如果程式化 單元在多重鋪單幼具有靖〗或鋪n 態，職程將遵 照第二具體實施例的方法進行，否則將按照第一具體實施例的方 法進行。 在步驟910裡，啟動程式化順序。因為圖7〇〇所示之第一程式 化方法與® _所示之第二程式化方法㈣始於位階m之程式 _ 化，所以方法900在步驟912進行位階in之程式化。步驟914時， 方法900進行位階ΠΙ程式化之確認檢查。在步驟916裡檢測上述 確認結果，以決定是否通過位階m之確認。如果步驟9〇6無法通 過結果檢測，則方法900決定-暫停極限。如果沒有達到暫停極 限，财法900回到步驟912，進行位階m之程式化。如果已經 達到暫停極限，則方法900在步驟908顯示位階m失敗。然而， 如果步驟916通過確認檢測，則方法9〇〇前進至一程式化 在步驟920分析是否程式化單元在一單元内具有位階j或位階… =早兀内具有位階！或位階Π”係指—單元之左侧為位階！而相同 早το右侧為位階II，或-單元左侧為位階π而相同單元右侧為位The unnecessary effect of Chinese^Macronix-P940126_031406 1297500 bit) will be programmed to the south level after the lower level bit is stylized, except for the erased bit area that does not need to be programmed. For example, after the stylization of the level, 11830 is completed, it is not necessary to consider whether nearby bits will be later programmed into a higher order (ie, level III), as caused by the complementary bit disturb, because the level is 111/20. Has been programmed. Therefore, it is relative to the conventional method. The reverse stylized sequence of the second method shown in Figure 8A reduces or eliminates the Avtl&Avt2 read range loss. Please refer to the ninth figure, which is a flow chart showing the stylized flow of multiple level units in a multi-bit unit in the first and second embodiments. Although the stylized method of the first embodiment of the first embodiment and the stylized method of the second embodiment shown in the eighth figure can be separately implemented, the matrix-like stylization behavior is due to the limited capability of the current pump. I hope to implement it in a combination of several stylized units. In general, if the stylized unit is in a multi-ply mode or a n-state, the course will be followed in accordance with the method of the second embodiment, otherwise it will be carried out in accordance with the method of the first embodiment. In step 910, the stylization sequence is initiated. Since the first stylized method shown in Fig. 7 and the second stylized method (4) shown in ®_ start from the program of the level m, the method 900 performs the staging of the level in in step 912. At step 914, method 900 performs a level-by-step stylization confirmation check. The above confirmation result is detected in step 916 to determine whether or not to confirm by the level m. If step 9〇6 fails the result detection, then method 900 determines the -pause limit. If the pause limit is not reached, the method 900 returns to step 912 to program the level m. If the pause limit has been reached, the method 900 displays the level m failure at step 908. However, if step 916 passes the acknowledgment detection, then method 9 proceeds to a stylization. At step 920, it is analyzed whether the stylized unit has a level j or a level within a unit... = has a level in the early !! Or the level Π" means that the left side of the unit is a level! and the same as early το the right side is the level II, or - the left side of the unit is the level π and the right side of the same unit is the bit

Chmese_Macronix-P94〇l26 031406 1297500 階I。如果方法900測定到程式化單元在一單元内 階II，則方法進行圖700所示之第一 h或位 ^ ^ - 罘私式化方法。如果方法9〇〇 _所示H式化方法。 财法進仃圖 階例ί方法時’方法900在步驟930進行位 pb J , ζ 白之程式化的同時，"預定位階II樣態"至位 =也被从化，崎低㈣財化赠η之 程式化位階叫，綠9⑽只__驗赠 /Chmese_Macronix-P94〇l26 031406 1297500 Order I. If method 900 determines that the stylized unit is in a unit of order II, then the method proceeds to the first h or bit ^^ - 罘 privateization method shown in diagram 700. If the method 9〇〇 _ shows the H-form method. When the method proceeds to the example ί method, the method 900 performs the bit pb J in step 930, and while the white stylized, the "predetermined level II pattern" is in place, and is low (four). The stylized level of η is called, green 9 (10) only __ acceptance /

II，而非如習知所教式者從位階〇到位階π。 在步驟930程式化位階；[_)後，方法9〇〇在步驟94〇進行位 ，I (Ι+ΙΙ)程式化確認。步驟942裡，方法_測定是否位階工確 認測試已經通過。如果位階〗確認未通過，則方法9⑻在步驟倾 檢查暫停極限。如果暫雜限未制，則方法9⑻回到步驟·。 如果暫停紐已經_，财法9⑻在步驟946絲赠〗程式化 失敗。如果位階I確認未通過，則方法900進行到步驟950， 位階I之程式化。 在開始程式化位階II之步驟950後，方法9〇〇在步驟952進 j亍位階II程式化確認。步驟954裡，方法9〇〇測定是否位階η確 wv則试已經通過。如果確認測試未通過，則方法9⑻在步驟956 檢查暫停極限。如果暫停極限未達到，則方法9〇〇回到步驟95〇。 如果暫停極限已經達到，則方法9〇〇在步驟958表示位階π程式 化失敗。如果確認通過，則方法9〇〇在步驟980結束程式化流程。 在實加弟一具體實施例的方法時，在步驟960裡，方法9〇〇進 行位階II之程式化。方法9〇〇在步驟962進行位階II程式化確認。 步驟964裡，方法900檢查是否位階π程式化確認通過。如果確 認未通過，則方法900在步驟966測定一暫停極限。如果暫停極 限未達到，則方法900進行步驟960。如果暫停極限已經達到，則 13 ChineseJMacronix-P940126 031406 1297500 方法900在步驟968表示位階π程式化失敗。 如果程式化確認通過’則方法9〇(y在步驟97〇進行位階I之程 式化。方法900在步驟972進行位階I之程式化確認。步驟974 裡，方法900檢查是否程式化續認通過。如果程式化確認未通過， 則在步驟976裡方法9GG檢查-暫停極限。如果暫停極限沒有達 到，則方法900進行到步驟970。然而，如果暫停極限已經達到， 則方法900在步，驟978顯示位階j程式化失敗。如果程式化確認通 過，則方法900在步驟980結束程式化操作。 —每個多重位元單元具有—左側位元（或位元A31G)及一右侧 ，元（位元B 320)，如弟二圖所示。多重位元單元内之多重位階 單兀創造出四個位元：左侧上的位元〗51〇及位元π 52〇及右侧上 的位元III及位元4，以及在單一多重位元單元内有四個程式化位 Ρ白’位階0’位階I’位階π及位階ΙΠ。因此，有十六個可能組合·· (位1¾ 0 ’位階〇) ’（位階0，位階〗），（位階〇，位階H)，（位階 〇位卩自III)，（位階I ’位階0)，（位階〗，位階【），（位階I，位階 II)，（位階I，位階III)，（位階n，位階〇)，（位階π，位階υ，（位 階II，位階II)，（位階η，位階冚），（位階m，位階〇)，（位階 in位I) ’（位階in，位階h)及（位階m，位階m)。 夕重位元單元氮化物捕捉材料内多重位階單元之程式化的方 法順序可以視選定設計或實施方式而定。例如，方法順序程式化 位於左侧上的第-位元，右側上的第三位元，及左侧上的第二位 元在另一實施例裡，方法順序程式化一位於右側上的第三位元， 位於左侧上的第一位元，及右侧上的第四位元。 第十圖繪示四個程式化位階之起始電壓的圖式1000。在一具 體實施例裡，四個不同位階編碼為：位^bQ=u，位階ι=〇ι，ςII, rather than as taught by a person from the level to the level π. After the step is programmed in step 930; [_), the method 9 is performed in step 94, and the I (Ι + ΙΙ) stylized confirmation. In step 942, the method _ determines if the step-by-step worker confirms that the test has passed. If the level acknowledgment fails, then method 9(8) checks the pause limit at the step. If the temporary mismatch is not established, then method 9 (8) returns to step . If the pause is already _, the method 9(8) fails in step 946 and the stylization fails. If the level I is confirmed to have failed, the method 900 proceeds to step 950, stylizing the level I. After the step 950 of the programming level II is started, the method 9 is stepped into the step 952 to verify the level II. In step 954, method 9 〇〇 determines if the level η is indeed wv and the test has passed. If the confirmation test fails, then method 9(8) checks the pause limit at step 956. If the pause limit is not reached, then method 9 returns to step 95. If the pause limit has been reached, then method 9 表示 indicates at step 958 that the level π stylization failed. If the confirmation is passed, then the method 9 ends the stylization process at step 980. In the case of a specific embodiment of the method, in step 960, the method 9 performs the stylization of the level II. Method 9: In step 962, the level II programming is confirmed. In step 964, method 900 checks if the level π stylization confirmation is passed. If the determination fails, the method 900 determines a pause limit at step 966. If the pause limit is not reached, then method 900 proceeds to step 960. If the pause limit has been reached, then the Chinese JMacronix-P940126 031406 1297500 method 900 indicates in step 968 that the level π stylization failed. If the stylization is confirmed by 'method 9' (y is programmed in step 97 to perform the staging of step I. Method 900 performs a stylization confirmation of level I in step 972. In step 974, method 900 checks if the stylized renewal is passed. If the stylization confirmation has not passed, then method 9GG checks the -pause limit in step 976. If the pause limit is not reached, then method 900 proceeds to step 970. However, if the pause limit has been reached, then method 900 is shown in step 978. The level j stylization fails. If the stylization confirmation is passed, the method 900 ends the stylization operation at step 980. - Each multi-bit unit has - left bit (or bit A31G) and one right side, meta (bit) B 320), as shown in the second diagram, the multi-level unit in the multi-bit unit creates four bits: the bit on the left side is 51〇 and the bit on the right side is π 52〇 and the bit on the right side III and bit 4, and four stylized bits in a single multi-bit cell, white 'level 0' level I' level π and level ΙΠ. Therefore, there are sixteen possible combinations · (bit 13⁄4 0 ' Level 〇) '(level 0, level 〖), (position 〇, level H), (level 〇 卩 from III), (level I 'level 0), (level), level [), (level I, level II), (level I, level III ), (level n, level 〇), (level π, level υ, (level II, level II), (level η, level 冚), (level m, level 〇), (level in bit I) ' (level) In, level h) and (level m, level m). The order of the stylized method of multiple-level cells within the nitride-capture material can be determined by the selected design or implementation. For example, the method sequence is programmed The first bit on the left side, the third bit on the right side, and the second bit on the left side. In another embodiment, the method sequentially stylizes a third bit on the right side, on the left side. The first bit on the upper bit and the fourth bit on the right side. The tenth figure shows a pattern 1000 of the starting voltages of the four stylized levels. In one embodiment, the four different levels are encoded as: Bit ^bQ=u, level ι=〇ι,ς

Pf π，ιο，位階m=oo。熟習此項技藝者應瞭解其他編碼或定義 可以實施，部不脫離本發明之精神範缚。四個不同位階形成從Pf π, ιο, level m = oo. Those skilled in the art will appreciate that other codes or definitions may be implemented without departing from the spirit of the invention. Four different steps are formed from

Chinese_Macronix-P940126 031406 14 1297500 左侧到多重位階單元右側共十六個可能條件組合， 表1 (左側，右側） 一_(位階0，位階0) 一階（左侧，右侧） (11，11) ~~ _(位階0,位階I) _ -------- \丄丄 / ___(11，01) 一_(位階0,位階II)___ '^~---一 —，10) .~—1^階 〇，位階 in)__ ____(11，00) ' __(位階I，位階0) (4立P皆T，々r R由T、 一___(01，11) —— \ *上* 1臼丄 I W |為 | J (位階I，位階II、 _—(01，01) (01，10) (位階I，位階III) Γοι，〇(n (位階II，位階〇) 一 -- \ v A W V / (10，11) ^ (位階II，位階I) (10, 01) (位階II，位階TT、 (10，10) _____(位階II，位階III) -----* CIO y 00) ___(位階III，位卩^2____ \ XV/ \J\J J _(00, 11) (位階III，位階η ----- (00，01) __(位階III，位階II) (00，10) ~ (位階III，位階ΠΙ) (00,00) 名1010程式化（以雙位數11編碼）具有大約4.5伏特之 ，口電壓’設定約在抹除確認（EV)電壓位階體。位階工刪 (以雙位數01編碼）具有大約4.5伏特+ 200微伏+ 200 微伏的起始電壓。位階π _程式化（以雙位數ι〇編 、有大約4.5伏特+2GG微伏+2GG微伏+35G微伏+2G〇微伏 微伏+350微伏的起始電壓。位階III1040程式化(以雙位數 15 Chinese_Macronix-P940126 031406 1297500 - 00編碼）具有大約4.5伏特+ 200微伏+ 200微伏+350微伏+ 200 微伏+ 200微伏+350微伏+ 200微伏+ 200微伏+350微伏的起始 , 電壓。第一讀取電壓RD1 1014設定在位階0 1010電壓及位階工 1020電壓。第二讀取電壓RD2 1022設定在位階I 1020電壓及位 階π 1030電壓之間。第三讀取電壓奶3 1032設定在位階1]; 1〇3〇 電壓及位階in 1〇4〇電壓之間。第一程式化確認PV11016設定接 近位階11020程式化電壓範圍的底限。第二程式化確認ρνι〇 1〇24 設定接近位階II 1030程式化電壓範圍之底限。第三程式化電壓範 圍PV00 1034設定接近位階III1040程式化電壓範圍之底限。 雖然本發明係已參照較佳實施例來加以描述，將為吾人 所瞭解的是，本發明創作並未受限於其詳細描述内容。以 電荷捕捉介電層為主實施多重位元單元内之多重位階單元的記憶 體單元結構例如包括此領域所知的氮化物唯讀記憶體（NR〇M)， SONOS及PHINES等。雖然多重位元單元內之多重位階單元的程 式化已揭露如上，但是本發明仍可應用於頁程式化或其他類型如 記憶體陣列内MBC之MLC區塊，區段或次區塊的程式化。替換 方式及修改樣式係已於先前描述中所建議，並且其他替換 鲁方式及修改樣式將為熟習此項技藝之人士所思及。特別 是，根據本發明之結構與方法，所有具有實質上相同於本 發明之構件結合而達成與本發明實質上相同結果者皆不脫 離本發明之精神範疇。因此，所有此等替換方式及修改樣 式係意欲落在本發明於隨附申請專利範圍及其均等物所界 定的範疇之中。 【圖式簡單說明】 第一圖係繪示一種習知多重位元單元程式化方法，其依序程式 化一具四個位元之氮化物捕捉記憶體單元的流程圖； 16 Chinese_Macronix-P940126 031406 1297500 第二圖係繪示一種在一氮化物捕捉記憶體單元内進行不同程 式化電壓位階順序程式化的圖式； 第三A圖係繪示根據本發明一種具二個位元之氮化物捕捉記 憶體元件内多重位元單元的結構剖面圖； 第二B圖係繪示根據本發明利用通道熱電子程式化技術進行 程式化之氮化物儲存單元的簡化操作剖面視圖； 第四圖係繪示根據本發明在一多重位元單元内多重位階單元 之不同程式化電壓位階的示意圖； 第五圖係繪示根據本發明在―多重位元單元氮化物捕捉材料 内之多重位階單元的結構視圖； 一立第六圖係繪示根據本發明在多重位階單元内互補位元擾亂之 不意圖； 比-第七，騎示根據本發明之第—具體實施例，—種提高多重位 ，单70程式化速度*同時抑個互補位元祕所引起之讀取範圍 損失的方法； 鱗秘縣發明H財關，—_相反順序 位階早_式化速度關時抑制因互補位元擾亂所引起 之碩取範圍損失的方法； 第=係繪祕據本發明第—及第二具 早兀*之程式化流程的流程圖；及 起本發μ—具體魏例，四姉式化位階之 17 Chinese Macronix-P940126 031406 1297500 【主要元件符號說明】Chinese_Macronix-P940126 031406 14 1297500 A total of sixteen possible combinations of conditions from the left to the right of the multi-level unit, Table 1 (left, right) one _ (level 0, level 0) first order (left, right) (11,11 ) ~~ _(position 0, step I) _ -------- \丄丄/ ___(11,01) A _(level 0, level II)___ '^~---一—,10 ) .~—1^级〇, level in)__ ____(11,00) ' __(level I, level 0) (4 P is T, 々r R is T, ___(01,11) — — \ *上* 1臼丄IW | is | J (level I, level II, _—(01,01) (01,10) (level I, level III) Γοι,〇(n (level II, level 〇 ) --- \ v AWV / (10,11) ^ (Level II, Level I) (10, 01) (Level II, Level TT, (10,10) _____ (Level II, Level III) ---- -* CIO y 00) ___ (level III, position 卩^2____ \ XV/ \J\JJ _(00, 11) (level III, level η ----- (00,01) __ (level III, level II) (00,10) ~ (Level III, Level ΠΙ) (00,00) Name 1010 Stylized (coded with double digit 11) has approximately 4.5 volts, and the port voltage 'sets approximately at erase confirmation (EV) Voltage level body. The meta-destruction (coded with double digits 01) has a starting voltage of approximately 4.5 volts + 200 microvolts + 200 microvolts. The level π _ stylized (coded in double digits ι〇, with approximately 4.5 volts + 2 GG microvolts) +2GG microvolts +35G microvolts + 2G 〇 microvolts microvolts + 350 microvolts starting voltage. The level III1040 stylized (coded in double digits 15 Chinese_Macronix-P940126 031406 1297500 - 00) has approximately 4.5 volts + 200 micro Volt + 200 microvolts + 350 microvolts + 200 microvolts + 200 microvolts + 350 microvolts + 200 microvolts + 200 microvolts + 350 microvolts starting, voltage. The first read voltage RD1 1014 is set at level 0 1010 voltage and step 1020 voltage. The second read voltage RD2 1022 is set between the voltage of the step I 1020 and the voltage of the step π 1030. The third read voltage milk 3 1032 is set at the level 1]; 1 〇 3 〇 voltage and level In between 1〇4〇 voltage. The first stylized confirmation PV11016 sets the bottom of the stylized voltage range close to the level 11020. The second stylized confirmation ρνι〇 1〇24 sets the bottom of the stylized voltage range close to the level II 1030. The third stylized voltage range PV00 1034 sets the bottom of the programmed voltage range close to the level III1040. Although the present invention has been described with reference to the preferred embodiments, it is understood that the invention is not limited by the detailed description. The memory cell structure in which the charge trapping dielectric layer is mainly used to implement the multi-level cell in the multi-bit cell includes, for example, a nitride read-only memory (NR〇M), SONOS, and PHINES as known in the art. Although the stylization of multiple-level cells within a multi-bit cell has been disclosed above, the present invention is still applicable to page stylization or other types of MLC blocks such as MBC in a memory array, stylized segments or sub-blocks. . Alternatives and modifications are suggested in the previous description, and other alternatives and modifications will be contemplated by those skilled in the art. In particular, the structures and methods of the present invention, all of which are substantially identical to the components of the present invention and which achieve substantially the same results as the present invention, do not depart from the spirit of the invention. Therefore, all such alternatives and modifications are intended to be within the scope of the invention as defined by the appended claims and their equivalents. [Simplified Schematic] The first figure shows a conventional multi-bit unit stylization method, which sequentially programs a four-bit nitride capture memory unit; 16 Chinese_Macronix-P940126 031406 1297500 The second figure shows a diagram of different stylized voltage level order stylization in a nitride trap memory cell; the third A diagram shows a nitride trap with two bits in accordance with the present invention. A cross-sectional view of a simplified operation of a nitride cell in a memory device; a second block diagram showing a simplified operational cross-sectional view of a nitride cell using a channel thermal electron staging technique; Schematic diagram of different stylized voltage levels of multiple-order cells in a multi-bit cell in accordance with the present invention; Figure 5 is a structural view of multiple-level cells in a multi-bit cell nitride capture material in accordance with the present invention. The sixth figure shows the intention of disturbing the complementary bit in the multi-level cell according to the present invention; the ratio - seventh, riding according to the present invention The first embodiment, a method for increasing the multiple bits, the single 70 stylized speed * simultaneously suppressing the loss of the reading range caused by the complementary bit secret; the scale secret county invented the H financial customs, - the reverse order level is early _ Method for suppressing the loss of the range of the mastery caused by the interference of the complementary bit when the speed is off; the system is a flow chart of the stylized flow of the first and second early versions of the present invention; Μ—specific Wei case, four-squared level 17 Chinese Macronix-P940126 031406 1297500 [Main component symbol description]

100 傳統多單元程式化方法 227 △Vtl 237 △Vt2 247 Η區域 215 Α區域 300 氮化物捕捉記憶體元件 310 位元A 320 位元B 330， 332位元線n+植入 334 p型基板 336 通道 338 氧化物-氮化物-氧化物介電層 340 底部二氧化矽層 342 氮化矽層 344 上二氧化矽層 346 位元線氧化物 348 多.晶砍閘極 352 位元I 354 位元I 356 >及極區域 358 阻障層擴散N+(BDN+) 364 源極區域 366 阻障層擴散N+ Vs 虛擬接地 500 氮化物捕捉記憶體單元 18 Chinese Macronix-P940126 031406 1297500100 Traditional multi-unit stylized method 227 △Vtl 237 △Vt2 247 Ηregion 215 Αregion 300 nitride capture memory component 310 bit A 320 bit B 330, 332 bit line n+ implanted 334 p-type substrate 336 channel 338 Oxide-nitride-oxide dielectric layer 340 bottom ceria layer 342 tantalum nitride layer 344 upper ceria layer 346 bit line oxide 348. crystal cut gate 352 bit I 354 bit I 356 > and pole region 358 barrier diffusion N+(BDN+) 364 source region 366 barrier diffusion N+ Vs virtual ground 500 nitride capture memory cell 18 Chinese Macronix-P940126 031406 1297500

510 位元I510 bit I

520 位元II520 bit II

530 位元III 540 位元4 610L1 區域 620L2 區域 710 位階0530 bit III 540 bit 4 610L1 area 620L2 area 710 level 0

720 位階III 730 位階（I+II)720-bit III 730-level (I+II)

740 位階II 725 B區域 735 C區域740 Position II 725 B Area 735 C Area

742 AVtO 744 AVtl 750 HI區域 752 Η區域742 AVtO 744 AVtl 750 HI area 752 Η area

810，1010 位階 0 820，1040 位階 III 830，1030 位階 II 840, 1020 位階 I 911 開始程式化 912 位階III程式化 914 位階III程式化-確認 916 通過？ 906 脈衝極限？ 908 位階III失敗 920 程式化單位的一單位裡具有(位階I或位階II)? 19 Chinese Macronix-P940126 031406 1297500 • 930 位階(Ι+Π)程式化 942 通過？ • 940 位階I程式化-確認 946 位階I失敗 944 脈衝極限？ 950 位階II程式化 952 位階II程式化-確認 954 通過？ 956 脈衝極限？ • 958 位階II失敗 960 位階II程式化 962 位階II程式化-確認 964 通過？ 966 脈衝極限？ 968 位階II失敗 978 位階I失敗 974 通過？ 972 位階I程式化-確認 • 97Q 位階I程式化 980 程式化結束810, 1010 Level 0 820, 1040 Level III 830, 1030 Level II 840, 1020 Level I 911 Start Stylization 912 Level III Stylized 914 Level III Stylized - Confirm 916 Pass? 906 pulse limit? 908 Level III Failure 920 Stylized unit has one unit (Level I or Level II)? 19 Chinese Macronix-P940126 031406 1297500 • 930-level (Ι+Π) stylized 942 Pass? • 940-bit I stylized - confirmed 946 level I failed 944 pulse limit? 950-level II stylized 952-level II stylized-confirmed 954 passed? 956 pulse limit? • 958 level II failure 960 level II programming 962 level II programming - confirmation 964 pass? 966 pulse limit? 968 Level II Failure 978 Level I Failure 974 Passed? 972 Level I Stylized - Confirmation • 97Q Level I Stylized 980 Stylized End

1012 抹除確認電壓EV 1014 第一讀取電壓RD1 1022 第二讀取電壓RD2 1032 第三讀取電壓RD3 1016 第一程式化確認PV01 1024 第二程式化確認PV10 1034 第三程式化電壓範圍PV00 20 Chinese Macronix-P940126 0314061012 erase confirmation voltage EV 1014 first read voltage RD1 1022 second read voltage RD2 1032 third read voltage RD3 1016 first stylized confirmation PV01 1024 second stylized confirmation PV10 1034 third stylized voltage range PV00 20 Chinese Macronix-P940126 031406

Claims (1)

1297500 十、申請專利範圍 • L 一種程式化一四位元氮化物捕捉記憶體單元之一多重位元單元 • 内一多重位階單元的方法，該方法包括： 早疋 進行該亂化物捕捉§己憶體早元内之一位階三的程式化，豆中， 位階三的程式化具有一第三起始電壓位階； 、“ 比在該位階三程式化後，進行該氮化物捕捉記憶體單元内之一位 ΐ二的程式化，其中該位階二的程式化具有一第二起始電壓位 階；及 比在该位階二程式化後，進行該氮化物捕捉記憶體單元内之一位 階-的程式化，其中該位階一的程式化具有一第一起始電壓位階； 々其中該第三起始電壓位階高於該第二起始電壓位階，且其中該 第二起始電壓位階高於該第一起始電壓位階。 八^ 2·如申請專利範圍第1項之方法，更包括進行該位階二之程式 化，如果該位階三之程式化已經通過一位階三確認測試。 • 3·如申請專利範圍第1項之方法，更包括進行該位階一之程式 化，如果该位階二之程式化已經通過一位階二確認測試。 申請專利範圍第1項之方法，更包括確認該氮化物捕捉記憶 體t朗之位階三雜式化；確職氮化物捕捉記憶體單元内之 一的程式化，及確忍該氮化物捕捉記憶體單元内之位階一的 程式化。 5. 一f程式化一記憶體陣列之一氮化物捕捉記憶體單元内一多重 位階單元的方法，該方法包括： ChineseJVlacronix-P940126 031406 1297500 - 進行該氮化物捕捉記憶體單元内之一位階三的程式化； 在該位階三程式化後，進行該氮化物捕捉記憶體單元内之一位 階一的程式化及一位階二的程式化，其中該位階二程式化係程式 化至該位階一程式化；及 在該位階一程式化後，以一起始電壓從該位階一的程式化開始 進行該氮化物捕捉記憶體單元内之位階二的程式化； 其中該位階三程式化之起始電壓位階高於該位階二程式化之起始 電壓位階，且其中該位階二程式化之起始電壓位階高於該位階一 程式化之起始電壓位階。 6·如申晴專利範圍第5項之方法，更包括進行至該位階一之程式 化，如果該位階三程式化已經通過一位階三確認測試。 7·如申请專利範圍第6項之方法，更包括進行該位階二之程式 化，如果該位階一程式化已經通過一位階一確認測試。 8·如申請專利範圍第7項之方法，更包括確認該氮化物捕捉記憶 鲁體早元内位)¾二之矛王式化，確§忍§亥氣化物捕捉記憶體單元内位階 一之程式化；及確認該氮化物捕捉記憶體單元内位階二之程式化。 9· 一種在一具位階一程式化、位階二程式化及位階三程式化之記 憶體陣列内一氮化物捕捉記憶體單元之一多重位元單元裡進行一 多重位階單元程式化的方法，該方法包括·· 進行該氮化物捕捉記憶體單元内之一位階三的程式化； 在該位階三程式化後，決定該氮化物捕捉記憶體單元是否需要 該位階一程式化及該位階二程式化。 22 Chinese_Macr〇nix-P940126 031406 1297500 10·如申請專利範圍第9項之方法，更包括進行該位階二之程式 化，如果該氮化物捕捉記憶體單元需要該位階一程式化或該位階 二程式化。 11·如申請專利範圍苐10項之本法，更包括進行一位階一之程式 化。 12·如申請專利範圍第9項之方法，更包括進行該位階一程式化及 該位階二程式化，如果該氮化物捕捉記憶體單元不需要位階一程 式化或位階二程式化。 U·如申請專利範圍第12項之方法，更包括自該位階一程式進行 該位階二的程式化。 14·如申請專利範圍第9項之方法，更包括進行該位階二程式化， 如果該記憶體陣列内之一程式化單元需要該位階一程式化或該位 階二程式化。 Μ·如申請專利範圍第9項之方法，更包括進行該位階一程式化及 該位階二程式化，如果該記憶體陣列内之一程式化單元不需要該 位階一程式化或該位階二程式化。 23 Chinese_Macronix-P940126 0314061297500 X. Scope of Application • L A method of stylizing a four-bit nitride capture memory cell, a multi-bit cell • a multi-level cell, the method comprising: early detection of the disordered capture In the bean, the stylization of the third dimension has a third starting voltage level; a stylized one in which the stylization of the second order has a second starting voltage level; and after the stylization of the level, the nitride captures a level within the memory unit - Stylized, wherein the programming of the level one has a first starting voltage level; wherein the third starting voltage level is higher than the second starting voltage level, and wherein the second starting voltage level is higher than the first A starting voltage level. 八^2· The method of claim 1 includes the stylization of the level 2, if the stylization of the level 3 has passed the one-order three confirmation test. 3. The method of applying for the first paragraph of the patent scope further includes performing the stylization of the rank one, if the stylization of the rank 2 has passed the one-order second confirmation test. The method of claim 1 of the patent scope further includes confirming the The nitride capture memory t-level three-hybridization; the stylization of one of the nitride-capture memory cells, and the stylization of the rank of the nitride-capturing memory cell. f. A method of staging a memory array to capture a multi-level cell in a memory cell, the method comprising: Chinese JVlacronix-P940126 031406 1297500 - Performing a stylization of one of the rank three in the nitride capture memory cell After the three-level programming of the level, a stylization of a level 1 in the nitride capture memory unit and a programming of a first order two are performed, wherein the level two programming is programmed to the level of a stylization; After the program is programmed, the program of the level 2 in the nitride capture memory unit is started from the stylization of the level 1 by a starting voltage. Wherein the starting voltage level of the three-stylized level of the level is higher than the starting voltage level of the two-level programming of the level, and wherein the starting voltage level of the two-stylized level of the level is higher than a stylized starting voltage level of the level 6. The method of claim 5 of the Shenqing patent scope further includes performing the stylization to the rank one, if the third-order stylization has passed the one-step three-confirmation test. 7. The method of claim 6 Further, the stylization of the second order is performed, if the staging of the rank has passed the one-step confirmation test. 8. The method of claim 7, further includes confirming that the nitride capture memory is in the early element. The 3⁄4 two spears are made, and the stylization of the level 1 in the memory cell is confirmed; and the stylization of the level 2 in the memory cell is confirmed. 9. A method for performing a multi-level cell stylization in a multi-bit cell of a nitride-capturing memory cell in a memory array with level-level stylization, level two-programming, and level three-programming The method includes: performing a stylization of a level III in the nitride capture memory unit; after the three-stylization of the level, determining whether the nitride capture memory unit requires the level-stylization and the level 2 Stylized. 22 Chinese_Macr〇nix-P940126 031406 1297500 10. The method of claim 9, further comprising performing the programming of the level 2, if the nitride capture memory unit requires the level of a stylization or the level 2 stylization . 11. If the patent application scope is 10, the law includes a step-by-step stylization. 12. The method of claim 9, further comprising performing the level stylization and the level two programming, if the nitride trapping memory unit does not require a level 1 or a level 2 stylization. U. For example, the method of claim 12 of the patent scope further includes the stylization of the level 2 from the program of the rank. 14. The method of claim 9, further comprising performing the second programming of the level, if a stylized unit in the memory array requires the staging of the level or the staging of the level. The method of claim 9 further includes performing the programming of the level and the programming of the level, if a stylized unit in the memory array does not require the staging or the second program Chemical. 23 Chinese_Macronix-P940126 031406