TWI297366B - Semiconductor device including mosfet having band-engineered superlattice - Google Patents

Description

1297366 玖、發明說明： 【發明所屬之技術領域】 本發明係有關半導體之領域，且特別是有關於以能帶工程卜^以灯 band engineering)為基礎而具有增進特性之半導體及其相關之方法。 【相關申請案】 本申請案係為2003年6月26日申請，題為「具有增進之傳導等 效質量之半導體構造」（“Semiconductor Struetures Ifeviiig Improved Conductivity Effective Mass”)及「製作具有增進之傳導等效質量半導體 構造之方法」（“Method of Fabricating SemiecmduetOT Stmetures Ifeviiig Improved Conductivity Effective Mass，，)之美國專利第 10/603.696 %.Ά 第10/603,621號兩申請案之部份連續申請案(Continuation-in-part apphcation)。該兩案之整體揭示内容在此列為本發明之參考資料。 【先前技術】 利用諸如增強電荷載體(charge carriers)之遷移率(mobility)，以便 增進半導體元件性能之相關結構及技術，已多有人提出。例如，Cunie 等人之美國專利申請第2003/0057416號案中揭示了矽，矽_鍺 (silicon-germanium)，與釋力石夕(reiaxed silicon)，以及包括了原本將合 導致性能劣退的無雜質區(impUrity_丘ee z〇nes)等的形變材質^ (strained material layers)。其在上石夕層中所形成的雙軸向形變化 s^ain)改變了載體的遷移率，並得以製作較高速與/或較低功 ^。Fitzgerald等人的美國專利申請公告第2003/0034529號案中則揭 示了同樣亦以類似的形變石夕技術(strained siHcon )為其“二 ，（:MOS ^ 。 马暴礎的1297366 玖, DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to the field of semiconductors, and more particularly to semiconductors having enhanced characteristics based on band engineering, and related methods . [Related application] This application is filed on June 26, 2003, entitled "Semiconductor Struetures Ifeviiig Improved Conductivity Effective Mass" and "Production with Enhanced Conduction" "Method of Fabricating SemiecmduetOT Stmetures Ifeviiig Improved Conductivity Effective Mass," US Patent No. 10/603.696%. Ά No. 10/603,621, part of the consecutive applications (Continuation- In-part apphcation. The entire disclosure of the two cases is hereby incorporated by reference. [Prior Art] Utilizing, for example, enhancing the mobility of charge carriers to improve the performance of semiconductor components Structures and techniques have been proposed, for example, in US Patent Application No. 2003/0057416 to Cupie et al., which discloses silicon, silicon-germanium, and reiaxed silicon, and includes A deformed material such as an impurity-free zone (impUrity_丘 ee z〇nes) that would cause poor performance ^ (strained material layers). The biaxial shape change s^ain formed in the layer of the upper layer changes the mobility of the carrier and enables higher speed and/or lower work. Fitzgerald et al. U.S. Patent Application Publication No. 2003/0034529 discloses that a similar strained siHcon is also used as its "two, (: MOS ^ .

Takagi的第6,472,685 B2號美國專利中揭示了一種半導體元件， 包含有夾在石夕層之間的一層石夕及破層，以使其第二石夕層的傳導檸 (conduction band)及鍵結能帶(vaience band)承受伸張形變(t ·】 有較小等效質量(effeCtivein㈣，並由施加於閘電極上的带 琢所誘卷的電子，便會被限制在其第二矽層内，因此即假】 道MOSFET得以具有較高的遷移率。 心疋其η通U.S. Patent No. 6,472,685, issued to U.S. Patent No. 6, 472, the entire disclosure of which is incorporated herein by reference to the entire disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of the disclosure of The vaience band is subjected to tensile deformation (t ·). The smaller equivalent mass (effeCtivein (4), and the electrons trapped by the band applied to the gate electrode are confined to the second layer. Therefore, the false MOSFET can have a higher mobility.

Ishibashi等人的第4,937,2〇4號美國專利中揭示了一種超晶格，宜 中包含一整層的或部份層的雙元化合物(binary c〇mp_d)的半曰 192130133號專利申請案 $明專利說明書無劃線修訂本 2〇〇8年3月修訂 ，包3整層的或部份層的雙元化合物(binary compound)的半導體層 夕層於八個單層(monolayer))結構，係交替地以磊晶成長(epkaxial 的方式增長而成。其中的主電流流動方向係垂直於超晶格中的 各層平面。U.S. Patent No. 4,937, issued to U.S. Patent No. 4,937, issued to, the entire entire entire entire entire entire entire entire entire entire entire entire content The patent specification is not revised. The revision of the patent document is carried out in March, 2008. The semiconductor layer of the whole layer or part of the binary compound is composed of eight monolayer structures. The growth is alternately epitaxially grown (epkaxial) in which the main current flow direction is perpendicular to the planes of the layers in the superlattice.

Wang等人的第5,357，119號美國專利中揭示了 Si-Ge的一種短週 ，超晶格(short period superlattice)，利用減低超晶格中的合金散佈 (alloy scattering)而達成其較高的遷移率。依據類似的原理，Canddaria 的美國弟5,683,943號專利中揭示了 一種具增進遷移率之mqsfeT， 其通^層(channel layer)包括有石夕之一種合金與第二種物質，此第二種 速質係以能使通道層處於伸張應力(tensile批哪)況態下的百分比而於 石夕晶格之中替代性地出現。 丁犯的第5,216,262號美國專利中揭示了一種量子井(quantum well) 構這，其包含有兩個屏蔽區(barrierregion)，以及夾於其間的一薄層的 磊晶長成半導體層。其每一屏蔽區各係由厚度範圍大致在二至六個交 疊SiO^Si之單層所構成。屏蔽區之間另亦夾有矽材質的一段遠為較 厚的段落。 2000年9月6日線上發行的應用物理及材料科學及製程(AppliedA short period superlattice of Si-Ge is disclosed in U.S. Patent No. 5,357,119, the entire disclosure of which is incorporated herein by reference. Mobility. In accordance with a similar principle, a mqsfeT having an improved mobility is disclosed in U.S. Patent No. 5,683,943, the entire disclosure of which is incorporated herein by reference. The channel layer is replaced by a percentage of the tensile stress in the state of the tensile stress. U.S. Patent No. 5,216,262 to U.S. Patent No. 5,216,262, the disclosure of which is incorporated herein by reference to the entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire entire all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all all Each of the shielded regions is composed of a single layer having a thickness ranging from approximately two to six overlapping SiO^Si. A section of the material that is too thick is also placed between the shielded areas. Applied Physics and Materials Science and Processes (Applied), published online September 6, 2000

Physics and Materials Science & Processing) ρρ· 391 - 402 之中，Tsu 於 一篇通為「石夕質奈米構造元件中之現象」in silk⑽ nanostructure devices”)的文章之中揭示了矽及氧的一種半導體_原子超 晶格(semiconductor-atomic superlattice，SAS)。此 Si/O 超晶格構造被揭 ^是為一種有用的石夕量子及發光元件。其中特別揭示了如何製作並測 試一種綠色電輝光二極體(electroluminescence diode)的結構。該二極體 結構中的電流流動方向是垂直的，亦即，垂直於SAS的層面。該文 中所揭示的SAS可以包含由諸如氧原子及C0分子等的被吸收^質 (adsorbed species)戶斤分離開的半導體層。在氧的此被吸收單層以夕卜戶^ 長成的矽，被描述是為磊晶層，並具有相當低的缺陷密^(defect density)。其中的一種SAS結構包含有一個ΐ·ι邮厚度的石夕質部份， 其係約為八個原子層的石夕，而其另一種結構中的石夕質部份的厚度則有 此厚度的兩倍。物理評論通訊(Physics Review Letters)，Vbl 89 No 7 (2002$年8月12日）中，Luo等人所發表的一篇題為「直接間隙^光矽 之化學設計」（“Chemical Design of Direct-Gap Light-Emitting Silicon，，） 的文章，更進一步地討論了 Tsu的發光SAS構造。Physics and Materials Science &Processing; ρρ· 391 - 402 Among them, Tsu reveals the enthalpy and oxygen in an article entitled "Phenomenon in the stone (10) nanostructure devices" A semiconductor-atomic superlattice (SAS). This Si/O superlattice structure is revealed as a useful Shixi quantum and illuminating element, which specifically reveals how to make and test a green electric The structure of an electroluminescence diode. The direction of current flow in the diode structure is vertical, that is, perpendicular to the surface of the SAS. The SAS disclosed herein may include molecules such as oxygen atoms and C0 molecules. The semiconductor layer separated by the absorbed species, which is formed by the absorption of a single layer of oxygen, which is described as an epitaxial layer and has a relatively low defect density. ^(defect density). One of the SAS structures contains a stone-like part of the thickness of the ι·ι, which is about eight atomic layers of Shi Xi, and the other part of the structure is the stone part. The thickness is twice that thickness. In Physics Review Letters, Vbl 89 No 7 (August 12, 2002), an article published by Luo et al. The article "Chemical Design of Direct-Gap Light-Emitting Silicon," further discusses the luminescent SAS structure of Tsu.

Wang，Tsu及Lofgren等人的國際申請公報w〇 02/103,767 A1號案 1297366 ， 第92130133號專利申請案 、 發明專利說明書無劃線修訂本 2008年3月修訂 ^揭示了薄矽及氧，碳，氮，磷，銻，砷或氫的一種屏蔽建構區 其可以將垂直流經晶格的電流減小超過四個十之次方冪次尺度 orders of magnitude)。其絕緣層/屏蔽層可容許在鄰接著絕緣層$虛= 要沉積的磊晶石夕層中形成較少的缺陷。 工等人的英國專利申請第2,347,520號案中揭示，非週期性光 工月匕’間隙構造(aperiodic photonic band_gap，APBG)可應用於電子处 帶$隙工程(electronicbandgapengineering)之中。特別是了該一請案g ，不’材料參數(material parameters)，例如，能帶最小值的位^，、辇International Application Bulletin of Wang, Tsu and Lofgren et al., WO 〇 02/103, 767 A1, 1297366, Patent Application No. 92130133, Patent Description of the Invention, Unlined Revision, Revised March 2008, Reveals Thin and Oxygen, Carbon A shielding construction of nitrogen, phosphorus, antimony, arsenic or hydrogen that reduces the current flowing vertically through the crystal lattice by more than four power orders of magnitude. The insulating/shielding layer allows for the formation of fewer defects in the layer of the epitaxial layer adjacent to the insulating layer. In the case of the British Patent Application No. 2,347,520, the non-periodic optical photonic band_gap (APBG) can be applied to electronic bandgap engineering. In particular, the request g, not the material parameters, for example, the bit with the minimum value ^, 辇

Sis、:？等’皆可ί以調節’以便獲致具有所要能帶結構特性的， f ## ° 5 ^t^(electrical conductivity), ϊίϊ:(腿1 C〇nduCtivi⑺及介電係數 磁係數(magneticpermeability)，皆被宣稱亦可能被設計於材料之;f 杜由工程領域之巾已有投人相當的努力，_增加半導體元 ί中的電何，體之遷移率，但其間仍有更大改進的需求。較大 ^可低元件的功率消耗。若有較大的遷移 、Jlk者70件的尺度細侍越來越小，元件仍可以維持較佳的性能。 【發明内容】 .-r:有之較 材接及的 源55S的災於 复ί:工;導K份的複數;固的堆疊基 1半㈣S各SiSis, :? Etc. 'Equipped to adjust' to obtain the desired properties of the band, f ## ° 5 ^t^(electrical conductivity), ϊίϊ: (leg 1 C〇nduCtivi (7) and magnetic coefficient (magnetic permeability), It has been claimed that it may also be designed in materials; f Du has been working hard on the towel in the engineering field, _ increasing the electricity and the mobility of the semiconductor element, but there is still a need for greater improvement. Larger ^ can reduce the power consumption of the component. If there is a large migration, the size of the 70-piece Jlk is smaller and smaller, the component can still maintain better performance. [Invention] [-r: Material connection and source 55S disaster in the complex: work; guide K parts of the plural; solid stack base 1 half (four) S each Si

方向上具有tbJfe二非+導體早層，以使超晶格在平行 中具有存掏知的電荷鑛遷移率。超晶格通H 中，中之厂。在某些較佳實施例之 1297366 第92130133號專利申請案 發明專利說明書無劃線修訂本 2008年3月修訂 ΐΐϊϊΞϊϊ單層的厚度，例如二至六個單層的厚度，如同在某些 隙。結果，超晶格通道更可具有—實f直接能帶間 Λ介有—閘％極層，與閘電極層及基底半導體蓋層之間的一 之之中’所有的基底半導體部份全皆為相同數目單層 論if單基底半導體部份之中的至料些係為不 目單層之厚度。每—個非半導體單層在下一層沉』 體n固ϋΐίϊ部份各可包含有* w族半導體，m_v族半導 每-所構成之群組中選定的一基底半導體。此外 中選包含有由氧，氮，i及碳氧所構成之群組 專。tit電ϊ載體遷移率，係為較低導電性等效質量所導致之!士 八彳 1等效質量係比無雜構_導電性等效質量之： 刀之一為低。當然，超晶格通道内更可包含有至少一種導電性摻雜物^ 【實施方式】 明太Si本所關式，後面的綱文字段落之巾將詳細說 不1形式實地施行，因此本發明之料 使之實Ϊ例上。相反的，此些實補僅是被提供ΐ 料。在本發_整篇說 示⑽當的元件’而加撇φ—符號則係用 2ϊίίΐ辮別’創造以及使用，以便將其應“半ίίί=&amp; 1297366 一 第92130133號專利申請案 、 發明專利說明書無劃線修訂本 2008年3月修訂 本發明案申請人所提之理論顯示，本發明此地所揭示描述的某些 超晶，構造，可$減小電荷載體的等效質量，並可由於此種減小而導 • 致電荷載體的較高遷移率，但申請人同時聲明本發明之範疇不應限定 於此理論上。本發明所屬技藝領域内的文獻之中，對於等效質量有多 ， 種定義加以描述說明。作為等效質量上之增進的一種量測尺度，申請 人分別為電子及電洞分別使用「導電性反等效質量張量」(“c〇nductivity reciprocal effective mass tensor”) M/1及的定義： Σ J(V^(k5W))/(V^(k,n))7.组逆^，Γ)Α Μ；^(^,Γ) =㈣ B，z.__ 泥_ ’ Σ \KE{Kn\EFJ)d\ e&gt;ef B.Z. 為電子之定義，以及： - Σ f (V^(k^)).(V^(k?n)).d3k = ___dA_ Σ ](^f(m,n\EF9T))d3k e&lt;ef B.z· •則為電洞之定義，其中/係為費米-狄拉克分佈(Fermi-Dirac distribution) ’ EF為費米能量(Fermi energy)，T 為溫度，E(k，n)為電子 在對應於波向量k及第η個能帶的狀態之中的能量，下標丨’及]係指 直交座標X，y及z，積分係在布里羅因區(Β·ζ·，Brillouin zone)内進行， 而加總則是在電子及電洞的能帶分別高於及低於費米能量的能帶之 中進行。 ^申請人對導電性反等效質量張量之定義，係使得材料之導電性反 等效質量張量之對應分量中的較大數值者，其導電性的一張量分量 (tensorial component)亦得以較大些。在此申請人再度提起下述理論， 即此地所描述說明之超晶格所設定導電性反等效質量張量之數值11，係 可增進材料的導電性質，諸如電荷載體傳輸的典型較佳方向之性質' ，過’同樣地，申請人仍聲明本發明之範疇不應限定於此理論上。、適 當張量項數的倒數，在此被稱為是導電性等效質量。換句話說，若要 描述半導體材料構造的特性，則前述電子/電洞的導電性等效質量，以 及在載體預定要傳輸的方向上的計算結果，便可用來分辮出功峙 有增進的該些材料。 1297366 第92130133號專利申請案 、 發明專利說明書無劃線修訂本 2008年3月修訂 應用前述方法便可為特定目的而選出具有較佳能帶構造 CMOS元件通道區(channelregion)内具有超晶格25的材料 /搂 的一種實例。下面將參考圖1說明包含有依據本發明之超 一個平面型MOSFET 20。不過，習於本技藝者所可以理， 地所分辮出來的材料係可以應用於許多種不同型態的丰導 上，諸如離散式元件及/或積體電路。 守殿兀什 圖中所描述的MOSFET20包括有一底材(substrate) 21 ，22，23，源極級極延伸區26，27，以及由超晶格所提 夾於其間的一通道區。源極/汲極金屬矽化物層(s〇urce/drain s layers) 30，3卜以及源極/汲極接觸32，33係疊覆於源極/汲極區 於本技藝者所可以理解的情形。虛線34，35所標示的區域 為原先與超晶格一起形成的選擇性殘跡部份(〇pti〇nal vesti kj portions)，但其後則以濃滲透處理。在其他之實施例之中，此些歹I 超晶格區34，35亦可能不存在，如同習於本技藝者所可以理 圖中顯示閘極35包括有鄰接著由超晶格25所提供通道的一 層37」以及在閘極絕緣層之上的一閘電極層36。圖中2M〇sfet^〇 亦顯示包含有側壁隔絕層(sidewall spacer) 40，41。 ^請人已分辮出MOSFET 20之通道區的改良材料或結構。更特 定而言，申請人已分辮出一些材料或構造，其能帶結構之中，電 /或電洞之適當導電性等效質量，較之石夕的對應數值，乃是相當低得多二 ^著同，參考圖2及3，其中的材料或結構係屬超晶格25的形 式，其構造係在原子或分子的尺度上加以控制的，並可以利用習知的 原子或分子層沉積的技術(techniques of atomic or molecular layer deposition)製作形成。超晶格25包括有以堆疊形式安排的多個層組 (ay，rgroups)45a-45η，由圖2中的示意橫截面圖即可以瞭解其堆疊 關係。 ㈣ί ϋ的f 一個層組45a — 45η，如圖所示包含有界定了一個 別基，半導^4份(base semiconductor portion) 46a - 46η 的多個堆疊 f ί 半導體單層(baSe Semiconductor monolayer) 46 ’ 以及其上的一個 ，帶修改層(energy-band modifying layer) 50。λ 了說明清楚之故，能 帶修改層50於圖2之中係以雜點加以標示。 圖中之能帶修改層50包含有被限制於其鄰接基底半導體部份的 日日體日日格内的一個非半導體單層(n〇n_SemjC〇n(jUct〇r m〇n〇layer)。在其 11 1297366 第92130133號專利申請案 、 發明專利說明書無劃線‘訂本 2008年3月修訂 之中’、多於—個的此種單層亦是可行的。申請人再度提出 • ^述玲3二/f同樣地申請人仍聲明本發明之範疇不應限定於此理論 士二^卩此帶修改層50及其所鄰接之基底半導體部份46a_46n，會使 - 之方向上的電荷載體，較無此安排者，具有 iit ϊΐίί性等效質量。考慮另-種方式，其中此平行方向係與 f 向3。能帶修改層5G亦可能使超晶格25具有_般常見的 。f ^明之理論顯示，諸如圖中所顯示的m〇sfet 2〇之類 以看?車電性等效質量，亦可以享有 巧ΐΐ體遷移率。在某些實施例之中，亦由於本發明所達成的 果丄超ί格25亦可以具有—個實質的直接能帶間隙，其 對光電70件而言乃係特別地適合，如同後面所將詳細說明的情形。 ^ =同熟習於本技藝，所可以理解的，M0SFET 20的源極/没極區 二3及閘極35，可被認為是為可以導致電荷載體以相對於堆疊層 ί :樣4方傳輸通過超晶格的作腦域。本發明 、圖中亦顯示超晶格25包括有頂部層組45η之上的一個蓋層, =0 52。蓋層52亦可包含多個的基底半導體單 曰^ 擁有2至励個單層的基底半導體，且最佳應有1〇至別個胃單層 母一個的基底半導體部份46a-46η，可以包含有由ιγ族丰導f 導體，以及㈣辭導體等所域體」 個基底半導體。如同熟習於本技藝者 二 當然亦包含了 IV-IV族的半導體。 卿nv財導體凋 ^每一層的能帶修改層50可以包含有由諸如氧，氮，氟，以及讲 氧等的組合之中選定的一種非半導體(non_semicond t If 3利2對接續的-層進行沉積以鑛程的進行，而亦^擁 1的熱穩定性(thermally stable)。在其他的實施例之中，如 ^ 4者所可以理解的，非半導體亦可為相容於特定半導製^ ㈣-種織或錢滅化合物。 爾理ί壬序 應予注意的是，單層一詞在此亦應包含單原子芦( · layer)以及單分子層(single molecular layer)。另亦▲、:主：的甘山 子層所提供的該些能帶修改層5〇,亦應孟以5填 底半導體材質，及以氧作為能帶修改材質的，一種、4/\、5‘|念急基 12 1297366 - 第92130133號專利申請案 、 發明專利說明書無劃線修訂本 2008年3月修訂 ，氧的可能位置被佔滿。在其他的實施例之中及/咬在不 ”ϊί情況之τ，如同f於本技藝者所可以理解的 ί if況。即如同此示意圖中所顯現的:、在二特定ΐ ίίΐ者沿—平面射地制，侧ί原= 商被廣泛地應用於—般的半導體製程之中，製造 即用ί發日月所描述的方式來應用此些材質。 意的，半導體元件即得以立即而方便 在此申請人提出下述理論，但申請人聲明本發明之 宗 於此理論上，即，就一個超晶格而言，諸如si/〇 、 好應或更少，以使超晶格的能帶在整體範圍内共通▲相 f f而言，其獅顯現了 x方向上電子及_峨佳ΐϊϊ。 =或ίί子(就大範圍的石夕而言具等向性)經計算過的導質 ί 。同樣的，電洞方面的計算所得結果，大顧石夕的ίί 為〇·36，4/1 Si/O超晶格則為〇·ΐ6，兩者比例為〇·44。 歡值 /種方向取性上的特性對某些半導體元件而言可能有利，但 體元件之中，平行於層組的群組平面中任何方向^遷移ΐ ^均，增加，則可能更為有利。對習於本技藝者而言，電子 $ 增加，或只有其中一種電荷載體遷移率的增加，亦〆皆可 超晶格25之4/1 Si/O實施例的較低導電性等效質量，可能晷 25=者而言皆然、。雜，超晶格25其中更亦可以 導電性摻雜質(conductivity dopant)，如同習於本技藝者所可 額外地同時參考圖4，接著描述依據本發明具有不同性質的 巧，的另一實施例。在此實施狀中，其重覆模式是超1 言，最底下的基底半導體部份46a，具有三個單層，而第二最ί 層的基底半導體部份46b，則有五個單層。此種組合模式在整個超晶| 13 1297366 第92130133號專利申請案 、 發明專利說明書無劃線修訂本 2008年3月修訂 * 25 層之平面中的指向無關的。圖4之中㉝曾進是與各 係與前述圖2中所討論者類似，故的其他構造部份 可能為；同數目厚部份，其厚度 少_基底半導體部份，KJ可晶，至 在另外的實施例之中，超晶格的所有基^丰導 I $厚度。 完全是為不同數目單層疊合之厚度。· v _邛伤，其厚度則可能 f ί f^?^(DenSity FunCti〇nal ^ory, DFT) ‘ ί 麵fcorrection”)加以偏移。不過，能帶的形狀則是公認 遂較為可罪。縱軸的能帶尺度應在此等認知之下加以考量。 〜 圖5A為，知技藝中之整體區塊碎（bulk silicon，實線表示)以及圖 之炉帶Si/=晶格(虛線)，兩者由迦瑪1點⑼之處計算得 1中之方向係指4/1似〇結構之單位晶元_ 又早位晶兀，雖然圖中其(001)之方向係與Si之一般 =曰曰^向符合，並因而顯示了 Si傳導能帶最小值義待 方中的方向係與沿之一般單位晶元的(110)及(·110) $向1於本技藝者可以理解，圖中Si之能帶係以摺合方向顯 似0構造的適當反晶格方向(reCipr〇Cal lattiCe direCti〇nS) 見到，雛触她之下，4/1 ’構造傳導能帶最小 ，巧迦碼點(G)之處，而其鍵結能帶的最小值則是出現在(⑻丨)方 H里兹羅因區的邊緣，稱之為z點之處。另亦可以注意到，4/1 ’ 構導能帶最小值之曲率，與Si的傳導能帶最小值曲率比較之 了丄/、較大的曲率’係起因於額外氧層引入了擾亂所造成的能帶分離 之故。 圖5B為習知技藝中之整體區塊矽(實線)以及圖i - 3中所顯示之 4/1 Si/O超晶格25 (虛線），兩者由Z點之處計算得之能帶構造之曲線 圖。此圖中所顯示的是(1〇〇)方向上鍵結能帶之增加的曲率。 圖5C為習知技藝中之整體區塊矽(實線)以及圖4中所顯示之 14 1297366 第92130133號專利申請案 、 發明專利說明書無劃線修訂本 2008年3月修訂 5=1/3/1 Si/O超晶格乃’（虛線），兩者由迦碼及2點之處 構造之曲線圖。由於5/2/3/:1 Si/〇構造的對稱性，在(1〇〇) 於(〇〇1)的堆疊方向上，導電性等效f量及遷移率，可以 預期疋4向性的。注意到在5/1/3/1 Si/O的實例之中，僂導沪鹞异丨 ΐϊ ί f ^值兩者皆位於或近於Z點之處。雖然曲率^增加^ 為寺效質罝減小的一個指標，但經由導電性反等效質量張#^曾疋 仍可以進行適當的比較及判別。此使得本案申請人進一ϋ， 5^1/3/1的超晶格25’實質上應是為直接的能帶間隙。如同習於本^蓺 者所可以理解的，可供光學轉移(Gptieal加驗)的適|矩㈡殳 fiatnx element)乃是直接及間接能帶間隙行為間之區別的另一種指 標0 m/rrl面η同日守苓考圖6A-6H，其中討論利用前述超晶格25，在製作 ^ 電晶體的一種簡化CM〇S製程中形成通道區的情 ^。，實例製程係由具&lt;1〇〇&gt;指向的淡摻雜p型或單晶矽的八英 ΐ 402開始。此實例之中顯示一 及一 PM0S兩電晶體的 形成情形。在圖6A之中，深N井404被植入於底材402中以便進行 二3 3^之中，使用已知技術所製傷的沿仏/私凡遮罩被用來分 j形，N井區及p井區406，408。此會，例如，牵涉到n井及p井 植入(implantation)，剝離(strip)，驅入(drive-in)，清洗，以及再生長 (re-g^〇wth)的步驟。剝離步驟所指的是遮罩(在此實例中為光阻及氮化 石移除。驅入步驟被用來將摻雜質定置於適當的深度之處，這是 假，:植入程序是為低能量(即8〇 keV)而非高能量(200-300 keV)的植入 程序。典型的驅入條件應為IKKMl^C下植入處理94〇小時。驅入 的$驟亦同時將因植入所造成的損傷予以回火(anneal〇ut)。若植入處 王以足將離子打入至正確深度的足夠能量進行的，則接著便進行回 步ΐ、，此回火處理的溫度較低，時間較短。清洗的步驟係在氧 卞步驟，則進行，以避免有機物，金屬等對爐具造成污染。可以達成 此點的其他方法或製程處理，同樣亦可以應用於此。 圖6C-6H之中顯示，一 NM〇s元件在一侧2〇〇 ,另一 pM〇s元件 另一侧400。圖6C顯示晶圓分區的淺溝隔絕，溝41〇先被银出 (=·3_0·8ΐΗη)，再生長一薄層氧化物，之後以Si〇2填充淺溝，接著再將 表面平坦化(planarized)。圖6D顯示本發明之超晶格作為通道區412， 414時被界疋並&gt;儿積的情形。先形成一層沿〇2層（圖中未顯示），再利 用原子層沉積法沉積形成本發明之超晶格，之後形成一磊晶矽蓋層， 再將表面平坦化以形成圖6D中所形成的構造。 15 1297366 - 第92130133號專利申請案 發明專利說明書無劃線修訂本 ' 2008年3月修訂 有一個較佳厚度以避免在閘極氧化物生長，或任何 ; = Iff時造ί超晶格的耗損，而同時並可使矽蓋層的厚 ί ^，以在超晶格内縮短任何傳導的平行路徑。根據 大約會將其底下財層耗損45%的習知關係，石夕! 可比長出的雜氧化物層厚度的45%加上—個小量的增幅 Ϊ要ft 於本技藝者所f知的製程誤差。就本實施例而 ^大長iff個％埃(angStr〇m)厚度的閉極，石夕蓋層的厚度便可 i it極^化物層416及閘極418本身形成之後元件的構 念了要1作此些各層，先沉積閘極氧化物的一薄層，再進行多晶 f 的步驟，之後區分成形，並再進行蝕刻。多晶 /儿巧係彳日利用低壓化學氣相沉積法^ 曰LPCVD)將石夕沉積於一層氧化層上(其因此亦形成了 一種多 日日;^^(polycrystalline material))。此步驟包含以p+或as_進行摻雜， 以使其具‘電性，而整層的厚度則約為25〇nm。 ’ 、此步驟係依實際的製程而定，因此250咖的厚度只是一個例子。 成像f驟(patterning step)係由光阻的旋轉，供烤，曝光(光學影步驟）， 光阻定像(developing resist)等處理所構成的。通常，圖形接著 移到在鍅刻步驟之中作為蝕刻遮罩的另一層(氧化物或氮化物層） ΐ蝕刻6^步驟典型是屬於針對材料有選擇性的電漿蝕刻(非等 向性，乾钱刻)處理(例如對矽的蝕刻較對氧化物快上1〇倍者），並 微影的圖形轉移到相關的材料上。 圖6F之中’淡摻雜的源極與沒極區420，422即可形成相鄰通道 ^4及426。此些區係利用n型及p型ldd植入，回火，以及清洗的 處^而製成的。”LDD”係指n型淡摻雜的汲極，或在源極側，p型的 ^払雜源極。此係為與源極/汲極相同離子型式的低能量/低濃度植入 f理。在LDD植入之後便可以進行一次回火的步驟，不過，依特定 製私而定，此回火處理也可能可以省略掉。清洗的步驟則是屬一種化 f蝕刻的處理，其可在氧化物層進行沉積之前先將金屬及有機物去除 掉0 圖6G中顯示隔離層428的形成及源極與汲極的植入。先沉積一 巧Si〇2遮罩並進行回蝕刻(etchback)。再利用n型及p型離子植入以 形成源極及沒極區430 ’ 432，434與436。之後此構造即進行回火及 16 即抛㈣號⑽ 請案 發明專利說明書無割線修訂本 2008年3月修訂 i 不金屬石夕化物的自動對準成形，亦即習知 ί ίif石夕化合(saiicidati〇n)的處理。自動對準金屬石夕化合的製 ^=括金屬沉積(例如ή)，氮氣回火，金屬餘刻，以及第1二^ 回火4處理。此當然僅只是本發明所可以應用於其中 #儀綱乡細 用及使用情形。在其他的製程及元件之中，本發明構 的-部份或全部範酬製作形成。 仏知了以在曰曰0 $據本發明之另一種製程，其中不使用選擇性沉積的作法反 =，“可f形成一毯覆層，並可應用遮罩的步驟來將元 件之間的材料移轉，例如，利用STI區域來作為侧的阻播$將此 1=利用在成像的氧化物/石夕晶圓上進行控制下的沉積處理而達^。 子層沉積工具的使用在某些實施例之中可能是不需要、的。例如，單; 也可以應用CVD工具，在與控制單層時相符相容的處理條件之下^ 形成，如同習於本技藝者所可以理解的。雖然前面討論了平坦化，但 製^的實施例之中，平坦化的處理可能是不需要的。超晶格結 構也可以在STf區之前先形成，以便去掉遮罩的處理步驟。此外，在 他變化作法之中，超晶格結構則可以，例如，在井區形成 $不同的說法來考量，本發明之方法可以包括形成一個包含有多 個堆疊的層群組45a-45n。本發明之方法亦可以包括，在相對於堆疊 層群組的平行方向上，形成可以造成電荷載體傳輸通過超晶格的^ 域。^晶格的每一個層群組可包含有界定了一個基底半導體部份的多 個堆疊的基底半導體單層以及其上的一個能帶修改層。如同前述，能 帶修改層可以包含有限定於其相鄰基底半導體部份的一晶體晶格内 的至少一個非半導體單層，以使超晶格中得以具有一個共同能帶 (common energy band)構造，並具有比其他方式為高的電荷載體遷移 率。 與本發明相關聯之其他要點亦係揭示於與本案同時申請的，題為「具 有能帶工程建構超晶格之半導體元件」（“Semiconductor Device Including Band-Engineered Superlattice”），以及題為「具有能帶工程建 構超晶格之半導體元件製作方法」(“Method for Making Semiconductor Device Including Band-Engineered Superlattice”)的兩共同專利申請案 中，該兩案在此列為本案之參考。此外，習於本技藝者在瞭解了本案 於前述說明文字及附圖所描述的發明揭示内容的情況之下，當可推知 瞭解針對本發明的許多修改變動以及其他不同的實施例作法。因此， 17 1297366i33 號專利申請案 - 書無劃線修訂本 千3月修訂 、， 應予瞭解的是，本發明之範脅不應限定於前述特定實施例的範圍’其 他的修改變動及其他實施例仍應是屬本發明之精神範_。 ' 〔圖式之簡要說明】 ^1之示意圖顯示依據本發明一半導體元件之橫截面圖。 ^2之示意圖為圖1之超晶格之大比例放大橫截面圖。 g 3之立體圖顯示圖1中超晶格之一部份之原子結構。 ^4之示意圖為圖1之超晶格另一實施例之大比例放大橫截面圖。 _ 5八為習知技藝中之整體區塊矽以及圖1-3中所顯示之4/1 Si/O超 晶格，兩者由迦碼點(G)之處計算得之能帶構造之曲線圖。 回B為習知技藝中之整體區塊石夕以及圖1 — 3中所顯示之4/1 Si/O超 脑晶格，兩者由2點之處計算得之能帶構造之曲線圖。 ° f習知技藝中之整體區塊石夕以及圖4中所顯示之5/謂Si/O超 日日格，兩者f 及Z點之處計算得之能帶構造之曲線圖。 據 之另—半導體元件—部^之製作^之横There is a tbJfe two non-conductor early layer in the direction so that the superlattice has a well-known charge-mine mobility in parallel. Super Crystal Pass H, the factory in the middle. In some preferred embodiments, 1297366, No. 92130133, the patent specification of the invention is not underlined. The revised thickness of the ΐΐϊϊΞϊϊ single layer, for example, the thickness of two to six single layers, as in some gaps. As a result, the superlattice channel can have a real-state direct-band inter-band Λ-gate % pole layer, and one of the gate semiconductor layer and the base semiconductor cap layer. The same number of single-layered if single-substrate semiconductor portions are the thickness of the un-monolayer. Each of the non-semiconductor monolayers in the next layer may comprise a *w family of semiconductors, and the m_v family of semiconductors each selected from the group consisting of a base semiconductor. In addition, the selection includes a group consisting of oxygen, nitrogen, i and carbon and oxygen. The mobility of the tit-electron carrier is caused by the lower conductivity equivalent mass! The equivalent mass of the tantalum 1 is lower than that of the non-homogeneous _ conductivity equivalent: one of the knives is low. Of course, the superlattice channel may further comprise at least one conductive dopant ^ [Embodiment] Ming Tai Si is closed, and the following paragraphs of the paragraph will be described in detail in the form of a solid, so the present invention It is expected to be an example. On the contrary, these actual supplements are only provided as materials. In the present article, the entire component (10) is labeled as the component 'and the φ-symbol is created and used by 2 ϊ ίί ΐ辫 以便 以便 以便 以便 以便 以便 以便 半 半 1 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 921 The specification of the applicant of the present invention is revised in March 2008. It is shown that certain supercrystals and structures disclosed in the present invention can reduce the equivalent mass of the charge carrier. Because of this reduction, the higher mobility of the charge carriers is induced, but the applicant also states that the scope of the invention should not be limited to this theory. Among the documents in the art to which the present invention pertains, there is Many definitions are described. As a measure of the improvement in equivalent quality, the applicants respectively use the "electrically conductive inverse equivalent mass tensor" for electrons and holes ("c〇nductivity reciprocal effective mass tensor" ” Definition of M/1 and: Σ J(V^(k5W))/(V^(k,n)) 7. Group inverse^,Γ)Α Μ;^(^,Γ) =(4) B,z .__ 泥 _ ' Σ \KE{Kn\EFJ)d\ e&gt;ef BZ is the definition of electrons, and: - Σ f (V ^(k^)).(V^(k?n)).d3k = ___dA_ Σ ](^f(m,n\EF9T))d3k e&lt;ef Bz· • is the definition of the hole, where / For the Fermi-Dirac distribution, EF is Fermi energy, T is temperature, and E(k,n) is the state of electrons corresponding to the wave vector k and the nth band. Among the energy, the subscripts 及' and ') refer to the orthogonal coordinates X, y and z, the integrals are carried out in the Brillouin zone, and the sum is in the electronics and holes. The energy bands are carried out in energy bands above and below the Fermi energy, respectively. Applicant's definition of the conductivity inverse equivalent mass tensor is such that the larger of the corresponding components of the conductivity inverse equivalent mass tensor of the material, the tensorial component of the conductivity Can be bigger. The Applicant hereby reaffirms the following theory that the value of the conductivity inverse equivalent mass tensor set by the superlattice described herein can improve the conductive properties of the material, such as the typical preferred direction of charge carrier transport. The nature of the 'over the same', the applicant still states that the scope of the invention should not be limited to this theory. The reciprocal of the appropriate number of tensor items is referred to herein as the conductivity equivalent mass. In other words, if the characteristics of the structure of the semiconductor material are to be described, the conductivity equivalent of the aforementioned electron/hole and the calculation result in the direction in which the carrier is intended to be transmitted can be used to improve the power. These materials. 1297366 Patent Application No. 92130133, Invention Patent Specification, Unlined Revision, Revised March 2008, Applicable to the foregoing method, a super-lattice 25 having a preferred energy band structure CMOS element channel region can be selected for a specific purpose. An example of a material/搂. An ultra-planar MOSFET 20 incorporating the present invention will now be described with reference to FIG. However, it is within the skill of the art to understand that the materials that are separated by the ground can be applied to a wide variety of different types of features, such as discrete components and/or integrated circuits. The MOSFET 20 depicted in the figure includes a substrate 21, 22, 23, source-level pole extensions 26, 27, and a channel region sandwiched by the superlattice. Source/drain s layers 30, 3 and source/drain contacts 32, 33 are overlaid on the source/drain regions as understood by those skilled in the art. situation. The area indicated by the dashed lines 34, 35 is the selective remnant portion (〇pti〇nal vesti kj portions) originally formed with the superlattice, but thereafter treated with concentrated permeation. In other embodiments, such 歹I superlattice regions 34, 35 may also be absent, as is apparent to those skilled in the art that the gate 35 includes abutment provided by the superlattice 25. A layer 37" of the channel and a gate electrode layer 36 over the gate insulating layer. 2M〇sfet^〇 in the figure also shows a sidewall spacer 40,41. ^Please have extracted the improved material or structure of the channel region of MOSFET 20. More specifically, the Applicant has delineated some materials or structures in which the appropriate conductivity equivalent mass of the electric and/or electrical holes is much lower than the corresponding value of Shi Xi. Referring to Figures 2 and 3, the material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular scale and can be deposited using conventional atomic or molecular layers. The technique of atomic or molecular layer deposition is formed. The superlattice 25 includes a plurality of layer sets (ay, rgroups) 45a-45n arranged in a stacked form, the stacking relationship of which can be understood from the schematic cross-sectional view in Fig. 2. (d) 层 f a layer set 45a - 45n, as shown, includes a plurality of stacked f λ semiconductor monolayers (baSe Semiconductor monolayer) defining an individual base, a semiconductor semiconductor portion 46a - 46n 46' and one of them, with an energy-band modifying layer 50. λ For clarity, the band modification layer 50 is labeled with noise in Figure 2. The energy band modification layer 50 in the figure includes a non-semiconductor monolayer (nU n_SemjC〇n (jUct〇rm〇n〇layer) which is confined to the day and day of the base semiconductor portion. Its patent application No. 11 1297366, No. 92130133, and the invention patent specification are not underlined, and it is also feasible to make more than one such single layer in the March 2008 revision. The applicant has again proposed • ^述3b/f Similarly, the Applicant still claims that the scope of the present invention should not be limited to the theoretical charge carrier 50 and its adjacent base semiconductor portion 46a-46n, which will cause charge carriers in the direction of - Compared with this arrangement, it has iit ϊΐίί equivalent quality. Consider another way, where the parallel direction is f to 3. The band modification layer 5G can also make the superlattice 25 have the same _. The theory of Ming shows that, like the m〇sfet 2〇 shown in the figure, it is also possible to enjoy the carotid mobility, and in some embodiments, also by the present invention. The fruit can also have a substantial direct energy zone. It is particularly suitable for the photovoltaic 70 piece, as will be explained in detail later. ^ = As is familiar with the art, it can be understood that the source/no-pole region 2 and gate of the MOSFET 20 35, which can be considered to be a brain domain that can cause the charge carrier to travel through the superlattice relative to the stacked layer. The present invention also shows that the superlattice 25 includes a top layer group 45n. a cap layer, =0 52. The cap layer 52 may also comprise a plurality of base semiconductors, a base semiconductor having 2 to a single layer, and preferably a substrate of 1 to a single stomach layer. The semiconductor portions 46a-46n may include a base semiconductor of a f-conductor from the ιγ family, and (a) a conductor, etc. As is well known to those skilled in the art, the IV-IV semiconductor is of course included. The energy band modification layer 50 of each layer may include a non-semiconductor (non_semicond t If 3 pair of 2 pairs of layers) selected from a combination of, for example, oxygen, nitrogen, fluorine, and oxygen. The deposition is carried out in the course of the mine, and the thermal stability of the Mally stable. Among other embodiments, as can be understood by those skilled in the art, non-semiconductors may also be compatible with a particular semiconducting compound. Note that the term single layer should also include monoatomic reeds and single molecular layers. Also, ▲, main: the energy band modification layer provided by the Ganshan sublayer 5〇, also should be filled with 5 semiconductor materials, and oxygen as a band to modify the material, a type, 4 / \, 5 '| 急急基12 1297366 - Patent No. 92130133 patent application, invention patent specification without The line revision was revised in March 2008 and the possible location of oxygen was filled. In other embodiments and/or biting in the τ situation, as is the case of the art, as can be seen by the skilled person, as shown in this diagram: in the second specific ΐ ίίΐ Plane shot system, side ί original = quotient is widely used in the general semiconductor process, manufacturing is to use these materials in the way described by 发 日 。. In the meantime, the semiconductor components are immediately and conveniently The Applicant proposes the following theory, but the Applicant declares that the invention is based on the theory that, in the case of a superlattice, such as si/〇, good or less, to enable the energy of the superlattice In terms of the overall range of ▲ ff, the lion shows the electrons in the x direction and _ 峨 ΐϊϊ. = or ίί子 (isometric in the case of a large range of stone eves) calculated conductivity ί. Similarly, the calculation results of the hole, the ίί of the 顾 石 夕 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 36 The directional characteristics may be advantageous for some semiconductor components, but among the body components, parallel to the layer group In any direction in the group plane, the migration ΐ ^ is increased, which may be more advantageous. For those skilled in the art, the electron $ increases, or only one of the charge carriers has an increased mobility, and all of them can be supercrystalline. The lower conductivity equivalent mass of the 4/1 Si/O embodiment of the lattice 25 may be 晷25=. The hetero-cell 25 is more conductive dopant. Another embodiment, which has different properties according to the present invention, will be described with additional reference to Figure 4, as will be appreciated by those skilled in the art. In this embodiment, the repeat mode is over 1, at the bottom. The base semiconductor portion 46a has three single layers, and the second most preferred base semiconductor portion 46b has five single layers. This combination pattern is used throughout the supercrystal | 13 1297366 Patent No. 92130133 The invention patent specification has not been stipulated in the revised version of March 2008. The orientation in the plane of the 25th layer is irrelevant. The figure 33 in Fig. 4 is similar to the various systems discussed in the above-mentioned Fig. 2, so other structures Partially possible; the same number of thick parts, the thickness Less _ base semiconductor portion, KJ can be crystallized, and in other embodiments, all bases of the superlattice are thick. It is completely different thickness for a single number of laminations. · v _ bruises, The thickness may be offset by f ί f^?^(DenSity FunCti〇nal ^ory, DFT) ' ί face fcorrection'). However, the shape of the band is recognized as more guilty. The energy band scale of the vertical axis should be considered under these cognitions. ~ Figure 5A shows the bulk of the art in the art (bulk silicon, solid line) and the furnace belt Si / = lattice (dashed line), which are calculated from the 1 point (9) of Gamma. The direction refers to the unit cell of the 4/1 〇-like structure _ the early crystal 兀, although the direction of the (001) in the figure is consistent with the general 曰曰^ of the Si, and thus shows that the Si conduction band is the smallest. The direction direction in the value of the waiting party and the general unit cell along the (110) and (·110) $ to 1 can be understood by the skilled person, in the figure, the energy band of Si is appropriately constructed in a folded direction. The anti-lattice direction (reCipr〇Cal lattiCe direCti〇nS) is seen, the younger one touches her, the 4/1 'construction conduction band is the smallest, the Qiaojia code point (G), and the minimum of the bond band The value appears at the edge of the ((8)丨) square H Rydroyne zone, called the z-point. It can also be noted that the curvature of the minimum of the 4/1 'conductance band is compared with the minimum curvature of the conduction band of Si. The larger curvature is caused by the extra oxygen layer introduced by the disturbance. The energy can be separated. Figure 5B is the overall block 矽 (solid line) in the prior art and the 4/1 Si/O superlattice 25 (dashed line) shown in Figure i-3, both calculated from the Z point Curve with construction. Shown in this figure is the increased curvature of the bond energy band in the (1 〇〇) direction. Figure 5C is an overall block 矽 (solid line) in the prior art and 14 1297366 No. 92130133 patent application shown in Fig. 4, the invention patent specification is not underlined revision, March 2008 revision 5=1/3 The /1 Si/O superlattice is '(dashed line), which is a graph of the structure of Gamma and 2 points. Due to the symmetry of the 5/2/3/:1 Si/〇 structure, in the stacking direction of (1〇〇) to (〇〇1), the conductivity equivalent f amount and mobility can be expected to be 疋4-directional. of. Note that in the example of 5/1/3/1 Si/O, both values are at or near the Z point. Although the curvature ^ increases ^ is an indicator of the reduction of the effect of the temple, it can still be properly compared and discriminated through the conductivity inverse equivalent mass Zhang #^ Zeng. This brings the applicant to the case that the 5^1/3/1 superlattice 25' should be substantially a direct energy gap. As can be understood by those skilled in the art, the appropriate moment (for the Gptieal test) is another indicator of the difference between direct and indirect band gap behavior. 0 m/rrl Fig. 6A-6H, which discusses the use of the aforementioned superlattice 25 to form a channel region in a simplified CM〇S process for fabricating a transistor. The example process is initiated by a lightly doped p-type or single crystal germanium octagonal 402 with a &lt;1〇〇&gt; pointing. The formation of one and one PM0S two transistors is shown in this example. In FIG. 6A, a deep N well 404 is implanted in the substrate 402 for performing two or three, and the edge/individual mask that is wound using known techniques is used to divide the j-shape, N. Well area and p well area 406, 408. This, for example, involves the steps of n-well and p-well implantation, stripping, drive-in, cleaning, and regrowth (re-g^〇wth). The stripping step refers to the mask (in this example, photoresist and nitride removal. The drive-in step is used to place the dopant at the appropriate depth, which is false, the implant procedure is Low-energy (ie 8 〇 keV) rather than high-energy (200-300 keV) implant procedure. Typical priming conditions should be 94 〇 hours for IKKMl^C implantation. The damage caused by the implant is tempered (anneal〇ut). If the implanted king is enough to drive the ions into the correct depth for sufficient energy, then the temperature of the tempering process is followed. Lower, shorter time. The cleaning step is carried out in the oxygen oxime step to avoid contamination of the stove by organic matter, metal, etc. Other methods or process processes that can achieve this point can also be applied to this. In the 6C-6H, one NM〇s component is on one side and the other pM〇s on the other side 400. Figure 6C shows the shallow trench isolation of the wafer partition, and the trench 41 is first silvered out (= · 3_0·8ΐΗη), regenerate a thin layer of oxide, then fill the shallow trench with Si〇2, and then planarize the surface (pla Narized. Figure 6D shows the superlattice of the present invention as a channel region 412, 414 when it is bounded and &gt; lumps. First, a layer of 〇 2 layers (not shown) is formed, and then atomic layer deposition is used. Depositing to form the superlattice of the present invention, then forming an epitaxial germanium cap layer, and planarizing the surface to form the structure formed in Figure 6D. 15 1297366 - Patent No. 92130133 Patent Application No-line Revision 'The March 2008 revision has a better thickness to avoid the growth of the gate oxide, or any; = Iff 造 超 super-lattice loss, while at the same time can make the 矽 cover layer thick ί ^, in the super Shorten any parallel path of conduction within the crystal lattice. According to the conventional relationship that will consume 45% of the underlying financial layer, Shi Xi! 45% of the thickness of the heterogeneous oxide layer added plus a small increase Ϊ It is necessary to ft the process error known to the skilled person. For the present embodiment, the thickness of the angstr〇m thickness is closed, and the thickness of the layer is ith. And after the formation of the gate 418 itself, the construction of the component has to be made for each of these layers, first to deposit the gate A thin layer of oxide is then subjected to a polycrystalline f step, which is then shaped and etched again. Polycrystalline/childry is deposited by a low pressure chemical vapor deposition method (LPCVD) On the layer (which therefore also forms a multi-day; ^ (polycrystalline material)). This step involves doping with p+ or as_ to make it "electrical, while the thickness of the entire layer is about 25 〇 nm. </ br /> This step is determined by the actual process, so the thickness of the 250 coffee is just an example. The imaging step is formed by the rotation of the photoresist, the baking, the exposure (optical shadow step), the developing resist, and the like. Typically, the pattern is then moved to another layer (oxide or nitride layer) as an etch mask during the engraving step. The etch 6^ step is typically a plasma-selective plasma etch (non-isotropic, Dry money engraving) (for example, the etching of germanium is 1 times faster than that of oxide), and the pattern of lithography is transferred to the relevant material. The lightly doped source and the non-polar regions 420, 422 of Figure 6F form adjacent channels ^4 and 426. These areas are made using n-type and p-type ldd implants, tempering, and cleaning. "LDD" means an n-type lightly doped drain or a p-type ^ dopant source on the source side. This is a low energy/low concentration implant with the same ion type as the source/drain. A tempering step can be performed after the LDD is implanted, but this tempering process may also be omitted depending on the particularity of the particulars. The cleaning step is a f-etching process that removes the metal and organic material prior to deposition of the oxide layer. 0 The formation of the isolation layer 428 and the implantation of the source and drain are shown in Figure 6G. A mask of Si 2 is first deposited and etchback is performed. N-type and p-type ion implantation are utilized to form source and non-polar regions 430' 432, 434 and 436. After that, the structure is tempered and 16 is thrown (four) (10). The invention patent specification has no secant revision. In March 2008, the automatic alignment forming of the non-metal lithium compound was also known, that is, the conventional ί ίif Shi Xihua ( Processing of saiicidati〇n). Automated alignment of metallurgical alloys = including metal deposition (such as ruthenium), nitrogen tempering, metal remnant, and 1st 2 tempering 4 treatment. Of course, this is only the case where the present invention can be applied to the use and use of the instrument. Among other processes and components, some or all of the invention is formed. It is known that in another process of the present invention, in which no selective deposition is used, "a blanket can be formed and a mask can be applied to The material is transferred, for example, using the STI region as the side of the blocking. $1=Using the deposition process under the control of the imaged oxide/shixi wafer to achieve the use of the sublayer deposition tool at some Some of these embodiments may be unnecessary. For example, a single CVD tool may also be applied under processing conditions compatible with controlling a single layer, as would be understood by those skilled in the art. Although flattening has been discussed above, planarization may not be required in the embodiment of the fabrication. The superlattice structure may also be formed prior to the STf region to remove the processing steps of the mask. Among his variations, the superlattice structure can be considered, for example, in the well region to form a different statement. The method of the present invention can include forming a layer group 45a-45n comprising a plurality of stacks. Methods can also include For the parallel direction of the stacked layer groups, a region is formed which can cause charge carriers to pass through the superlattice. Each layer group of the crystal lattice may include a plurality of stacked base semiconductors defining a base semiconductor portion. The single layer and one of the energy band thereon may have a modified layer. As described above, the band modification layer may include at least one non-semiconductor monolayer defined in a crystal lattice of its adjacent base semiconductor portion such that the superlattice It has a common energy band structure and has a higher charge carrier mobility than other methods. Other points associated with the present invention are also disclosed in the same application as the present application, entitled "Energy "Semiconductor Device Including Band-Engineered Superlattice", and "Method for Making Semiconductor Device Including Band" ("Method for Making Semiconductor Device Including Band") In the two joint patent applications of Engineered Superlattice", the two cases are hereby incorporated by reference. In addition, many variations of the present invention, as well as various other embodiments, are apparent to those skilled in the art in the light of the present disclosure. Therefore, the patent application No. 17 1297366i33 - the text is not revised, it is understood that the scope of the present invention should not be limited to the scope of the foregoing specific embodiment 'other modification changes and other implementations The example should still be the spirit of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [1] A schematic view showing a cross section of a semiconductor device in accordance with the present invention. The schematic diagram of ^2 is a large scale enlarged cross-sectional view of the superlattice of Fig. 1. The perspective view of g 3 shows the atomic structure of a portion of the superlattice in Figure 1. The schematic diagram of ^4 is a large scale enlarged cross-sectional view of another embodiment of the superlattice of FIG. _ 5 8 is the overall block in the conventional art and the 4/1 Si/O superlattice shown in Figure 1-3, both of which are calculated from the energy point of the Gamma point (G). Graph. Back B is a plot of the energy band structure calculated from the 2 points of the overall block in the conventional technique and the 4/1 Si/O superlattice lattice shown in Fig. 1-3. ° f The overall block in the skill of the art and the 5/ pre-Si/O super-day grid shown in Figure 4, the curve of the band structure calculated from the f and Z points. According to the other - the semiconductor component - the production of ^ ^

Claims (1)

1297366, 拾^申請專利範圍·· κ； 11 ι· 一半導體元件，其包含有： 一底材；與 與該底材相鄰接的至少一^10|§1^11，其包含有 了 2晶袼通道，包含有複數個;:隹疊的 格通目^^源極與沒極區，及疊覆於該超晶 通過該超晶袼於知於堆疊的層群組的方向上傳輸 每一個層群組各包含有界定了-個基底半導體 5„的堆疊基底半導體單層，以及其上之— 内的t基，半導體部份的=曰ί體£格 體原子的所有至少—非半導體單層内非半導 晶袼通道在平行方^卜且‘_王』皮非半導體原子所佔滿，以使該超 移率Λ斜仃方向上具有比無此構造存在時為高的電荷載體遷 共同能帶她圍1項之半導體元件，其巾該超晶格通道之t具有- 向上具該超晶格通道在平行方 及電洞兩者其中之一。為间的電何载體遷移率，其電荷載體包含電子 矽 。胃專輸11 1項之半導體元件，其巾絲解導體部份包含有 5.如中請專利範圍1項之半導體元件，射能帶修改層包含有氧。 的厚度專利關1項之半導體树，其中能帶修改層係為單-單層 個單層的厚度。说圍1項之轉體元件，射基底半導體部份為小於八 8. 士口申請專 4}| ρε| 六 個單層的厚度。&amp; :貞之轉體元件，其中基底半導體部份為二至 I如申請專利範圍1項之半導體元件，其働晶格通道更具有一 19 1297366 質直接能帶間隙 10·如申請專利範圍1項之丰霉，, 層群組之上更包含有-絲fin70件，射_晶格猶在最頂端的 11·如申請專利範圍1〇項之丰導靜士 目單專利耗圍1項之半導體元件，其中基底轉體部份為相同數 至少某些絲以二^^严件，其巾該基底轉體部份之中的 目單1利耗圍1項之半導體元件，其中基底半導體部份為不同數 積期間具kit311項之轉n其巾料導鮮層在下一層沉 IV ΐι=半1^基底半導體部份包含有由 基底半導體。 及ΠΛα私半導體所構成之群組中選定的一 18·如申凊專利範圍1項丰莫 方向上傳輸通過該超晶袼通f中於平行於堆疊的層群組的 果。 门之中電何載體的較低導電性等效質量所導致之結 ’其中較低之導電性等效質量係 、貝里&amp;二刀之_為低。 至少-)奴半_元件，其中該超晶格通道内更包含有 21. 一半導體元件，其包含有： 一底材；與 20 1297366 與該底材相鄰接的至少一 MOSFET，JL包含有 a ίϊίΐΐ:通導道致的⑼於平行於堆⑽群 數部份的複 構造存在時為高的電荷載“道奸仃方向上具蝴 共同能帶利範圍21項之半導體元件，其中該超晶格通道之令具有- 方向上傳^ %其中於平行於堆疊的層群組的 洞兩者其中之一。 σ 、的，具較鬲遷移率之電荷載體包含電子及電 層的厚度巾4利關21項之半導體it件，其中能帶修改層係為單一原子 的厚度。申明專利乾圍21項之半導體元件，其中石夕部份為小於八個原子層 的厚ί如中μ專利範圍21項之轉體元件，其中梦部份為二至六個原子層 質直接能帶間隙。範圍21項之半導體元件’其中該超晶格通道更具有_實 28. 如申請專利範 層群組之上更包含有1^層之+㈣讀，射該超晶格通道在最頂端的 29. 如申請專利範 、 30·如申請專利範 格 子層之厚度。 頁之半導體元件，其中該些石夕部份為相同數 層’與該閘電極層及該基底層包含有—間電極 30. 如由令主击丄,々λ* — ' 目&gt; 21 1297366 . 念半導體元件，其中該些彻之中的至少某 目原 32·如申請專利範圍21項之丰導濟开杜，甘击# 子層之厚度。 传體讀其中该麵部份為不同數 33.如申請專利範圍21項之半導I#开株，使由 ίίίί移率，係為在平行方向之中電荷載體的較戶 1ί 至少 ^ΐΙΙίϊϊ；&quot;? 35·—半導體元件，其包含有： 一底材；與 與該底材相鄰接的至少一 M〇SFET，i包含有 iiiiiSS?於平：⑽ 内的 有鳘基底t半導體部份的-晶體晶格 子的所有可置i非導體單層内非半導體原 通道在平彳访心具槪減 共=ΐίϊ糊細35奴铸狀件，射該超晶_叙中具有- 方二群組的 洞兩者其中之一。 ^ ，、f乂间遷私率之電何載體包含電子及電 實 t «ί ίϊί!]|^35 ^ ^ 層二ΪΙΪΚΪ圍讲，其中該超晶格通道在最頂端的 22 1297366 數目利範圍35項之半導體元件，其中該基底半導體部份為相同 至少度導體元件，其中該基底半導體部份之中的 數目單層35項之半導體元件，其巾該基底半導體部份為不同 電荷载體的較低導電性等移率’係為在平行方向之中 至少項之半導體元件，其中該超晶格通道内更包含有 4一Ϊ材半導ί元件，其包含有·· 與該底材相鄰曰接的至少一 M〇SFET，其包含有 通過該超:曰^；^=;於平行於堆疊的層群組的方向上傳輸 於 部份的少 -氧鄰？二 全被^原^所&amp;滿一氧單層内氧原子的所有可能位置.，並非 組之上體元件’其_該超晶格在最頂端的層群 49.如申„月專利域46項之半導體元件’其中該些基底半導體部份為相 23 1297366 同數目原子層之厚度。 的至少某元件’其巾_基底半導體部份之中 同數目圍46項之半導體元件，其中該些基底半導體部份為不 .一種導電以^範圍46項之半導體元件，其中該超晶格内更包含有至少 ^^元件，其包含有: 與該底目鄰接的至少_mosfet，其包 、曾2有複數個堆疊的層群組;以及 通道上且 的源極與沒極區，及疊覆於該超晶格 該超晶袼通I的—&amp;ff於平订於堆疊的層群組的方向上傳輸通過 份的界定了一個基底半導體部 的至少—個鄰^底半導，部，-晶體晶格内 質量。 八有比無此構造存在時為低的電荷載體導電性等效 共同利補53項之半導體树，其中該超晶格通道之中具有- 向上具半導體元件，其中使該超晶格通道在平行方 及電洞存麵為高的電荷紐遷料，«荷 沉如申請專利範圍a項之半導體元件，其中基底半導體部份包含有石夕。 57·如申請專利範圍53項之半導體元件，其愧帶修改層包含有氧。 厚度％如中請專利細53之半導體元件，其中能帶修改層係為單—單層的 24 1297366 個單專利乾圍53項之半導體元件，其中基底半導體部份為小於八 個單專利範圍53項之半導體元件，其中基底半導體部份為二至六 質直接能域53項之半導體树，其中該超晶格通道更具有-實 導體單層在下一層沉 數目ΐίΐΐί，1153項之半導體元件，其中該基底半導體部份為相同 至少某層導體元件，其t該基底半導體部份之，的 數.目單層之^利域53項之半導體元件，其中該基底半導體部份為不同 積期間具53項之半導體元件，其中非半 68.如申請專利範圍53項之 基底半導體 69·如申請專利範圍53 導 氮，氟勝氧所構成之群組半g能帶修改層包含有由氧， 70·如申請專利範圍53項之 方向上f輸，過該超晶袼通道的電丑 二^7二平行於堆疊的層群組的 該結構牯的導電性等效質量之三分之二為豆£。乂低之導電性等效質量係比無 ^晶袼通道内更包含有 至少項之半導體元件，其中該超 25 1297366 ' 第92130133號專利申請案 、 發明專利說明書無劃線修訂本 2008年3月修訂 柒、指定代表圖： ； (一)本案指定代表圖為：第（1 )圖。 (二)本代表圖之元件代表符號簡單說明: 捌、本案若有化學式時，請揭示最能顯示發明特徵的化學式： 20 金氧半電晶體 21 底材 22,23 源極Λ及極區 25 超晶格 26, 27 源極/汲極延伸區 30,31 源極/沒極金屬石夕化物層 32, 33 源極/汲極接觸 34, 35 虛線 36 閘電極層 37 閘極絕緣層 40, 41 側壁隔絕層1297366, picking up the patent application range·· κ; 11 ι· a semiconductor component, comprising: a substrate; and at least one of the ^10|§1^11 adjacent to the substrate, which includes 2 a wafer channel comprising a plurality of; a folded source of a source and a source region, and a superposition of the supercrystal through the supercrystal in a direction of a group of layers known to be stacked A layer group each comprises a stacked base semiconductor monolayer defining a base semiconductor 5 „, and a t-base therein, all at least a non-semiconductor of the semiconductor portion The non-semiconducting germanium channel in the single layer is filled in parallel with the non-semiconductor atom of the '_wang', so that the overshoot rate has a higher charge carrier in the oblique direction than in the absence of the structure. The interaction can bring her a semiconductor component, and the t-cell of the superlattice channel has - one of the parallel lattice and the hole with the superlattice channel. Rate, its charge carrier contains electrons. The semiconductor component of the 11th item of the stomach, its wire-wound conductor The semiconductor element includes 5. The semiconductor element of the patent scope 1 and the modified band of the emitter band contain oxygen. The thickness of the patented semiconductor tree of 1 item, wherein the band modification layer is a single-single layer single layer Thickness. Speaking of the rotating element of the first item, the base semiconductor part is less than eight 8. The application of the special 4}| ρε| the thickness of six single layers. &amp;: the rotating element of the ,, the base semiconductor part For the semiconductor components of the patent range 1 to 2, the 働 lattice channel has a 19 1 297 366 direct energy band gap. 10. As claimed in the patent scope 1 item, the layer group further includes -The wire fin 70 piece, the shot_lattice is still at the top of the 11th. For example, the patented range 1 之 之 导 静 目 目 目 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利 专利The wire is made of two parts, and the semiconductor element of the base part of the substrate is divided into one item, wherein the base semiconductor part has a different number of products during the period of the kit 311. The material guide layer is in the next layer of sinking IV ΐι=half 1^ base semiconductor package There is a selected one of the group consisting of a base semiconductor and a 私α private semiconductor. The result is transmitted in the direction of the super-crystal f f in the parallel layer group. The lower conductivity equivalent mass of the carrier in the gate is the junction of which the lower conductivity equivalent mass system, Berry & second knife is low. At least -) slave half_component, The superlattice channel further comprises: 21. a semiconductor component, comprising: a substrate; and at least one MOSFET adjacent to the substrate of 20 1297366, JL comprising a ίϊίΐΐ: (9) A high electrical load in the presence of a complex structure parallel to the number of clusters (10). "The semiconductor component with a common energy range of 21 in the direction of the gangster, wherein the superlattice channel has a - direction Upload ^ % one of the holes in the layer group parallel to the stack. The charge carrier of σ, which has a higher mobility, comprises a thickness of the electron and the electrical layer of the semiconductor element of the item 21, wherein the band of the modified layer is a single atom. Declaring a patented semiconductor component of 21 products, in which the part of Shi Xi is a thickness of less than eight atomic layers, such as the rotating element of the 21st patent range of the medium μ, wherein the dream part is two to six atomic layer direct energy. With a gap. The semiconductor component of the range of 21's, wherein the superlattice channel has more _ real 28. If the patent application layer group further contains 1^ layer + (four) read, the superlattice channel is at the topmost 29 If you apply for a patent, 30. If you apply for a patent, the thickness of the grid layer. The semiconductor component of the page, wherein the plurality of layers are the same number of layers 'and the gate electrode layer and the base layer comprise the inter-electrode 30. If the main layer is killed, 々λ* — '目> 21 1297366 The semiconductor component, in which at least some of the elements are 32. For example, the thickness of the sub-layer is the thickness of the sub-layer. The transective reading is in which the face portion is a different number 33. For example, the semi-conductive I# of the patent application scope 21 is opened, so that the rate of the carrier is ίίίί, which is the charge carrier in the parallel direction 1ί at least ^ΐΙΙίϊϊ; &quot; 35--a semiconductor device comprising: a substrate; and at least one M〇SFET adjacent to the substrate, i comprising iiiiiSS? in a flat: (10) germanium-containing substrate t semiconductor portion - all crystallizable lattices of all non-conductor single-layer non-semiconductor original channels in the Pingyi visitor with a total of ΐ ϊ ϊ ϊ 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 35 One of the holes. ^ , , f 迁 迁 迁 何 何 载体 载体 « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « « The semiconductor component of claim 35, wherein the base semiconductor portion is the same at least one conductor component, wherein the number of single-layer 35-th semiconductor components in the base semiconductor portion, the base semiconductor portion of the substrate is a different charge carrier The lower conductivity isobaric rate is a semiconductor component of at least one of the parallel directions, wherein the superlattice channel further comprises a 4-cylinder semi-conducting element, which comprises... </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The second is all the possible positions of the oxygen atoms in the mono-oxide single layer. It is not the upper body element of the group. The _ the superlattice is at the topmost layer group. 49. The semiconductor element of the 46th item, wherein the base semiconductor portions are the thickness of the phase 23 1297366 and the number of atomic layers. At least one of the elements 'the semiconductor element of the substrate-substrate portion has the same number of semiconductor elements of 46, of which The base semiconductor portion is not a semiconductor element having a range of 46, wherein the superlattice further includes at least a component including: at least _mosfet adjacent to the substrate, 2 having a plurality of stacked layer groups; and source and immersion regions on the channel, and -&amp;ff superimposed on the superlattice of the super-lattice I in a stacked layer group The direction of transmission of the pass-through portion defines at least one of the bottom semiconductor portions of the base semiconductor portion, the portion, and the mass within the crystal lattice. Eight has a lower charge carrier conductivity than the absence of this structure. a 53-item semiconductor tree in which the super-lattice Among them, there is a semiconductor component, wherein the superlattice channel has a high charge in the parallel side and the hole storage surface, and the semiconductor component of the patent application range a, wherein the base semiconductor portion Including the semiconductor element of claim 53, the modified layer of the tape contains oxygen. The thickness is as shown in the semiconductor component of the patent 53, wherein the band modification layer is a single-layer 24 1297366 semiconductor components of 53 patents, wherein the base semiconductor portion is a semiconductor component of less than eight single patent ranges, wherein the base semiconductor portion is a semiconductor tree of two to six mass direct energy domains, Wherein the superlattice channel further has a solid conductor single layer in a lower layer of semiconductor elements, wherein the base semiconductor portion is the same at least one layer of the conductor element, and the number of the base semiconductor portion The semiconductor component of the item 53 of the monolayer, wherein the base semiconductor portion is a semiconductor component having 53 items during different accumulation periods, wherein the non-half 68. The base semiconductor of the 53th item 69. The patented range 53 nitrogen, the fluorine-containing oxygen group consists of a group of half-g energy band modified layer containing oxygen, 70 · as in the scope of patent application 53 The electrical ugly of the super-crystalline channel is parallel to the stacked layer group. Two-thirds of the conductivity equivalent mass of the structure is Bean. The lower conductivity is equivalent to the mass. The wafer channel further includes at least a semiconductor component, wherein the super 25 1297366 ' patent application No. 92130133, the invention patent specification has not been revised, revised in March 2008, designated representative map: (1) The representative representative figure of this case is: (1). (2) A brief description of the symbol of the symbol of the representative figure: 捌 If there is a chemical formula in this case, please disclose the chemical formula that best shows the characteristics of the invention: 20 gold oxide semi-transistor 21 substrate 22, 23 source Λ and polar region 25 Superlattice 26, 27 source/drain extension 30, 31 source/electrode metallization layer 32, 33 source/drain contact 34, 35 dashed line 36 gate electrode layer 37 gate insulating layer 40, 41 sidewall insulation