I2964^8tw,doc/g 九、發明說明： 【發明所屬之技術領域】 • 本發明是有關於一種低電壓差動訊號(Low Voltage • Differential Signal)驅動器和其前置增強電路(pre-emphasis • Circuit),且特別是有關於一種具有高切換速度且具有高解 析度之低Μ差動訊5虎驅動為和其前置加強電路。 【先前技術】 低電壓差動訊號(以下簡稱LVDS)技術係用於資料傳 輸系統中。由線驅動器(Line Driver)產生的LVDS，典型來 说具有250mV到450mV之間的峰對峰(peak_tCKpeak)值增 益。在維持高傳輸速度時，低電壓的切換可以有助於減小 功率的消耗。所以LVDS技術特別適用於高速資料傳輸的 應用，例如視訊資料的處理。因此，在專業的視訊處理設 備和消費電子產品中，例如平面顯示器（Flat pand Display，FDP)可以發現LVDS的應用。 圖1係繪示一種習知之低壓差動訊號驅動器之電路 I 圖。請參照圖1，在習知之LVDS驅動器中包括了電晶體I2964^8tw, doc/g IX. Description of the Invention: [Technical Field] The present invention relates to a Low Voltage • Differential Signal driver and its pre-emphasis Circuit), and in particular, relates to a low-contrast differential 5 drive with high switching speed and high resolution as its pre-hardening circuit. [Prior Art] A low voltage differential signal (hereinafter referred to as LVDS) technology is used in a data transmission system. The LVDS generated by the Line Driver typically has a peak-to-peak value of between 250 mV and 450 mV. Switching at low voltages can help reduce power consumption while maintaining high transmission speeds. Therefore, LVDS technology is particularly suitable for high-speed data transmission applications, such as the processing of video data. Therefore, LVDS applications can be found in professional video processing equipment and consumer electronics such as Flat Panel Display (FDP). 1 is a circuit diagram of a conventional low voltage differential signal driver. Referring to FIG. 1, a transistor is included in a conventional LVDS driver.
Mil、M12、M13和M14。其中，電晶體M11的第一源/ 沒極知係透過一驅動電流源11而麵接至一電壓源vdd， 並且與電晶體M13的第一源/汲極端彼此互相耦接，而電 晶體Mil的閘極端係接收驅動訊號VIN1，其第二源/汲極 女而則與電晶體M12的第一源/汲極端彼此互相搞接，並且 柄接至負載電阻Rt的其中一端。類似地，電晶體的 閘極端與第二源/汲極端則分別耦接驅動訊號VIN2和電晶 5 I2964§lwfdoc/g 體M14的第一源/汲極端，並且電晶體M13的第二源/汲極 端也I馬接至負載電阻Rt的另一端。此外，電晶體M12的 • 閘極端和第二源/汲極端，係分別接收驅動訊號VIN2以及 透過電阻R1而接地。相對地，電晶體M14的閘極端和第 - 二源/汲極端’則分別耦接驅動訊號VIN1和電晶體M12 的第二源/汲極端。 當驅動訊號VIN1被致能(Enable)時，就會導通電晶體 > Mil和M14。此時，驅動電流源η所產生之驅動電流的 路徑，會從電晶體Mil的第一源/汲極端流入，通過節點 1〇3，然後循A路徑通過負載電阻Rt。接著，驅動電流會 通過節點105，然後通過電晶體M14和電阻R1到地。相 對地，當驅動訊號VIN2被致能時，就會導通電晶體M13 和M12。此時，驅動電流改從電晶體M13的第一源/汲極 端流入，然後通過節點1〇5而循路徑b通過負載電阻Rt 到達節點103。接著，驅動電流會通過電晶體M12的第一 和弟一源/>及極端’並且通過電阻R1到地。 _ 圖1所纟會不之LVD S驅動為的缺點，在於流過負載電 阻Rt之電流的切換速度，受限於驅動電流源n的大小。 也就是說，流過負載電阻Rt的電流，在路徑A和B之間 切換的速度，係受限於驅動電流源η的大小，因而導致了 LVDS驅動器的切換速度變慢。其詳細原因，可以參照美 國專利公告第6281715號專利的說明。 為了解決上述的問題，在美國專利公告第6281715號 專利也提供了一種LVDS驅動器。請參照美國專利公告第 6 I2964l^Xf,oc/g 6281715號專利的圖2，其中所揭露的LVDS驅動器，係 在流過負載電阻RL之電流切換的瞬間，利用電流鏡電路 207另外再產生電流ID2至電流控制電路2〇1，以致於電 流控制電路201可以利用電流ID1和ID2增加切換的速度^ 然而，由於美國專利公告第6281715號專利所揭露的 LVDS驅動器，係使用了五個反向器(Im〜ID5)和一反或閉 (XNOR)等邏輯閘來盛收輸入訊號IN，以分別控制電晶體 M2卜M22、M23和M24的導通順序。因此，這些邏g閘 會消耗很多處理時間，尤其當訊號通過反或閘時所耗費的 延遲時間更是佔了絕大的部分。 此外，由於控制電晶體M25和M27導通的訊號與控 制電晶體M26和M28導通的訊號不同步’因此會造成電 晶體M25和M26以及電晶體M27和M28導通的時間會有 差異，以致於美國專利公告第6281715號專利所揭露之 LVDS驅動器的解析度的表現下降。 【發明内容】 因此，本發明的目的就是在提供一種前置增強電路， 係適用於LVDS驅動器。本發明之前置增強電路可以在 LVDS驅動器切換電流方向的瞬間’能夠彳艮精確地提供額 外的電流至LVDS驅動器。 本#明的再一目的是提供一種LVDS驅動器，係具有 很南的切換速度’以操作在高速傳輸的壞境。 本發明係提供一種前置增強電路，可以適用於一 LVDS驅動器，而此LVDS驅動器係具有一電流輸入端和 I2964^8twfdoc/g 一電流輸出端。本發明之前置增強電路包括了第一 PM〇s 電晶體、第二pmos電晶體、第三pM〇s電晶體和第四 pmos電晶體。其中，第一 PM0S電晶體的第一和第二源 /没極端，係分別與第三PM0S電晶體和第二PM〇s電晶 體的第一源/汲極端彼此互相耦接，並且透過一第一電阻耦 接至一電壓源，而第一 PMOS電晶體的閘極端則接收延遲 一預設時間後的一第一驅動訊號。類似地，第三PM〇s電 晶體的第二源/没極端係|馬接至第四PMOS電晶體的第一 源/汲極端，而閘極端則接收延遲預設時間後的一第二驅動 訊號。而原始的第一驅動訊號和第二驅動訊號，係分別送 至第二PMOS電晶體和第四pmos電晶體的閘極端，並且 第二PMOS電晶體和第四PM0S電晶體的第二源/汲極端 係共同耦接至LVDS驅動器的電流輸入端。此外，本發明 之前置增強電路還包括第一 NMOS電晶體、第二NMOS 電晶體、第三NMOS電晶體和第四NMOS電晶體。其中， 第一 NMOS電晶體的第一與第二源/汲極端，係分別與第 三NMOS電晶體和第二NMOS電晶體的第一源/汲極端彼 此互相耦接，並且耦接至LVDS驅動器的電流輪出端，而 第一 NMOS電晶體的閘極端則接收一第三驅動訊號。類似 地，第三NMOS電晶體的閘極端與第二源/汲極端，係分 別耦接第四驅動訊號和第四NMOS電晶體的第一源/汲極 端。而將第三和第四驅動訊號延遲預設時間後，再分別送 至第二NMOS電晶體和第四NMOS電晶體的閘極端，並 且第二NMOS電晶體和第四NMOS電晶體的第二源/汲極 8 I2964^8twf.d〇c/g 端係共同透過一第二電阻而接地。 在較佳的情況下，本發明之前置增強電路還包括第一 緩衝模組和第二緩衝模組。其中，第一緩衝模組包括第一 反向器、第二反向器、第三反向器和第四反向器。第一和 第二反向器的輸入，係分別接收第二和第一驅動訊號，而 第一和第二反向器的輪出，則分別耦接至第三和第四反向 器的輸入，以致於第三和第四反向器可以分別產生延遲預 設時間後的第二和第一驅動訊號至第三和第一 PM〇S電晶 體的閘極。相同地，第二緩衝模組也包括第五反向器、第 六反向器、第七反向器和第八反向器。其中，第五和第六 反向裔的輸入，係分別接收第四和第三驅動訊號，並且第 五和第六反向器的輸出，係分別耦接至第七和第八反向器 的輸入，以致於第七和第八反向器可以產生延遲預設時間 後的第四和第三驅動訊號至第二和第四NM0S電晶體的 閘極。 從另一觀點來看，本發明係提供一種具有前置增強電 路之LVDS驅動器，係包括了上述的前置增強電路，並且 還包括了一電流控制電路。其中，電流控制電路具有一電 流輸入端和一電流輸出端，係分別耦接至上述之第二 PMOS電晶體和第四pM〇s f晶體的第二源/汲極端，以及 ，择至上述之第一 NM〇s電晶體和第三Nm〇s電晶體的 第一源/汲極端。此外，電流控制電路的電流輸入端，係透 過一，:驅動電流源耦接至電壓源，而其電流輸出端則透 過一第二驅動電流源接地。除此之外，電流控制電路還包 9 I2964Stwf,oc/g 括一第一輸出端和一第二輸出端，係共同耦接一負載。 攸另一觀點來看，本發明係提供一種具有前置增強電 • 路之LVDS驅動器，其結構大致上與上述之LVDS驅動器 相同。較特別的是，電流控制電路的電流輸出端係透過二 •電阻而接地。 在本發明的實施例中，上述之電流控制電路包括了第 五PMOS電晶體、第六PMOS電晶體、第五nm〇S電晶 體和第六NMOS電晶體。其中，第五pm〇s電晶體的第 一源/>及極端和第二源/汲極端係分別輕接上述之電流輸入 端與第一輸出端，而其閘極端則接收第二驅動訊號。類似 地，第六PMOS電晶體的第一源/汲極端和第二源/汲極端 係分別搞接上述之電流輸入端與第二輸出端，而其閘極端 則接收第一驅動訊號。此外，第五NMOS電晶體的第一源 /汲極端和第二源/汲極端係分別耦接上述之第一輸出端與 電流輸出端，而其閘極端則接收第四驅動訊號。相同地， 第六NMOS電晶體的第一源/汲極端和第二源/汲極端係分 別耦接上述之第二輸出端與電流輸出端，而其閘極端則接 收第三驅動訊號。 從另一觀點來看，本發明係提供一種前置增強電路， 可以適用於一 LVDS驅動器，而此LVDS驅動器係具有一 電流輸入端和一電流輸出端。本發明之前置增強電路包括 了第一電晶體、第二電晶體、第三電晶體和第四電晶體。 其中，第一電晶體的第一和第二源/汲極端，係分別與第二 曰曰體和第二電晶體的第一源/、;反極端彼此互相輛I接，並且 I2964^8twfdoc/g 透過一第一電阻耦接至一電壓源，而第一電晶體的閘極端 則接收延遲一預設時間後的第一驅動訊號。類似地，第三 電晶體的第二源/汲極端係耦接至第四電晶體的第一源/汲 極端’而閘極端則接收延遲預設時間後的第二驅動訊號。 原始的第一驅動訊號和第二驅動訊號，係分別送至第二電 晶體和第四電晶體的閘極端，並且第二電晶體和第四電晶 體的第二源/汲極端係共同耦接至LVDS驅動器的電流輸 入端。此外，本發明之前置增強電路還包括第五電晶體、 第六電晶體、第七電晶體和第八電晶體。其中，第五電晶 體的第一與第二源/汲極端，係分別與第六電晶體和第七電 晶體的第一源/汲極端彼此互相耦接，並且耦接至lVDS驅 動為的電流輸出端，而第五電晶體的閘極端則接收一第三 驅動訊號。類似地，第七電晶體的閘極端與第二源/汲極 端，係分別耦接第四驅動訊號和第八電晶體的第一源/汲極 端。而將第三和第四驅動訊號延遲預設時間後，會分別送 至第六電晶體和第八電晶體的閘極端，並且第六電晶體和 第八電晶體的第二源/汲極端係共同透過—第二電阻而接 地0 從另-觀點來看，本發明係提供一種具有前置增強電 路之LVDS驅動器，其包括了上述之第—電晶體、第二電 晶體、第二電晶體、第四電晶體、第五電晶體、第六電晶 體、第七電晶體和第八電晶體所組成之前置增強電路，並 且也包括了-電赫制電路。其巾，電流控制電路具有一 電流輸入端和一電流輸出端，係分_接第二電晶體和第 I2964^twfd〇c/g 四電晶體的第二源/汲極端’以及第五電晶體和第七電晶體 : 的第一源/汲極端。此外，電流控制電路還包括第一輸出端 和一第二輸出端，係用來耦接一負載。 • 在本發明的實施例中，電流控制電路包括了第九電晶 * 體、第十電晶體、第十一電晶體和第十二電晶體。其中， 第九電晶體的第-源/汲極端和第二源/汲極端係分別減 上述之電流輸入端與第一輸出端，而其閘極端則接收第二 驅動訊號。類似地，第十一電晶體的第一源/汲極端和第二 源/汲極端係分別耦接上述之電流輸入端與第二輸出端，而 其閘極端則接收第一驅動訊號。此外，第十電晶體的第一 源/汲極端和第二源/汲極端係分別耦接上述之第一輸出端 與電流輸出端，而其閘極端則接收第四驅動訊號。相同地， 第十二電晶體的第一源/汲極端和第二源/汲極端係分別耦 接上述之第二輸出端與電流輸出端，而其閘極端則接收第 三驅動訊號。在較佳的倩況下，電流輸入端係透過一第一 驅動電流源而耦接至電壓源，而電流出端則透過一第二驅 φ 動電流源或是一第三電阻而接地。 在本發明中，上述之第一電晶體、第二電晶體、第三 、 電日日體、弟四電晶體、第九電晶體和第十一電晶體之電氣 ： 特性相同，而與第五電晶體、第六電晶體、第七電晶體、 第八電晶體、第十電晶體和第十二電晶體之電氣特性相反。 综上所述，本發明只需要將第一驅動訊號與第二驅動 訊號設為同步並且反相，以及將第三驅動訊號與第四驅動 訊號没為同步並且反相，就可以使本發明所提供的前置增 12 I2964^8twfdoc/g 強电路，在LVDS切換電流方向的瞬間，很糈確地提供額 . 外的電流以加快其切換的速度。 a/ … 此外，由於每個驅動訊號至多需要兩個反向器的處 • 理，因此本發明之LVDS驅動器所耗費的延遲時間可以縮 ， 短，而具有較高的切換速度。 、 為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說Mil, M12, M13 and M14. The first source/nothing of the transistor M11 is connected to a voltage source vdd through a driving current source 11, and is coupled to the first source/汲 terminal of the transistor M13, and the transistor Mil is coupled to each other. The gate terminal receives the driving signal VIN1, and the second source/drain electrode and the first source/汲 terminal of the transistor M12 are connected to each other, and the handle is connected to one end of the load resistor Rt. Similarly, the gate terminal and the second source/汲 terminal of the transistor are respectively coupled to the first source/汲 terminal of the driving signal VIN2 and the electric crystal 5 I2964 §lwfdoc/g body M14, and the second source of the transistor M13/ The 汲 extreme is also connected to the other end of the load resistor Rt. In addition, the gate terminal and the second source/namp terminal of the transistor M12 receive the drive signal VIN2 and the ground through the resistor R1, respectively. In contrast, the gate terminal and the -2-second source/汲 terminal of the transistor M14 are coupled to the second source/汲 terminal of the driving signal VIN1 and the transistor M12, respectively. When the drive signal VIN1 is enabled, the crystals > Mil and M14 are turned on. At this time, the path of the driving current generated by the driving current source η flows from the first source/汲 terminal of the transistor Mil, passes through the node 1〇3, and then follows the A path through the load resistor Rt. Next, the drive current will pass through node 105 and then through transistor M14 and resistor R1 to ground. In contrast, when the drive signal VIN2 is enabled, the transistors M13 and M12 are turned on. At this time, the drive current is changed from the first source/drain terminal of the transistor M13, and then passes through the node 1〇5 and follows the path b to reach the node 103 through the load resistor Rt. Next, the drive current will pass through the first source and/or the extremes of the transistor M12 and through the resistor R1 to ground. The disadvantage of the LVD S drive in Figure 1 is that the switching speed of the current flowing through the load resistor Rt is limited by the magnitude of the drive current source n. That is to say, the speed at which the current flowing through the load resistor Rt is switched between the paths A and B is limited by the magnitude of the driving current source η, thereby causing the switching speed of the LVDS driver to be slow. For detailed reasons, reference may be made to the description of U.S. Patent Publication No. 6281815. In order to solve the above problems, an LVDS driver is also provided in U.S. Patent No. 6,281,715. Referring to Figure 2 of the U.S. Patent Publication No. 6, I2964, which is incorporated herein by reference in its entirety, the LVDS driver disclosed herein utilizes the current mirror circuit 207 to generate additional current at the instant of current switching through the load resistor RL. ID2 to current control circuit 2〇1, so that current control circuit 201 can increase the speed of switching by using current ID1 and ID2. However, due to the LVDS driver disclosed in U.S. Patent No. 6,281,715, five inverters are used. (Im ~ ID5) and a reverse or closed (XNOR) logic gate to receive the input signal IN to control the conduction sequence of the transistor M2, M22, M23 and M24, respectively. Therefore, these logic gates consume a lot of processing time, especially when the signal passes through the reverse or gate, which is the most important part. In addition, since the signals that control the transistors M25 and M27 are turned on and the signals that control the transistors M26 and M28 are not synchronized, the timings of the transistors M25 and M26 and the transistors M27 and M28 are different, so that the US patent The performance of the resolution of the LVDS driver disclosed in the publication No. 6281815 is degraded. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a pre-emphasis circuit suitable for use in an LVDS driver. The pre-emphasis circuit of the present invention can accurately supply additional current to the LVDS driver at the instant when the LVDS driver switches the direction of the current. A further object of the present invention is to provide an LVDS driver having a very south switching speed to operate in a high speed transmission environment. The present invention provides a pre-emphasis circuit that can be applied to an LVDS driver having a current input and an I2964^8twfdoc/g current output. The pre-emphasis enhancement circuit of the present invention includes a first PM〇s transistor, a second pmos transistor, a third pM〇s transistor, and a fourth pmos transistor. Wherein the first source and the second source/no terminal of the first PMOS transistor are coupled to the first source/deuterium terminal of the third PMOS transistor and the second PM NMOS transistor, respectively, and are coupled to each other A resistor is coupled to a voltage source, and the gate terminal of the first PMOS transistor receives a first driving signal delayed by a predetermined time. Similarly, the second source/no extremity of the third PM〇s transistor is connected to the first source/汲 terminal of the fourth PMOS transistor, and the gate terminal receives a second drive after the delay time is preset. Signal. The original first driving signal and the second driving signal are respectively sent to the gate terminals of the second PMOS transistor and the fourth pmos transistor, and the second source/汲 of the second PMOS transistor and the fourth PMOS transistor are respectively The extremes are commonly coupled to the current input of the LVDS driver. Furthermore, the preamplifier circuit of the present invention further includes a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, and a fourth NMOS transistor. The first source and the second source/汲 terminal of the first NMOS transistor are coupled to each other and to the first source/drain terminal of the third NMOS transistor and the second NMOS transistor, respectively, and coupled to the LVDS driver. The current wheel of the first NMOS transistor receives a third driving signal. Similarly, the gate terminal of the third NMOS transistor and the second source/deuterium terminal are coupled to the first source/drain terminal of the fourth driving signal and the fourth NMOS transistor, respectively. And delaying the third and fourth driving signals by a predetermined time, and then sending them to the gate terminals of the second NMOS transistor and the fourth NMOS transistor, respectively, and the second source of the second NMOS transistor and the fourth NMOS transistor /汲 pole 8 I2964^8twf.d〇c/g The terminal system is grounded through a second resistor. In a preferred case, the pre-emphasis circuit of the present invention further includes a first buffer module and a second buffer module. The first buffer module includes a first inverter, a second inverter, a third inverter, and a fourth inverter. The inputs of the first and second inverters respectively receive the second and first driving signals, and the rounding of the first and second inverters are respectively coupled to the inputs of the third and fourth inverters Therefore, the third and fourth inverters can respectively generate the second and first driving signals delayed by the preset time to the gates of the third and first PM 〇S transistors. Similarly, the second buffer module also includes a fifth inverter, a sixth inverter, a seventh inverter, and an eighth inverter. Wherein the inputs of the fifth and sixth reverse are respectively receiving the fourth and third driving signals, and the outputs of the fifth and sixth inverters are respectively coupled to the seventh and eighth inverters. The input is such that the seventh and eighth inverters can generate the fourth and third driving signals delayed by the preset time to the gates of the second and fourth NMOS transistors. From another point of view, the present invention provides an LVDS driver having a pre-emphasis circuit, including the pre-emphasis circuit described above, and a current control circuit. The current control circuit has a current input end and a current output end coupled to the second source/汲 terminal of the second PMOS transistor and the fourth pM〇sf crystal, respectively, and A first source/汲 terminal of an NM〇s transistor and a third Nm〇s transistor. In addition, the current input terminal of the current control circuit passes through one: the driving current source is coupled to the voltage source, and the current output terminal is grounded through a second driving current source. In addition, the current control circuit also includes 9 I2964Stwf, and the oc/g includes a first output end and a second output end, which are coupled to a load. Viewed from another point of view, the present invention provides an LVDS driver having a pre-emphasis circuit that is substantially identical in construction to the LVDS driver described above. More specifically, the current output of the current control circuit is grounded through a two-resistor. In an embodiment of the invention, the current control circuit includes a fifth PMOS transistor, a sixth PMOS transistor, a fifth nm 〇S transistor, and a sixth NMOS transistor. Wherein, the first source of the fifth pm〇s transistor and/or the extreme source and the second source/汲 terminal are respectively connected to the current input terminal and the first output terminal, and the gate terminal thereof receives the second driving signal. . Similarly, the first source/汲 terminal and the second source/汲 terminal of the sixth PMOS transistor respectively connect the current input terminal and the second output terminal, and the gate terminal thereof receives the first driving signal. In addition, the first source/汲 terminal and the second source/汲 terminal of the fifth NMOS transistor are respectively coupled to the first output end and the current output end, and the gate terminal thereof receives the fourth driving signal. Similarly, the first source/汲 terminal and the second source/汲 terminal of the sixth NMOS transistor are coupled to the second output terminal and the current output terminal, respectively, and the gate terminal receives the third driving signal. From another point of view, the present invention provides a pre-emphasis circuit that can be applied to an LVDS driver having a current input and a current output. The pre-emphasis enhancement circuit of the present invention includes a first transistor, a second transistor, a third transistor, and a fourth transistor. Wherein the first and second source/deuterium terminals of the first transistor are respectively connected to the first source/, and the opposite ends of the second body and the second transistor, and I2964^8twfdoc/ g is coupled to a voltage source through a first resistor, and the gate terminal of the first transistor receives the first driving signal delayed by a predetermined time. Similarly, the second source/汲 terminal of the third transistor is coupled to the first source/汲 terminal ' of the fourth transistor and the gate terminal receives the second driving signal delayed by the preset time. The original first driving signal and the second driving signal are respectively sent to the gate terminals of the second transistor and the fourth transistor, and the second source/汲 terminal of the second transistor and the fourth transistor are coupled together To the current input of the LVDS driver. Further, the pre-emphasis enhancement circuit of the present invention further includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. Wherein the first and second source/汲 terminals of the fifth transistor are coupled to each other and to the first source/drain terminal of the sixth transistor and the seventh transistor, respectively, and coupled to the current driven by the 1VDS The output terminal, and the gate terminal of the fifth transistor receives a third driving signal. Similarly, the gate terminal and the second source/drain terminal of the seventh transistor are coupled to the first source/drain terminal of the fourth driving signal and the eighth transistor, respectively. After the third and fourth driving signals are delayed by a preset time, they are respectively sent to the gate terminals of the sixth transistor and the eighth transistor, and the second source/antenna terminal of the sixth transistor and the eighth transistor are respectively sent. Commonly through-second resistance and grounding 0. From another perspective, the present invention provides an LVDS driver having a pre-emphasis circuit including the above-described first transistor, second transistor, second transistor, The fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor constitute a pre-emphasis circuit, and also include an electro-helix circuit. The towel, the current control circuit has a current input end and a current output end, which is connected to the second transistor and the second source/汲 terminal of the I2964^twfd〇c/g four transistors and the fifth transistor And the seventh transistor: the first source / 汲 extreme. In addition, the current control circuit further includes a first output end and a second output end for coupling to a load. • In an embodiment of the invention, the current control circuit includes a ninth electromorph*, a tenth transistor, an eleventh transistor, and a twelfth transistor. Wherein, the first source/sigma terminal and the second source/sigma terminal of the ninth transistor respectively reduce the current input terminal and the first output terminal, and the gate terminal thereof receives the second driving signal. Similarly, the first source/汲 terminal and the second source/汲 terminal of the eleventh transistor are respectively coupled to the current input terminal and the second output terminal, and the gate terminal receives the first driving signal. In addition, the first source/汲 terminal and the second source/汲 terminal of the tenth transistor are respectively coupled to the first output end and the current output end, and the gate terminal thereof receives the fourth driving signal. Similarly, the first source/汲 terminal and the second source/汲 terminal of the twelfth transistor are respectively coupled to the second output terminal and the current output terminal, and the gate terminal thereof receives the third driving signal. In a preferred case, the current input terminal is coupled to the voltage source through a first driving current source, and the current output terminal is grounded through a second driving φ current source or a third resistor. In the present invention, the electrical properties of the first transistor, the second transistor, the third, the electro-Japanese, the fourth transistor, the ninth transistor, and the eleventh transistor are the same, and the fifth The electrical characteristics of the transistor, the sixth transistor, the seventh transistor, the eighth transistor, the tenth transistor, and the twelfth transistor are opposite. In summary, the present invention only needs to synchronize and invert the first driving signal and the second driving signal, and synchronize and invert the third driving signal and the fourth driving signal to enable the present invention. Provided with a pre-increased 12 I2964^8twfdoc/g strong circuit, in the LVDS switching current direction, it is very accurate to provide the external current to speed up the switching speed. a/ ... In addition, since each driver signal requires at most two inverters, the delay time of the LVDS driver of the present invention can be shortened and shortened, and has a high switching speed. The above and other objects, features, and advantages of the present invention will become more apparent from the aspects of the invention.
明如下。 W ^ 【實施方式】 圖2係繪示依照本發明之一較佳實施例的一種具有前 置增強電路之低壓差動訊號驅動器的電路圖。請參照圖 2，在LVDS驅動器200中，包括了電流控制電路21〇和 萷置增強電路220。其中，前置增強電路220又分為源流 電路220a和沒流電路220b，係分別耦接至電流控制電路 210的電流輸入端N1和電流輸出端N2。而電流控制電路 210還具有輸出端R+和R_，係用來麵接負載rl。 • 在電流控制電路21〇中，係配置了電晶體M21、M22、 M23和M24。其中，電晶體M21的第一源/汲極端係耦接 ' 電流輸入端N1，閘極端係接收驅動訊號VB，而第二源/ - 汲極端則透過節點201而耦接至輸出端R+。類似地，電晶 體M23的第一源/汲極端和第二源/汲極端，係分別耦接電 流輸入端N1以及透過節點203耦接至輪出端R_，而其閘 極端則接收驅動訊號VA。此外，電晶體M22的第一源/ 汲極端和第二源/汲極端，係分別透過節點2〇1耦接至輸出 13 I2964§lw,doc/g 端R+以及耦接至電流輸出端N2，而其閘極端則接收驅動 ： 吼號VD。相對地，電晶體M24的第一源/汲極端和第二源 • _ /汲極端，係分別耦接電晶體M23和M22的第二源/汲極 : 端，而其閘極端則接收驅動訊號VC。在本實施例中，電 • 流控制電路的電流輸入端係透過驅動電流源n而耦接 至電壓源VDD，而電流輸出端N2則透過驅動電流源12 而接地。 另外，在本實施例中，電晶體M21和M23可以是 PMOS電晶體，而電晶體M22和M24則可以是NMOS電 晶體。 在源流電路220a中，也配置了四個電晶體(m3 1、 M32、M33和M34)。其中，電晶體M31的第一源/汲極端 係透過電阻R1耦接至電壓源VDD，閘極端則接收驅動訊 號delay—VA ’而第二源/汲極端則耦接電晶體M32的第一 源/汲極端。類似地，電晶體M33的第一和第二源/汲極端， 係分別搞接電晶體M31和M34的第一源/汲極端，而電晶 • 體M33的閘極端則接收驅動訊號delay_VB。其中，驅動 訊號delay—VA和delay—VB，係分別為延遲一預設時間後 ' 的驅動訊號VA和VB。另外，電晶體M32和M34的第二 ! 源/汲極端，係共同麵接至電流控制電路210的電流輸入端 N1 ’而電晶體M32和M34的閘極端則分別接收驅動訊號 VB 和 VA 〇 與源流電路220a相同，在沒流電路220b中，同樣也 配置了四個電晶體，其分別為M41、M42、M43和M44。 14 I2964^8twfdoc/g 其中，電晶體M41的第一源/汲極端係I馬接至電流控制電 路210的電流輸出端N2，閘極端則接收驅動訊號vc，而 第二源/汲極端則耦接電晶體M42的第一源/汲極端。類似 地，電晶體M43的第一和第二源/汲極端，係分別耦接電 晶體M41和M44的第一源/没極端，而電晶體M43的閘極 端則接收驅動訊號VD。另外，電晶體M42和M44的第二 源/没極端，係共同透過電阻R2而接地，而電晶體M32和 M34的閘極端則分別接收驅動訊號delay_VD和 delay—VC '其中，驅動訊號delay—VC和delay_VD，係分 別為延遲預設時間後的驅動訊號VC和VD。 在本發明的實施例中，電晶體M31、M32、M33和 M34可以是PMOS電晶體，而電晶體M41、M42、M43 和M44則可以是NMOS電晶體。 另外，在本發明的實施例中，驅動訊號VA、VB、VC 和VD可以由訊號產生器230所產生。訊號產生器230可 以由鎖相迴路所組成，其係依據一輸入時脈訊號CLK而分 別產生驅動訊號VA、VB、VC和VD。 而為了 產生驅動訊號 delay_VA、delay_VB、delay_VC 和delay_VD，因此在前置增強電路220中，還配置有緩衝 模組240和250。 在緩衝模組240中，係配置有反向器p/21、IV22、IV23 和IV24。其中，反向器IV21的輸入，係接收驅動訊號VB， 而其輸出則透過反向器IV23而送至電晶體M33的閘極 端。因此，當驅動訊號VB經過反向器IV21和IV23的延 15 I2964^8twf.doc/g 遲後，就會產生驅動訊號delay一VB。換句話說，上述的預 設時間，就是反向器IV21和IV23所具有的延遲時間。同 樣的原理，當驅動訊號VA通過反向器IV22和IV24之後， 就會產生驅動訊號delay一VA，並且會被送至電晶體M31 的閘極端。 與緩衝模組240相同，在緩衝模組250内同樣也配置 了反向器IV25、IV26、IV27和IV28。同樣的原理，當驅 動訊號VC和VD分別通過反向器IV26和IV28，以及通 過反向器IV25和IV27之後，就會產生驅動訊號（jeiay VC 和delay一VD，並且會被分別送至電晶體M44和M42的閘 極端。 圖3係繪示圖2中之驅動訊號的時序圖。請合併參照 圖2和圖3。當訊號產生器230接收時脈訊號CLK之後， 會產生驅動訊號VA、VB、VC和VD。其中，驅動訊號 VA和VB係彼此同步但是互為反相。此外，驅動訊號VA 和VC可以是同一個訊號，而驅動訊號VB和VD則可以 是另一個訊號。 在T0週期内，驅動訊號VA和VC會是高電位，而驅 動訊號VB和VD則是低電位，以致於電晶體M21、M24、 M32和M41會導通，而電晶體M23、M22、M34和M43 則是關閉狀態。而由於驅動訊號delay_VA、delay_VB、 delay一VC 和 delay—VD 與驅動訊號 VA、VB、VC 和 VD 僅 僅相差預設時間T2而已，故驅動訊號delay_VA和 delay_VC在T0時會與驅動訊號VA和VC同相，而驅動 1296偏·/g 訊號VB和VD則與驅動訊號VB和VD同相，以致於電 • 晶體M33和]V144會導通，而電晶體M31和]VI42則是關閉 狀悲。此日守’僅有驅動電流源Π所產生的驅動電流江)1 • 流入電流控制電路210的電流輸入端N1，然後通過電晶體See below. W ^ [Embodiment] FIG. 2 is a circuit diagram of a low-voltage differential signal driver having a pre-emphasis circuit in accordance with a preferred embodiment of the present invention. Referring to Fig. 2, in the LVDS driver 200, a current control circuit 21A and a set enhancement circuit 220 are included. The pre-emphasis circuit 220 is further divided into a source current circuit 220a and a no-flow circuit 220b, which are respectively coupled to the current input terminal N1 and the current output terminal N2 of the current control circuit 210. The current control circuit 210 also has outputs R+ and R_ for interfacing the load rl. • In the current control circuit 21A, transistors M21, M22, M23, and M24 are disposed. The first source/汲 terminal of the transistor M21 is coupled to the current input terminal N1, the gate terminal receives the driving signal VB, and the second source/− terminal is coupled to the output terminal R+ through the node 201. Similarly, the first source/汲 terminal and the second source/汲 terminal of the transistor M23 are respectively coupled to the current input terminal N1 and the transmission node 203 coupled to the wheel terminal R_, and the gate terminal thereof receives the driving signal VA. . In addition, the first source/汲 terminal and the second source/汲 terminal of the transistor M22 are coupled to the output 13 I2964 §lw, the doc/g terminal R+, and the current output terminal N2 through the node 2〇1, respectively. The gate terminal receives the drive: nickname VD. In contrast, the first source/汲 terminal and the second source _ /汲 terminal of the transistor M24 are coupled to the second source/drain terminal of the transistors M23 and M22, respectively, and the gate terminal receives the driving signal. VC. In this embodiment, the current input terminal of the current control circuit is coupled to the voltage source VDD through the driving current source n, and the current output terminal N2 is grounded through the driving current source 12. Further, in the present embodiment, the transistors M21 and M23 may be PMOS transistors, and the transistors M22 and M24 may be NMOS transistors. In the source circuit 220a, four transistors (m3 1, M32, M33, and M34) are also disposed. The first source/汲 terminal of the transistor M31 is coupled to the voltage source VDD through the resistor R1, the gate terminal receives the driving signal delay-VA′, and the second source/汲 terminal is coupled to the first source of the transistor M32. /汲 Extreme. Similarly, the first and second source/deuteration terminals of the transistor M33 respectively connect the first source/deuterium terminals of the transistors M31 and M34, and the gate terminals of the transistor M33 receive the driving signal delay_VB. The driving signals delay_VA and delay-VB are respectively driving signals VA and VB after a predetermined time delay. In addition, the second source/deuterium terminals of the transistors M32 and M34 are connected in common to the current input terminal N1' of the current control circuit 210, and the gate terminals of the transistors M32 and M34 receive the driving signals VB and VA, respectively. The source circuit 220a is the same. In the no-flow circuit 220b, four transistors are also arranged, which are M41, M42, M43, and M44, respectively. 14 I2964^8twfdoc/g, wherein the first source/汲 terminal of the transistor M41 is connected to the current output terminal N2 of the current control circuit 210, the gate terminal receives the driving signal vc, and the second source/汲 terminal is coupled. The first source/汲 terminal of the transistor M42 is connected. Similarly, the first and second source/namp terminals of transistor M43 are coupled to the first source/no terminal of transistors M41 and M44, respectively, and the gate terminal of transistor M43 receives drive signal VD. In addition, the second source/no terminal of the transistors M42 and M44 are grounded through the resistor R2, and the gate terminals of the transistors M32 and M34 receive the driving signals delay_VD and delay_VC respectively, wherein the driving signal delay-VC And delay_VD are the drive signals VC and VD after the preset time delay. In an embodiment of the invention, transistors M31, M32, M33 and M34 may be PMOS transistors, while transistors M41, M42, M43 and M44 may be NMOS transistors. Additionally, in embodiments of the present invention, drive signals VA, VB, VC, and VD may be generated by signal generator 230. The signal generator 230 can be composed of a phase locked loop which generates drive signals VA, VB, VC and VD according to an input clock signal CLK. In order to generate the drive signals delay_VA, delay_VB, delay_VC, and delay_VD, the pre-emphasis circuit 220 is further provided with buffer modules 240 and 250. In the buffer module 240, inverters p/21, IV22, IV23, and IV24 are disposed. The input of the inverter IV21 receives the driving signal VB, and the output thereof is sent to the gate terminal of the transistor M33 through the inverter IV23. Therefore, when the driving signal VB is delayed by the delay of the inverters IV21 and IV23, the driving signal delay-VB is generated. In other words, the above preset time is the delay time of the inverters IV21 and IV23. The same principle, after the drive signal VA passes through the inverters IV22 and IV24, the drive signal delay VA is generated and sent to the gate terminal of the transistor M31. Like the buffer module 240, the inverters IV25, IV26, IV27, and IV28 are also disposed in the buffer module 250. The same principle, when the drive signals VC and VD pass through the inverters IV26 and IV28, respectively, and through the inverters IV25 and IV27, the drive signals (jeiay VC and delay-VD) are generated and sent to the transistors respectively. The gate terminals of M44 and M42. Fig. 3 is a timing diagram of the driving signals in Fig. 2. Please refer to Fig. 2 and Fig. 3. When the signal generator 230 receives the clock signal CLK, the driving signals VA, VB are generated. , VC and VD, wherein the driving signals VA and VB are synchronized with each other but are mutually inverted. In addition, the driving signals VA and VC may be the same signal, and the driving signals VB and VD may be another signal. Inside, the drive signals VA and VC will be high, while the drive signals VB and VD will be low, so that the transistors M21, M24, M32 and M41 will be turned on, while the transistors M23, M22, M34 and M43 are turned off. Since the driving signals delay_VA, delay_VB, delay-VC, and delay-VD are only different from the driving signals VA, VB, VC, and VD by the preset time T2, the driving signals delay_VA and delay_VC are combined with the driving signals VA at T0. VC is in phase, The drive 1296 bias / / g signal VB and VD are in phase with the drive signals VB and VD, so that the crystal M33 and ] V144 will be turned on, while the transistors M31 and ] VI42 are closed. The driving current generated by the driving current source 江)) • flows into the current input terminal N1 of the current control circuit 210, and then passes through the transistor
- M2卜並且從節點2〇1流至負載RL。一般來說，負載RL 的傳統規格大約是100歐姆，惟本發明並不加以限定。當 驅動電流ID1循路徑A通過負載RL後，會從流入節點 203，並且經過電晶體μ 2 4和驅動電流源12後流至接地端。 ⑩ 假設在tl的瞬間，驅動訊號VA和VC從高電位切換 至低電位，而驅動訊號VB和VD則從低電位切換至高電 位。此時，電晶體M23和M22會導通，而電晶體M21和 M24則會關閉，以致驅動電流ID1會轉而從電晶體M23 的第一源/汲極端流入，然後通過節點203後到達負載RL。 接著，驅動電流RL會循著路徑B流過負載RL，然後進入 節點201，並且通過電晶體M22和驅動電流源12後而流至 接地端。 _ 此外，電晶體M34和M43會導通，而電晶體M32和 M41則會關閉。然而，驅動訊號delay_VA、delayJ/B、 ' delay—VC和delay_VD在tl的瞬間還不會轉態，因此電晶 : 體M33和]M44仍舊維持導通狀態，而電晶體M31和M42 則仍舊維持關’閉狀態。此時，前置增強電路220會產生一 額外的驅動電流ID2從電流輸入端N1流入，然後循著驅 動電流ID1相同的路徑而流至接地端。此一過程，會持續 預設時間T2，以致於在預設時間T2的週期内，前置增強 17 I2964^8twfdoc/g 電路220可以加快LvDS驅動器200的切換速度。 接著在t2時，驅動訊號delay_VA和delay_VC會從高 電位轉態為低電位，而驅動訊號delay_VB和delay_VD則 會從低電位轉態為高電位，以致於電晶體M33和M44會 關閉’而電晶體M31和M42則轉而導通。此時，驅動電 流1D2會被禁能(Disable)，使得LVDS驅動器200仍舊維 持正常運作。 經過T1週期後，在t3時，驅動訊號VA和VC會再 次從低電位切換至高電位，而驅動訊號VB和VD則再次 從高電位切換至低電位。此時，電晶體M21和M24會再 次導通’而電晶體M23和M22則會重新關閉。因此，驅 動電流ID1流過電流控制電路21〇的路徑，會與在το週 期期間相同。 此外，電晶體M32和M41會再次導通，而電晶體M34 和M43會重新關閉。同樣的原理，由於驅動訊號 delay一VA、delay—VB、delay—VC 和 delay—VD 在 t3 的瞬間 還不會轉態，因此電晶體M31和M42會維持導通狀態， 而電晶體M33和M44會維持關閉狀態。此時，前置增強 電路220又會產生額外的驅動電流ID2從電流輸入端N1 流入，然後循著驅動電流Π)1相同的路徑而流至接地端。 此一過程，同樣會持續預設時間T2。 接著在t4時，驅動訊號dday_VA和delay_VC會從低 電位轉態為高電位，而驅動訊號delay_VB和delay_VD則 會從高電位轉態為低電位，以致於電晶體M33和M44會 I2964^8twf.doc/g 導通，而電晶體M31和M42則轉而關閉。此時，驅動電 : 流1D2會被禁能，以使得LVDS驅動器200維持正常運作。 •- 在圖3中所繪示之前置增強脈衝訊號，係表示驅動訊 • 號VA和VC與驅動訊號delay—VB和delay—VD進行 '互 • 斥或(XOR)"運算的結果，或者是驅動訊號VB和VD與 驅動訊號delay—VA和delay一VC進行、、互斥或(xqr)//運 异的結果。這個結果，說明了圖2中之前置增強電路220 僅在電流控制電路切換驅動電流ID1路徑的瞬間，才會提 供額外的驅動電流ID2，因此並不會影響lVDS驅動器2〇〇 正常的運作。此外，前置增強脈衝訊號也說明了本發明可 以具有較高的解析度。- M2 and flow from node 2〇1 to load RL. In general, the conventional specification of the load RL is approximately 100 ohms, but the invention is not limited. When the drive current ID1 follows the path A through the load RL, it flows from the inflow node 203 and through the transistor μ 24 and the drive current source 12 to the ground. 10 Assume that at the instant of tl, the drive signals VA and VC are switched from high to low, and the drive signals VB and VD are switched from low to high. At this time, the transistors M23 and M22 are turned on, and the transistors M21 and M24 are turned off, so that the driving current ID1 will in turn flow from the first source/汲 terminal of the transistor M23, and then pass through the node 203 to reach the load RL. Then, the drive current RL flows through the load RL following the path B, then enters the node 201, and flows to the ground through the transistor M22 and the drive current source 12. _ In addition, transistors M34 and M43 will turn on, while transistors M32 and M41 will turn off. However, the drive signals delay_VA, delayJ/B, 'delay-VC and delay_VD will not change at the instant of tl, so the crystal: body M33 and] M44 remain in the on state, while the transistors M31 and M42 remain unchanged. 'Closed state. At this time, the pre-emphasis circuit 220 generates an additional drive current ID2 flowing from the current input terminal N1, and then flows to the ground terminal in the same path as the drive current ID1. In this process, the preset time T2 is continued, so that the pre-amplification 17 I2964^8twfdoc/g circuit 220 can speed up the switching speed of the LvDS driver 200 during the period of the preset time T2. Then at t2, the drive signals delay_VA and delay_VC will transition from a high potential to a low potential, while the drive signals delay_VB and delay_VD will transition from a low potential to a high potential, so that the transistors M33 and M44 will turn off while the transistor M31 and M42 turn to turn on. At this time, the drive current 1D2 is disabled, so that the LVDS driver 200 is still operating normally. After the T1 cycle, at t3, the drive signals VA and VC are switched from low to high again, and the drive signals VB and VD are switched from high to low again. At this time, the transistors M21 and M24 will be turned on again, and the transistors M23 and M22 will be turned off again. Therefore, the path through which the drive current ID1 flows through the current control circuit 21A is the same as during the period of το. In addition, transistors M32 and M41 will turn on again, and transistors M34 and M43 will turn off again. The same principle, because the drive signals delay VA, delay-VB, delay-VC, and delay-VD will not change at the moment t3, the transistors M31 and M42 will maintain the conduction state, and the transistors M33 and M44 will Stay closed. At this time, the pre-emphasis circuit 220 generates an additional drive current ID2 flowing from the current input terminal N1, and then flows to the ground terminal following the same path of the drive current Π)1. This process will also last for the preset time T2. Then at t4, the drive signals dday_VA and delay_VC will transition from a low potential to a high potential, while the drive signals delay_VB and delay_VD will transition from a high potential to a low potential, so that the transistors M33 and M44 will be I2964^8twf.doc /g turns on, while transistors M31 and M42 turn off. At this time, the drive power: stream 1D2 will be disabled to keep the LVDS driver 200 operating normally. •- The pre-enhanced pulse signal is shown in Figure 3, which is the result of the 'mutual repulsion or (XOR)" operation of the drive signal VA and VC with the drive signals delay-VB and delay-VD. Alternatively, the drive signals VB and VD are combined with the drive signals delay-VA and delay-VC, and are mutually exclusive or (xqr)//transported. This result shows that the pre-emphasis circuit 220 of Fig. 2 provides an additional drive current ID2 only when the current control circuit switches the drive current ID1 path, and thus does not affect the normal operation of the lVDS driver 2. In addition, the pre-emphasis pulse signal also indicates that the present invention can have a higher resolution.
圖4係纟會示依照本發明另一實施例的一種具有前置增 強電路之低壓差動訊號驅動器的電路圖。請參照圖4，本 實施例所提供的LVDS驅動器400的架構，大致上與圖2 之LVDS驅動器200相同。而LVDS驅動器400與LVDS 驅動器200的不同點，在於電流控制電路21〇的電流輸出 φ 端N2 ’係透過電阻R3而接地。而LVDS驅動器400的操 作方法’係與LVDS驅動杰200相同，請熟習此技藝者自 〜 行參照LVDS驅動器200之敘述。 : 雖然在圖2和圖4中，電晶體M21、M23、M31、M32、 M33和M34係PMOS電晶體，而電晶體M22、M24、m4卜 M42、M43和M44則為NMOS電晶體，然而本發明並不 以此限定。熟習此技藝者當知，本發明僅需要電晶體M21、 M23、M31、M32、M33和M34彼此的電氣特性相同，而 19 I2964^8twfdoc/g 與電晶體M22、M24、M41、M42、M43和M44的電氣特 . 性相反即可。 綜上所述，本發明至少有以下優點： m m • 丨·由於本發明内所使用之驅動訊號皆彼此同步，因此 • 可以使得本發明具有較高的解析度。 2·由於在本發明中，驅動訊號至多僅需要經過兩個反 向器的處理，因此本發明具有較高的切換速度。 鲁雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1係繪示一種習知之低壓差動訊號驅動器之電路 圖。 圖2係繪示依照本發明之一較佳實施例的一種具有前 置增強電路之低壓差動訊號驅動器的電路圖。 • 圖3係繪示圖2中之驅動訊號的時序圖。 圖4係繪示依照本發明另一實施例的一種具有前置增 " 強電路之低壓差動訊號驅動器的電路圖。 : 【主要元件符號說明】 200、400 ·· LVDS 驅動器 210 :電流控制電路 220 :前置增強電路 230 :訊號產生器 I2964^8twfdoc/g 240、250 :緩衝模組 II、12:驅動電流源 IV2卜 IV22、IV23、IV24、IV25、IV26、IV27、IV28 : 反向器4 is a circuit diagram showing a low voltage differential signal driver having a preamplifier circuit in accordance with another embodiment of the present invention. Referring to FIG. 4, the architecture of the LVDS driver 400 provided in this embodiment is substantially the same as the LVDS driver 200 of FIG. The difference between the LVDS driver 400 and the LVDS driver 200 is that the current output φ terminal N2' of the current control circuit 21 is grounded through the resistor R3. The operation method of the LVDS driver 400 is the same as that of the LVDS driver 200. Please refer to the description of the LVDS driver 200 by those skilled in the art. : Although in FIGS. 2 and 4, the transistors M21, M23, M31, M32, M33, and M34 are PMOS transistors, and the transistors M22, M24, m4, M42, M43, and M44 are NMOS transistors, but this is The invention is not limited by this. As is known to those skilled in the art, the present invention only requires that the electrical characteristics of the transistors M21, M23, M31, M32, M33 and M34 are the same, and that the 19 I2964^8twfdoc/g and the transistors M22, M24, M41, M42, M43 and The electrical characteristics of the M44 can be reversed. In summary, the present invention has at least the following advantages: m m • 丨· Since the driving signals used in the present invention are synchronized with each other, the present invention can be made to have a higher resolution. 2. Since in the present invention, the drive signal only needs to be processed by two reversers, the present invention has a higher switching speed. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing a conventional low voltage differential signal driver. 2 is a circuit diagram of a low voltage differential signal driver having a front enhancement circuit in accordance with a preferred embodiment of the present invention. • Figure 3 is a timing diagram of the drive signal of Figure 2. 4 is a circuit diagram of a low voltage differential signal driver having a preamplifier and a strong circuit in accordance with another embodiment of the present invention. : [Main component symbol description] 200, 400 ·· LVDS driver 210: current control circuit 220: pre-emphasis circuit 230: signal generator I2964^8twfdoc/g 240, 250: buffer module II, 12: drive current source IV2 IV22, IV23, IV24, IV25, IV26, IV27, IV28: reverser
Mil、M12、M13、M14、M21、M22、M23、M24、 M31、M32、M33、M34、M41、M42、M43、M44 :電晶 體Mil, M12, M13, M14, M21, M22, M23, M24, M31, M32, M33, M34, M41, M42, M43, M44: electromorph
Rl、R2 :電阻 RL :負載 Rt ··負載電阻 VDD :電壓源 21Rl, R2: resistance RL: load Rt · load resistance VDD: voltage source 21