1291215 九、發明說明： 【發明所屬之技術領域】 =發明係關於_種金屬内連線製程與結構，尤指―種利用硬 罩幕作為金屬内連線製程與結構。 【先前技術】 隨著積體電路的線寬不斷地縮小，半導體元件的微小化 已進入到奈米等級’而單一晶片的積集度亦即其上之半導 體兀件的密度愈大表示元件之間的間隔也就愈小 ，這使得 接觸洞與金屬内連線的製作愈來愈困難。 請參考S 1圖至第11圖。第！圖至第u圖係為習知技 術在製作接觸洞與金屬内連線的方法示意圖。如第丨圖所 示，首先提供一半導體基底1〇，且半導體基底1〇上形成 有至少一金屬氧化半導體(MOS)電晶體元件20，其包括有 源極/没極區域12設於半導體基底10中.，一閘極結構14 設於半導體基底10上，以及一側壁子16設於閘極結構14 之周圍側壁。同時MOS電晶體元件20並以淺溝絕緣區域 24電性隔離。此外，在MOS電晶體元件20以及半導體基 底1 〇表面上覆蓋有一接觸洞餘刻停止層（c〇ntact etch stop layer，CESL)32，而在接觸洞蝕刻停止層32之上則覆蓋有 一層第一介電層34。接著，在第一介電層34上方依序形 成一抗反射層36與一光阻層40，再利用曝光暨顯影製程， 1291215 在光阻層40 t形成帝 與閘極結構14上方/之開^ 42，以於職/祕區域12 乃別定義出接觸洞之位置。 如弟2圖所示，技 行非等向性餘刻！^用光阻層40作為餘刻遮罩以進 36以及第-介電層:广由各開口 42來蝕刻抗反射層 面，以形成開口 4^ H並停止於接觸洞餘刻停止層32表 随後，如第3圖所示，再利用光卩且# ::及=射層36作為"刻遮罩以進行蘭製程二 ::二接觸洞敍刻停止層32，形成接觸洞46。 =:如第4圖所示，將第一介電層別上方剩餘的 40與抗反射層36去除。 如第5圖所示為增加金屬與第一介電層如之間的附著力， 並同時防止後續於接铜巾断金屬填充時所可錢生之尖峰 ㈣_題與電移(細omigration)等現象，因此需先沉積一擴散 ^F#(diffusion barrier)^ 47，nitride, ΤίΝ)/|λ _nium，Ti)的複合金屬層，覆蓋在各接觸洞*侧壁表面與底部之 閘極結構Η及源極級極區域12上，然後再沉麟(tungsten % 等金屬48填滿各接觸洞46並覆蓋在擴散阻障層47表面，如第6 圖所示。隨後再如第7圖所示，進行第一化學機械研磨⑽伽^ mechanical polishing，CMP)製程’把第一介電層34表面上多餘的 金屬48去除’以形成所需之接觸插塞(c〇mactplug)49。 Ί2912151291215 IX. Description of the invention: [Technical field to which the invention belongs] = The invention relates to the process and structure of the metal interconnection process, especially the use of a hard mask as a metal interconnect process and structure. [Prior Art] As the line width of the integrated circuit is continuously reduced, the miniaturization of the semiconductor element has entered the nanometer level 'the degree of integration of the single wafer, that is, the higher the density of the semiconductor element thereon indicates the element The smaller the spacing between them, the more difficult it is to make contact holes and metal interconnects. Please refer to S1 to 11. The first! Figures to U are schematic views of a method of making contact holes and metal interconnects in the prior art. As shown in the first drawing, a semiconductor substrate 1 is first provided, and at least one metal oxide semiconductor (MOS) transistor element 20 is formed on the semiconductor substrate 1 , and the source/drain region 12 is disposed on the semiconductor substrate. 10, a gate structure 14 is disposed on the semiconductor substrate 10, and a sidewall 16 is disposed on a sidewall of the gate structure 14. At the same time, the MOS transistor element 20 is electrically isolated by the shallow trench isolation region 24. In addition, a surface stop etch stop layer (CESL) 32 is covered on the surface of the MOS transistor element 20 and the semiconductor substrate 1 , and a layer is covered on the contact hole etch stop layer 32 . A dielectric layer 34. Then, an anti-reflection layer 36 and a photoresist layer 40 are sequentially formed on the first dielectric layer 34, and then exposed and developed on the photoresist layer 40t by using an exposure and development process, 1291215. ^ 42, for the job / secret area 12 is not to define the location of the contact hole. As shown in Figure 2, the technique is an isotropic remnant! Using the photoresist layer 40 as a mask to advance 36 and the first dielectric layer: the anti-reflection layer is widely etched by each opening 42 to form an opening 4^H and stop at the contact hole to stop the layer 32. Thereafter, as shown in FIG. 3, the stop and the stop layer 32 are formed by using the aperture and #: and = shot layer 36 as the "cut mask to perform the blue process:: two contact holes. =: As shown in Fig. 4, the remaining 40 above the first dielectric layer and the anti-reflection layer 36 are removed. As shown in Fig. 5, it is to increase the adhesion between the metal and the first dielectric layer, and at the same time prevent the spikes that can be generated when the metal towel is broken. (4) _ questions and electromigration (fine migration) And so on, so it is necessary to deposit a diffusion metal layer of ^F# (diffusion barrier)^47,nitride, ΤίΝ)/|λ _nium,Ti), covering the gate structure of the sidewall and bottom of each contact hole*Η And the source-level pole region 12, and then the metal 48 (tungsten% and other metal 48 fills the contact holes 46 and covers the surface of the diffusion barrier layer 47, as shown in Fig. 6. Then as shown in Fig. 7. A first chemical mechanical polishing (10) process is performed to remove the excess metal 48 on the surface of the first dielectric layer 34 to form a desired contact plug (49). Ί291215
田如第8,所不’接著在第_介電層別與接觸插塞仍上依 豐-钱刻停止層50、-第二介電層义與一圖案化光阻層％，並 利用圖案化光阻層Μ作為钱刻遮罩來侧部份之第二介電層幻 :蝕刻停止層50，以形成溝渠56，如第9圖所示。之後再“一 ‘準之銅縣’崎各輕％ t依序沉積—統鈦⑽)/欽 之擴散阻障層(未顯示)以及一晶種層㈣_ (未顯示懷蓋在各 溝渠56側壁表面與底部之第二介電層％及各接觸插塞49上 電鑛形摘金屬58，如㈣騎示。最後進行第二化學機械研 磨’將第二介電層52表面上多餘的銅金屬％去除，即分卿成 電連接各接_塞49之金屬導線6〇，如第u圖所示。 如上所述’目前半導體的接觸洞姓刻製程皆僅使用光阻層圖案 做為姓刻遮罩，但隨著半導體元件對接觸洞之侧後臨界尺寸 (Afte^Etch-Inspection Critical Dimension, ΑΕΙ ^ φ而微和製私在193nm光阻上的光學限制卻愈來愈多，因此於目前 心準之65奈米的接觸洞製程中’微影製程必須降低光阻厚度至 2800埃才月b製作出65奈米的接觸洞’而且在45奈米的接觸洞製 程中，微影製程更必卿減光阻厚度至22〇0.埃以下。然而厚度過 薄的光阻層卻會在侧製程中產生屏蔽不足造成邊界缺陷等問 題所以蝕刻製程無法只使用光阻層圖案做為蝕刻遮罩，而必須 使用硬罩幕的製程。但是45奈米製程卻無法使用一般常用的多晶 石夕硬罩幕’因為其會導致元件表面之石夕化鎳等金屬石夕化物㈣ 、 發生相變化。 1291215 步驟 此外，上述之習知技術製作金屬内 點，就是在形綱”編韻刻停止/有如^缺 本=所提出之硬罩幕製程，即可省略输刻停止層此 【發明内容】 本毛月之目的之-在於提出一種利用 遮罩與蝕刻停止層之全眉 千夢作马蚀幻 技術之_。屬内連線製程與結構，以克服習知 連線=!所揭露之專利範圍，本發明係提供-製作金屬内 ί 述方法與結構至少包含有：提供一設置有 二導電體之基底，且於該基底與該第一導電體上依序形 μ電層與-第-圖案化硬罩幕，用以定義至少一第一開 並利贿第—職化硬罩幕作為_遮罩來_該第-二中开二以於該第一介電層中形成該第一開口。接著於該第一開 案=!，’並電連接該第-導電體，且於該第-圖 化硬罩幕，用體=形成-第二介電層-第二圖案 幕乍為蝕刻遮罩並利用該第_ _ ^ 面作為敍刻停止層來_㈣化更罩幕”私―¥電體表 成該第二H e，、 介電層，以於該第二介電層中形 接1笛、1，以及於該第二開σ中形成—第三導電體，並電連 接该弟二導電體。 '1291215 由於本發明係先將Tian Ru 8th, no, then on the _ dielectric layer and the contact plug still on the Effort-money stop layer 50, the second dielectric layer and a patterned photoresist layer%, and use the pattern The photoresist layer is used as a second dielectric layer of the side portion of the mask: the etch stop layer 50 is formed to form the trench 56 as shown in FIG. After that, the "one's quasi-copper county' is a lighter % t sequentially deposited - Titanium (10)) / Qin diffusion barrier (not shown) and a seed layer (four) _ (not shown in the side walls of each trench 56 The second dielectric layer of the surface and the bottom portion and the contact plugs 49 are electrically metal-cut metal 58 as shown in (4). Finally, a second chemical mechanical polishing is performed to remove excess copper metal on the surface of the second dielectric layer 52. % removal, that is, the connection to the metal wire 6〇 of each connection _ plug 49, as shown in Figure u. As mentioned above, the current semiconductor contact hole name process only uses the photoresist layer pattern as the surname Mask, but with the semiconductor element on the side of the contact hole after the critical dimension (Afte^Etch-Inspection Critical Dimension, ΑΕΙ ^ φ and micro-and optical privacy on the 193nm photoresist is more and more, so the current heart In the 65nm contact hole process, the 'lithographic process must reduce the photoresist thickness to 2800 angstroms to produce 65nm contact holes' and in the 45nm contact hole process, the lithography process is more The thickness of the photoresist is reduced to 22 〇 0. angstroms. However, the thin layer of the photoresist layer will In the side process, there are problems such as insufficient shielding and boundary defects. Therefore, the etching process cannot use the photoresist layer pattern as an etch mask, but a hard mask process must be used. However, the 45 nm process cannot use the commonly used polycrystalline stone. The eve of the hard mask "because it causes the surface of the element to be etched into the metal, such as nickel, and the phase change occurs. 1291215 In addition, the above-mentioned conventional technique for making the metal inner point is to stop at the shape" / If there is a lack of this = the hard mask process proposed, you can omit the inscription stop layer. [Inventive content] The purpose of this month is to propose a full-browed dream horse using a mask and an etch stop layer. The eclipse technology is an internal connection process and structure to overcome the patent range disclosed by the conventional connection =! The present invention provides - the method of fabricating the metal and the structure at least includes: providing a set of two a substrate of the electrical conductor, and sequentially forming an electrical layer and a -patterned hard mask on the substrate and the first electrical conductor to define at least one first opening and bribing first-level hard mask As a cover The first opening is formed in the first dielectric layer, and then the first opening ==, 'and electrically connected to the first conductor, and the first figure Hard mask, body = formation - second dielectric layer - second pattern curtain is an etch mask and use the first _ _ ^ surface as a stop stop layer _ (four) more masks "private - ¥ electricity Forming the second H e, the dielectric layer, forming a flute 1 in the second dielectric layer, and forming a third electrical conductor in the second open σ, and electrically connecting the brother Two conductors. '1291215
二電層，形成接觸洞，因此餘刻後臨界尺寸(AMD)可小 更^後I界尺寸(ADI CD)。而林發明之圖案化硬罩幕 ^具有接卿之侧罩幕、接_塞之化學機械研磨製程 =止層以及㈣的金屬内連線製程之溝渠祕刻停止層 力能。此外，本發_彻低溫製備之碳切(SiC)或碳 Γ石夕卿贈侧㈣硬罩幕，故可有效㈣設於間極 、-構與源極/汲極區域表面之9⑽(NiSi)產生相變化。 ^為了使貴審查委員能更近-步了解本發明之特徵及脑内 容，請參閱以下有關本發明之詳細說明與附圖。然而所附圖式僅 供參考與說明用，並非用來對本發明加以限制者。 【實施方式】 請參考第12圖至第20圖。第12圖至第20圖為本發明 一較佳實施例製作一金屬内連線之方法示意圖。如第12圖 所示，首先提供一半導體基底02，例如一半導體晶圓（wafer) 或矽覆絕緣基底（SOI)等，且半導體基底62上形成有至少 一 M0S電晶體元件72,其包括有源極/汲極區域64設於半 導體基底62中，一閘極結構66設於半導體基底62上，以 及一側壁子68設於閘極結構66之周圍壁。同時M0S電晶 體元件72之閘極結構66與源極/汲極區域64之表面另包 1291215 含有一層金屬石夕化物(Silidde)7G’其材質可為.利用自對準 金屬石夕化製程(salicuie)所形成之石夕化錄(NiSi)等而 電晶體元件72並以淺溝絕緣區域74電性隔離。此 MOS電晶體元件72以及半導體基底62表面上依序覆 一接觸洞蝕刻停止層76,而在接觸洞蝕刻停止層凡之上 則覆蓋有一層第一介電層78。 9 前述之第-介電層78與接觸洞餘刻停止層76在材料之 選擇上應考量其㈣選擇比。—般而言，構成第—介電層 %之材料可包含有TEOS錢層、未摻雜錢層或爛^夕 氧化層、氟⑦氧層、御氧層或卿氧料之摻㈣氧層， 其並可利用至少-次之各式旋塗(spi請_)或化學氣相 ，積(CVD)等技術，例如電漿加強化學氣相沈積(pEcvD) 等製程加以形成，而接觸洞㈣冑止層76 Μ可為氮化石夕層 等具高應力之材料或其他與第—介電層78具有高餘刻選 擇比之材料。 接著，在第一介電層78上方依序形成一硬罩幕層8〇、 一第一抗反射層82與一圖案化光阻層84，且圖案化光阻 層84係包含有複數個開口 86，分別對應於閘極結構％與 源極/汲極區域64，藉以定義各個所需之接觸洞。其中，在 本發明之較佳實施例中，硬罩幕層8〇的材料是選用可以低 溫製備之碳化矽（SiC)或碳氮化矽（siCN)等等包含有矽與碳 Ί291215 選擇硬罩幕層80的材料時，其薄膜 400°C ’以避免設於閘極結構66與 之矽化鎳(NiSi)產生相變化，而第一 或氮之化合物，因為在 生成反應溫度必須小_ 源極/汲極區域64表面 抗反射層82則可為氮氧石夕化合物(Si〇N)等。 隨後利用圖案化光阻層84作為餘刻遮罩進行一非等 向蝕刻製程，經由開口 86蝕刻第一抗反射層82與硬罩幕 _層80,以將圖案化光阻層84之圖案轉移至硬罩幕層8〇中， 形成第一圖案化硬罩幕81，如第13圖所示，其中值得注 意的是，在正常的蝕刻參數的控制與調整下，本發明之圖 案化光阻層84之顯影後臨界尺寸(adi cd)88係略大於第 一圖案化硬罩幕81之蝕刻後臨界尺寸(AEICD)9〇，而可滿 足45奈米以下之半導體製程。 • ^ . 如第14圖所示，在去除圖案化光阻層84與抗反射層 • 82之後，本發明即係利用第一圖案化硬罩幕81作為蝕刻 遮罩來#刻第一介電層78與接觸洞姓刻停止層76，以於 第一介電層78與接觸洞餘刻停止層76中形成作為接觸洞 92之開口，且於接觸洞92形成後可另進行一清潔製程， 其中清潔製程可為一溼式清洗製程或一乾式清洗製程，並 利用同位(in_situ)或非同位（ex-situ)方式進行，以去除餘刻 第一介電層78時於接觸洞92之内壁所殘留之高分子副產 物。隨後於苐一圖案化硬罩幕81之表面與接觸洞92之内 1291215 壁上形成一擴散阻障層94。其中擴散阻障層94為一氮化 鈦(titanium nitride，TiN)/欽(titanium，Ti)或一氮化如 (tantalum nitride，TaN)/组（tantalum，Ta)的複合金屬層，用以 避免金屬原子的擴散所引發的破壞元件特性等問題，並同 時增加金屬與第一介電層78之附著力。另外值得注音的 是，為確保閘極結構66與源極/汲極區域64之導電良好或 維持接觸洞92内壁之潔淨度，於形成接觸洞幻後另可進 ⑩行至少一表面處理製程 '例如利用一摻雜製程以降低閘極 結構66與源極/汲極區域64之電阻值，以利於後續接觸插 塞之製作。 ' 如第15圖所示，接著沉積鎢(tungsten，w)等第一金屬芦 98填滿接觸洞92，並覆蓋於擴散阻障層·94上，以電連接 閘極結構66與源極/沒極區域64，然後再利用第一圖 硬罩幕81當做停止層，對第一金屬層98以及擴散阻障声 94進行第-化學機械研磨製程，以於第一介電層π中： 成各個接觸插塞100之製程，如第16圖所示。 疋 隨後如第17圖所示，於第一圖案化硬罩幕81盘各 插塞100上方依序形成一第二介電層1〇2、—第二;觸 層刚與-第二圖案化硬罩幕106，且第二圖案化:士 應包含有魏_口齡齡卿胁_ 66與源極/汲極區域64之各接觸插塞1〇〇 、·，。構 棺从疋義所需 12 1291215 溝渠110的位置。然後再利用第二圖案化硬罩幕106作為 蝕刻遮罩並利用第一圖案化硬罩幕81與接觸插塞1〇〇之表 面作為蝕刻停止層來蝕刻第二抗反射層104與第二介電層 102,以於第二抗反射層104與第二介電層1〇2中形成相對 應之溝渠110，之後去除第二圖案化硬罩幕1〇6與第二抗 反射層104，如第18圖所示。其中，第二介電層1〇2之材 料可以包含有TEOS矽氧層、未摻雜矽氧層或硼磷矽氧化 層、氣石夕氧層、磷砂氧層或删石夕氧層等之摻雜石夕氧層，其 亦可利用至少一次之各式旋塗或化學氣相沈積(CVD)等技 術，例如電漿加強化學氣相沈積等之沉積製程加以形成， 而第二圖案化硬罩幕106則係為光阻材料。 如第19圖所示，接著再進行一標準之銅製程或其他低 電阻導電體的沉積製程。例如先於各溝渠110中依序沉積 :氮化鈦(TiN)/鈦(Ti)或一氮化鈕(TaN)/鈕(Ta)的之擴散阻 p早層（未顯不）以及一晶種層（seedlayer)(未顯示）覆蓋在各 溝渠iig側絲面與底部之第二介料1()2及各接觸插塞 100上，再電錢銅以形成第二金屬層112填滿溝渠11〇，此 為習知相關技藝者與通常知識者所熟知，在此不多加資 述。最後再利用第二介電層1()2#做停止層，對第二金屬 ^ 2二及擴散阻障層（未顯示）進行第二化學機械研磨製 耘乂凡成所需之金屬導線1M並分別電連接各接觸插塞 100，如第20圖所示。 1291215 綜上所述，本發明亦同時揭露一種金屬内連線結構。如 第20圖所示，本發明之金屬内連線結構係位於一半導體基 底62上，且半導體基底62中設置有至少一第一導電體， 例如包含閘極66、源極/汲極區域64與側壁子68之moS 電晶體元件72，而本發明之金屬内連線結構包含有一位於 半導體基底62上並覆蓋第一導電體之第一介電層78，/ 位於第一介電層78上之第一圖案化硬罩幕81，，一設置 • 於第一圖案化硬罩幕81與第一介電層78中並電連接第〆 導電體之接觸插塞100，，一設置於接觸插塞1〇〇與第一 圖案化硬罩幕81上之弟二介電層102，，以及一設置於第 二介電層102中且位於第一圖案化硬罩幕81上並電連接接 觸插塞100之金屬導線114，。其中構成各薄膜層以及各 導電體之材料已揭露於第12圖至第2〇圖之實施例中，在 此亦不詳加敘述。 由於本發明係先利圖案化光阻層84作為蝕刻遮罩來 餘刻硬罩幕層8G，以將圖案化光阻層84之圖案轉移至硬 轉層80中，形成第—圖案化硬罩幕8卜然後再利用第 1案化硬罩幕81作為㈣遮罩來㈣第—介電層78, ^成所需之接觸洞92。如此-來，便可以祕刻程式丰 制弟一圖案化硬罩幕81上圖宰 : 展 口茶之臨界尺寸，使得蝕刻後g 發明、（^EICD)小於顯影後臨界尺寸(ADICD)。同時，4 X之弟一圖案化硬罩幕81不但是用來當作接觸洞92之 1291215 姓刻罩幕，以及用來當作接觸插塞100之化學機械研磨製 程的停止層，而且更可以用來作為後續的金屬内連線製程 中溝渠110的飯刻停止層，省去習知技術中需額外沉積一 钱刻停止層的步驟。此外，由於65奈米以下之製程需要使 用石夕化鎳(NiSi)作為閘極結構66與源極/沒極區域64表面 之金屬矽化物70，所以在本發明中，硬罩幕層8〇的材料 是採用可以低溫製備之碳化矽（Sic)或碳氮化矽（SiCN)，其 _薄膜生成反應溫度必須小於40(rc，以避免設於閑極結構 66與源極/汲極區域64表面之矽化鎳（Nisi)產生相變化。 以上所述僅為本發明之較佳實關，驗本發明申請專 利範圍所狀均㈣化與修飾1應屬本發明之涵蓋範圍。 圖式簡單說明 主要元件符號說明 10 半導體基底 14 閘極結構 20 MOS電晶體元件 12 源極/汲極區域 16 側壁子 24 淺溝絕緣區域 1291215 32 接觸洞蝕刻停止層 34 第一介電層 36 抗反射層 40 光阻層 42 開口 44 開口 46 接觸洞 47 擴散阻障層 48 金屬 49 接觸插塞 50 名虫刻停止層 52 第二介電層 54 圖案化光阻層 56 溝渠 • 58 銅金屬 60 金屬導線 62 半導體基底 64 源極/汲極區域 66 閘極結構 68 側壁子 70 金屬矽化物 72 MOS電晶體元件 74 淺溝絕緣區域 76 接觸洞蝕刻停止層 78 第一介電層 80 硬罩幕層 81 第一圖案化硬罩幕 82 第一抗反射層 84 圖案化光阻層 86 開口 • 88 顯影後臨界尺寸 90 蝕刻後臨界尺寸 92 接觸洞 94 擴散阻障層 98 第一金屬層 100 接觸插塞 102 第二介電層 104 第二抗反射層 106 第二圖案化硬罩幕 108 開口 110 溝渠 112 第二金羼層 114 金屬導線 16The second electrical layer forms a contact hole, so the critical dimension (AMD) can be smaller and later the I dimension (ADI CD). The patterned hard mask of the invention of Lin has the side shield of the joint, the chemical mechanical polishing process of the plug, the stop layer, and the metal interconnecting process of the trench. In addition, the carbon cutting (SiC) prepared by the present invention is a low-temperature preparation (SiC) or carbon gangue Xiqing gift side (four) hard mask, so it can be effective (4) 9(10) (Ni) provided on the surface of the interpole, -structure and source/drain regions. ) produces a phase change. In order to enable the reviewing committee to get closer to the features and brain content of the present invention, please refer to the following detailed description of the invention and the accompanying drawings. The drawings are to be considered in all respects as illustrative and not limiting. [Embodiment] Please refer to Figures 12 to 20. 12 to 20 are schematic views showing a method of fabricating a metal interconnect in accordance with a preferred embodiment of the present invention. As shown in FIG. 12, a semiconductor substrate 02, such as a semiconductor wafer or a silicon-on-insulator substrate (SOI), etc., is first provided, and at least one MOS transistor element 72 is formed on the semiconductor substrate 62, which includes The source/drain region 64 is disposed in the semiconductor substrate 62, a gate structure 66 is disposed on the semiconductor substrate 62, and a sidewall spacer 68 is disposed on the surrounding wall of the gate structure 66. At the same time, the gate structure 66 of the MOS transistor component 72 and the surface of the source/drain region 64 are further covered with a layer 1291215 containing a layer of metal silicide (Silidde) 7G'. The material can be made by using a self-aligned metallization process ( The electro-crystal element 72 formed by the salicuie is formed by NiSi or the like and electrically isolated by the shallow trench isolation region 74. The MOS transistor element 72 and the semiconductor substrate 62 are sequentially covered with a contact etch stop layer 76, and a contact layer etch stop layer is overlaid with a first dielectric layer 78. 9 The aforementioned first-dielectric layer 78 and contact hole residual stop layer 76 should be considered in terms of material selection (iv) selection ratio. In general, the material constituting the first dielectric layer may include a TEOS layer, an undoped layer or a ruthenium oxide layer, a fluorine 7 oxygen layer, an oxygen barrier layer, or a doped oxygen layer. , and can be formed by using at least a plurality of techniques such as spin coating (CVD) or chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (pEcvD), and contact holes (4) The stop layer 76 Μ may be a material having high stress such as a nitride layer or other material having a high residual ratio to the first dielectric layer 78. Next, a hard mask layer 8 , a first anti-reflective layer 82 and a patterned photoresist layer 84 are sequentially formed over the first dielectric layer 78 , and the patterned photoresist layer 84 includes a plurality of openings. 86, corresponding to the gate structure % and the source/drain region 64, respectively, thereby defining each desired contact hole. Wherein, in the preferred embodiment of the present invention, the material of the hard mask layer 8 is selected from the group consisting of niobium carbide (SiC) or niobium carbonitride (siCN) which can be prepared at a low temperature, and the like. When the material of the curtain layer 80 is used, the film 400 ° C 'to avoid the phase change of the gate structure 66 and the nickel (NiSi) phase change, and the first or nitrogen compound must be small in the formation reaction temperature _ source The surface anti-reflection layer 82 of the drain region 64 may be a oxynitride compound (Si〇N) or the like. Subsequently, the non-isotropic etching process is performed by using the patterned photoresist layer 84 as a residual mask, and the first anti-reflective layer 82 and the hard mask layer 80 are etched through the opening 86 to transfer the pattern of the patterned photoresist layer 84. To the hard mask layer 8 ,, a first patterned hard mask 81 is formed, as shown in FIG. 13, wherein it is noted that the patterned photoresist of the present invention is controlled and adjusted under normal etching parameters. The post-development critical dimension (adi cd) 88 of layer 84 is slightly larger than the post-etch critical dimension (AEICD) of the first patterned hard mask 81, and can satisfy semiconductor processes below 45 nm. • ^ . As shown in FIG. 14 , after removing the patterned photoresist layer 84 and the anti-reflective layer • 82, the present invention utilizes the first patterned hard mask 81 as an etch mask to inscribe the first dielectric. The layer 78 and the contact hole are sequentially patterned to form an opening 76 as a contact hole 92 in the first dielectric layer 78 and the contact hole stop layer 76, and a cleaning process may be further performed after the contact hole 92 is formed. The cleaning process may be a wet cleaning process or a dry cleaning process, and is performed in an in-situ or ex-situ manner to remove the remaining first dielectric layer 78 from the inner wall of the contact hole 92. Residual polymer by-products. A diffusion barrier layer 94 is then formed on the surface of the patterned hard mask 81 and the wall 1291215 within the contact hole 92. The diffusion barrier layer 94 is a composite layer of titanium nitride (TiN)/titanium (Ti) or a tantalum nitride (TaN)/tantalum (Ta) layer to avoid Problems such as the destruction of the characteristics of the element caused by the diffusion of the metal atoms, and at the same time increase the adhesion of the metal to the first dielectric layer 78. It is also worth noting that in order to ensure good electrical conductivity of the gate structure 66 and the source/drain region 64 or to maintain the cleanliness of the inner wall of the contact hole 92, at least one surface treatment process can be performed after forming the contact hole illusion. For example, a doping process is utilized to reduce the resistance of the gate structure 66 and the source/drain regions 64 to facilitate subsequent contact plug fabrication. As shown in Fig. 15, a first metal reed 98 such as tungsten (tungsten, w) is deposited to fill the contact hole 92 and overlying the diffusion barrier layer 94 to electrically connect the gate structure 66 with the source/ The immersion region 64, and then using the first hard mask 81 as a stop layer, performs a first-chemical mechanical polishing process on the first metal layer 98 and the diffusion barrier sound 94 for the first dielectric layer π: The process of each contact plug 100 is as shown in FIG. Then, as shown in FIG. 17, a second dielectric layer 1 〇 2, - 2 is sequentially formed over the plugs 100 of the first patterned hard mask 81; the contact layer is just - the second pattern is formed. The hard mask 106, and the second patterning: should include the contact plugs of the Wei_mouth age _ 66 and the source/drain regions 64, . The position of the ditch 110 is 12 1291215. Then, the second patterned hard mask 106 is used as an etch mask and the second anti-reflective layer 104 and the second dielectric are etched by using the first patterned hard mask 81 and the surface of the contact plug 1 as an etch stop layer. The electric layer 102 is formed to form a corresponding trench 110 in the second anti-reflective layer 104 and the second dielectric layer 1〇2, and then the second patterned hard mask 1〇6 and the second anti-reflective layer 104 are removed, such as Figure 18 shows. The material of the second dielectric layer 〇2 may include a TEOS 矽 oxygen layer, an undoped yttrium oxide layer or a borophosphonium oxynitride layer, a gas oxysulfur oxide layer, a phosphate sand oxide layer or a ruthenium oxide layer. The doped Xiyang oxygen layer may also be formed by at least one of various spin coating or chemical vapor deposition (CVD) techniques, such as a plasma enhanced chemical vapor deposition deposition process, and the second patterning The hard mask 106 is a photoresist material. As shown in Figure 19, a standard copper process or other low resistance electrical conductor deposition process is then performed. For example, prior to deposition in each of the trenches 110: titanium nitride (TiN) / titanium (Ti) or a nitride button (TaN) / button (Ta) diffusion resistance p early layer (not shown) and a crystal A seed layer (not shown) covers the second material 1() 2 and each of the contact plugs 100 on the side and bottom sides of each trench, and then the copper is formed to form the second metal layer 112 to fill the trench. 11〇, this is well known to those skilled in the art and the general knowledge, and is not mentioned here. Finally, the second dielectric layer 1 () 2# is used as the stop layer, and the second metal CMP and the diffusion barrier layer (not shown) are subjected to the second chemical mechanical polishing process. And each of the contact plugs 100 is electrically connected, as shown in FIG. In summary, the present invention also discloses a metal interconnect structure. As shown in FIG. 20, the metal interconnect structure of the present invention is disposed on a semiconductor substrate 62, and at least one first conductor is disposed in the semiconductor substrate 62, for example, including a gate 66 and a source/drain region 64. And the moS transistor element 72 of the sidewall 68, and the metal interconnect structure of the present invention comprises a first dielectric layer 78 on the semiconductor substrate 62 and covering the first conductor, / on the first dielectric layer 78 The first patterned hard mask 81 is disposed in the first patterned hard mask 81 and the first dielectric layer 78 and electrically connected to the contact plug 100 of the second conductive body, and is disposed at the contact plug a first dielectric layer 102 on the first patterned hard mask 81, and a second dielectric layer 102 disposed on the first patterned hard mask 81 and electrically connected to the plug The metal wire 114 of the plug 100. The materials constituting each of the film layers and the respective conductors are disclosed in the embodiments of Figs. 12 to 2, and are not described in detail herein. Since the present invention uses the patterned photoresist layer 84 as an etch mask to engrave the hard mask layer 8G, the pattern of the patterned photoresist layer 84 is transferred into the hard-transfer layer 80 to form a first patterned hard mask. The screen 8 then uses the first hard mask 81 as the (four) mask to (4) the first dielectric layer 78, into the desired contact hole 92. In this way, it is possible to sculpt the program on the patterned hard mask 81. The critical size of the tea is made so that the post-etching g invention (^EICD) is smaller than the post-development critical dimension (ADICD). At the same time, the patterned hard mask 81 of the 4X is used not only as a cover for the 1291215 of the contact hole 92, but also as a stop layer for the chemical mechanical polishing process of the contact plug 100, and more preferably It is used as a rice stop layer for the trench 110 in the subsequent metal interconnect process, eliminating the need for additional deposition of a stop layer in the prior art. In addition, since the process of 65 nm or less is required to use Nisha as the gate structure 66 and the metal telluride 70 on the surface of the source/demagnet region 64, in the present invention, the hard mask layer 8〇 The material is made of strontium carbide (Sic) or bismuth carbonitride (SiCN) which can be prepared at a low temperature, and the film formation reaction temperature must be less than 40 (rc) to avoid being disposed in the idler structure 66 and the source/drain region 64. The surface of the nickel (Nisi) produces a phase change. The above is only a preferred embodiment of the present invention, and the scope of the present invention should be within the scope of the present invention. Main component symbol description 10 Semiconductor substrate 14 Gate structure 20 MOS transistor component 12 Source/drain region 16 Sidewall 24 Shallow trench insulation region 1291215 32 Contact hole etch stop layer 34 First dielectric layer 36 Anti-reflection layer 40 Light Resistor layer 42 opening 44 opening 46 contact hole 47 diffusion barrier layer 48 metal 49 contact plug 50 insect stop layer 52 second dielectric layer 54 patterned photoresist layer 56 trench • 58 copper metal 60 metal wire 62 semiconductor base 64 source/drain region 66 gate structure 68 sidewall spacer 70 metal germanide 72 MOS transistor element 74 shallow trench isolation region 76 contact hole etch stop layer 78 first dielectric layer 80 hard mask layer 81 first patterning Hard mask 82 first anti-reflective layer 84 patterned photoresist layer 86 opening • 88 post-development critical dimension 90 post-etching critical dimension 92 contact hole 94 diffusion barrier layer 98 first metal layer 100 contact plug 102 second dielectric Layer 104 second anti-reflective layer 106 second patterned hard mask 108 opening 110 trench 112 second metal layer 114 metal wire 16