1287831 九、發明說明： 【發明所屬之技術領域】 本發明係一種應用於半導體晶圓之製程技術，特別係 指使用半導體晶圓之良好離子佈植冷卻系統技術。 【先前技術】 目前離子佈植在晶圓蠢晶過程中，已經是一種基本且 廣為半導體晶圓製造業應用的技術。半導體晶圓在低溫下 進行離子佈植將使製作而成之半導體元件具備許多優點。 例如：低漏電流、低寄生電容、低寄生電阻，使得半導體 元件在高溫下長期使用，亦具備高穩定性及低輸出訊號失 真度。 值得一提的是，在晶圓製作過程中，不當的加熱程序 將導致晶格缺陷或是晶格排列錯位，造成不當的電荷累積 埋藏在晶圓之中，通常在不同晶格結構物質之交界處附 近。以致P_N接合面產生不當的漏電流、寄生電容、寄生 電阻因此產生於半導體元件之中。若在高溫下長期使用半 導體元件則容易損壞，導致應有的電性功能喪失，尤其在 大型積體電路或是超大型積體電路等對不當的漏電流、寄 生電容、寄生電阻，要求更高的電路應用上，此一缺點則 更加明顯。 尤其在大型積體電路或是超大型積體電路等需要一連 串繁雜的製程步驟，晶圓成長的過程中需要大量的摻雜物 1287831 :寺緣層’在離子佈植過程中具有高能量的離 子持、，不W速撞擊晶圓基材，藉此 :铸，晶格中，此時由原子_== =溫::何使得半導體晶圓在㈣ ' >、准持晶圓應有的品質，就更顯重要。 囝。1目’其侧子佈植之習知技藝結構示意 1白知技藝包含-晶圓20 ’ —靜電夾具30，一液冷式散 熱器40。一晶圓2fl，曰 K她 日日® 20日日0 2〇係設置於靜電夾具30之上， 方切：=所使用之基材。一靜電夾具3〇，藉靜電感應 方式將B曰圓20固定於液冷式散熱器4〇之上，且在曰圓別 與散熱器40基底之間利用氣體流動方式，用以加強二晶圓 2〇上的熱量傳送至散熱器4〇，使晶圓2〇表面的溫度在離 子植入的過程中，不至於持續的升高，但是此—方法盈法 使得晶圓20溫度低於散熱器4Q的溫度無法達到更低溫離 子植入的目的，是以此-習知技藝之冷卻效果不佳，無法 使得晶圓20在足夠低的低溫下（例如：冰溫，代）進行離 子佈植。 依據貝伊（Bae)的研究指出【第十五屆國際離子佈值技術 會議參考文件一】，進行離子佈植之時，晶圓溫度降低5〇c， 將可有效減低非晶體及晶體間介面之氟元素濃度，而氟元 素濃度下降，乃是因為離子佈植期間之低晶圓溫度可以減 低晶圓之自身退火效應。然而近年來所有的晶圓製造大 廠，均持續尋求方法使得能在低於冰溫下進行離子佈植。 1287831 • 依據須黑(Sugur〇)的研究指出(美國專㈣6570169 . 號），其研究所使用之矽基板於進行離子佈植時，將其溫 度維持在-60°C甚至更低的低溫。然而須黑的報告中，並沒 有提到在進行離子佈植時如何使溫度維持在所需要的低 溫。依照目前半導體晶圓製造業在進行離子佈植時所使用 的晶圓冷卻方式，並無法達刻上述之冷卻效果。 美國專利第5338940號之中，武山（Takeyama)揭示一 φ 種進行離子佈植時之無機械接觸式冷卻方法，晶圓以電磁 力支撐。其中一熱輻射散熱功能的環狀溝槽設置於晶圓下 方，正對著晶圓之非離子佈植面。一溫度低至接近液態氮 溫度的冷卻片以無接觸點的方式設置於溝槽之中，藉熱輻 射的方式冷卻晶圓。環狀溝糟之内表面以及冷卻片之外表 面，更可加以電解氧化或者塗佈一層黑色吸熱漆，藉以增 強其吸熱之能力。此處之晶圓在無任何實際機械接觸支樓 情況下，再加上運用上述冷卻系統，則離子可以少劑量的 # 方式植入高速旋轉的晶圓之中，同時可以有效地改善晶圓 之品質。離子佈植時產生之熱能則藉由熱輻射方式，由晶 圓傳送至具備冷卻作用之低温面板，然而此時熱量傳送之 速率卻非常的低，並不能滿足大量離子佈植時對冷卻效果 之需求。 美國專利第4282924號之中，揭示一種舊式的離子佈 植冷卻系統。一晶圓以機械方式固定於一基底上，二者中 間存在一狹小間隙，少量氣體被注入此一間隙之中藉以將 1287831 ’ 熱量由晶圓傳送至基底，而此一基底以室溫之水或者冷凝 • 水冷卻。然而此一冷卻方式之限制為其最低溫只能到達 0〇C 〇 【發明内容】 有鑑於上述習知技藝之缺點，本發明乃揭示一種進行 離子佈植時，使晶圓與基底介面間（或者基底間介面）冷 卻之系統，其中一電熱冷卻器（Thermoelectric cooler) φ 在此被利用。此一冷卻器之冷卻原理乃是根據派利電熱效 應（Pelier effect)。當一電流通過兩個完全不同的金屬 或者半導體，而金屬或者半導體以派利導電端子（Pel ier junctions)相互連接時，此一電流則將熱量由一派利低溫 面板（Cool Pel ier surface)傳送至另一派利高溫面板（Hot Pel ier surface)，使得低溫面板（Cool Pel ier surface) 處於被冷卻狀態，同時高溫面板（Hot Pelier surface) 處於被加熱狀態。 ® 派利冷卻器（Pel ier cooler )設置於晶圓與基底之 間，冷卻器之低溫面板（Cool Pel ier surf ace)與晶圓之 靜電夾具（E-chuck)連接，晶圓與低溫面板之間利用氣體 流動方式，用以加強將晶圓上的熱量傳送至基底，使晶圓 表面的溫度在離子植入的過程中，不至於持續的升高，而 冷卻器之高溫面板（Hot Pelier surface)與基底連接， 此時冷卻器之高溫面板（Hot Pelier surface)等同於一 散熱裝置，並以冷水冷卻高溫面板（Hot Pel ier surface)。 1287831 一個最簡單的派利冷卻器（只有一個低溫面板以及一個高 溫面板），其最大的冷卻效果，可以使得低溫面板（Cool Pel ier surface)與高溫面板（Hot Pel ier surface)之 間有70°C的溫度差。幾個派利冷卻器相互串接，可以更有 效的達到冷卻效果。根據報導熱量移除速率可達12W/cm2， 而進行離子佈植期間，離子轟擊對晶圓產生之熱輻射量只 有約2W/cm2，利用派利電熱幫浦可以使得基底與晶圓接觸 的表面’其能夠保持低於散熱器的溫度，能夠進一步達成 更低溫離子植入製程的目的。 派利冷卻器（Pel ier cooler)以固體材質之材料製 作’並且可以適用於真空系統之中。在進行離子佈植期間， 夕層式派利電熱冷卻器（Multi-stage Pelier cooler)， 可以將晶圓冷卻，使晶圓溫度低於真空環境110°C。 相較於上述之習知技藝，派利電熱冷卻器（Pelier cooler)具備下列之特點以及相對之優點： 1·外觀尺寸、體積、重量等輕巧化迷你化。 2·機構不需拆卸，以致無相關之磨耗產生，穩定性佳， 無須維修。抗震，抗晃動性佳，且無噪音產生。 3·運用派利電熱冷卻效應（Pel ier effect )，可精準 控制溫度，使之高於或者低於周圍環境且無電子雜訊。 4·符合環保之要求，無有毒氣體產生以及化學冷卻劑 之需求。 ^87831 5·可與風扇式以及液冷式散熱裝置結合，增強原有的 破動式冷卻功能。 【實施方式】 、 明參考第2圖，其係本發明之指定代表圖。首先提供 ‘ 一液冷式散熱器40, 一派利電熱幫浦10，一靜電夾具3〇， 圓20 ; —液冷式散熱器4〇，散熱器4〇設置於派利電 _浦10 了方，用以吸收派利電熱幫浦10高溫面板16之 • 熱量。 、運用派利電熱幫浦10，派利電熱幫浦1〇設置於一 液冷式散熱H 40與-靜電夾具3〇之間，—派利電熱幫浦 1G包含··-高溫面板16’ —低溫面板η，·—高溫面板^， 高溫面板16設置於液冷式散熱器40與低溫面板η之間， 两溫面板16之材質為陶莞等高熱容值之材料，用以吸收經 由低溫面板Π所傳送之熱量；一低溫面板u，低溫面板 φ 11設置於高溫面板16與靜電夾具3G之間，低溫面板u 之材質為陶莞等高熱容值之材料，用以吸收離子佈植於晶 圓時所產生之熱量，其中複數對N型半導體13-p型半導體 14 (或者複數對的不同材f的金屬）設置於高溫面板^盘 低溫面板11之間’並使複數對N型半導體i3_p型半導體 14 (或者餘對的不的㈣）兩兩相互電性連接。 運用派利電熱幫浦1G之原理如下（請參考第7圖）： -直流電流” ί，，由况型半導體13一端之高溫面板料 電端子15 (” +，，正電極）流至ρ型半導體14 -端之低 10 1287831 溫面板11導電端子12 (” 一”負電極），電流” I ”之 • 流動路徑請參考第7圖中之箭號方向。依據派利電熱效 應，藉由電荷在低溫面板11吸收熱量，經由直流電流流 動，隨後電荷在高溫面板16釋放熱量，則可以將熱量快速 由低溫面板11傳送至高溫面板16。離子佈植期間，因離 子佈植於晶圓20所產生的熱量，則由晶圓20經由靜電夾 具30，傳送至低溫面板11，再由低溫面板11傳送至高溫 面板16。 另外運用一靜電夾具30，靜電夾具30係設置於派利 電熱幫浦10低溫面板11與晶圓20之間，用以藉靜電感應 方式將晶圓20固定於派利電熱幫浦10之上，且在晶圓20 與低溫面板11之間利用氣體流動方式，加強將晶圓20上 的熱量傳送至低溫面板11，使晶圓20表面的溫度在離子 植入的過程中不至於持續的升高。 提供一晶圓20，晶圓20置設於靜電夾具30之上，做 • 為離子佈植所使用之基材；綜上所述之方法，利用派利電 熱幫浦10可以達成快速傳送熱量，快速冷卻晶圓20，使 其能夠保持低於散熱器的溫度，能夠進一步達成更低溫離 子植入製程的目的。 請參考第3圖，首先提供一液冷式散熱器40，一導熱 片60，一派利電熱幫浦10，一靜電夾具30，一晶圓20 ; 一液冷式散熱器40，散熱器40設置於導熱片60下方，用 以吸收導熱片60之熱量；一導熱片60，導熱片60設置於 11 1287831 • 液冷式散熱器40與高溫面板11之間，用以使得熱量更快 • 速地由高温面板16傳導至散熱器40。 運用一派利電熱幫浦10，派利電熱幫浦10設置於一 導熱片60與一靜電夾具30之間，一派利電熱幫浦10包 含：一高溫面板16，一低溫面板11。 運用一靜電夾具30，靜電夾具30係設置於派利電熱 幫浦10低溫面板11與晶圓20之間，用以藉靜電感應方式 φ 將晶圓20固定於派利電熱幫浦10之上，且在晶圓20與低 溫面板11之間利用氣體流動方式，加強將晶圓20上的熱 量傳送至低溫面板11，使晶圓20表面的溫度在離子植入 的過程中不至於持續的升高；一晶圓20，晶圓20置設於 靜電夾具30之上，做為離子佈植所使用之基材；綜上所述 之方法，利用導熱片60可以達成更加快速傳送熱量，快速 冷卻晶圓20，使其能夠保持低於散熱器的溫度，能夠進一 步達成更低溫離子植入製程的目的。 ® 請參考第4圖，首先提供一液冷式散熱器40，一導熱 片60, 一派利電熱幫浦10, 一導熱片50, 一靜電夾具30， 一晶圓20 ; —液冷式散熱器40，散熱器40設置於導熱片 60下方，用以吸收導熱片60之熱量；一導熱片60，導熱 片60設置於液冷式散熱器40與高溫面板11之間，用以使 得熱量更快速地由高溫面板16傳導至散熱器40。 運用一派利電熱幫浦10,派利電熱幫浦10設置於一 導熱片60與一導熱片50之間，一派利電熱幫浦10包含： 12 1287831 一高溫面板16， 一低溫面板11。1287831 IX. Description of the Invention: [Technical Field] The present invention relates to a process technology for a semiconductor wafer, and more particularly to a good ion implantation cooling system technology using a semiconductor wafer. [Prior Art] At present, ion implantation is a basic and widely used technology for semiconductor wafer manufacturing in the wafer splicing process. Ion implantation of semiconductor wafers at low temperatures will provide many advantages to fabricated semiconductor components. For example, low leakage current, low parasitic capacitance, and low parasitic resistance make semiconductor components long-term use at high temperatures, and also have high stability and low output signal distortion. It is worth mentioning that in the wafer fabrication process, improper heating procedures will cause lattice defects or lattice alignment misalignment, resulting in improper charge accumulation buried in the wafer, usually at the junction of different lattice structure materials. Near the place. As a result, improper leakage current, parasitic capacitance, and parasitic resistance of the P_N junction surface are generated in the semiconductor element. If the semiconductor component is used for a long period of time at a high temperature, it is easily damaged, resulting in loss of electrical function, especially in large integrated circuits or ultra-large integrated circuits, such as improper leakage current, parasitic capacitance, and parasitic resistance. This shortcoming is more obvious in the application of the circuit. Especially in large integrated circuits or very large integrated circuits, which require a series of complicated process steps, a large amount of dopants 1287831 is needed in the wafer growth process: the temple edge layer has high energy ions during ion implantation. Holding, not W-speed impact on the wafer substrate, thereby: casting, in the lattice, at this time by the atom _== = temperature:: What makes the semiconductor wafer at (4) ' >, the wafer should have Quality is even more important. child. The structure of the prior art of the 1st's side is shown in the art. The white technology includes a wafer 20', an electrostatic chuck 30, and a liquid-cooled heat sink 40. A wafer 2fl, 曰 K her day ® 20 day 0 2 〇 system is placed on the electrostatic fixture 30, square cut: = the substrate used. An electrostatic chuck 3〇 is used to fix the B circle 20 on the liquid-cooled heat sink 4〇 by electrostatic induction, and uses a gas flow method between the circle and the base of the heat sink 40 to strengthen the two wafers 2 The heat on the crucible is transferred to the heat sink 4〇, so that the temperature of the surface of the wafer 2 is not continuously increased during the ion implantation process, but the method of the method makes the temperature of the wafer 20 lower than the heat sink 4Q. The temperature does not achieve the goal of cryogenic ion implantation, and this is a poor cooling effect of the prior art, and the wafer 20 cannot be ion implanted at a sufficiently low temperature (for example, ice temperature, generation). According to Bae's research, [the fifteenth International Ion Cloth Technology Conference Reference Document 1], when the ion implantation is performed, the wafer temperature is lowered by 5〇c, which will effectively reduce the amorphous and intercrystalline interfaces. The concentration of fluorine and the decrease in the concentration of fluorine are due to the low wafer temperature during ion implantation which can reduce the self-annealing effect of the wafer. However, in recent years, all wafer fabrication plants have continued to seek ways to enable ion implantation at temperatures below freezing. 1287831 • According to a study by Sugur〇 (US No. 4570169.), the substrate used in the study was maintained at a temperature of -60 ° C or lower for ion implantation. However, in the report to be black, there is no mention of how to maintain the temperature at the required low temperature during ion implantation. According to the current wafer cooling method used in the semiconductor wafer manufacturing industry for ion implantation, the above cooling effect cannot be achieved. In U.S. Patent No. 5,338,940, Takeyama discloses a mechanical contactless cooling method for ion implantation, and the wafer is supported by electromagnetic force. An annular groove with a heat radiating heat dissipation function is disposed under the wafer and faces the non-ionized implant surface of the wafer. A cooling fin having a temperature as low as near the temperature of the liquid nitrogen is placed in the trench in a contactless manner to cool the wafer by heat radiation. The inner surface of the annular groove and the surface outside the cooling fin can be electrolytically oxidized or coated with a black heat absorbing paint to enhance its heat absorbing ability. In the case of a wafer without any actual mechanical contact, and with the above cooling system, the ions can be implanted into the high-speed rotating wafer in a low dose mode, and the wafer can be effectively improved. quality. The heat generated during ion implantation is transferred from the wafer to the cryogenic panel with cooling by thermal radiation. However, the rate of heat transfer is very low, which does not satisfy the cooling effect when a large number of ions are implanted. demand. An old ion plating cooling system is disclosed in U.S. Patent No. 4,282,924. A wafer is mechanically fixed to a substrate with a narrow gap therebetween, and a small amount of gas is injected into the gap to transfer 1287831' heat from the wafer to the substrate, and the substrate is water at room temperature. Or condensation • Water cooling. However, the limitation of this cooling mode is that the lowest temperature can only reach 0 〇C 〇. SUMMARY OF THE INVENTION In view of the above-mentioned shortcomings of the prior art, the present invention discloses a method of performing ion implantation between a wafer and a substrate interface ( Or a system for cooling the inter-substrate interface, in which a thermoelectric cooler φ is utilized. The cooling principle of this cooler is based on the Pelier effect. When a current passes through two completely different metals or semiconductors, and the metal or semiconductor is connected to each other by Peer junctions, this current transfers heat from a Cool Pelier surface to Another Hot Pelier surface allows the Cool Pelier surface to be cooled while the Hot Pelier surface is heated. ® Pelier cooler is placed between the wafer and the substrate. The cooler Pel ier surf ACE is connected to the E-chuck of the wafer. The wafer and the cryopanel are connected. The use of gas flow to enhance the transfer of heat from the wafer to the substrate, so that the temperature of the surface of the wafer does not continue to rise during the ion implantation process, and the high temperature panel of the cooler (Hot Pelier surface) ) Connected to the substrate, where the cooler's Hot Pelier surface is equivalent to a heat sink and cools the Hot Pelier surface with cold water. 1287831 One of the simplest Perli coolers (only one low temperature panel and one high temperature panel), with maximum cooling effect, allows 70° between the Cool Pelier surface and the Hot Pelier surface The temperature difference of C. Several Paley coolers are connected in series to achieve a more efficient cooling effect. According to the reported heat transfer rate, the removal rate can reach 12W/cm2, and during ion implantation, the ion bombardment generates only about 2W/cm2 of heat radiation to the wafer, and the surface where the substrate can be brought into contact with the wafer by using the Paley electric pump can be used. 'It can keep the temperature lower than the heat sink, and can further achieve the purpose of a lower temperature ion implantation process. The Peilier cooler is made of a solid material and can be used in a vacuum system. During the ion implantation process, the multi-stage Pelier cooler can cool the wafer so that the wafer temperature is lower than the vacuum environment by 110 °C. Compared with the above-mentioned prior art, the Pelier cooler has the following features and relative advantages: 1. Lightweight miniaturization of appearance size, volume, weight, and the like. 2. The mechanism does not need to be disassembled, so that no relevant wear is generated, the stability is good, and no maintenance is required. Anti-vibration, good anti-shake, and no noise. 3. Using the Pelican effect, the temperature can be precisely controlled to be higher or lower than the surrounding environment and without electronic noise. 4. Compliance with environmental requirements, no toxic gas generation and chemical coolant requirements. ^87831 5·Can be combined with fan-type and liquid-cooled heat sinks to enhance the original broken cooling function. [Embodiment] FIG. 2 is a designated representative diagram of the present invention. First of all, 'one liquid cooling radiator 40, one Paley electric pump 10, one electrostatic fixture 3 〇, round 20; liquid cooling radiator 4 〇, radiator 4 〇 set in Paley _ 浦 10 It is used to absorb the heat of the Perry Electric Pump. , using the Pele electric pump 10, the Pele electric pump 1 〇 is set between a liquid cooling heat sink H 40 and - electrostatic fixture 3 ,, - Paley electric pump 1G contains · · - high temperature panel 16 ' — The low temperature panel η, · - high temperature panel ^, the high temperature panel 16 is disposed between the liquid cooling radiator 40 and the low temperature panel η, and the material of the two temperature panel 16 is a high heat capacity material such as Taowan for absorption through the low temperature panel The heat transferred by the crucible; a low temperature panel u, the low temperature panel φ 11 is disposed between the high temperature panel 16 and the electrostatic fixture 3G, and the material of the low temperature panel u is a high heat capacity material such as Taowan, for absorbing ion implantation in the crystal The heat generated in the circle, wherein a plurality of pairs of N-type semiconductor 13-p-type semiconductors 14 (or a plurality of pairs of different materials f of metal) are disposed between the high-temperature panel and the low-temperature panel 11' and the complex pair of N-type semiconductors i3_p The type semiconductors 14 (or the remaining pairs of (four)) are electrically connected to each other. The principle of using the Parallel Electric Pump 1G is as follows (please refer to Figure 7): - DC current, ί, from the high temperature panel material terminal 15 (" +, positive electrode" at the end of the type semiconductor 13 to the p type Semiconductor 14 - terminal low 10 1287831 Temperature panel 11 conductive terminal 12 ("one" negative electrode), current "I" • For the flow path, refer to the arrow direction in Figure 7. According to the Paragon electrothermal effect, heat can be quickly transferred from the low temperature panel 11 to the high temperature panel 16 by the electric charge being absorbed by the low temperature panel 11 and flowing through the direct current, and then the electric charge is released from the high temperature panel 16. During the ion implantation, the heat generated by the ions implanted on the wafer 20 is transferred from the wafer 20 to the cryopanel 11 via the electrostatic chuck 30, and then transferred to the high temperature panel 16 by the low temperature panel 11. In addition, an electrostatic chuck 30 is disposed, and the electrostatic chuck 30 is disposed between the Pelico electric pump 10 low temperature panel 11 and the wafer 20 for fixing the wafer 20 on the Paley electric pump 10 by electrostatic induction. The gas flow between the wafer 20 and the cryopanel 11 is used to enhance the transfer of heat on the wafer 20 to the cryopanel 11 so that the temperature of the surface of the wafer 20 does not continuously increase during ion implantation. Providing a wafer 20, the wafer 20 is disposed on the electrostatic chuck 30, and is used as a substrate for ion implantation; in summary, the Paley electric pump 10 can achieve rapid heat transfer. The wafer 20 is rapidly cooled so that it can remain below the temperature of the heat sink, further enabling a lower temperature ion implantation process. Please refer to FIG. 3, firstly providing a liquid-cooled heat sink 40, a heat-conducting sheet 60, a Paragon electric pump 10, an electrostatic chuck 30, a wafer 20; a liquid-cooled heat sink 40, a heat sink 40 setting Under the heat conducting sheet 60, the heat of the heat conducting sheet 60 is absorbed; a heat conducting sheet 60, the heat conducting sheet 60 is disposed at 11 1287831 • between the liquid cooled heat sink 40 and the high temperature panel 11 for making the heat faster and faster. Conducted by the high temperature panel 16 to the heat sink 40. The Pelico electric pump 10 is disposed between a heat conductive sheet 60 and an electrostatic chuck 30, and the Pelico electric pump 10 includes: a high temperature panel 16, a low temperature panel 11. An electrostatic chuck 30 is disposed between the Pelico electrothermal pump 10 low temperature panel 11 and the wafer 20 for fixing the wafer 20 to the Paley electric pump 10 by electrostatic induction. The gas flow between the wafer 20 and the cryopanel 11 is used to enhance the transfer of heat on the wafer 20 to the cryopanel 11 so that the temperature of the surface of the wafer 20 does not continuously increase during the ion implantation process; A wafer 20 is disposed on the electrostatic chuck 30 as a substrate for ion implantation. In summary, the heat transfer sheet 60 can be used to transfer heat more quickly and rapidly cool the wafer. 20, to enable it to maintain a temperature lower than the heat sink, can further achieve the purpose of a lower temperature ion implantation process. ® Please refer to Figure 4, first to provide a liquid-cooled heat sink 40, a thermal pad 60, a Paragon electric pump 10, a thermal pad 50, an electrostatic chuck 30, a wafer 20; 40, the heat sink 40 is disposed under the heat conductive sheet 60 for absorbing the heat of the heat conductive sheet 60; a heat conductive sheet 60, the heat conductive sheet 60 is disposed between the liquid cooled heat sink 40 and the high temperature panel 11 for making the heat faster The ground is conducted by the high temperature panel 16 to the heat sink 40. Using a Pele electric heating pump 10, the Pele electric pump 10 is disposed between a thermal pad 60 and a thermal pad 50, and a Pelico electric pump 10 includes: 12 1287831 A high temperature panel 16, a low temperature panel 11.
運用一導熱片50,導熱片50設置於低溫面板11與靜 電夹具30之間’導熱片50使得熱量更快速地由靜電夾具 30 f導至低溫面板; 一靜電夾具30，靜電夾具30設置 於V熱片50與晶圓2〇之間，用以藉靜電感應方式將晶圓 固定於派利電熱幫浦1〇之上；一晶圓20,晶圓20置設 電夾/、30之上，做為離子佈植所使用之基材；綜上所 述之方法利用導熱片60以及導熱片50可以達成更加快 速傳C…、里快速冷卻晶圓20，使其能夠保持低於散熱器 的溫度’能夠進—步達成更低溫離子植人製程的目的。 °月 > 考第5圖，首先提供一機械式散熱器埶 一派利電熱幫浦10, 一靜電夾具30, _晶圓2〇 了機 械式散熱器或者散熱片70設置於派利電熱幫二下方.， 用以吸收派利電熱幫浦10高溫面板16之熱量。 運用一派利電熱幫浦10，派利電熱幫浦10設置於-機械式散熱器或者散熱片7G與-靜電夾具3G之間，-功 利電熱帛廣ίο包含：一高溫面板16，一低溫面板u。 運用一靜電失具3G，靜電A具30係設置於派利電㈣ 浦：ί面板U與晶圓20之間’用以藉靜電感應方式將! 圓2〇固定於_電熱幫義之上；—，晶圓2〇置言 ==上’做為離子佈植所使用之基材;綜上戶 二3:=派利電熱幫浦 快速冷U2G，使其能夠保持低於散熱器的溫度， 13 1287831 進4達成更低溫離子植入製程的目的。 請參考第6圖，首先提供一 7〇，-風屬80，一派利電敎幫機械式散熱器或者散熱片 晶圓20;機械式散執者=10 ’ 一靜電夹具3〇, 一 參 量；，風扇80，風扇8〇言史置於^ 10尚溫面板16之熱 70之週圍，用以使得空氣強卜、〃式散熱器或者散熱片 者散熱月7〇之冷卻效果。+^以加強機械式散熱器或 運用1利電熱幫浦1〇 機械式散熱器或者散熱片7。與—靜二設置於一 利電熱幫浦10包含：H U之間’-派 冋概面板16, 一低溫面板u。 運扣—靜電夾具30,靜 幫⑽低溫面板U與晶圓2=3: B 20 U 20之間，用以藉靜電感應方式 :二:Γ，電熱幫浦10 一晶圓㈣ 2〇7、^_3()之上’做為離子佈植所使用之基材； 細1::方法’利用派利電熱幫浦10可以達成快速傳送 ::，隹、、丰〜部晶圓20，使其能夠保持低於散熱器的溫度， 此夠進=達成更低㈣子植人製程的目的。 並非用S 月之較佳貫施例已揭露如上，然爾等實施例 發明之精限，本發明，任何熟知此項技藝者，在不脫離本 本發明何，圍内，所作之各種更動以及潤飾，均落在 之申利範圍内。此外，本發明之保護範圍當視後附 甲’範圍所界定者為準。 14 1287831 【圖式簡單說明】 第1圖係習知技藝之結構示意圖 第2圖係本發明之第一實施方式結構示意圖 第3圖係本發明之第二實施方式結構示意圖 第4圖係本發明之第三實施方式結構示意圖 φ 第5圖係本發明之第四實施方式結構示意圖 第6圖係本發明之第五實施方式結構示意圖 第7圖係本發明基本物理原理示意圖 【主要元件符號說明】 10派利電熱幫浦 U低溫面板 • 12導電端子 13 N型半導體 U P型半導體 15導電端子 16高溫面板 20晶圓 30靜電夾具 15 1287831 40散熱器 50導熱片 60導熱片 7◦機械式散熱器或者散熱片 80風扇Using a heat conducting sheet 50, the heat conducting sheet 50 is disposed between the low temperature panel 11 and the electrostatic chuck 30. The heat conducting sheet 50 allows heat to be more quickly guided from the electrostatic chuck 30f to the low temperature panel; an electrostatic chuck 30, and the electrostatic chuck 30 is disposed at V Between the hot film 50 and the wafer 2, the wafer is fixed on the Pele electric heater 1 by electrostatic induction; a wafer 20, the wafer 20 is placed on the electric clamp / 30, The substrate used for ion implantation; in summary, the thermal conductive sheet 60 and the thermal conductive sheet 50 can be used to achieve a faster transfer of the wafer 20, so that the temperature can be kept lower than the temperature of the heat sink. The goal of a lower temperature ion implantation process can be achieved. °月> Test No. 5, first provide a mechanical radiator 埶 派 派 电 电 10, an electrostatic fixture 30, _ wafer 2 机械 mechanical radiator or heat sink 70 set in the Paraly Below., used to absorb the heat of the Perry Electric Pump 10 high temperature panel 16. Using a Pele electric heater 10, the Pele electric pump 10 is placed between the mechanical radiator or the heat sink 7G and the -static clamp 3G, - utilitarian electric heating ί wide οο: a high temperature panel 16, a low temperature panel u . Using an electrostatic dislocation 3G, the electrostatic A has 30 series set in the Para (four) Pu: ί between the panel U and the wafer 20 'used by electrostatic induction! The round 2〇 is fixed on the _ electric heating aid; Wafer 2 〇 = = = 上 ' as the substrate used for ion implantation; above the household 2 3 = = Pele electric pump fast cold U2G, so that it can keep the temperature below the radiator, 13 1287831 Into the 4 to achieve the purpose of a lower temperature ion implantation process. Please refer to Figure 6, first to provide a 7 〇, - wind is 80, a Phillips electric mechanical radiator or heat sink wafer 20; mechanical scatterer = 10 'one electrostatic fixture 3 〇, a parameter; The fan 80 and the fan 8 are placed around the heat 70 of the 10 temperature panel 16 to cool the air, the heat sink or the heat sink. +^ to strengthen the mechanical radiator or use 1 electric heating pump 1 〇 mechanical radiator or heat sink 7. And the static two is set in one. The electric heating pump 10 includes: H U between the '----------------------------运扣—Electrostatic clamp 30, static (10) low temperature panel U and wafer 2=3: B 20 U 20, used for electrostatic induction: two: Γ, electric pump 10 a wafer (four) 2〇7, ^ Above _3() is used as the substrate used for ion implantation; Fine 1:: Method 'Utilize the Paley Electric Pump 10 to achieve fast transfer::, 隹, 丰~ Keeping below the temperature of the heat sink, this is enough to achieve the goal of lower (four) sub-planting process. It is not the preferred embodiment of the S month that has been disclosed above, and the invention has been limited to the details of the invention, and any of the various modifications and retouchings of the present invention, without departing from the invention, may be made. Both fall within the scope of Shenli. Further, the scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic structural view of a first embodiment of the present invention. FIG. 3 is a schematic structural view of a second embodiment of the present invention. FIG. 4 is a schematic view of the present invention. 3 is a schematic structural view of a fourth embodiment of the present invention. FIG. 6 is a schematic structural view of a fifth embodiment of the present invention. FIG. 7 is a schematic view showing the basic physical principle of the present invention. 10 Paley Electric Pump U Low Temperature Panel • 12 Conductor Terminal 13 N Type Semiconductor UP Type Semiconductor 15 Conductor Terminal 16 High Temperature Panel 20 Wafer 30 Static Fixture 15 1287831 40 Heat Sink 50 Thermal Piece 60 Thermal Pad 7 ◦ Mechanical Radiator or Heat sink 80 fan