1287262 九、發明說明： 【發明所屬之技術領域】 本發明提供一種製造摻雜氮之介電層的方法，尤指一 種製造均勻摻雜氮之閘極氧化層的方法。 【先前技術】 為了增加單一晶圓之積集度，半導體元件朝小而密集 之趨勢發展。而為了轉元件高效能要求，互補式金氧半 導體（complementaiy metal 〇xide semic〇nduct〇r，cm〇s ) 之:極氧化層厚度亦需隨之下降，以於閘極與通道 n I疋之％谷里。此係因在閘極氧化層電容量大時， 元件：‘I内的電~強度較低，從而可降低漏電流，提升 中，甚如’於130奈米（nm)以下之半導體製程 符八 ’、y、W造出厚度低於20埃（A)之Η朽气化厗以 付合元件效能之需求。…之閘極乳化層以 厚度之氧化發，=氣化層係由氧切所構成。然而，低 潰電壓、低漏電流=到高介電常數、熱穩定性高、高崩 即可能因f子和電、心永。例如厚度低於5G埃之氧化石夕， ‘ ’穿越氧化層之能量屏障而造成漏電流 1287262 然而’利用單一步驟DPN進行之氮化，無法在閉極氧 化層表面形成厚度且含氮量均勻之含氮層。特別是，曰 一、日白 圓的中央一帶之含氮量往往呈現不均勻的狀態，且晶圓整 體之含氮量均勻度亦不理想。以90奈米製程之晶圓為例， 一藉由DPN程序所形成之含氮氧化層之氮分佈均勻度約在 8.1%左右。而在氧化層含氮量不均的情況下，其電容、起 始電壓（threshold voltage)等電性亦會受到影響，從而造 成晶圓良率的下降。因此，需要一種提升氧化層中氮分佈 均勻度之方法，以提升晶圓之良率。 【發明内容】 本發明之主要目的在於提供一種製造摻雜氮之介電層 的方法，以解決上述習知掺雜氮之介電層中氮分佈不均勻 所產生之問題。 根據本發明之申請專利範圍，係揭露一種製造摻雜氮 之介電層的方法。根據該方法，係先於半導體基材上形成 一介電層，並對該介電層進行兩階段之氮化製程。其中該 氣化製私，係為分麵式電漿氮化製程，且其係利用一具有 雙線圈（dual coil)結構之裝置進行，其中於上述兩階段之氮 化製程中該兩線圈之電流比不相同。於氮化製程完成後， 1287262 。接著對該介電層上進行 對該介電層進行一低溫退火製程 一高溫退火製程。 本發明所提供之方法藉由兩階段之氮化程序 之退火程序有效地提高氧化層中氮離子分佈之均^階段 而確保元件之品質與晶圓之良率。 X，從 【實施方式】 目則貫施之摻雜氮氧化層製程皆以單一氮化掣程 退火製程進行，是以對氮含量均勻度之改善有限。上 發明提供—種兩階段氮化程序加上兩階'段退火程序之摻^ 氮氧化層製造方法，以更有效地解決習知方法之缺點。” 本發明之方法主要係利用DPN機台進行。DPN係—種 利用具有雙線圈結構之裝置進行電漿氮化之技術。該雙線 圈結構係由-内線圈與外線圈所構成，其中流經該内外線 圈之電流可調整，從而調整分配電容參數。藉由調整裝置 所產生之分配電容參數，可控制摻雜氮之濃度。然而，此 種雙線圈結構除存在於DPN機台外，其他進行電漿製程之 機台、蝕刻機台、或用於電漿增益化學氣相沈積（plasma enhanced chemical vapor deposition，PECVD)之機台皆包含 1287262 類似之結構。亦即，可依實際之需要，於上述各種機台中 進行本發明之方法。 此外’在進行氮化製程時；如提供不同之分配電容參 數，降對均勻度造成不同之影響。請參見第i圖，其顯示 利請N機台進行氮化程料，將分配電容參數調為5〜 ’〇 τ氧化石夕層各處之含氮量。根據第1圖，將分配電 容低而進行氮化製程時，可使晶圓中央附近有偏高 3氮里相反的將高分配電容參數調高而進行氮化製程1287262 IX. Description of the Invention: [Technical Field] The present invention provides a method of fabricating a nitrogen-doped dielectric layer, and more particularly to a method of fabricating a gate oxide layer uniformly doped with nitrogen. [Prior Art] In order to increase the degree of integration of a single wafer, semiconductor elements have been trending toward small and dense. In order to meet the high-performance requirements of the component, the complementary MOS (complementaiy metal 〇xide semic〇nduct〇r, cm〇s): the thickness of the epitaxial layer also needs to decrease, so that the gate and the channel n I %谷里. This is due to the fact that when the gate oxide layer has a large capacitance, the component: 'I' has a low electric-intensity, which can reduce the leakage current, and is as high as a semiconductor process symbol below '130 nm (nm). ', y, W create a 气 气 气 厚度 厚度 厚度 厚度 厚度 厚度 厚度 厚度 。 。 。 。 。 。 。 。 。 。 。 。 。 The gate emulsified layer is oxidized by thickness, and the gasified layer is composed of oxygen cut. However, low breakdown voltage, low leakage current = high dielectric constant, high thermal stability, high collapse may be due to f sub-electricity and power. For example, if the thickness is less than 5G angstrom, the energy barrier that passes through the oxide layer causes leakage current of 1287262. However, nitriding by a single step DPN cannot form a thickness on the surface of the closed oxide layer and the nitrogen content is uniform. Nitrogen containing layer. In particular, the nitrogen content in the central zone of the daylight circle tends to be uneven, and the uniformity of the nitrogen content of the wafer is not ideal. Taking a wafer of 90 nm process as an example, the nitrogen distribution uniformity of the nitrogen-containing oxide layer formed by the DPN process is about 8.1%. In the case where the nitrogen content of the oxide layer is not uniform, the capacitance, the threshold voltage, and the like are also affected, resulting in a decrease in wafer yield. Therefore, there is a need for a method of increasing the uniformity of nitrogen distribution in an oxide layer to increase wafer yield. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a method of fabricating a nitrogen-doped dielectric layer to solve the problem of uneven distribution of nitrogen in the above-described nitrogen-doped dielectric layer. In accordance with the scope of the present invention, a method of fabricating a nitrogen-doped dielectric layer is disclosed. According to the method, a dielectric layer is formed on the semiconductor substrate, and the dielectric layer is subjected to a two-stage nitridation process. Wherein the gasification process is a faceted plasma nitridation process, and the process is performed by a device having a dual coil structure, wherein the two coils are in the two-stage nitridation process The current ratio is not the same. After the nitriding process is completed, 1287262. Then, the dielectric layer is subjected to a low temperature annealing process and a high temperature annealing process. The method provided by the present invention effectively improves the quality of the component and the yield of the wafer by an annealing process of a two-stage nitridation process to effectively increase the uniformity of the distribution of nitrogen ions in the oxide layer. X. From [Embodiment] The process of doping the oxynitride layer is carried out by a single nitriding process, which is limited in the improvement of the uniformity of nitrogen content. The above invention provides a two-stage nitridation process plus a two-stage 'segment annealing process for the oxynitride layer fabrication process to more effectively address the shortcomings of the conventional process. The method of the present invention is mainly carried out by using a DPN machine. The DPN system is a technique for plasma nitriding using a device having a double coil structure. The double coil structure is composed of an inner coil and an outer coil, wherein The current flowing through the inner and outer coils can be adjusted to adjust the distribution capacitance parameter. The concentration of the doped nitrogen can be controlled by adjusting the distribution capacitance parameter generated by the device. However, the double coil structure is present in addition to the DPN machine. Other machines for plasma processing, etching machines, or plasma enhanced chemical vapor deposition (PECVD) machines all contain similar structures of 1,287,262. That is, they can be implemented according to the actual situation. It is necessary to carry out the method of the present invention in the above various machines. In addition, when performing the nitriding process, if different distribution capacitance parameters are provided, the drop has a different influence on the uniformity. Please refer to the figure i, which shows that the N is required. The machine performs the nitriding process, and adjusts the distribution capacitance parameter to the nitrogen content of the 5~'〇τ oxidized stone layer. According to Fig. 1, the distribution capacitance is low and nitrided. When, near the wafer center can have a high nitrogen 3 in the opposite assign a high capacitance parameter increase nitridation process is performed
時，則可使晶圓周圚古^ > A A 71圏有較兩之含氮量。是以，在經過低分 配電容參數與高分^容參數兩·之氮錄域，可使 晶：中綱邊之含氮量較為均句。例如’先提供。〜ι〇% 之二巧配電谷參數以進行一氮化製程，再提供Η〜观 之乂心配f谷參數以進行另—氮化製程 均勻之含氮量分佈。 于巧孕乂為 現請參見第2圖，复在拼姑 例之流程圖。根_ 2 _ ’，、样明n較佳具體實旋 弟2圖，本發明首先利用習知熱成長 (thermalgr〇Wth)方式在用於90奈米製程之半導體基材 上形成-氧化石夕層（步驟2〇2)。接著將顧之分 數調整為G〜_對該氧切層進域摻雜，從而完^ 1287262 ::的氮化製程(步驟2〇4)。在完成第-次氮化後，半導 體基材之中央將有較高之氮含量。接著，將咖之分配= 容參數調整為15〜5G%以對氧切層進行氮摻雜，從而二 成第二次的氮化製程（步驟206)。該第二氮化製程^ 導體基材周圍有較高之氮含量，從而彌補了第-次氮化製 程中基材周圍氮含量較中央少的問題。亦即，在經過兩階 段之氮化製程後，將可於氧化石夕表面達到較佳之氮含量均 勻度。事實上根據本發明之較佳具體實施例，將可於氧化 石夕表面達到4.3%之氮含量均衫，此較習知方法所達到的 8.1%有顯著之改善。此外，必須強調的是，上述之兩階段 氮化製程順序可以對調。亦即，亦可先將分配電容參數調 整為15〜50%而進行第—次氮化後，再將分配電容參數數 調整為0〜10%以進行第二次氮化。 此外’由於退火程序可進一步增進氧化石夕層中氮分钸之均勻 度以及其表面形狀之均勻度，因此，本發明於兩階段之氮化 程序後’更進-步進行兩階段之退火製程，以改善氧化石夕 層含氮畺之均勻度以及晶圓表面圖形之均勻度。請繼續參 見第2圖，首先，對該氧化矽進行一攝氏500度至攝氏700 度之低潰退火製程（步驟2〇8)。接著，再對該退火後之氧 化矽層進一步進行一攝氏850度至攝氏11〇〇度之高溫退火 11 1287262 製程（步驟2!G)。在完成兩階段之退火程序後，該氧化石夕 之氮含量均勻度已可達到3.8%。惟上述兩退火製程之順序 可對調，树，可先進行該高溫线火製程，再低 溫之退火製程。 請參見第3圖。第3圖顯示本發明之另—具體實施例 之&程圖。根據第3圖，本發明首先利用習知長 成—氧化♦層(步驟3。2)。接著將— 雜:從而^ MU，""對該氧切層進行氮換 雜從而元成弟一次的氮化製程（步驟3〇4)。在 氧分配電容參數調整為15; 氧化矽層進㈣摻雜，從而Μ :。6)。同樣地，上述之兩階段氮化製程順:::= =可先將分配電容參數數調整為15〜5〇%以進行氮化 ，，再將分配電容參數難為g〜1g% ::本Γ氧化，進行一退火製程(二：，。 二Τ1Γ，段之氮化製輯進行單-程序之 U，如此亦可獲得優於習知技藝所能獲得之均勾度。 相較於習知技藝，本發明所提供之方法可有效提高閘 層“含氦量之均勻度。耐含氮量均勻度提高 12 1287262 後，閘極氧化層之電容和起始電壓等電性接能得到相應之 提升。此外，由於本發明可利用既有DPN機台實施，因此 ' 極為經濟且可符合大量製造之需求。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 - 严 【圖式簡單說明】 第1圖係為一折線圖，其描述分配電容參數在5%〜50% 時，所進行之氮化程序中，氧化矽層各處之含氮量； .第2圖係為一流程圖，其描述一根據本發明之較佳具體實 施例；和 第3圖係為一流程圖，其描述另一根據本發明之具體實施 i 例0 13 1287262 【主要元件符號說明】 202於半導體基材上形成一氧化矽層 204將分配電容參數調整為〇〜1〇%以進行第一氮化製程 206將分配電容參數調整為15〜5〇%以進行第二氮化製浐 208對該氧化矽層進行一攝氏5〇〇度至攝氏7〇〇度之退火製程 210對該氧化石夕層進行一攝氏85〇度至攝氏11〇〇度之退火製程 302於半導體基材上形成一氧化石夕層 304將分配電容參數調整為〇〜ι〇%以進行第一氨化製程 306將分配電容參數調整為b〜兄％以進行第二氮化製程 3〇8對該氧化砍層進行—退火製程At that time, the wafers can be made to have a higher nitrogen content than the A A 71. Therefore, in the nitrogen recording field of the low-dispensing capacitance parameter and the high-division-capacitance parameter, the nitrogen content of the crystal: the middle side can be more uniform. For example, 'provided first. 〜 〇 〇 之 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电 配电As a result of seeing the second picture, please refer to the flow chart of the example. The root _ 2 _ ', the sample is better than the actual 2, the present invention first uses the conventional thermal growth (thermal gr 〇 Wth) method on the semiconductor substrate for the 90 nm process - oxidized stone Layer (step 2〇2). Then, the fraction is adjusted to G~_ to dope the oxygen cut layer, thereby completing the nitridation process of 1287262:: (Step 2〇4). After the completion of the first nitridation, the center of the semiconductor substrate will have a higher nitrogen content. Next, the distribution of the coffee = volume parameter is adjusted to 15 to 5 G% to nitrogen doping the oxygen cut layer to form a second nitridation process (step 206). The second nitriding process has a higher nitrogen content around the conductor substrate, thereby compensating for the problem that the nitrogen content around the substrate is less than the central portion in the first nitriding process. That is, after a two-stage nitriding process, a uniform nitrogen content uniformity can be achieved on the surface of the oxidized stone. In fact, in accordance with a preferred embodiment of the present invention, a nitrogen content of 4.3% can be achieved on the surface of the oxidized stone, which is a significant improvement over the 8.1% achieved by conventional methods. In addition, it must be emphasized that the two-stage nitriding process sequence described above can be reversed. That is, the first time nitriding may be performed by adjusting the distribution capacitance parameter to 15 to 50% and then performing the first nitriding, and then adjusting the number of distributed capacitance parameters to 0 to 10%. In addition, since the annealing process can further improve the uniformity of nitrogen enthalpy in the oxidized stone layer and the uniformity of the surface shape thereof, the present invention performs a two-stage annealing process after the two-stage nitriding process. To improve the uniformity of nitrogen oxides in the oxidized stone layer and the uniformity of the surface pattern of the wafer. Please continue to refer to Figure 2. First, the yttrium oxide is subjected to a low-annealing process of 500 degrees Celsius to 700 degrees Celsius (step 2〇8). Then, the annealed ruthenium oxide layer is further subjected to a high temperature annealing process of 850 ° C to 11 ° C (11 2287262) (step 2! G). After completing the two-stage annealing process, the nitrogen oxide content uniformity of the oxidized stone has reached 3.8%. However, the order of the two annealing processes can be reversed, and the tree can be first subjected to the high temperature wire fire process and then the low temperature annealing process. See Figure 3. Fig. 3 is a view showing another embodiment of the present invention. According to Fig. 3, the present invention first utilizes a conventionally grown-oxidized layer (step 3.2). Then, the Mn, "" nitrogen is exchanged for the oxygen-cut layer to form a nitridation process (step 3〇4). The oxygen distribution capacitance parameter is adjusted to 15; the yttrium oxide layer is (4) doped, thereby Μ:. 6). Similarly, the above two-stage nitridation process is as follows:::= = The number of distributed capacitance parameters can be adjusted to 15~5〇% for nitriding, and then the distribution capacitance parameter is difficult to be g~1g%: Oxidation, an annealing process (two:, two Τ1Γ, the nitriding process of the section is carried out by the single-procedure U, so that it can obtain a better than the conventional skill can obtain. The method provided by the invention can effectively improve the uniformity of the strontium content of the gate layer. After the uniformity of nitrogen content tolerance is increased by 12 1287262, the electrical conductivity of the gate oxide layer and the initial voltage are improved accordingly. In addition, since the present invention can be implemented by an existing DPN machine, it is extremely economical and can meet the requirements of mass production. The above is only a preferred embodiment of the present invention, and is made according to the scope of the patent application of the present invention. Equivalent changes and modifications shall fall within the scope of the present invention. - [Simplified description of the drawings] Figure 1 is a line diagram depicting the nitriding procedure performed when the capacitance parameter is 5% to 50%. In the middle, the nitrogen content of the yttrium oxide layer; A flow chart describing a preferred embodiment in accordance with the present invention; and FIG. 3 is a flow chart depicting another embodiment in accordance with the present invention. Example 0 13 1287262 [Explanation of main component symbols] 202 Forming a hafnium oxide layer 204 on the semiconductor substrate adjusts the distribution capacitance parameter to 〇~1〇% for performing the first nitridation process 206 to adjust the distribution capacitance parameter to 15~5〇% for performing the second nitridation 浐208 pair The ruthenium oxide layer is subjected to an annealing process 210 of 5 degrees Celsius to 7 degrees Celsius to form an annealing process 302 of 85 degrees Celsius to 11 degrees Celsius on the oxidized iridium layer to form a semiconductor substrate. The oxidized stone layer 304 adjusts the distribution capacitance parameter to 〇~ι〇% for the first ammoniation process 306 to adjust the distribution capacitance parameter to b~ brother% for the second nitridation process 3〇8 to perform the oxidized chopping layer - annealing process