TWI286692B - Apparatus, method and system for controlling at least one PC card - Google Patents

Abstract

A method according to one embodiment may include decoupling a CAUDIO/SPKR#BVD2 signal line from a PC Card controller integrated circuit. The method of this embodiment may also include controlling, by the PC Card controller integrated circuit, at least one PC Card independently of the CALJDIO/SPKR#BVD2 signal line. Of course, many alternatives, variation, and modifications are possible without departing from this embodiment.

Description

1286692 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種具有減少之引腳數的積體電路。 【先前技術】 習知PC卡控制器具有一個稱為cAum〇/SPKR#/BVD2 的引腳，該引腳在一些模式中被用作為一個來自PC卡的音 頻輸入’在另一些模式中則被用作為一個電池電壓檢測輸 入。習知控制器也具有一個引腳，一般稱為SPKROUT#或 SPRK—OUT# ’該引腳輸出與CAUDI0/SPKR#/BVD2相關的 音頻資料直接至一個揚聲器介面晶片、一個C0DEC，或者 一些其他使用該音頻資訊的邏輯。 其他習知控制器提供雙插槽PC卡控制器。在這些控制 斋中’母個插槽包括一個CAUDI0/SPKR#/BVD2引腳，在 PC卡控制器中的典型邏輯通常將來自該兩個輸入的音頻資 料結合為一個音頻輸出，稱為Spkrout#。 在一些PC卡的配置中，該CAUDI〇/spKR#/BVD2引腳 提供對一個電池狀態的指示。習知pc卡控制器包括傳統 Intel 82365 可交換卡結構(Exchangeable Card Architecture，1286692 IX. Description of the Invention: [Technical Field of the Invention] The present invention relates to an integrated circuit having a reduced number of pins. [Prior Art] The conventional PC card controller has a pin called cAum〇/SPKR#/BVD2, which is used as an audio input from a PC card in some modes' in other modes. Used as a battery voltage detection input. The conventional controller also has a pin, commonly referred to as SPKROUT# or SPRK_OUT# 'This pin outputs the audio data associated with CAUDI0/SPKR#/BVD2 directly to a speaker interface chip, a C0DEC, or some other use. The logic of the audio information. Other conventional controllers provide a dual slot PC card controller. In these control, the 'female slot includes a CAUDI0/SPKR#/BVD2 pin. The typical logic in the PC card controller usually combines the audio data from the two inputs into one audio output, called Spkrout# . In some PC card configurations, the CAUDI〇/spKR#/BVD2 pin provides an indication of the status of a battery. The conventional PC card controller includes the traditional Intel 82365 exchangeable card architecture (Exchangeable Card Architecture,

ExCA)程式暫存器，這些暫存器向軟體報告電池狀態。卡 標準定義了兩個電池電壓檢測引腳·· CAUDI〇/spKR#/BVD2 和 CSTSCHG/STSCHG#/BVD1。 這些習知控制器不提供減少引腳數，因此會增加封裝成 本及/或封裝尺寸。 02 28CIP (0188) ROC SPEC REPLACEMENT 200702^6 (2) .1286692 • 【發明内容】 本發明之至少一實施例提供一種能夠控制至少一個pc 卡的操作的積體電路。該實施例的積體電路進一步能獨立於 由PC卡產生的CAUDI0/SPKR#/BVD2信號線，而控制該 PC卡。 【實施方式】 圖1闡示一個本發明的控制至少一 PC卡之系統100之 實施例。該控制至少一 PC卡之系統1〇〇通常包括一主處理 态112、一匯流排122、一使用者介面系統、一晶片組 114、系統記憶體12卜PC卡控制器電路11〇、音頻子系統 電路106和電源開關電路1〇2。本文中任何實施例中使用的 “電路”包括，例如，單一的或任何組合的硬連線電路、可程 式化電路、狀態機電路及/或用來儲存被可程式化電路執行的 指令的韌體。同樣地，在文中的任何實施例中，該pc卡控 制器電路110及/或該電源開關電路1〇2可被具體化為一個或 多個積體電路，及/或構成它們的一部分。本文中所謂的‘‘積 拳 體電路”是指一個半導體裝置及/或微電子裝置，例如，一個 半導體積體電路晶片。具體化為一個積體電路而言，電路11〇 包括多個輸入/輸出引腳’該引腳操作耦接電路11〇至系統 100的一個或多個元件及/或外部元件。 該控制至少一 PC卡之系統1〇〇之實施例也包括一個儲 存裝置118。儲存裝置118包括，例如，一個磁性、光學性 及/或半導體媒體，例如，一個硬碟裝置。主處理器n2包括 本領域已公知的任何種類的處理器，例如一個Intd(g) 02 28CIP (0188) ROC SPEC REPLACEMENT 200702¾ (2) 1286692ExCA) program registers that report battery status to the software. The card standard defines two battery voltage detection pins, CAUDI〇/spKR#/BVD2 and CSTSCHG/STSCHG#/BVD1. These conventional controllers do not provide a reduction in pin count and therefore increase package cost and/or package size. 02 28CIP (0188) ROC SPEC REPLACEMENT 200702^6 (2) .1286692 • SUMMARY OF THE INVENTION At least one embodiment of the present invention provides an integrated circuit capable of controlling the operation of at least one pc card. The integrated circuit of this embodiment is further capable of controlling the PC card independently of the CAUDI0/SPKR#/BVD2 signal line generated by the PC card. [Embodiment] Figure 1 illustrates an embodiment of a system 100 of the present invention for controlling at least one PC card. The system for controlling at least one PC card generally includes a main processing state 112, a bus bar 122, a user interface system, a chipset 114, a system memory 12, a PC card controller circuit 11, and an audio sub- System circuit 106 and power switch circuit 1〇2. "Circuitry" as used in any embodiment herein includes, for example, a single or any combination of hardwired circuitry, programmable circuitry, state machine circuitry, and/or toughness for storing instructions executed by the programmable circuitry. body. Similarly, in any of the embodiments herein, the PC card controller circuit 110 and/or the power switch circuit 102 can be embodied as one or more integrated circuits and/or form part of them. The term ''integral box circuit'" as used herein refers to a semiconductor device and/or a microelectronic device, for example, a semiconductor integrated circuit chip. In the case of an integrated circuit, the circuit 11 includes a plurality of inputs/ The output pin 'this pin operates the coupling circuit 11' to one or more components and/or external components of the system 100. The embodiment of the system for controlling at least one PC card also includes a storage device 118. Apparatus 118 includes, for example, a magnetic, optical, and/or semiconductor medium, such as a hard disk device. Main processor n2 includes any type of processor known in the art, such as an Intd(g) 02 28CIP (0188). ROC SPEC REPLACEMENT 2007023⁄4 (2) 1286692

Pentium® IV處理器。匯流排122包括各種類型之匯流排可 傳輸資料和指令者。例如，匯流排122遵守2002年7月22 曰由美國俄勒岡州的波特蘭的週邊元件互連專業組公佈的 週邊元件互連（Peripheral Component Interconnect， PCI)ExpressTM基礎規範修訂版本1〇(下文中稱為一 “pci Express™匯流排”）。該匯流排122選擇地或額外地遵守一 個串列週邊介面(Serial Peripheral Interface，SPI)規範(下文中 稱為一 “SPI匯流排”)或一個與PCI區域匯流排規範版本2.2 相容的32位元並行匯流排(parauei bus)。處理器112、系統 記憶體121、晶片組114、匯流排122、PC卡控制器電路11〇、 音頻子糸統電路106和電源開關電路1〇2可被包含在一個單 一的電路板上，例如，主機板132，且這些元件可以共同或 單獨地構成一個主系統。 使用者介面116包括供使用者輸入指令及/或資料並且 監控系統之諸如键盤、定點裝置和視頻顯示器等的各種裝 置。晶片組114包括主橋/集線器系統(未顯示），該晶片組將 處理器112、系統記憶體12卜使用者介面系統116、儲存裝 置118、PC卡控制器電路no、音頻子系統電路撕和電源 開關電路102相互轉接並輕接至匯流排122。雖然其他的積 體電路晶片也可以或選擇性地被選用，但晶片組H4可包括 積體電路晶片，例如可選自商業上可得之積體電路晶片組者 (例如，圖形記憶體和I/O控制器集線器晶片組）。 系統記憶體121包括一個或多個下述類型的記憶體：半 導體朝體s己憶體、可程式化記憶體、非揮發性記憶體、唯讀 奋己體、電子式可程§己憶體（electrically programmable 02 28CIP (0188) ROC SPEC REPLACEMENT 200702§6 (2) 1286692Pentium® IV processor. Busbar 122 includes various types of busbars for transmitting data and instructions. For example, busbar 122 complies with the Peripheral Component Interconnect (PCI) ExpressTM Base Specification Revision 1 published by the Peripheral Component Interconnect Professional Group in Portland, Oregon, USA, July 22, 2002 (below) Called a "pci ExpressTM bus"). The bus bar 122 optionally or additionally adheres to a Serial Peripheral Interface (SPI) specification (hereinafter referred to as a "SPI bus") or a 32 bit compatible with the PCI area bus specification version 2.2. Meta parallel bus (parauei bus). The processor 112, the system memory 121, the chip set 114, the bus bar 122, the PC card controller circuit 11A, the audio sub-circuit circuit 106, and the power switch circuit 1〇2 may be included on a single circuit board, for example The motherboard 132, and these components may constitute a main system together or separately. The user interface 116 includes various means for the user to input commands and/or materials and to monitor the system such as a keyboard, pointing device, and video display. Wafer set 114 includes a host bridge/hub system (not shown) that tears processor 112, system memory 12, user interface system 116, storage device 118, PC card controller circuit no, audio subsystem circuitry, and The power switch circuits 102 are mutually coupled and lightly connected to the bus bar 122. While other integrated circuit chips may alternatively or alternatively be selected, the chip set H4 may comprise integrated circuit chips, such as may be selected from commercially available integrated circuit chipsets (eg, graphics memory and I). /O controller hub chipset). The system memory 121 includes one or more of the following types of memory: a semiconductor body suffix, a programmable memory, a non-volatile memory, a read-only body, an electronic readable form (electrically programmable 02 28CIP (0188) ROC SPEC REPLACEMENT 200702§6 (2) 1286692

memory)、隨機存取記憶體、快閃記憶體(其可包括 NAND或NOR型記憶體結構)、磁碟記憶體及/或光 體。記憶體121可額外地或其他地包括其他及/或最近發展^ 的類型之電腦可讀記_。機器可讀_程式指令可 記憶體121中’並可包括’例如，軟體ν這種軟體可= 理器m及/或pc卡控制器電路110存取和執行。冬被= 理器m及/或PC卡控制器電路110執行時，這些;= 主處理器112及/或rc卡控制器電路110執行本文中戶 的由主處理器112及/或PC卡控制器電路11〇所執行的操^ 音頻子线106可包括’例如能_動揚聲器丨^的 聲益介面電路、能編碼和解碼音頻資料的編碼器/解碼器電 (CODEC) ’及/或其他能夠操作音頻資料之電路。圖、所示 系統100也可包括-個PC卡插槽1〇7，該插槽能電性地和 機械地耦接一個或多個PC，1〇4<3pC卡1〇4可包括，例如， -個或多個遵守或相容於PC卡規範、CardBus規範及/或 PCMCIA夫見範之卡’且該卡的類型可包括，例如，一個輸入 /輸出(I/O)卡及/或記憶卡。Pc卡控制器電路i j 〇能夠以一個 與所在系統100中的卡類型相容的方式，控制至及/或來自卡 104的I/O傳輸。因此，例如，如果卡刚為一個pcMc⑽〇 卡，則控制器110可控制該卡類型。控制器11〇亦可經由電 源開關電路102將電源轉接至卡1〇4。 圖2闡示可交換卡結構(ExCA)介面狀態暫存器細。該 ExCA暫存器可被遵守或相容於^卡信號規範(其包括，例 如，PC卡、CardBus及/或PCMCIA相容卡)之pc卡控制器 使用。狀態暫存器200指定一可由控制器為傳達特定資訊所 02 28CIP (0188) ROC SPEC REPLACEMENT 20070206 (2) 1286692 彳ίΚ作的位元(例如，位元〇 — 7)。例如’位元1和q(i : 〇)可與 控制器的電池電壓檢測引腳(BVD1和BVD2)有關，且這些位 元的設置可操作為傳輸該PC卡控制器的電池條件狀態及/或 給一個或多個被一個主處理系統執行的應用(例如，軟體）。 回到圖1例示性系統實施例1〇〇，該PC卡控制器電路 110 可藉由移除 CAUDI0/SPKR#/BVD2 引腳和 SPKR OUT# 引腳來減少引腳數。同樣地，在此實施例中，PC卡控制器 電路110可維持相容於一個或多個可使用於所移除之引腳相 關信號的PC卡，例如，一個PCMCIA記憶卡，該記憶卡可 包括電池及/或特定配置下的BVD2信號。 如果卡104為一個CardBus卡，信號線1〇5可經由插槽 107耦接到CAUDIO信號線。該CAUDIO信號可以傳輸來 自該CardBus卡的音頻資訊。如果卡1〇4為一個16位元 PCMCIA I/O卡，信號線1〇5可經由插槽1〇7耦接到卯^ 信號線。該SPKR#信號可傳輸來自該PCMCIA卡的音頻資 訊。如果卡104為一個16位元PCMCIA記憶卡，信號線1〇5 可經由插槽107麵接到BVD2信號線。一個16位元PCMCIA 記憶卡可包括一個電池，且該BVD2信號可以傳輸來自該 PCMCIA卡的電池電壓資訊。 在該貫施例中’視輕接到插槽107的卡1〇4的類型而 定，該CAUDIO/SPKR#/BVD2信號線1〇5可以藉由一個外 部電阻器103而被保持在一個固定電壓值。電阻器1〇3可包 括一個能夠使CAUDIO/SPKR#/BVD2信號線105下拉至參 考接地(ground)的下拉(pull-down)電阻器。信號線ios可輕接 至該音頻子系統106 ,但是不耦接至？(：控制器電路110。以 02 28CIP (0188) ROC SPEC REPLACEMENT 20070208 (2) 1286692 此方式’控制盗電路110的CAUDI0/SPKR#/BVD2引腳和 SPKROUT#引腳都可祕除。因此，pc卡控㈣電路ιι〇 月έ夠獨立於由該PC卡1〇4產生的CAUDIO/SPKR#/BVD2信 號線而控制PC卡1〇4。當沒有卡***時，該電阻器1〇3能 保持該CAUDI〇/SPKR#/BVD2信號線105處於接地參考電 壓。在另一個實施例中，當沒有卡***時，一個上拉(pull_up) 電阻态可被用來保持該CAUDI〇/SPKR#/BVD2信號線105 處於一個有效邏輯位準。 , 在本貫施例的PC卡控制器電路no中，該bvd2狀態 位元(其對應圖2中描述的ExCA介面狀態暫存器2〇〇的位 元1)可被硬連線(hardwired)至一個數值“1”。這會使控制器 110產生指示一個與16位元PCMCIA記憶卡相關的電池狀 悲的彳§號。這能移除“警告”電池狀態，並根據BVD1的值來 提供“電池良好(Battery Good)，，和“電池沒電(Battery Bad)，，狀 態。這些信號能被用於主系統所執行的軟體中。為了維持與 傳統Intel 82365 ExCA可程式化方法的相容性，該pc卡控 > 制器電路110可強制BVD2狀態報告暫存器在傳輸一個“電 池良好”狀態時為一個固定的值。 圖3所示為根據本發明之一實施例的例示性操作之流程 圖。該操作包括耦接一個PC卡的CAUDIO/SPKR#/BVD2信 號線至一個外部電阻器(步驟302)。該操作進一步包括從一 個PC卡控制器積體電路上斷開CAUDI0/SPKR#/BVD2信號 線（步驟304)。該操作可額外包括獨立於 CAUDI0/SPKR#/BVD2信號線’藉由PC卡控制器積體電路 而控制至少一個PC卡（步驟306)。在至少一個實施例中， 02 28CIP (0188) ROC SPEC REPLACEMENT 20070204 (2) 1286692 該知作可進-步包括移除Pc卡控制 CAUDIO/SPKR#/BVD2 30S) 〇 sloT^l^r 腳二;斗卡控制器積體電路中之™一out引 隹为一個貫施例中 么、戰，爹可園1的系統100，在主 ϋ ^ mp c卡控制器電路11G上執行的軟體可忽略 EXCA,Memory), random access memory, flash memory (which may include NAND or NOR type memory structures), disk memory and/or light body. The memory 121 may additionally or otherwise include other and/or recently developed types of computer readable files. The machine readable program instructions can be '' can be included in memory 121', e.g., software ν can be accessed and executed by processor m and/or pc card controller circuit 110. When the winter is executed by the processor m and/or the PC card controller circuit 110, these; = the main processor 112 and/or the rc card controller circuit 110 performs the control of the home processor 112 and/or the PC card in this document. The audio circuit 106 that is executed by the processor circuit 11 can include, for example, a sound interface interface capable of moving the speaker, an encoder/decoder electrical (CODEC) capable of encoding and decoding audio data, and/or the like. A circuit that can operate audio data. The illustrated system 100 can also include a PC card slot 1〇7 that can be electrically and mechanically coupled to one or more PCs. The 1〇4<3pC card 1〇4 can include, for example, - one or more cards that comply with or are compatible with the PC Card Specification, CardBus Specification, and/or PCMCIA Profile and that may include, for example, an Input/Output (I/O) card and/or memory card. The Pc card controller circuit i j 控制 can control I/O transmissions to and/or from the card 104 in a manner compatible with the type of card in which the system 100 is located. Thus, for example, if the card is just a pcMc (10) card, the controller 110 can control the card type. The controller 11A can also transfer power to the card 1〇4 via the power switch circuit 102. Figure 2 illustrates the Exchangable Card Architecture (ExCA) Interface Status Register Detail. The ExCA register can be used or compatible with the pc card controller of the card signal specification (which includes, for example, PC Card, CardBus, and/or PCMCIA compatible cards). The status register 200 specifies a bit (e.g., bit 〇 - 7) that can be communicated by the controller to convey a particular message 02 28 CIP (0188) ROC SPEC REPLACEMENT 20070206 (2) 1286692 。ίΚ. For example, 'bits 1 and q(i: 〇) can be related to the battery voltage detection pins (BVD1 and BVD2) of the controller, and the settings of these bits can be operated to transmit the battery condition status of the PC card controller and/or Or to one or more applications (eg, software) that are executed by a primary processing system. Returning to the exemplary system embodiment of Fig. 1, the PC card controller circuit 110 can reduce the number of pins by removing the CAUDI0/SPKR#/BVD2 pin and the SPKR OUT# pin. Similarly, in this embodiment, the PC Card controller circuit 110 can maintain a PC card compatible with one or more pins that can be used for the removed pin related signals, such as a PCMCIA memory card, which can be Includes battery and/or BVD2 signals in a specific configuration. If the card 104 is a CardBus card, the signal line 1〇5 can be coupled to the CAUDIO signal line via the slot 107. The CAUDIO signal can transmit audio information from the CardBus card. If the card 1〇4 is a 16-bit PCMCIA I/O card, the signal line 1〇5 can be coupled to the 信号^ signal line via the slot 1〇7. The SPKR# signal can transmit audio information from the PCMCIA card. If the card 104 is a 16-bit PCMCIA memory card, the signal line 1〇5 can be connected to the BVD2 signal line via the slot 107. A 16-bit PCMCIA memory card can include a battery and the BVD2 signal can transmit battery voltage information from the PCMCIA card. In the embodiment, the CAUDIO/SPKR#/BVD2 signal line 1〇5 can be held in a fixed state by an external resistor 103 depending on the type of the card 1〇4 that is lightly connected to the slot 107. Voltage value. Resistor 1〇3 can include a pull-down resistor that pulls CAUDIO/SPKR#/BVD2 signal line 105 down to the reference ground. The signal line ios can be lightly connected to the audio subsystem 106, but not coupled to? (: Controller circuit 110. 02 28 CIP (0188) ROC SPEC REPLACEMENT 20070208 (2) 1286692 In this way, the CAUDI0/SPKR#/BVD2 pin and the SPKROUT# pin of the control circuit 110 can be secreted. Therefore, pc The card control (four) circuit ιι〇月έ can control the PC card 1〇4 independently of the CAUDIO/SPKR#/BVD2 signal line generated by the PC card 1〇4. When no card is inserted, the resistor 1〇3 can be maintained. The CAUDI〇/SPKR#/BVD2 signal line 105 is at the ground reference voltage. In another embodiment, a pull-up resistive state can be used to hold the CAUDI〇/SPKR#/BVD2 when no card is inserted. The signal line 105 is at an active logic level. In the PC card controller circuit no of the present embodiment, the bvd2 status bit (which corresponds to the bit of the ExCA interface status register 2〇〇 described in FIG. 2) 1) can be hardwired to a value of "1." This causes controller 110 to generate a battery-like slogan indicating a battery-related sorrow associated with a 16-bit PCMCIA memory card. This removes the "warning" battery. Status, and provide "Battery Good," and "Battery No Battery" based on the value of BVD1 (Batt Ery Bad), state. These signals can be used in the software executed by the host system. In order to maintain compatibility with the traditional Intel 82365 ExCA programmable method, the pc card controller > controller circuit 110 can force BVD2 The status report register is a fixed value when transmitting a "battery good" state. Figure 3 is a flow diagram of an exemplary operation in accordance with an embodiment of the present invention, including CAUDIO coupled to a PC card. The /SPKR#/BVD2 signal line is connected to an external resistor (step 302). The operation further includes disconnecting the CAUDI0/SPKR#/BVD2 signal line from a PC card controller integrated circuit (step 304). Including at least one PC card is controlled by the PC card controller integrated circuit independently of the CAUDI0/SPKR#/BVD2 signal line (step 306). In at least one embodiment, 02 28CIP (0188) ROC SPEC REPLACEMENT 20070204 (2 1286692 The knowledge can be further steps including removing the Pc card control CAUDIO/SPKR#/BVD2 30S) 〇sloT^l^r foot 2; the TM-out of the bucket controller integrated circuit is a continuous implementation In the example, the battle, the system 100 of the 爹可园1, ϋ ^ software running on the controller circuit card 11G mp c negligible EXCA,

參 :目4、— VD2#纽為使用—個數值τ。在該實施例中， ^ 1所矛i的外部電崎103可被忽略，與先前的實施例相 以’ PC卡控制器電路11〇的caudi〇/spkr#卿Μ和 SPKR#—OU丁引腳可被移除。 、在另外-個實施例中，圖〗可選擇地或額外地包括另一 们^似插槽107的插槽，該插槽能接收另一個pc卡(類似於 卡104)。-個第二PC卡控㈣電路可用來控繼第二卡的 f作。在此等實施例中，依上述參考圖1-3所描述的方式， 每個PC卡控制盗電路的caudi〇/spkr#/bvd2引腳和 SPKR#一OUT引腳可被移除。 本文使用的術語與措辭是描述性而非局限性之術語，在 使用這些術語和措辭時，並未意欲獅其他與這襄所揭示和 為，的特徵(或特徵的—部分)相似的等同物，且應該意識到 =是^在申請專利範助，本發明可能有多種修改。本發明 运可能存在其他-錄改、變誠雜。因此，相專利範 圍旨在覆蓋所有這些等同物。Reference: Item 4, - VD2# New is used - a value τ. In this embodiment, the external electric island 103 of the ^ 1 spear i can be ignored, and the previous embodiment is the same as the 'PC card controller circuit 11' caudi〇/spkr#卿Μ and SPKR#-OU The foot can be removed. In still another embodiment, the Figure may alternatively or additionally include another slot similar to slot 107 that can receive another pc card (similar to card 104). - A second PC card control (four) circuit can be used to control the second card's f. In such embodiments, the caudi(R)/spkr#/bvd2 pin and the SPKR#-OUT pin of each PC card control pirate circuit can be removed in the manner described above with reference to Figures 1-3. The terms and expressions used herein are terms of description rather than limitation, and the use of these terms and expressions does not mean that the lion is otherwise equivalent to the features (or parts of the features) disclosed and claimed herein. And should be aware that = is ^ in the application for patents, the invention may have a variety of modifications. The present invention may have other-recording changes and changes. Therefore, the patent scope is intended to cover all such equivalents.

02 28CIP (G188) R〇c SPEC -1286692 【圖式簡單說明】 本發明實施例的特徵和優點將通過下述詳細說明以及 參考附圖而變得更為明顯，其中·· 圖1為一例示性系統實施例； 圖2為ExCA介面狀態暫存器，以及 圖3為根據本發明一實施例的例示性操作的流程圖。 雖然實施方式係根據例示性的實施例說明，但是關於種 種選擇、修改以及變化對於本領域中具有通常知識者來說 顯而易見的。應當注意的是，所主張的主旨應被廣泛考庹’、 且由隨附之申請專利範圍所界定。 思’ 【主要元件符號說明】 1〇〇 :控制至少一 PC卡之系統 102:電源開關電路 103 :電阻器 104: PC 卡，卡 105 :信號線，CAUDIO/SPKR#/BVD2 信號線 107 :插槽 106 :音頻子系統電路 110 : PC卡控制器電路 112 ··主處理器 114 ·晶片組 116 :使用者介面系統 118 :儲存裴置 111 :揚聲器 02 28CIP (0188) ROC SPEC REPLACEMENT 20070203 (2) 1286692 :系統記憶體 :匯流排 :狀態暫存器 :流程 :步驟 :步驟 :步驟 :步驟 :步驟 02 28CEP (0188) ROC SPEC REPLACEMENT 2007020^ (2)02 28 C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C C Embodiments of the system; Figure 2 is an ExCA interface state register, and Figure 3 is a flow diagram of an exemplary operation in accordance with an embodiment of the present invention. While the embodiments are described in terms of illustrative embodiments, it will be apparent to those skilled in the art It should be noted that the claimed subject matter should be considered extensively and is defined by the scope of the accompanying patent application.思' [Main component symbol description] 1〇〇: System 102 that controls at least one PC card: Power switch circuit 103: Resistor 104: PC card, card 105: Signal line, CAUDIO/SPKR#/BVD2 Signal line 107: Plug Slot 106: Audio Subsystem Circuit 110: PC Card Controller Circuit 112 • Main Processor 114 • Chipset 116: User Interface System 118: Storage Device 111: Speaker 02 28CIP (0188) ROC SPEC REPLACEMENT 20070203 (2) 1286692 : System Memory: Bus Bar: Status Register: Process: Step: Step: Step: Step: Step 02 28CEP (0188) ROC SPEC REPLACEMENT 2007020^ (2)

Claims (1)

十、申請專利範圍： I 種控制至少一 PC卡之裝置(apparatus)，其包括·· 一可控制至少一 PC卡之操作之積體電路，該積體電路 亦可獨立於由該PC卡產生之CAUDI0/SPKR#/BVD2 信號線，而控制該PC卡。 2·如請求項第1項之裝置，其中： 該至少一 PC卡包括一 16位元PCMCIA記憶卡，該16 位元PCMCIA記憶卡包括一電池，且該積體電路進一 步可固定該CAUDI0/SPKR#/BVD2信號線之值，以產 生指示該電池狀態之信號。 3·如請求項第1項之裝置，其中·· 該至少一 PC卡係選自由包括一 16位元PCMCIA輸入 /輸出卡、一 16位元PCMCIA記憶卡和一 CardBus卡 組成之群組。 4·如請求項第1項之裝置，其中： 該積體電路亦可藉由從該積體電路斷開一 SPKR#一OUT信號而獨立於該SPKR#J3UT信號而操 作。 5·如請求項第1項之裝置，其中： 該積體電路遵守一可交換卡結構(Exchangeable Card Architecture，ExCA)介面狀態暫存器，該積體電路進一 步可在該狀態暫存器中設置一與一 BVD2信號相關之 位元為一偭預定值。 6· —種控制至少一卩(：卡之方法，其包括： 從一 PC卡控制器積體電路上斷開一 CAUDI〇/SPKR#/BVD2 信號線；以及 獨立於該CAUDI0/SPKR#/BVD2信號線，藉由該PC 02 28CIP (0188) ROC SPEC REPLACEMENT 2007020^ (2) •1286692 V 卡控制器積體電路而控制至少一 pc卡。 7·如明求項第6項之方法，進-步包括： • 耦接一 PC卡之該CAUDI0/SPKR#/BVD2信號線至該 PC卡控制器積體電路之外部電阻器。 δ·如請求項第6項之方法，進一步包括： 移除該PC卡控制器積體電路之一 CAUDI0/SPKR#/BVD2 引腳。 9· t請求項第6項之方法，進一步包括： 斷開該PC卡控制器積體電路之一 spKR#_〇UT信號； • 以及 一 移除該PC卡控制器積體電路之一 SPKR#一OUT引腳。 10·如=求項第6項之方法，其中該PC卡控制器積體電路 遵守一可交換卡結構(EXCA)介面狀態暫存器，該方法 進一步包括： 在一狀態暫存器中設置一與一 BVD2信號相關之位元 至一預定值。 11·如請求項第6項之方法，其中·· _ 該至少一 PC卡係選自由包括一 16位元PCMCIA輸入 • /輸出卡、- 16位元PCMCIA記憶卡和一 CardBus卡 組成之群組選出。 12· —種控制至少一 PC卡之裝置(article)，其包括： 一儲存媒體，當其儲存的指令被一機器執行時導致下 列操作： 藉由一遵守一可交換卡結構(ExCA)介面狀態暫存器之 一 PC卡控制器積體電路，以忽略一與該狀態暫= 關之BVD2信號：以及 " 固疋戎BVD2信號之值為一選定值。 02 28CIP (0188) ROC SPEC REPLACEMENT 2007020^ (2) .1286692 • 13.如請求項帛12項之裝置’其中當該機器執行該指令時 _ 進一步導致下列額外操作： 獨立於由該pc卡產生卜CAUDi〇/sPKR#mvm # 號線，而操作至少一 PC卡。 14·如請求項第12項之震置，其中當該機器執行該指令時 進一步導致下列額外操作： 獨立於一 SPKR#一OUT信號，而操作該pc卡控制器積 體電路。' 15· —種控制至少一 PC卡之系統，其包括： • 一主處理器；以及 與該主處理器通聯之PC卡控制器積體電路，該 卡控制器積體電路進一步可控制至少一 PC卡之操 作，該PC卡控制器積體電路亦可獨立於由該PC卡產 生之一 cAUDIO/SPKR#/BVD2信號，而控制該PC卡。 16·如請求項第15項之系統，其中： 該至少一 PC卡包括一包含一電池之16位元pcMCIA 5己憶卡，且該PC卡控制器積體電路進一步可固定一值 • 至該CAUDI0/SPKR#/BVD2信號線，以產生指示該電 • 池狀態之信號' 17·如請求項第15項之系統，其中·· 該至少一 PC卡係選自由包括一 Ιό位元PCMCIA輸入 /輸出卡、一 16位元PCMCIA記憶卡和一 CardBus卡 組成之群組。 18.如請求項第15項之系統，其中·· 該積體電路亦可藉由從該積體電路上斷開一 SPKR#-〇UT信號而獨立於該SPKR#_OUT信號而操 作0 02 28CIP (0188) ROC SPEC REPLACEMENT 2007020? (2) .1286692 " 19.如請求項第15項之系統，其中： 該積體電路遵守一可交換卡結構（ExCA)介面狀態暫 存器，該積體電路進一步可在該狀態暫存器中設置一 與一 BVD2信號相關之位元為一預定值。X. Application Patent Range: A device for controlling at least one PC card, comprising: an integrated circuit capable of controlling operation of at least one PC card, the integrated circuit can also be generated independently of the PC card The CAUDI0/SPKR#/BVD2 signal line controls the PC card. 2. The device of claim 1, wherein: the at least one PC card comprises a 16-bit PCMCIA memory card, the 16-bit PCMCIA memory card comprising a battery, and the integrated circuit further fixes the CAUDI0/SPKR #/BVD2 The value of the signal line to generate a signal indicating the status of the battery. 3. The device of claim 1, wherein the at least one PC card is selected from the group consisting of a 16-bit PCMCIA input/output card, a 16-bit PCMCIA memory card, and a CardBus card. 4. The device of claim 1, wherein: the integrated circuit is also operable independently of the SPKR#J3UT signal by disconnecting an SPKR#-OUT signal from the integrated circuit. 5. The device of claim 1, wherein: the integrated circuit complies with an Exchangeable Card Architecture (ExCA) interface state register, the integrated circuit further configurable in the state register A bit associated with a BVD2 signal is a predetermined value. 6 - a method of controlling at least one (: card, comprising: disconnecting a CAUDI 〇 / SPKR # / BVD2 signal line from a PC card controller integrated circuit; and independent of the CAUDI0 / SPKR # / BVD2 The signal line is controlled by the PC 02 28CIP (0188) ROC SPEC REPLACEMENT 2007020^ (2) • 1286692 V card controller integrated circuit to control at least one pc card. 7 · If the method of item 6 of the item, enter - The steps include: • coupling the CAUDI0/SPKR#/BVD2 signal line of a PC card to an external resistor of the PC card controller integrated circuit. δ. The method of claim 6, further comprising: removing the One of the PC card controller integrated circuit CAUDI0/SPKR#/BVD2 pin. The method of claim 6 further includes: disconnecting one of the PC card controller integrated circuit spKR#_〇UT signal • and a SPKR#-OUT pin that removes one of the PC card controller integrated circuits. 10. The method of item 6, wherein the PC card controller integrated circuit complies with a switchable card structure (EXCA) interface state register, the method further comprising: setting one and one B in a state register The bit associated with the VD2 signal is a predetermined value. 11. The method of claim 6, wherein the at least one PC card is selected from the group consisting of a 16-bit PCMCIA input/output card, - 16 bits A group consisting of a PCMCIA memory card and a CardBus card is selected. 12. An apparatus for controlling at least one PC card, comprising: a storage medium, when the stored instructions are executed by a machine, causing the following operations: A PC card controller integrated circuit that obeys a switchable card structure (ExCA) interface state register to ignore a BVD2 signal temporarily associated with the state: and the value of the " fixed BVD2 signal A selected value 02 28CIP (0188) ROC SPEC REPLACEMENT 2007020^ (2) .1286692 • 13. As requested in item 12 of the device 'where the machine executes the instruction _ further leads to the following additional operations: independent of The pc card generates a CAUDi〇/sPKR#mvm# line and operates at least one PC card. 14· If the item 12 is shocked, the following additional operations are further caused when the machine executes the instruction: Independent of one SPKR#一O UT signal, and operating the pc card controller integrated circuit. '15. - A system for controlling at least one PC card, comprising: • a main processor; and a PC card controller integrated with the main processor a circuit, the card controller integrated circuit further controls operation of at least one PC card, and the PC card controller integrated circuit can also control the PC independently of one of the cAUDIO/SPKR#/BVD2 signals generated by the PC card card. The system of claim 15, wherein: the at least one PC card comprises a 16-bit pcMCIA 5 memory card including a battery, and the PC card controller integrated circuit further fixes a value to the CAUDI0/SPKR#/BVD2 signal line to generate a signal indicating the state of the battery. 17. The system of claim 15, wherein the at least one PC card is selected from the group consisting of a PCMCIA input/ A group of output cards, a 16-bit PCMCIA memory card, and a CardBus card. 18. The system of claim 15, wherein the integrated circuit can also operate independently of the SPKR#_OUT signal by disconnecting an SPKR#-〇UT signal from the integrated circuit. 02 2 CIP (0188) ROC SPEC REPLACEMENT 2007020? (2) .1286692 " 19. The system of claim 15, wherein: the integrated circuit complies with a replaceable card structure (ExCA) interface state register, the integrated body The circuit can further set a bit associated with a BVD2 signal to a predetermined value in the state register. 02 28CIP (0188) ROC SPEC REPLACEMENT 20070208 (2) 1286692 - 七、指定代表圖： . (一)本案指定代表圖為：第（1)圖。 (二)本代表圖之元件符號簡單說明： - 100 :控制至少一 PC卡之系統 102:電源開關電路 103 ··電阻器 104 : PC 卡 105 ··信號線 107 :插槽 _ 106 ··音頻子系統電路 110 : PC卡控制器電路 112:主處理器 114 :晶片組 116 :使用者介面系統 118 :儲存裝置 111 ··揚聲器 121:系統記憶體 • 122:匯流排 八、本案若有化學式時，請揭示最能顯示發明特徵的化學式: 02 28CIP (0188) ROC SPEC REPLACEMENT 200702^6 (2)02 28CIP (0188) ROC SPEC REPLACEMENT 20070208 (2) 1286692 - 7. Designation of representative drawings: (1) The representative representative of the case is: (1). (2) A brief description of the component symbols of the representative figure: - 100: System 102 for controlling at least one PC card: Power switch circuit 103 · Resistor 104: PC card 105 · Signal line 107: Slot _ 106 · Audio Subsystem circuit 110: PC card controller circuit 112: main processor 114: chipset 116: user interface system 118: storage device 111 · speaker 201: system memory • 122: bus bar VIII, if there is a chemical formula in this case Please reveal the chemical formula that best shows the characteristics of the invention: 02 28CIP (0188) ROC SPEC REPLACEMENT 200702^6 (2)