1283925 Λ 【發明所屬之技術領域】 本發明是有關於一種半導體元件，且特別是有關於 種縛狀場效電晶體。 - 【先前技術】 自從1960年代發展出積體電路之後，其元件密度至 • 現在已經大幅增加不少。在積體電路之元件密度增加的同 時’元件的尺寸也不斷地跟著縮小。尤其是閘極的厚度與 源極/汲極之間通道（channel)的長度，其需求尺寸已經進 入微米（micrometer)至奈米（nanometer)的等級。在元件尺 寸不斷縮小的過程中，元件操作的特性（characteristies)、 可信度（reliability)、耐久度（durability)以及元件製造的可 信度和成本，一直是受重視的課題。 在元件最小化的過程中，也產生了好幾個問題，包括 瞻短通道效應、穿擊效應（punch-through)與漏電流。這些問 題影響了元件的操作與製程。短通道效應常見於通道長度 小於0·5至1.0微米的fet，其影響為降低元件的閥值電 壓（threshold voltage)與增加副閥值電流（sub-threshold current)。更具體地說，當通道長度縮小的時候，源極與 ;及極的空乏區（depletion region)會向彼此靠近，而使得源 極與汲極的空乏區互相重疊，佔據部分的通道長度。因 此’需要改變源極與汲極電▲大小的閘極電壓也跟著減少 了0 1283925 解决短通道效應的方法之一為減少閘氧化層的厚 此方法不僅減少了短通道效應，還增加了 FET的驅 動電流（drive current)，使得元件操作速率增加了。但是 薄氧化層的製作仍然存在有許多問題，包括製造上的可重 複丨生與均一性，還有在製造過程中如何控制氧化層的生長 速率。 為了解決元件需要不斷縮小化的課題，在1999年12 月加州大學柏克萊分校發表一種全新的場效電晶體 (Pield Effect Transist〇r ; FET)，稱做鰭狀場效電晶體 (FinFET)。請參考第！圖，第！圖為習知的場效電晶體結 構的俯視示意圖。在覆蓋著氧化矽層的基底1〇〇上，分佈 著源極/汲極11〇與閘極12〇，兩個源極/汲極間為鰭狀通 道 130。 請參考第2A - 2B圖，第2A圖為第i圖之AA'剖面 的結構示意圖，而第2B圖為第i圖之BB，剖面的結構示 意圖。在第2A與2B圖中，基底1〇〇上有氧化矽層ι〇5、 源極/汲極110、鰭狀通道130、閘氧化層135、閘極12〇 與矽化金屬層125。在第2B圖中，可以清楚地看到鰭狀 通道130之表面被閘氧化層135與氧化矽層1〇5所包圍， 而閘極120又跨越於鰭狀通道13〇之上。 上述閘極與鰭狀通道結構之設計，為鰭狀場效電晶體 没计上的突破之處。藉由此種設計，使得場效電晶體通道 之厚度、寬度與長度可以完全由需求來決定。原先一般之 %效電晶體之閘極的設計為僅覆蓋通道其中之一平面而 1283925 已’但是若閘極之長度繼續縮短的話，將無法關閉流經通 道之電流，亦即前面所述之短通道效應所帶來的問題。但 是使用鰭狀場效電晶體的閘極設計，讓閘極圍繞著通道的 三個平面，使得元件的尺寸可以繼續縮小。不過上述鰭狀 通道的結構設計，也使其亦成為矽在絕緣層上（silicon on 、 insulator，· SOI)的結構’成為一浮置體（fi〇ating body)的狀 、態，而無法控制其電壓。 【發明内容】 因此本發明的目的就是在提供一種具有體接觸窗 (body contact)之鰭狀場效電晶體與其製造方法，以利控 制鰭狀通道之電壓。 本發明的另一目的是在提供一種具有體接觸窗之鰭 狀場效電晶體與其製造方法，可用來測量閘氧化層的厚度 與品質。 • 根據本發明之上述目的，提出一種具有體接觸窗之鰭 狀場效電晶體。此鰭狀場效電晶體至少包含鰭狀通道、源 、極、汲極、體接觸窗、閘介電層與閘極。其中源極與汲極 _ 分別與鰭狀通道之兩端相接，體接觸窗位於鰭狀通道之一 側並藉由導線與其相接。閘介電層覆蓋在鰭狀通道之表 面，而閘極位於鰭狀通道之另一側，並跨越其上。 根據本發明之上述目的，提出一種具有體接觸窗之鰭 狀場效電晶體的製造方法。此製造方法至少包含依序形成 絕緣層與半導體層於基底上，然後圖案化半導體層以形成 1283925 τ形通道’並同時形成源極、波極與體接觸窗分別於τ形 通(道之三個端點上，其中源極與没極位於τ形通道之橫 向通道的相對兩端點上。接著形成閘介電層於Τ形通道' 源極、没極與體接觸窗上，再形成導電層於基底上。缺後 圖案化導電層以形成閉極跨越於Τ形通道之橫向通道 上’且閘極與體接觸t分別位於τ形通道之橫向通道的 兩側。 依照本發明-較佳實施例，還包含形成多個絕緣間隙 壁於閘極、源極、汲極、體接觸窗與τ形通道之側壁上。 閘介電層包含以熱氧化法或化學翁一 成-飞化予轧相况積法所形成之閘 氧化層或以化學氣相沉積法所形成之具有高介電常數之 2層爲而絕緣間隙壁的材質包含氮化石夕。半導體層可為 蟲晶矽層、多晶矽層、磊曰々蚀 猫日日矽鍺或早晶鍺，而導電層的材 夤例如可為半導體材料，或是其 屬、氣化金屬1化金屬等。導電陡的材質，如金 根據上述，因為鰭狀通道與體接觸窗相接，因此 控制鰭狀通道的電壓，並藉此丨旦 質。 工精此測里閘虱化層的厚度與其品 【實施方式】 根據上述’本發明提供一種具有 電晶體與其製造方法，以 -狀场效 〜徑制鰭狀通道之電壓，並可用 來測量閘氧化層的厚度與品質。 工了用 請參照第3Α — 3D圖，盆給 八、日不依π本么明一較佳實施 1283925 例的一種具有體接觸窗之鰭狀場效電晶體的製造流程剖 面圖。在第3A圖中，在基底2〇〇上依序形成第一絕緣層 ”半導體層210。第一絕緣層2〇5的材質例如可為氧 化夕其形成方法例如可為化學氣相沈積法或熱氧化法。 半導體層21G的材質例如可切層（如··蟲晶梦或多晶 夕）猫日日矽鍺層或單晶鍺層，其形成方法例如可為化學 氣相沈積法。1283925 Λ BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor device, and more particularly to a field-effect field effect transistor. - [Prior Art] Since the development of integrated circuits in the 1960s, the component density has increased significantly. At the same time as the component density of the integrated circuit is increased, the size of the component is continuously reduced. In particular, the thickness of the gate and the length of the channel between the source and the drain have been required to enter the micrometer to nanometer rating. In the process of shrinking component sizes, the characteristics of component operation, reliability, durability, and the reliability and cost of component manufacturing have always been the subject of attention. Several problems have arisen during the minimization of components, including short channel effects, punch-through and leakage currents. These issues affect the operation and process of the component. Short channel effects are common in fet with channel lengths less than 0.5 to 1.0 microns, with the effect of lowering the threshold voltage of the component and increasing the sub-threshold current. More specifically, when the channel length is reduced, the source and the depletion regions of the poles are close to each other, and the source and drain regions of the drain overlap each other, occupying part of the channel length. Therefore, the gate voltage that needs to change the size of the source and the drain ▲ is also reduced by 0 1283925. One of the ways to solve the short channel effect is to reduce the thickness of the gate oxide. This method not only reduces the short channel effect, but also increases the FET. The drive current increases the component operating speed. However, there are still many problems in the fabrication of thin oxide layers, including reproducible twinning and homogeneity in manufacturing, and how to control the growth rate of the oxide layer during the manufacturing process. In order to solve the problem of the need for components to continue to shrink, in December 1999, the University of California at Berkeley published a new field effect transistor (FET), called the fin field effect transistor (FinFET) . Please refer to the first! Figure, the first! The figure is a top plan view of a conventional field effect transistor structure. On the substrate 1 covered with the ruthenium oxide layer, a source/drain 11 〇 and a gate 12 分布 are distributed, and a fin-like channel 130 is formed between the two source/drain electrodes. Please refer to Fig. 2A - 2B, Fig. 2A is a structural diagram of the AA' section of Fig. i, and Fig. 2B is BB of Fig. i, the structure of the section is shown. In Figs. 2A and 2B, the substrate 1 has a hafnium oxide layer ι 5, a source/drain 110, a fin channel 130, a gate oxide layer 135, a gate electrode 12, and a deuterated metal layer 125. In Fig. 2B, it can be clearly seen that the surface of the fin channel 130 is surrounded by the gate oxide layer 135 and the yttrium oxide layer 1〇5, and the gate electrode 120 is again over the fin channel 13〇. The design of the above-mentioned gate and fin channel structure is a breakthrough for the fin field effect transistor. With this design, the thickness, width and length of the field effect transistor channel can be completely determined by the demand. The gate of the original general-purpose transistor is designed to cover only one of the planes of the channel and 1283925 has been used. However, if the length of the gate continues to be shortened, the current flowing through the channel cannot be turned off, that is, the short as described above. The problem caused by the channel effect. However, the gate design of the fin field effect transistor is used, so that the gate surrounds the three planes of the channel, so that the size of the component can continue to shrink. However, the structural design of the above-mentioned fin channel also makes it become a structure of a silicon-on-insulator (silicon on, insulator, SOI), which becomes a state of a floating body and cannot be controlled. Its voltage. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a fin field effect transistor having a body contact and a method of fabricating the same to control the voltage of the fin channel. Another object of the present invention is to provide a fin field effect transistor having a body contact window and a method of fabricating the same that can be used to measure the thickness and quality of a gate oxide layer. • According to the above object of the present invention, a fin field effect transistor having a body contact window is proposed. The fin field effect transistor includes at least a fin channel, a source, a pole, a drain, a body contact window, a gate dielectric layer and a gate. The source and the drain _ are respectively connected to the two ends of the fin channel, and the body contact window is located on one side of the fin channel and is connected thereto by a wire. The gate dielectric layer covers the surface of the fin channel, and the gate is located on the other side of the fin channel and spans thereon. According to the above object of the present invention, a method of manufacturing a fin field effect transistor having a body contact window is proposed. The manufacturing method comprises at least forming an insulating layer and a semiconductor layer on the substrate in sequence, and then patterning the semiconductor layer to form a 1283925 τ-shaped channel' and simultaneously forming a source, a wave and a body contact window respectively in a τ-shaped pass (3 of 3) At the end points, where the source and the pole are located at opposite ends of the transverse channel of the τ-shaped channel, then the gate dielectric layer is formed on the 源-channel 'source, the immersion and the body contact window, and then the conductive is formed. Layered on the substrate. The conductive layer is patterned to form a closed pole across the lateral channel of the meandering channel and the gate and body contacts t are respectively located on opposite sides of the transverse channel of the channel. According to the invention - preferably The embodiment further includes forming a plurality of insulating spacers on the sidewalls of the gate, the source, the drain, the body contact window and the τ-shaped channel. The gate dielectric layer comprises a thermal oxidation method or a chemical Weng Yicheng-Feihua The gate oxide layer formed by the rolling phase method or the two layers having a high dielectric constant formed by chemical vapor deposition is a material of the insulating spacer. The semiconductor layer may be a worm layer or a polycrystalline layer. Lei Lei cat The corrugated or early crystal crucible, and the material of the conductive layer can be, for example, a semiconductor material, or a genus, a vaporized metal, a metal, etc. A material having a strong electrical conductivity, such as gold, according to the above, because the fin channel is in contact with the body The windows are connected to each other, so that the voltage of the fin channel is controlled, and thereby the quality of the gate layer is determined by the method. [Embodiment] According to the above, the present invention provides a transistor having a transistor and a manufacturing method thereof. The voltage of the fin channel can be measured by the field effect and can be used to measure the thickness and quality of the gate oxide layer. For the work, please refer to the 3rd - 3D map, the basin is given to the 8th, and the day is not according to the π. A cross-sectional view showing a manufacturing process of a fin-shaped field effect transistor having a body contact window in a case of 1283925. In FIG. 3A, a first insulating layer "semiconductor layer 210" is sequentially formed on a substrate 2A. The first insulating layer For example, the material of the second layer may be a chemical vapor deposition method or a thermal oxidation method. The material of the semiconductor layer 21G may be, for example, a sliceable layer (eg, insect crystal or polycrystalline eve) cat day a layer of germanium or a single crystal layer, For example, as a method for the chemical vapor deposition method.
請同時參考第3B圖與第4圖，其中第4圖為第把 圖：俯視示意圖，而第3B圖為第4圖之AA，剖面的結構 二圖在第3B圖與第4圖中，先利用微影银刻法將半 導體層210定義出源極/沒極_、縛狀通道麗、 觸由21Ge與基底通道21Qd (亦即第3b冑中之半導體層 210)，其中鰭狀通道、^ ^ 、21〇b與基底通道21〇d形成T形通 2V::、用熱氧化法或化學氣相沉積法在…極 的矣而:欠通道210b、體接觸窗210c與基底通道210d 介電層215β閘介電層215的材質例如可為 材料 有高介電常數(如介電常…0-30)之介電 明冋時參考第3C圖與第 甘Please refer to FIG. 3B and FIG. 4 at the same time, wherein FIG. 4 is a first drawing: a top view, and FIG. 3B is AA of FIG. 4, and the second structure of the cross section is in FIG. 3B and FIG. The semiconductor layer 210 is defined by a lithography method to define a source/depolarization_, a ring-like channel, a contact 21Ge, and a substrate channel 21Qd (that is, a semiconductor layer 210 in the third layer), wherein the fin channel, ^ ^, 21〇b and the base channel 21〇d form a T-shaped pass 2V:: by thermal oxidation or chemical vapor deposition at the extreme: the under-channel 210b, the body contact window 210c and the base channel 210d are dielectrically The material of the layer 215β gate dielectric layer 215 can be, for example, a dielectric alum having a high dielectric constant (such as dielectric constant...0-30). Refer to FIG. 3C and the first Gan.
图夕偷、目-立 弗5圖，其中第5圖為第3C 圖之俯視不思圖，而第3C圖A諠《的 -立θ >咕 罘圖為弟5圖之ΑΑ，剖面的結構 不忍圖。在弟3C圖與第5圖中， 可ΑI^ , 无沈積導電層，其材質 了為+導體材枓（如：多晶矽 雪祕认从所， 夕日日石夕鍺）、或其他具導 電性的材貝，如金屬、氮化金屬、矽化 旦> 為方丨丨、么啦：甘—μ 屬專’再利用4 以钱刻法將其疋義出閘極220。在筐 社弟5圖中，可以清楚地 10 1283925 極22〇和體㈣窗_位在鰭狀通道聽之兩 ::閉極220跨越在縛狀通道纏之上，而體接觸窗· 則猎由基底通道21Gd與鰭狀通道2i〇b直接相接。 在第3D圖中’先钱刻暴露出之閉介電層215，蚀刻 ^電層215的方法例如可為濕㈣法。再形成第二絕緣 '(圖上未示出)於基底2〇〇上’然後以非等向性蝕刻法蝕 刻此第二絕緣層，在源極/沒極21〇a、續狀通道、體 接觸窗210c與基底通道21〇d(亦即第扣圖中之半導體層 21〇)的側壁上形成間隙^ 23G，亦同時於閘極22〇和; "電層2 1 5之疊層結構的侧壁上形成間隙壁23〇。第二絕 緣層的材質例如可為氮切，其形成方法例如可為化學氣 相沈積法。 然後藉由快速熱製程（rapid thermal pr〇cess ; RTp)在 暴露出之源極/汲極210a、鰭狀通道21〇b、體接觸窗2i〇c 與基底通道210d (亦即第3D圖中之半導體層21〇)之上Figure XI steals, eye-Liver 5, where the fifth picture is the 3C picture overlooking, and the 3C picture A 喧 "- θ > 咕罘 picture is the 5 5 picture, the profile The structure cannot bear the picture. In the 3C and 5th figures, there is no deposited conductive layer, which is made of +conductor material (such as: polycrystalline 矽 snow secrets, 夕日日石锗), or other conductive Material shells, such as metal, metal nitride, sputum and sputum, are square 丨丨, 么啦: Gan-μ belongs to the special 'reuse 4' to use money to engrave the gate 220. In the picture of the basket brother 5, it can be clearly 10 1283925 pole 22 〇 and body (four) window _ position in the fin channel to hear two:: the closed pole 220 spans over the bound channel, and the body contact window The base channel 21Gd is in direct contact with the fin channel 2i〇b. In the 3D diagram, the method of etching the dielectric layer 215 and etching the electrical layer 215 may be, for example, a wet (four) method. Forming a second insulation '(not shown) on the substrate 2' and then etching the second insulating layer by anisotropic etching, at the source/no pole 21〇a, the continuous channel, the body The contact window 210c forms a gap ^ 23G on the sidewall of the substrate channel 21 〇d (that is, the semiconductor layer 21 第 in the first figure), and also at the same time as the gate 22 and the laminated structure of the electric layer 2 1 5 A spacer 23 is formed on the side wall. The material of the second insulating layer may be, for example, nitrogen cutting, and the forming method thereof may be, for example, a chemical vapor deposition method. Then, through the rapid thermal pr〇cess (RTp), the exposed source/drain 210a, the fin channel 21〇b, the body contact window 2i〇c and the base channel 210d (ie, the 3D map) Above the semiconductor layer 21)
形成矽化金屬層240，以降低源極/汲極21〇a、鰭狀通道 21〇b、體接觸窗210c與基底通道21〇d (亦即第3d圖中之 半導體層210)之電阻值。若閘極22〇的材質為多晶矽材 質’則在此亦會同時在其表面形成矽化金屬層24〇，如圖 所示。 此外，閘極220與矽化金屬層240之組合的材質除了 上述之矽與矽化金屬之外，還可以為金屬（如鎢、鈦或翻: 或氮化金屬（如氮化鈦）。 由上述本發明較佳實施例可知，因為鰭狀通道與體接 11 1283925 觸窗相接，因此可以藉由體接觸窗上施加不同大小的電麼 至鰭狀通道上，做出閘介電層的電容（c)_電壓（v)曲線， 並藉此測量閘氧化層的厚度與其品質。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 •神和範圍内，當可作各種之更動與潤飾，因此本發明之保 . 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 第1圖為習知的場效電晶體結構的俯視示意圖。 第2A圖為第i圖之AA/剖面的結構示意圖。 • 第2B圖為第1圖之BB'剖面的結構示意圖。 第3A - 3D圖係繪示依照本發明一較佳實施例的一 ，種’、有體接觸囪之鰭狀場效電晶體圖的製造流程剖面圖。 第4圖為第3B圖之俯視示意圖。 第5圖為第3C圖之俯視示意圖。 【主要元件符號說明】 100、2〇〇 :基底 1 〇5 :氧化矽層 12 1283925 110、210a :源極/汲極 120、220 :閘極 125、240 :矽化金屬層 130、210b ：鰭狀通道 1 3 5 :閘氧化層 205 :第一絕緣層 2 1 0 :半導體層 210c :體接觸窗 210d :基底通道 2 1 5 :閘介電層 230 :間隙壁The deuterated metal layer 240 is formed to lower the resistance values of the source/drain 21a, the fin-shaped channel 21b, the body contact window 210c, and the base channel 21〇d (i.e., the semiconductor layer 210 in FIG. 3d). If the material of the gate 22 is polycrystalline germanium, then a layer of germanium metal 24 is formed on the surface thereof as shown in the figure. In addition, the material of the combination of the gate electrode 220 and the deuterated metal layer 240 may be a metal (such as tungsten, titanium or a metal nitride (such as titanium nitride) in addition to the above-mentioned germanium and germanium metal. According to the preferred embodiment of the present invention, since the fin channel is in contact with the body contact 11 1283925, the capacitance of the gate dielectric layer can be made by applying different sizes of electricity to the fin channel through the body contact window ( c) _ voltage (v) curve, and thereby measuring the thickness of the gate oxide layer and its quality. Although the invention has been disclosed above in a preferred embodiment, it is not intended to limit the invention, and anyone skilled in the art, The scope of protection of the present invention is subject to the definition of the scope of the appended patent application, without departing from the spirit and scope of the invention. The above and other objects, features, and advantages of the present invention will become more apparent and understood. Top view of the crystal structure Fig. 2A is a structural diagram of the AA/section of the i-th figure. Fig. 2B is a structural diagram of the BB' section of Fig. 1. Fig. 3A - 3D is a diagram showing a preferred embodiment of the present invention. Fig. 4 is a top plan view of Fig. 3B. Fig. 5 is a top plan view of Fig. 3C. [Main component symbol description] 100, 2 〇〇: substrate 1 〇 5 : yttrium oxide layer 12 1283925 110, 210a: source/drain 120, 220: gate 125, 240: bismuth metal layer 130, 210b: fin channel 1 3 5 : gate Oxide layer 205: first insulating layer 2 1 0 : semiconductor layer 210c: body contact window 210d: substrate channel 2 1 5 : gate dielectric layer 230: spacer
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