TWI283412B - High-speed memory sensing circuit - Google Patents

Abstract

The present invention discloses a sensing circuit that uses high-speed charge transferring technique when reading data inside the memory for sensing voltage variation of data input terminal. In the invention, the purpose of high-speed sensing is obtained according to the difference of charge transferring amount generated during the precharge and data reading period.

Description

1283412 五、發明說明α) 發明所屬之技術領域 本發明係關於一種用於記憶體之高速感測電路，特別 是關於一種利用電荷轉移的技巧來提升讀取記::憶體内部資 料速率之感測電路。 先前技術 半導體記憶體的資料讀取係利用電壓感測放大器 (voltage sense amplifier)或電流感測放大器（current s e n s e a m p 1 i f i e r )來達成。電壓感測放大器的原理係感測 記憶體的感測節點在資料'讀取期間的電壓變化，以決定資 料的邏輯值。不幸地，在高速元件中，常因製程變動或偏 差使得資料讀取容易發生錯誤，造成系統的不正常運作。 發明内容 / 本發明提出一種偵測乎/同路徑的電荷轉移所產生的電 荷差值，以達到高速感測的目的。因為經由不同路徑進行 預充電（p r e - c h a r g e )與感測資料所產生的電荷量並不相 同；因此只要些微的電荷量差即可感測到記憶體資料。本 發明的目的，在於提供一種記憶體内部資料讀取之高速感 測電-路。該感測電4係將電荷儲存元件***感測節，〆與判 斷電路之間，使得資料讀取期間感測節點只要有些微的電 壓變化，判斷電路就能立即地產生因應的輸出，因而達到 快速感測的目的。 根據本發明，一種記憶體之高速感測電、路及方法包括BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-speed sensing circuit for a memory, and more particularly to a technique for utilizing charge transfer to enhance the reading of a memory: Measuring circuit. Prior Art Data reading of semiconductor memory is achieved using a voltage sense amplifier or current sense amplifier (current s e n s e a m p 1 i f i e r ). The principle of the voltage sense amplifier is to sense the voltage change of the sense node of the memory during the reading of the data to determine the logical value of the data. Unfortunately, in high-speed components, data reading is often erroneous due to process variations or deviations, causing abnormal operation of the system. SUMMARY OF THE INVENTION / The present invention proposes a charge difference generated by detecting charge transfer of the same path to achieve high speed sensing. Since precharging (p r e - c h a r g e ) via different paths is not the same as the amount of charge generated by the sensing data; therefore, the memory data can be sensed with a small amount of charge difference. It is an object of the present invention to provide a high speed sensing electric path for reading data inside a memory. The sensing circuit 4 inserts the charge storage element into the sensing section, and between the 〆 and the judging circuit, so that the sensing node can generate the corresponding output immediately as long as the sensing node has a slight voltage change during the data reading, thereby achieving The purpose of rapid sensing. According to the present invention, a high speed sensing power, method and method for a memory body includes

1283412 五、發明說明（2) 連接一預充電電路至該記憶體的感測節點以及在該感測節 點與判斷電路之間連接一電荷儲存元件。在預充電期間， 該感測節點被充電至一預充電電壓，然後在感測期間，當 記憶陣列連接至感測節點時，藉由該電荷儲存元件的電壓 變化，使判斷電路能快速感測出記憶資料。較佳者，該判 斷電路包括一比較器，使該感測電路有較大之雜訊容忍能 力。 實施方式 圖1顯示本發明之一貪施例，其中記憶體電路1 〇 〇包括 電流鏡1 0 2、參考陣列1 0 8及記憶陣列1 1 0 ，信號B I A S開關 電晶體1 0 4及1 0 6以分別連接參考陣列1 0 8及記憶陣列1 1 0到 電流鏡1 0 2，信號G N為資料讀取之致能信號。電流鏡1 0 2之 參考端連接到電晶體104，晶體112受控於信號GN以連接 參考陣列1 0 8到電源電壓V s,/。電流鏡1 0 2之鏡射端經感測 節點1 2 4連接電晶體1 0 6，電晶體1 1 4受控於信號G N以連接 記憶陣列1 1 0到電源電壓V s s。預充電電路1 2 0耦接至感測 節點1 2 4，感測節點1 2 4亦連接電荷儲存元件1 2 8，電荷儲 存元件128連接至判斷電路134。此外，一開關132跨接在 判斷-電路1 3 4之輸入f a與輸出0 U T之間。 ， 預充電電路1’2 0及開關1 3 2受控於預充電信號，在預充 電期間，該預充電信號控制預充電電路1 2 0以及開關1 3 2導 通，使該預充電電路1 2 0將感測節點1 2 4充電至一預充電電 壓。當此電路切換到感測模式後，預充電.電路1 2 0不再作1283412 V. DESCRIPTION OF THE INVENTION (2) A precharge circuit is connected to the sensing node of the memory and a charge storage element is connected between the sensing node and the determining circuit. During pre-charging, the sensing node is charged to a pre-charge voltage, and then during the sensing, when the memory array is connected to the sensing node, the determining circuit can quickly sense when the voltage of the charge storage element changes. Out of memory data. Preferably, the decision circuit includes a comparator to provide greater noise tolerance to the sense circuit. Embodiments FIG. 1 shows an embodiment of the present invention in which a memory circuit 1 includes a current mirror 1 0, a reference array 1 0 8 and a memory array 1 1 0 , a signal BIAS switching transistor 1 0 4 and 1 0 6 to connect the reference array 1 0 8 and the memory array 1 10 to the current mirror 1 0 2, respectively, and the signal GN is an enable signal for data reading. The reference terminal of current mirror 102 is coupled to transistor 104, which is controlled by signal GN to connect reference array 108 to supply voltage Vs, /. The mirror end of the current mirror 1 0 2 is sensed. Node 1 2 4 is connected to the transistor 1 0 6. The transistor 1 1 4 is controlled by the signal G N to connect the memory array 1 10 to the supply voltage V s s. The precharge circuit 120 is coupled to the sense node 1 2 4, and the sense node 1 24 is also coupled to the charge storage element 1 2 8 and the charge storage element 128 is coupled to the decision circuit 134. In addition, a switch 132 is connected across the input f a of the decision-circuit 1 34 and the output 0 U T . The pre-charging circuit 1'20 and the switch 1 3 2 are controlled by the pre-charging signal. During the pre-charging, the pre-charging signal controls the pre-charging circuit 1 220 and the switch 1 3 2 to be turned on, so that the pre-charging circuit 1 2 0 charges the sense node 1 24 to a precharge voltage. When this circuit is switched to the sensing mode, the pre-charging circuit 1 2 0 is no longer

12834121283412

用’且開關1 3 2開路，信號B I AS控制電晶體1 Ο 4與1 〇 6導 通’以及信號GN控制電晶體1 1 2與11 4導通，在記憶陣列 11 0中所儲存之資料經由電流鏡1 〇 2比較參考陣列1 〇 8而在 感測節點1 2 4產生電壓變化。該電壓變化值經由電荷儲存 凡件1 2 8會立即呈現在判斷電路輸入端Va上，再由判斷電 路1 3 4判斷後輸出其資料。 兒 圖2所示為圖1電路之一實施例，記憶體電路2 q 〇如習 知之技術，包括電流鏡2 〇 2、參考陣列2 0 8及記憶陣列 2 1 ◦’信號GN為資料讀取之致能信號。電流鏡2 〇 2包含參考 ，電晶體2 0 3連接到電晶體2 0 4與鏡射端電晶體2 0 5經感^則 節點2 2 4連接到電晶體2 〇 6，電晶體2 1 6受控於預充電信號 連接電源電壓Vdd至電晶體2 0 5。 口〜 電晶體2 2 0連接到電源電壓v d d，電晶體2 2 2連接在電 曰曰體2 2 0與感測節點2 2 4.之間〆，電晶體2 2 0之閘極_接到反 相器2 1 8的輸出，反相器2 l/的輸入耦接預充電信號，電晶 體2 2 2之閘極耦接到信號BIAS。電容2 2 8連接在感測節點 2 2 4及反相器2 3 4之間。另外，一開關2 3 2跨接在反相器2 3 4 之輸入Va與輸出OUT之間。 在預充電期間，預充電信號為”丨π ，該信號控制電晶 體2 L.6截止，切斷電流鏡2 0 2鏡射端電晶體2 〇 5的電丨原_。另 外，預充電信號經過反相器2 1 8使得電晶體2 2 〇導通，經電 晶體2 2 2對感測節點2 2 4充電至一預充電電壓。開關2 3 2亦 受控於預充電信號為”厂，而導通，電容22δ因此而儲存電 荷0With 'and switch 1 3 2 open circuit, signal BI AS controls transistor 1 Ο 4 and 1 〇6 conducts' and signal GN controls transistors 1 1 2 and 11 4 to conduct, the data stored in memory array 110 is current Mirror 1 比较 2 compares reference array 1 〇 8 to produce a voltage change at sense node 1 24 . The voltage change value is immediately presented on the input terminal Va of the judging circuit via the charge storage unit 128, and then the data is outputted by the judging circuit 134. FIG. 2 shows an embodiment of the circuit of FIG. 1. The memory circuit 2 q is a conventional technique including a current mirror 2 〇 2, a reference array 208, and a memory array 2 1 ◦ 'signal GN for data reading. The enable signal. The current mirror 2 〇 2 contains a reference, the transistor 2 0 3 is connected to the transistor 2 0 4 and the mirror end transistor 2 0 5 is sensed, then the node 2 2 4 is connected to the transistor 2 〇 6, the transistor 2 1 6 The power supply voltage Vdd is connected to the transistor 2 0 5 controlled by the precharge signal. Port ~ 2 2 0 is connected to the power supply voltage vdd, the transistor 2 2 2 is connected between the electric body 2 2 0 and the sensing node 2 2 4. The gate of the transistor 2 2 0 is connected The output of the inverter 2 1 8 , the input of the inverter 2 l / is coupled to the precharge signal, and the gate of the transistor 2 2 2 is coupled to the signal BIAS. The capacitor 2 2 8 is connected between the sensing node 2 2 4 and the inverter 2 3 4 . In addition, a switch 2 3 2 is connected across the input Va of the inverter 2 3 4 and the output OUT. During pre-charging, the pre-charge signal is "丨π, which controls the transistor 2 L.6 to turn off, and cuts off the current mirror of the current mirror 2 0 2 mirror terminal transistor 2 〇 5. In addition, the pre-charge signal The transistor 2 2 〇 is turned on via the inverter 2 18 , and the sensing node 2 24 is charged to a pre-charge voltage via the transistor 2 2 2 . The switch 2 3 2 is also controlled by the pre-charge signal as “factory,” And turned on, the capacitor 22δ thus stores the charge 0

第7頁 1283412 五、發明說明（4) 在預充電之後的感測期間，電晶體21 6受控於預充電 信號為” 0”而導通，信號BIAS與GN使得電晶體2〇4、20^ 2 1 2、2 1 4導通’ β己憶體2 0 0中所儲存的資料經由感測節點 2 2 4使電容2 2 8上產生電荷變化。當所感測的資料 為"1"時，電容2 2 8上的電荷變化量很小，無法使得後級 反相器2 3 4轉態；而當資料為”〇”時，電容2 2 8上的電荷^ 化ϊ較大’足夠使反相器2 3 4轉態，因此，此電路是夢= 電荷轉移的變化量來讀取記憶體2 〇 〇内部資料。 曰 圖3所示係圖1電路之:第二實施例，其與圖2之電路 同，但是判斷電路使用比較器3 3 4。比較器334呈 入330與一正輸入3 3 8，負輸入33〇連接至電容3 2 8，正輪， 3 3 8連接至一參考信號Vref ，一開關3 3 2跨接在比 之負輸入3 3 0與輸出0UT之間。在此實施列中，參考^號 'ef輸人一電壓至比較器3 34之正輪人3 3 8。在預充 間，開關3 3 2受預充電信號‘制導通造成比較哭之间 授，負輸人端33〇與正輪入端338虛短成車相等負回 期間，開關332受預充雷俨麥妒制齡叫電位相寺在感測Page 7 1283412 V. INSTRUCTIONS (4) During sensing after pre-charging, the transistor 21 is controlled to be turned on by the pre-charge signal being "0", and the signals BIAS and GN are made to make the transistors 2〇4, 20^ 2 1 2, 2 1 4 Turn on the data stored in the β-resonance 2 0 0 to cause a charge change on the capacitor 2 2 8 via the sense node 2 2 4 . When the sensed data is "1", the amount of charge change on the capacitor 2 2 8 is too small to make the post-stage inverter 2 3 4 transition; and when the data is "〇", the capacitor 2 2 8 The charge on the larger ^ is larger enough to make the inverter 2 3 4 transition state, therefore, this circuit is the amount of change of the memory = charge transfer to read the internal data of the memory 2 。.曰 Figure 3 shows the circuit of Figure 1: The second embodiment is identical to the circuit of Figure 2, but the decision circuit uses a comparator 343. Comparator 334 is input 330 and a positive input 3 3 8, negative input 33 〇 is connected to capacitor 3 2 8, positive wheel, 3 3 8 is connected to a reference signal Vref, and a switch 3 3 2 is connected across the negative input Between 3 3 0 and output 0UT. In this implementation column, reference to the ^ number 'ef input a voltage to the positive wheel 3 3 8 of the comparator 3 34. During the pre-charging, the switch 3 3 2 is pre-charged by the pre-charge signal, and the negative input terminal 33〇 is equal to the positive wheel-in terminal 338, and the switch 332 is pre-charged. Buckwheat 妒 age is called potential phase temple in sensing

^^3 3 0 〇 ^ ^ I Ιξ ΐ f !J ^ ^ 5 ^ # ^ ^ I 、文e电何茭化，立即反應於 雜訊容忍度較圖2的電路高。 、輸出OUT。此電路的 -圖4為本發明之/另一竑，， 測節點424及電荷儲存元件* 二充電電路42◦气接·至感 另一電荷儲存元件43 8以 7儲存兀件428連接至 438連接至開關44〇，開關44^=434，電荷儲存元件 參考㈣。，開關432跨接在。電=^^3 3 0 〇 ^ ^ I Ιξ ΐ f !J ^ ^ 5 ^ # ^ ^ I, Wen e, and immediately respond to the noise tolerance is higher than the circuit of Figure 2. And output OUT. 4 of the present invention, the node 424 and the charge storage element * the second charging circuit 42 are connected to the other charge storage element 43 8 and connected to the 438 by the storage element 428. Connected to switch 44A, switch 44^=434, charge storage element reference (4). The switch 432 is connected across. Electricity =

1283412 五、發明說明（5) . " — 〜——：-— OUT之間。 預充電電路4 2 0及開關43 2受控於預 …:電期間，該預充電信號押制預充雷雷L就在預充 通，使該預充雷雷攸ϋ 電畫◦以及開關4 3 2導 壓。當此電路切換到感測模式後，預 J 、充电電 用，且開關4 3 2開路，作缺βΤΑς缺座丨φ曰％路4 2 0不再作 'g , ^ ^ΓΜ L 號B 1 AS t 制電日日體4 0 4 與4 0 6 蓬 ^ “號GN控制電晶體4 1 2與4 1 4導通，在士己产陆 410中所儲存之資料經由電流鏡4 0 2比較表考J二二陣列 感測節點424產生電壓變化。該電壓變化值考二列= 兀件4 2 8及4 3 8會立即呈境在判斷電路輸入端^ 何^存 斷電路4 3 4判斷後輪出其資料。 柒Va丄，再由判 在預充電與感測資料期間， ^ 儲存元件4 2 8與4 3 8儲存之總電荷量唯 旦所理使電荷 荷儲存元件、持一定比值，心；= 只要電 出。 使τ μ利用判斷電路將資料快速輸 為具一比例之兩個電容體館存元件52j及538 接電源電壓Vdd至感測節點524 :巧广二.於預充電信號連 528 -，電容5 2 8連接£電即容=4以及感點5 2 4連” 接至開關5 4 0，以受控連接至接妯^益5 34，電今5 3 8連 反相器5 34之輸心4;0=也間“『^^^ 電晶體5 2 0及開關5 3 2受控於預充 間，該預充電信號控制電晶妒5 ? nL .儿在預充電』 电日日體5 2 〇以及開關5 3 2導通，使電1283412 V. Description of invention (5) . " — ~——:-- between OUT. The pre-charging circuit 410 and the switch 43 2 are controlled by the pre-charge: the pre-charge signal is pre-charged, and the pre-charged thunderbolt and the switch 4 are controlled. 3 2 pressure guide. When this circuit is switched to the sensing mode, the pre-J, charging power, and the switch 4 3 2 open circuit, the lack of β ΤΑς 丨 丨 丨 曰 路 4 4 4 4 4 4 4 4 4 4 4 4 4 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再 不再AS t power generation day and body 4 0 4 and 4 0 6 蓬 ^ "No. GN control transistor 4 1 2 and 4 1 4 conduction, the data stored in the Shiji production land 410 via the current mirror 4 0 2 comparison table The test J 221 array sensing node 424 generates a voltage change. The voltage change value is tested in two columns = 兀 4 4 8 and 4 3 8 will be immediately presented at the input end of the judgment circuit ^ ^ ^ ^ ^ ^ 4 4 4 The rear wheel outputs its data. 柒Va丄, and then during the pre-charging and sensing data, ^ the total charge stored in the storage elements 4 2 8 and 4 3 8 is only responsible for the charge-load storage element, holding a certain ratio , heart; = as long as the electricity is out. Let τ μ use the judgment circuit to quickly convert the data into a two-capacity capacitor library component 52j and 538 connected to the power supply voltage Vdd to the sensing node 524: Qiao Guang II. Pre-charging Signal connection 528 -, capacitor 5 2 8 connection £ electricity capacity = 4 and sense point 5 2 4 connection" connected to switch 5 4 0, with controlled connection to the connection 益 ^ benefits 5 34, electricity today 5 3 8 even reverse The phase of the phaser 5 34 is 4; 0 = also "" ^ ^ ^ transistor 5 2 0 and switch 5 3 2 controlled by pre-charge, the pre-charge signal controls the transistor ? 5 ? nL. Charging 』Electric day body 5 2 〇 and switch 5 3 2 turn on, make electricity

1283412 五、發明說明（6) 晶體5 2 0將感測節點5 2 4充電至一預充電電壓。當此電路切 換到感測模式後，電晶體5 2 0停止作用，且開關5 3 2開路。 記憶體電路5 0 0在感測節點5 2 4之電壓變化值經由.電容5 2 8 及5 3 8會立即呈現在判斷電路輸入端V a上，再由判斷電路 5 3 4判斷後輸出其資料。 在此實施例中使用反相器5 3 4作為判斷電路，在不同 的實施列中，亦可使用比較器或其他類似的裝置。1283412 V. DESCRIPTION OF THE INVENTION (6) The crystal 520 charges the sense node 524 to a precharge voltage. When this circuit is switched to the sensing mode, the transistor 52 0 stops acting and the switch 5 3 2 opens. The voltage change value of the memory circuit 500 at the sensing node 524 is immediately presented at the input terminal Va of the determining circuit via the capacitors 5 2 8 and 5 3 8 , and then outputted by the determining circuit 543 data. In this embodiment, an inverter 534 is used as the judging circuit, and in different implementations, a comparator or the like can also be used.

以上對於本發明之較佳實施例所做的敘述係為闡明之 目的，而無意限定本發明精確地為所揭露的形式，基於以 上的教導或從本發明的實施例學習而作修改或變化是可能 的，實施例係為解說本發朋的原理以及讓熟習該項技術者 以各種實施例利用本發明在實際應用上而選擇及敘述，本 發明的技術思想企圖由以下的申請專利範圍及其均等來決 定。. ’ /The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the present invention. The embodiments are intended to illustrate the principles of the present invention and to enable those skilled in the art to use the present invention in various embodiments to select and describe the present invention. The technical idea of the present invention is intended to be Equal to decide. . /

第10頁 1283412 圖式簡單說明 對於熟習此項技藝之人士而言，從以下所做的詳細敘 述配合伴隨的圖示本發明將能夠更清楚地被了解，其上 述及其他目的及優點將會變得更明顯，.:其中： 圖1係根據本發明之第一實施例的示意圖； 圖2係圖1之裝置的第一實施例電路； 圖3係圖1之裝置的第二實施例電路； 圖4係根據本發明之第二實施例的示意圖； 圖5係圖4之裝置的一個實施例電路。 元件及其標號對照表 100 記憶體電路 102 電流鏡 104 MOS電晶體 106 MOS電晶體 108 參考陣列 110 記憶陣列 112 MOS電晶體 1 14 MOS;電晶體 120 預充電電路 1 24 _ 感測節點 / 128 電荷儲存元件 1 3 2 開關 134 判斷電路 200 記憶體電路</ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> <RTIgt; 1 is a schematic view of a first embodiment of the apparatus of FIG. 1; FIG. 3 is a circuit of a second embodiment of the apparatus of FIG. 1; Figure 4 is a schematic illustration of a second embodiment of the present invention; Figure 5 is an embodiment of an apparatus of the apparatus of Figure 4. Component and its label comparison table 100 Memory circuit 102 Current mirror 104 MOS transistor 106 MOS transistor 108 Reference array 110 Memory array 112 MOS transistor 1 14 MOS; transistor 120 Precharge circuit 1 24 _ sense node / 128 charge Storage element 1 3 2 switch 134 judgment circuit 200 memory circuit

第11頁Page 11

12834121283412

第12頁 圖式簡單說明 202 電流鏡 203 MOS電晶體 204 MOS電晶體 20 5 MOS電晶體 206 MOS電晶體 208 參考陣列 21 0 記憶陣列 212 MOS電晶體 214 MOS電晶體 21 6 MOS電晶體 218 反相器 220 MOS電晶體 222 MOS電晶體 224 感測節點 228 電容 232 開關 234 反相器 30 0 記憶體電路 31 6 MOS電晶體 311 反相器 320 MOS電晶體 322 MOS電晶體 324 感測節點 328 電容 1283412Page 12 Schematic description 202 Current mirror 203 MOS transistor 204 MOS transistor 20 5 MOS transistor 206 MOS transistor 208 Reference array 21 0 Memory array 212 MOS transistor 214 MOS transistor 21 6 MOS transistor 218 Inverted 220 MOS transistor 222 MOS transistor 224 sensing node 228 capacitor 232 switch 234 inverter 30 0 memory circuit 31 6 MOS transistor 311 inverter 320 MOS transistor 322 MOS transistor 324 sensing node 328 capacitor 1283412

第13頁 圖式簡單說明 330 V a節點 332 開關 334 比較器二 338 比較器參考電壓 400 記憶體電路 402 電流鏡 404 MOS電晶體 406 MOS電晶體 408 參考陣列 410 記憶陣列 412 MOS電晶體 414 MOS電晶體 420 預充電電路 424 感測節點 428 電荷儲存元件 432 開關 43 4 判斷電路 438 電荷儲存元件 440 開關 5 0 0 _ 記憶體電路/ 520 MOS電晶體 524 感測節點 528 電容 532 開關 1283412 圖式簡單說明 5 3 4 反相器 5 3 8 電容 5 40 開關 111 第14頁Page 13 Schematic description 330 V a node 332 switch 334 comparator two 338 comparator reference voltage 400 memory circuit 402 current mirror 404 MOS transistor 406 MOS transistor 408 reference array 410 memory array 412 MOS transistor 414 MOS Crystal 420 precharge circuit 424 sense node 428 charge storage element 432 switch 43 4 decision circuit 438 charge storage element 440 switch 5 0 0 _ memory circuit / 520 MOS transistor 524 sense node 528 capacitor 532 switch 1283412 5 3 4 Inverter 5 3 8 Capacitor 5 40 Switch 111 Page 14

Claims (1)

1283412 六、申請專利範圍 1 · 一種記憶體之高速感測電路，藉以在一感測期間 感測一感測節點上的電壓變化而決定該記憶體的儲存資 料，該感測電路包括： 一預充電電路，在該感測期間以前的預充電期間對該 感測節點充電至一預充電電壓； 一判斷電路，連接一輸入信號而在該感測期間因應該 輸入信號輸出一資料信號； 一電荷儲存元件，耦接在該感測節點及判斷電路的輸 入之間；以及； 一開關，連接在該判'斷電路之輸入與輸出之間，藉以 在該預充電期間旁通該判斷電路。 2 ·如申請專利範圍第1項之感測電路，其中該預充電 電壓小於電源電壓。 3 ·如申請專利範圍第1項之感測電路，其中該判斷電 路包括一反相器。 / 4 ·如申請專利範圍第1項之感測電路，其中該判斷電 路包括一比較器，以比較該輸入信號與一參考電壓，以決 定該資料信號。 5 · —種記憶體之高速感測電’路，藉以在一感測期間 感測一感測節點上爲電壓變化而決定該記憶體的儲,存~資 料，該感測電路包括： 一預充電電路，在該感測期間以前的預充電期間對該 感測節點充電至一預充電電壓； .一判斷電路，連接一輸入信號而在該感測期間因應該1283412 VI. Patent Application No. 1 · A high-speed sensing circuit for memory, which determines the stored data of the memory by sensing a voltage change on a sensing node during a sensing period, and the sensing circuit includes: a charging circuit, charging the sensing node to a pre-charging voltage during a pre-charging period during the sensing period; a determining circuit connecting an input signal and outputting a data signal according to the input signal during the sensing; a storage component coupled between the sensing node and the input of the determining circuit; and a switch coupled between the input and the output of the interrupting circuit to bypass the determining circuit during the precharging. 2. The sensing circuit of claim 1, wherein the precharge voltage is less than a power supply voltage. 3. The sensing circuit of claim 1, wherein the determining circuit comprises an inverter. The sensing circuit of claim 1, wherein the determining circuit includes a comparator for comparing the input signal with a reference voltage to determine the data signal. 5—— A high-speed sensing electric circuit of a memory, wherein a sensing voltage is determined during a sensing period to determine a voltage change of the sensing node, and the sensing circuit includes: a charging circuit that charges the sensing node to a pre-charge voltage during a pre-charging period during the sensing period; a determining circuit that connects an input signal during the sensing period 1283412 六、申請專利範圍 輸入信號輸出一資料信號； 一第一電荷儲存元件，耦接在該感測節點及判斷電路 的輸入之間；. 一第二電荷儲存元件，受控在該感測期間***該判斷 電路的輸入與一參考電壓之間，以從該第一電荷 儲存元件移轉一電荷量；以及 一開關，連接在該判斷電路之輸入與輸出之間，藉以 在該預充電期間旁通該判斷電路。 6 ·如申請專利範圍第5項之感測電路，其中該預充電 電壓小於電源電壓。 / 7 ·如申請專利範圍第5項之感測電路，其中該判斷電 路包括一反相器。 8 ·如申請專利範圍第5項之感測電路，其中該判斷電 路包括一比'較器，以比較該嫜入信號與一第二參考電壓， / 以決定該資料信號。 / 9 ·如申請專利範圍/第5項之感測電路，更包括第三開 關受控連接該參考電壓皇該第二電荷儲存元件。 1 0 · —種記憶體之高速感測方法，以從該記憶體之感 測節點感測該記憶體的儲存資料，該方法包括下列步驟： 連接-一電荷儲存元#至該感測節點； t 在預充電期間對該感測節點充電至預充電電壓； 在感測期間連接記憶陣列至該感測節點；以及 根據該電荷儲存元件產生的電壓變化決定一資料信 號01283412 6. The patent application range input signal outputs a data signal; a first charge storage element coupled between the sensing node and the input of the determining circuit; a second charge storage element controlled during the sensing period Inserting between the input of the determination circuit and a reference voltage to shift a charge amount from the first charge storage element; and a switch connected between the input and the output of the determination circuit, thereby being adjacent to the precharge period The circuit is judged. 6. The sensing circuit of claim 5, wherein the pre-charging voltage is less than a power supply voltage. / 7 - The sensing circuit of claim 5, wherein the determining circuit comprises an inverter. 8. The sensing circuit of claim 5, wherein the determining circuit comprises a comparator to compare the inrush signal with a second reference voltage to determine the data signal. / 9 · The sensing circuit of the patent application scope/the fifth item further includes a third switch controlled connection of the reference voltage to the second charge storage element. a high-speed sensing method for sensing memory of a memory from a sensing node of the memory, the method comprising the steps of: connecting a charge storage element # to the sensing node; t charging the sensing node to a pre-charge voltage during pre-charging; connecting the memory array to the sensing node during sensing; and determining a data signal based on a voltage change generated by the charge storage element % 16 I 1283412 六、申請專利範圍 1 1 ·如申請專利範圍第1 0項之方法，更包括在該感測 期間連接第二電荷儲存元件至該第一電荷儲存元件，以從 該第一電荷儲存元件移轉一電荷、.量。 1 2 ·如申請專利範圍第1 1項之方法，更包括連接一參 考電壓至該第二電荷儲存元件。% 16 I 1283412 VIII. Patent Application 1 1 · The method of claim 10, further comprising connecting a second charge storage element to the first charge storage element during the sensing to extract from the first charge The storage element transfers a charge, amount. 1 2 The method of claim 11, further comprising connecting a reference voltage to the second charge storage element. 第17頁Page 17