1282860 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種時間數位轉換裝置和方法，尤指一種 以脈寬減縮方式為基礎的時間數位轉換裝置和方法，特別 適合運用於計數微小之時間間隔。此外，本發明又關於一 種訊號抖動量測裝置及訊號抖動分析方法，尤指一種以該 時間數位轉換裝置為基礎之訊號抖動量測裝置及訊號抖動 分析方法，特別適合運用於高速訊號抖動之量測。 【先前技術】 時間數位轉換器（time-to-digital converter ; TDC)已廣泛 使用在許多領域，包括利用時域反射儀（time d〇main reflectometer)來量測訊號通道（signaipath)的反射條件、軍 事用途的雷達搜索、1C工業中利用半導體分析儀量測定時 關係（timing relation)、量測許多物理現象的精密儀器、雷 射測距儀、類比數位轉換器、量測微小時間差之計數器等 (counters for measUring tiny time differences)。一般時間數 位轉換器的設計方法有以下三種：（1)雙重斜率法 slope method):透過控制單一電容器之充放電電流，由該 電容器之充放電特性來決定此轉換器的增益比。然而因環 境而引起之電容值改變，將導致不穩定且造成增益過大、 轉換時間過長、回復時間過長等缺點。（2)時間振幅轉換法 (time-to-amplitiide conversion method):以一電流源對一電 容器充電，並利用充電電流的變化相對於電壓的變化關 係，將電壓轉換成數位訊號以獲得時間和數位訊號的關 1282860 係。此法的優點是轉換速度快，但其精準仍取決於電容器 的穩定性。（3)單位延遲緩衝法（unit delay buffer meth〇d): 複數個數位緩衝器串接時具有一定的時間延遲效果。當輸 入一特定脈衝時，於每個數位緩衝器的輸出可辨識出一微 小的時間差，利用此時間差可達成量測的目的。但此法不 僅電路複雜，而且在每個緩衝器可能發生的抖動（jitt^)而 • 影響量測的精確度。 ^ 抖動（jitter)係定義為訊號邊緣的位置對於其理想位置於 時間上偏移（deviation)，也常被稱為時序失真（timing distortion)。其係因熱、電磁雜訊、電路不穩或傳輸損失而 產生。對於資料傳送系統而言，抖動會造成資料傳輸的錯 誤，進而降低系統的整體可靠度。 抖動可以分為定量性抖動（deterministic jitter)和隨機抖 動（random jitter)。隨機抖動本質上是屬於高斯分佈 (Gaussian distributi〇n)，一 般係由熱雜訊（加啦“ n〇ise)、 • 散粒雜訊（shot noise)等因素造成。定量性抖動包含下列成 份：周期性抖動（Periodic Jitter ; PJ)、f料相關抖動⑺伽1282860 IX. Description of the Invention: [Technical Field] The present invention relates to a time-digital conversion device and method, and more particularly to a time-digital conversion device and method based on a pulse width reduction method, which is particularly suitable for use in counting small time interval. In addition, the present invention relates to a signal jitter measurement device and a signal jitter analysis method, and more particularly to a signal jitter measurement device and a signal jitter analysis method based on the time digital conversion device, which is particularly suitable for the application of high-speed signal jitter. Measurement. [Prior Art] Time-to-digital converters (TCCs) have been widely used in many fields, including measuring the reflection conditions of signalaipaths using a time d〇main reflectometer. Radar search for military use, timing relation using semiconductor analyzers in the 1C industry, precision instruments for measuring many physical phenomena, laser range finder, analog digital converter, counter for measuring small time difference, etc. Counters for measUring tiny time differences). The general time digital converter is designed in the following three ways: (1) Double slope method: By controlling the charge and discharge current of a single capacitor, the gain ratio of the converter is determined by the charge and discharge characteristics of the capacitor. However, changes in the capacitance caused by the environment will cause instability and cause excessive gain, long conversion time, and long recovery time. (2) Time-to-amplitiide conversion method: charging a capacitor with a current source, and converting the voltage into a digital signal by using a change in the charging current with respect to the voltage to obtain time and digits. The signal is off 1282600. The advantage of this method is that the conversion speed is fast, but its accuracy still depends on the stability of the capacitor. (3) unit delay buffer meth〇d: A plurality of digital buffers have a certain time delay effect when connected in series. When a specific pulse is input, the output of each digital buffer can recognize a small time difference, and the time difference can be used to achieve the purpose of measurement. However, this method is not only complicated, but also jitter that can occur in each buffer (jitt^) and affects the accuracy of the measurement. ^ Jitter is defined as the temporal offset of the position of the signal for its ideal position, also known as timing distortion. It is caused by heat, electromagnetic noise, circuit instability or transmission loss. For data transmission systems, jitter can cause errors in data transmission, which in turn reduces overall system reliability. Jitter can be divided into deterministic jitter and random jitter. Random jitter is essentially Gaussian distributi〇n, which is usually caused by factors such as thermal noise (“〇”), “shot noise”, etc. Quantitative jitter contains the following components: Periodic Jitter (PJ), f-related jitter (7) gamma
Dependent Jitter ; DDJ)、工作周期失真（Duty Cycie ' 以灿⑴011 ; DCD)等。就本質而言，周期性抖動通常為正弦 ' (SinUS〇idal)形式，資料相關抖動通常來自於系統的頻寬限 制之碼間干擾（Inter_Symb〇1 Interference ; isi)等讓資料改 文的口素而工作周期失真來自於差動訊號之間的電壓偏 移與系統上升、下降時間的差異。總抖動係定量性抖動與 隨機抖動的加總。 S39958 107364 005017439-2 1282860 -般常用來量測抖動之方式包括：眼狀圖（eye diagram) 和時間區段誤差統計圖（Time Interval Error ; TIE)，兩者皆 提供總抖動的相關訊息。其他的量測方式，如頻譜分析等， 則可對於不同的抖動成份提供更深入的了解。 參照圖1，一眼狀圖15係藉由偵測器所接收到的一連串脈 衝之升、降緣11覆寫在高速示波器上得到，即將各脈衝重 疊而成。眼狀圖因形狀類似眼睛而得名，較大的眼開（Eye Opening; EO)值代表傳輸品質良好。反之，「瞇眼」則表示 吼號品質很差。將眼狀圖之遮罩（mask)丨2與標準的眼狀圖 遮罩相比較’即可驗證和檢定訊號的品質。 TIE統計圖係統計實際上與理想上抖動發生時間的誤差 量，可以顯示出定量性抖動成份與隨機抖動造成的分散現 象。 然而，關於抖動的量測可能因為無法產生一理想之參考 訊號源，使得額外摻入之抖動量造成量測值放大的錯誤現 象，如圖2所示。另外抖動訊號之統計特性不易收斂，容易 造成量測失真。於硬體實現上，在高速訊號之設計和製造 的限制相當多，例如高速訊號經過反相器串列（inverter chain)時，因速度過快，經反相器反相後之訊號來不及反 應’造成傳輸訊號延遲並使得訊號無法辨識。因此，如何 在較低速的環境下準確地進行抖動量測之技術仍待突破。 【發明内容】 本發明之主要目的係提供一種時間數位轉換裝置和方 法，利用縮寬胞而非電容器充放電的方式，將具一脈寬之 S39958 107364 005017439-2 1282860 待測讯唬轉換成一二進位數字，以避免因電容器影響而產 生的轉換誤差。 本發明之另一目的係提出一種訊號抖動量測裝置，運用 該時間數位轉換裝置，將該訊號抖動由連續訊號量化成一 組數位訊號，該組數位訊號係表示該訊號之循環抖動 (cycle-to-cycle jitter)之時間寬度。 本發明之又一目的係提出一種訊號抖動分析Dependent Jitter; DDJ), duty cycle distortion (Duty Cycie 'can (1) 011; DCD). In essence, periodic jitter is usually in the form of SinUS〇idal, and data-dependent jitter usually comes from the inter-symbol interference (Inter_Symb〇1 Interference; isi) of the system's bandwidth limitation. The duty cycle distortion comes from the difference between the voltage offset between the differential signals and the rise and fall times of the system. Total jitter is the sum of quantitative jitter and random jitter. S39958 107364 005017439-2 1282860 - Commonly used methods for measuring jitter include: eye diagram and Time Interval Error (TIE), both of which provide information about total jitter. Other measurement methods, such as spectrum analysis, provide a deeper understanding of the different jitter components. Referring to Fig. 1, an eye pattern 15 is obtained by overwriting a rising and falling edge 11 of a series of pulses received by a detector on a high speed oscilloscope, that is, by overlapping the pulses. The eye diagram is named for its shape resembling the eye, and the larger Eye Opening (EO) value indicates good transmission quality. Conversely, "Blinking" means that the quality of the nickname is very poor. The quality of the signal can be verified and verified by comparing the mask of the eye diagram 丨2 with the standard eye mask. The amount of error between the TIE chart system and the ideal jitter occurrence time can show the dispersion of quantitative jitter components and random jitter. However, the measurement of jitter may be due to the inability to generate an ideal reference source, such that the amount of jitter that is additionally incorporated causes an error in the amplification of the measurement, as shown in Figure 2. In addition, the statistical characteristics of the jitter signal are not easy to converge, which is easy to cause measurement distortion. In hardware implementation, there are quite a few restrictions on the design and manufacture of high-speed signals. For example, when a high-speed signal passes through an inverter chain, the speed is too fast, and the signal after being inverted by the inverter is too late to react. This causes the transmission signal to be delayed and the signal to be unrecognizable. Therefore, the technology for accurately performing jitter measurement in a lower speed environment remains to be broken. SUMMARY OF THE INVENTION The main object of the present invention is to provide a time-to-digital conversion device and method for converting a signal width of a S59958 107364 005017439-2 1282860 signal into a signal by means of a widened cell instead of a capacitor charge and discharge. Binary digits to avoid conversion errors due to capacitor effects. Another object of the present invention is to provide a signal jitter measuring device, which uses the time digital conversion device to quantize the signal jitter into a set of digital signals by a continuous signal, and the set of digital signals represents the cyclic jitter of the signal (cycle-to -cycle jitter) The time width. Another object of the present invention is to provide a signal jitter analysis
直接分析一待測訊號之脈寬流而非其抖動訊號，來降低因 脈寬縮減單元或可調整脈寬縮減單元所引起的誤差訊號。 為達到上述目的，本發明揭示一種時間數位轉換裝置， 其！要包括一縮寬胞群、-縮寬閂鎖胞群。該縮寬胞群包 3複數個縮見胞且該等縮寬胞依序串接成複數級縮寬胞。 該縮寬胞群係用以接收具-脈寬之-待測訊號，使該待測 訊號經該等每縮寬胞後，該脈寬長度縮減—解析量，直到 該脈寬長度無法驅動下一級之縮寬胞為止，且每該等縮寬 胞均產生-第-數位輪出碼。該縮寬閃鎖胞群包含與該縮 寬胞相同數目之縮寬閂鎖胞，每縮寬閂鎖胞與每縮寬胞一 一相互對賴列，心接㈣第—數輯出碼並進行問鎖 以產生一第二數位輸出碼。爷兮 、 ^ w專弟一數位輸出碼係以溫 度汴編碼（thermometer c〇de)方式表示。 該：二數位輸出碼可經一優先編碼器及一輸出閃鎖單元 ::理；亥：先編碼器係用來將該等第二數位輸出碼編 -成一-進位數字，該輪出閃鎖單元則 字並接受與該時脈訊號同步之一 子-一進位數 觸毛成號後輸出該二進位 S39958 x〇7364 005017439-2 1282860 數字。 就貝施方法而a，其主要可分為以下步驟··⑴將一待测 訊號之脈寬依序延遲一解析量以產生複數個第一數位輸出 碼；⑺將該複數個第—數位輸出碼進行閃鎖處理以產生複 數個第二數讀出碼；以及（3)將該複數個第二數位輸出瑪 轉換為以二進位數字表示的第三數位輸出碼。 本發明之訊號抖動量測裝置之第—實施例係配合一第— 時脈訊號運作，用以將與該第一時脈訊號同步且具一第一 脈寬之-第-測待訊號轉換為—二進位數字。該訊號抖動 量測裝置包含：一輸入控制器’用以將該第-時脈訊號之 頻率降低一奇數倍而成一第二時脈訊號及產生一鱼該第二 時脈訊號具-時間延遲之—第三時脈訊號；—取樣保㈣ 路’係配合該第三時脈訊號之高低位準，用以將該第—待 測訊號轉換成具-第二脈寬之—第二待測訊號；—脈寬調 變單元’係配合-邊界偵測閥值將該第二待測訊號轉換成 具-第三脈寬之-第三待測訊號；一脈寬縮減單元，用以 將該第三待測訊號之該第三脈寬縮減成具一第四脈寬之一 第四待測訊號；一時間數位轉換裝置，用以將該第四待測 訊號轉換成至少-第二數位輸出㉟；以及—閃鎖㈣器， 係用以I生一#出重置訊號至該時間數位轉換袭置中之縮 寬閂鎖胞以清除該縮寬閂鎖胞之内容。 本發明之訊號抖動量測裴置之第二實施例係直接將一第 一待測訊號轉換為一二進位數字而不需配合任何時脈訊 號。該訊號抖動量測裝置包含··一輸入控制器，用以將一 S39958 107364 〇〇5〇17439-2 1282860 帛—待測訊號轉換成—取樣保持控制訊號；-取樣保持電 路’係配合該取樣保持控制訊號’將該第一待測訊號轉換 成具一第二脈寬之一第二待測訊號；一脈寬調變單元，係 2 口一邊界谓測閥值將該第二待測訊號轉換成具—第三脈 . 見之一第二待測訊號；一可調整脈寬縮減單元，用以將該 第三待測訊號之該第三脈寬縮減成具一第四脈寬之一第四 . ㈣訊號；-時間數位轉換裝置，用以將該第四待測訊號 Φ 轉換成至夕帛一數位輸出碼；以及一閃鎖控制器，係接 收來自該可調整脈寬縮減軍元之一第一㈣訊號以產生一 輸出重置訊號至該時間數位轉換裝置中之縮宽閃鎖胞以清 除该縮寬問鎖胞之内容。 為降低因脈寬縮減單元或可調整脈寬縮減單元所引起的 誤差訊號，本發明揭示一種訊號抖動分析方法其包含以下 γ驟（1 )&供一具一脈寬流之待測訊號及一具一理想脈寬 之理想訊號；（2)計算該脈寬流之標準差；以及（3)根據該脈 _ 寬流之標準差，計算該待測訊號之隨機抖動流之標準差。 【實施方式】 圖3為本發明所揭示的一種時間數位轉換裝置丨，主要包 * 含一縮寬胞群10及一縮寬閂鎖胞群20。該縮寬胞群1〇包含 • 至少一縮寬胞1〇i(i為1至η之正整數）且該等縮寬胞1〇i依序 串接形成複數級。該縮寬胞群丨〇係用以接收具一脈寬w之一 待測訊號aG。該待測訊號a()經每一縮寬胞丨，其脈寬長度 縮減一解析量r，即經一縮寬胞l〇i後其脈寬長度為w_r，經 二縮寬胞l〇i後其脈寬長度為〜_21·，依此類推直到該脈寬長 S39958 107364 〇〇5〇17439-2 -10- 1282860Directly analyze the pulse width of a signal to be measured instead of its jitter signal to reduce the error signal caused by the pulse width reduction unit or the adjustable pulse width reduction unit. In order to achieve the above object, the present invention discloses a time digital conversion device, which is! It should include a widened cell population, and a narrowed latch cell population. The constricted cell packet 3 has a plurality of constricted cells and the constricted cells are sequentially connected in series to a plurality of constricted cells. The convoluted cell group is configured to receive a signal-to-measurement signal having a pulse width, such that the pulse width is reduced by the amount of the pulse width after the signal to be measured, until the pulse width length cannot be driven. The first-order rounding is wide, and each of the narrowed cells produces a --digit rounding code. The narrowed flash lock cell group includes the same number of widened latch cells as the widened cells, and each of the widened latch cells and each of the widened cells are aligned with each other, and the heart is connected to the (four) first-numbered code and A challenge lock is performed to generate a second digit output code. The digital output code of the grandfather and ^w specializes is expressed by the temperature meter (汴mometer c〇de). The two-digit output code can pass through a priority encoder and an output flash lock unit::; the first: the encoder is used to encode the second digit output code into a one-digit number, the round flash lock The unit is word and accepts one of the sub-digits synchronized with the clock signal to output the binary S39958 x〇7364 005017439-2 1282860 number. For the Besch method, a can be mainly divided into the following steps: (1) sequentially delaying the pulse width of a signal to be tested by a resolution amount to generate a plurality of first digit output codes; (7) outputting the plurality of first digits The code performs a flash lock process to generate a plurality of second number read codes; and (3) converts the plurality of second digital output codes into a third digital output code represented by a binary number. The first embodiment of the signal jitter measuring device of the present invention cooperates with a first clock signal to convert a first-to-first signal having a first pulse width synchronized with the first clock signal into - binary digits. The signal jitter measuring device includes: an input controller' for reducing the frequency of the first-clock signal by an odd multiple to form a second clock signal and generating a second clock signal with a time delay - the third clock signal; - the sampling guarantee (four) road 'matching the high and low levels of the third clock signal, for converting the first - to-be-measured signal into a - second pulse width - the second to be tested a pulse width modulation unit' is configured to convert the second signal to be tested into a third to be measured signal having a third pulse width; a pulse width reduction unit for The third pulse width of the third signal to be tested is reduced to a fourth signal to be tested having a fourth pulse width; a time digital conversion device for converting the fourth signal to be tested into at least a second digital output 35; and - the flash lock (four) device, is used to generate a reset signal to the time-scale conversion of the narrowed latch cell to clear the contents of the reduced latch cell. The second embodiment of the signal jitter measurement device of the present invention directly converts a first signal to be tested into a binary number without any clock signal. The signal jitter measuring device comprises: an input controller for converting a S39958 107364 〇〇 5 〇 17439-2 1282860 待 - signal to be tested into a - sample hold control signal; - a sample hold circuit is coupled with the sample Maintaining the control signal 'converting the first signal to be tested into a second signal to be tested having a second pulse width; a pulse width modulation unit, the boundary value threshold of the port 2, the second signal to be tested Converting into a third pulse. See one of the second signals to be tested; an adjustable pulse width reduction unit for reducing the third pulse width of the third signal to be tested to have a fourth pulse width Fourth, (4) a signal; a time digital conversion device for converting the fourth signal to be tested Φ into a digital output code; and a flash lock controller for receiving the adjustable pulse width reduction A first (four) signal is generated to generate an output reset signal to the widened flash lock cell in the time digit conversion device to clear the content of the narrowed lock cell. In order to reduce the error signal caused by the pulse width reduction unit or the adjustable pulse width reduction unit, the present invention discloses a signal jitter analysis method, which includes the following γ (1) & for a signal to be measured with a pulse width and An ideal signal having an ideal pulse width; (2) calculating a standard deviation of the pulse width stream; and (3) calculating a standard deviation of the random jitter stream of the signal to be tested according to the standard deviation of the pulse width. [Embodiment] FIG. 3 is a time digital conversion device disclosed in the present invention. The main package includes a constricted cell group 10 and a convoluted latch cell group 20. The constricted cell group 1 includes at least one constricted cell 1〇i (i is a positive integer from 1 to η) and the convoluted cells 1〇i are sequentially connected in series to form a complex level. The convoluted cell is used to receive a signal aG having a pulse width w. The signal to be tested a() is reduced by a resolution amount r by each narrowed cell, that is, the pulse width length is w_r after a widened cell l〇i, and the width of the cell is narrowed. After the pulse width is _21·, and so on until the pulse width is S39958 107364 〇〇5〇17439-2 -10- 1282860
度無法驅動下一級之縮寬胞1〇i+i為止。每縮寬胞1〇〖均產生 一第一數位輸出碼ai(i為1至!!之正整數），並作為下一級縮 寬胞l〇i+1之輸入。該等第一數位輸出碼〜可為1(高準位）或 〇(低準位）。該縮m鎖胞群2G包含與該等縮寬胞^相同數 目之縮寬問鎖胞20i(i為in之正整數n)，每一縮寬閃鎖胞 2〇i與每-縮寬胞1(M系相互對應排列，且接受該第一數位輸 出碼心以產生-第二數位輸出碼bi(iW至n之正整數）。該縮 寬閃鎖胞2哺收來自相對應之該第一數位輸出碼〜後，依 該第-數位輸出碼ai之高、低位準，該縮寬閃鎖胞冰即輸 出一與該第-數位輸出碼以目同位準之該第二數位輸出碼 bi。該等縮寬閃鎖胞2〇i以複數抑型正反器為實施例時，該 複數個正反器的輸入埠D連接—電源\，該複數個正反哭 的時脈輸入埠（CLK)連接相對應的該等第—數位輸出； 〜。此時健存在該等縮寬閃鎖胞叫之該等第二數位輸出碼 bi係以溫度計編碼（therm()meter eGde)的方式儲存。在使用 該縮寬㈣胞群20之前，先連接與該時脈訊制步之一輸 出重置訊號Reset至該複數個正反器的清除埠（clr卜將該 複數個正反器之内容清除。 X 圖4為說明該縮寬胞1〇i之電路示意圖，其中之正 :數。該縮寬胞關用來將具—脈寬*之訊號縮減該解析 ^ 第互補式金氧半導體（CMOS)反相器 ，’係用以接收一輸入訊號a…並產生一中間訊號 :弟二互補式金氧半導體反相器受該中間訊 號a丨並產生一輸出訊號a，該輸出 出汛號…即為下一級縮寬胞 1282860 i〇i+1之輸入訊號；以及一調整單元1〇1。，係用以接收該中間 訊號a’i和該輪出訊號ai並接收一控制訊號Vc來調整該解析 里r之大小。對第一級縮寬胞丨〇1而言，其輸入訊號即為該待 測汛號aG。該調整單元1 〇ie包含一 p型金氧半導體元件 PM〇S2及一N型金氧半導體元件NMOS2。該P型金氧半導體 兀件PMOS2係利用一第一端點1〇ici接收該輸出訊號…，利 • 用一第二端點10心2連接該電源vdd，利用一第三端點1〇ic 3 籲 接收該中間訊號吣。該N型金氧半導體元件NM〇S2係利用 一第四端點ioic_4連接該第一端點1〇ie i且接收該輸出訊號 a,，利用一第五端點1〇ic_5連接該第三端點1〇心3且接收該中 間訊號a，i，利用一第六端點1〇^6以接受該控制訊號、。該 輸入訊號與該輸出訊號…之關係，請參照圖$。 圖5虎明忒待測訊號a〇連續經由複數個該等縮寬胞1 ^ 時，其脈寬由w逐次縮減解析量1<之時序示意圖。需注意的 是，a!、k、&···等訊號之脈寬雖逐次縮減^，但其位準還 • 是保持在高準位，直到該脈寬長度無法驅動下一級縮寬胞 為止。 圖6(a) A明該控制訊號Vc與該解析量『之關係。其中、 TT及FF表示4等縮寬胞1〇i在三種不同的製程條件下所得 • A的三條關係曲線。就單一曲線而t，在運用時可藉由改 變该控制訊號Vc之大小調整該解析量r之大小。就多條曲線 (圖6僅以三條曲線為例）而言，可藉由改變該控制訊號^之 大小來排除因製程變異所造成該解析量r之變異。又本實施 例中該控偶號〜之較㈣整範圍齡敎44〜g.8伏特，而 S39958 107364 005017439-2 -12- 1282860 f相對之較佳解析量r之調整範圍係介於2〇χΐ(Γΐ2 〜70χ1(Γ12 斤為肖b得更精確（更小）之解析量r，在設計縮寬胞⑺〗時 (復多圖4) ’可選擇相對於PMOS1、PMOS3、NMOS1及 NMOS3具較小尺寸（即較小之最小線寬㈣―咖㈣） MOS2及NMOS2。圖6(b)即顯示具較精確（小於1〇微微秒） 解析里r與控制讯號Vc之關係，其中該控制訊號％之較佳The degree cannot be driven until the next level of the widened cell 1〇i+i. Each of the wide cells 1 产生 produces a first digit output code ai (i is a positive integer from 1 to !!) and serves as the input to the next level of the narrow cell l〇i+1. The first digit output code ~ can be 1 (high level) or 〇 (low level). The reduced-locked cell group 2G includes the same number of narrowed cells 20i (i is a positive integer n of in), and each of the reduced flash cells 2〇i and each-widened cell 1 (M lines are arranged corresponding to each other, and the first digital output code center is accepted to generate - the second digital output code bi (iW to n is a positive integer). The narrowed flash lock cell 2 is fed from the corresponding one After the digital output code 〜, according to the high-level and low-level output of the first-digit output code ai, the reduced-flash icy cell ice outputs a second digital output code bi which is identical to the first-digit output code. When the narrowed flash lock cell 2〇i is a multi-reactor type flip-flop as an embodiment, the input of the plurality of flip-flops is connected to the power source, and the plurality of positive and negative crying clock inputs are ( CLK) is connected to the corresponding first-digit output; ~. At this time, there is such a narrowed flash-lock cell called the second-digit output code bi is stored by thermometer code (therm()meter eGde) Before using the narrowed (four) cell group 20, first connect and output a reset signal Reset to one of the plurality of flip-flops to the clearing of the plurality of flip-flops (clr The contents of the plurality of flip-flops are cleared. X Figure 4 is a schematic diagram showing the circuit of the widened cell 1〇i, where the positive: number. The narrowed cell is used to reduce the signal with the pulse width * by the resolution ^ A complementary complementary metal oxide semiconductor (CMOS) inverter for receiving an input signal a... and generating an intermediate signal: the second complementary CMOS inverter receives the intermediate signal a and generates an output signal a, the output apostrophe... is the input signal of the next level of the widened cell 1282860 i〇i+1; and an adjustment unit 1〇1 is used to receive the intermediate signal a'i and the round signal ai And receiving a control signal Vc to adjust the size of r in the parsing. For the first-stage widened cell 1, the input signal is the apostrophe aG. The adjusting unit 1 〇ie includes a p-type a MOS device PM 〇 S2 and an N-type MOS device NMOS 2. The P-type MOS device PMOS 2 receives the output signal by using a first terminal 1 〇 ici, and uses a second terminal 10 heart 2 is connected to the power source vdd, and the third terminal 1 〇ic 3 is used to receive the intermediate signal 吣. The MOS device NM〇S2 is connected to the first terminal 1〇ie i by a fourth terminal ioic_4 and receives the output signal a, and is connected to the third terminal 1 by using a fifth terminal 1〇ic_5. The heart 3 receives the intermediate signal a, i, and uses a sixth endpoint 1 〇 ^ 6 to accept the control signal. The relationship between the input signal and the output signal is shown in Figure 5. Figure 5 When the signal to be measured a continuously passes through the plurality of such widened cells 1 ^, the pulse width thereof is successively reduced by w from the resolution amount 1 < time series diagram. It should be noted that signals such as a!, k, & Although the pulse width is reduced by ^, the level is still kept at a high level until the pulse width length cannot drive the next level of shrinkage. Fig. 6(a) A shows the relationship between the control signal Vc and the amount of analysis. Among them, TT and FF represent the three relationship curves of the four equalized cells 1〇i obtained under three different process conditions. In the case of a single curve and t, the magnitude of the analysis amount r can be adjusted by changing the size of the control signal Vc during operation. For a plurality of curves (for example, only three curves are taken as an example), the variation of the analytic quantity r caused by the process variation can be eliminated by changing the size of the control signal ^. In this embodiment, the control number is compared with (4) the entire range of ages 敎 44 to g. 8 volts, and the adjustment range of the preferred sizing amount r of S39958 107364 005017439-2 -12 - 1282860 f is between 2〇. Χΐ(Γΐ2 ～70χ1 (Γ12 斤 is the more accurate (smaller) resolution r of Xiaob, when designing the widened cell (7)〗 (multiple Figure 4) 'Selectable with respect to PMOS1, PMOS3, NMOS1 and NMOS3 Smaller size (ie smaller minimum line width (four) - coffee (four)) MOS2 and NMOS2. Figure 6 (b) shows a more accurate (less than 1 〇 picosecond) resolution r and control signal Vc, where Control signal % is better
調整範圍係介於G.34〜G.94伏特，而其相對之較佳解析量犷 之調整範圍係介於3xl〇-12〜26x10-丨2秒。 “、、圖7 »亥第_數位輸出碼bi係經由一優先編碼器和 一輸出問鎖單元50進行處理。該優先編碼器40係用以將儲 存在該等縮寬問鎖胞20i之該等第二數位輸出碼哺換成至 少-個第三數位輸出碼正整數），其中^為最 低有效位7G值（Least Signifieant Bit ; 為最高有效The adjustment range is between G.34 and G.94 volts, and the relative resolution of the better 犷 is between 3xl〇-12~26x10-丨2 seconds. ",, Fig. 7»Hai_digital output code bi is processed by a priority encoder and an output challenge unit 50. The priority encoder 40 is used to store the pinned cells 20i. Wait for the second digit output code to be fed into at least a third digit output code positive integer), where ^ is the least significant digit 7G value (Least Signifieant Bit; is the most effective
位το值（Most Significant Bh ;聰），因此該等第三數位輸 出碼〜可代表—二進位數字。該輸計 1鎖單元50包係用來儲 存該等第三數位輪出碼^，並在接收—觸發訊號响之後輸 出該第三數位輸出碼ej(二進位數字）。該觸發訊號响係由 一閂鎖控制器55(請參圖9)產生。 復參圖2,其係顯示習知之訊號抖動量財法。—高速資 料訊號頻率為f’_頻率同為f之第一時脈訊號咖係= 以進行該資料訊號A之抖動量測。若咖在高速時欲達到誤 差小於2微微秒（ps)之高準確性，其常必須仰賴如♦錯等特 殊製程。細係以目前之石夕製程產生，其本身於高速時 極可能因發生抖動而與資料訊號A之抖動形成如圖2之虛線 S39958 107364 0〇5〇17439-2 • 13 - !282860 框所示之抖動重疊（jitter aliasing)現象，而大幅降低抖動量 測之準確性。 參照圖8(a)，利用一頻率為f/3之較低頻率之第三時脈訊 就clk3針對頻率為f之第一待測訊號(1以&1進行抖動量測。其 類似一照相（photography)技術，藉由cik3之高位準訊號部分 涵盍第一待測訊號datal之升、降緣，如此可免除上述抖動 重疊之問題發生。其中該第三時脈訊號clk3可由圖8(b)所示 之一實施例之輸入控制器54藉該第一時脈訊號clkl轉換為 弟一時脈訊號clk2，再經控制器54中之一 D型正反器542產 生時間延遲而得。 以下詳述本發明之一種運用該時間數位轉換裝置1之訊 號抖動量測裝置。 圖9為本發明所揭示之一種訊號抖動量測裝置5之第一實 施例之系統方塊圖，其係利用前述之時間數位轉換裝置1 和輸入控制器54來達成計算該訊號之循環抖動的功能。一 第一時脈訊號clkl進入該輸入控制器54後，該輸入控制器 54將該第一時脈訊號clkl之頻率降低一奇數倍k(本實施例 k-3)而成一弟一時脈訊號cik2，並進而產生一與cik2同頻率 且具一時間延遲之一第三時脈訊號clk3(參圖8(a))。一第一 待測訊號datal進入一取樣保持電路51後，配合clk3之高低 位準，將datal轉換成具一脈寬〜2之一第二待測訊號data2。 圖10(a)揭示一取樣保持電路51，係利用datal&clk3為其輸 入訊號用以產生一第二待測訊號data2。在該取樣保持電路 51之較佳之實施例中，反相器a之尺寸大小較反相器b大， S39958 107364 005017439-2 -14 - 1282860 以增進運作時之穩定性。該取樣保持電路5〖之作用方式描 述如下·當clk3為咼位準時，該取樣保持電路5丨之輸出訊 號（即為data2)即相當於datal。當clk3為低位準時，該取樣 保持電路51之輸出訊號係保持當時4“心之位準。圖1〇(b) 為clkl、Clk2、clk3、datal及data2各訊號之時序圖。 當數位訊號之高低位準切換時並非為單純之切換（參照 圖11 (a))，實際上資料訊號由”〇”至”丨”（或由”丨，，至"〇π)，係如 圖11(b)所示之圖形（圖11(a)之”Μ”部位放大圖），而其變化 之斜率將影響到其相應眼狀圖的脈衝升、降緣丨丨之斜率， 也會影響循環抖動之大小。一般電壓由” 〇 ”至"丨，，或由”丨"至 π〇"之取樣點可設於高、低邊界偵測閥值（b〇undary detecti〇n threshold)511 及 512。 取樣保持電路51之輸出訊號data2先經由一脈寬調變單 元52之處理而產生具一第三脈寬w3之一第三待測訊號 data3 〇 圖12(a)、12(b)係脈寬調變單元52之兩種實施例。圖12(a) 之電路係採咼邊界偵測閥值5 11等於電源乂心電壓值大小之 百分之九十的設計，而圖12(b)之電路係採低邊界偵測閥值 512等於電源Vdd電壓值大小之百分之十的設計。一般邊界 偵測閥值511、512之設定常分別大於電源Vdd電壓值之8〇% 及小於電源Vdd電壓值之20%。比較兩種電路設計之訊號時 序圖，可知同樣的訊號si輸入，以後者所得到之輸出值S4 之脈寬較寬。 一般我們所要量測的訊號抖動大小為微微秒（i 〇-12秒）等 S39958 107364 005017439-2 -15- 1282860 級’且訊號抖動之資訊乃存在訊號之升、降緣，因此利用 一脈寬縮減單元53將來自脈寬調變單元52之輸出訊號（即 為data3)之脈寬縮減成具一第四脈寬w4之一第四待測訊號 data4 ’其中data4只保留含有訊號抖動資訊之脈寬。圖13(a) 為脈見縮減單元5 3之一實施例。該脈寬縮減單元5 3由偶數 個反相器依序串接用以產生一與data3具一時間延遲之訊號Bit το value (Most Significant Bh; Satoshi), so these third digit output codes ~ can represent - binary digits. The load unit 1 lock unit 50 is configured to store the third digit rounds of codes ^ and output the third digit output code ej (binary digits) after the receive-trigger signal. The trigger signal is generated by a latch controller 55 (see Figure 9). Referring to Figure 2, it shows a conventional signal jitter amount method. - The high-speed data signal frequency is f'_the first clock signal with the frequency f is the same as the jitter measurement of the data signal A. If the coffee is to achieve a high accuracy of less than 2 picoseconds (ps) at high speeds, it must often rely on special processes such as ♦ error. The fine system is produced by the current Shixi process, and it is very likely to form a jitter with the data signal A due to the occurrence of jitter at high speed as shown by the dotted line in Figure 2, S39958 107364 0〇5〇17439-2 • 13 - !282860 The jitter aliasing phenomenon greatly reduces the accuracy of jitter measurement. Referring to FIG. 8(a), a third time pulse with a lower frequency of f/3 is used for clk3 for the first signal to be measured with frequency f (1 is jitter measurement with & 1. The photography technology, by the high-level signal part of cik3, covers the rise and fall of the first signal to be tested, and thus avoids the problem of the above-mentioned jitter overlap. The third clock signal clk3 can be obtained from Figure 8 ( b) The input controller 54 of one embodiment shown is converted into the clock signal clk2 by the first clock signal clk1, and then generated by a time delay of one of the D-type flip-flops 542 of the controller 54. DETAILED DESCRIPTION OF THE INVENTION A signal jitter measurement device using the time digital conversion device 1 of the present invention is illustrated in detail. FIG. 9 is a system block diagram of a first embodiment of a signal jitter measurement device 5 according to the present invention. The time digital conversion device 1 and the input controller 54 achieve a function of calculating the cyclic jitter of the signal. After the first clock signal clk1 enters the input controller 54, the input controller 54 transmits the first clock signal clkl The frequency is reduced by an odd multiple of k (this is The embodiment k-3) forms a clock signal cik2, and further generates a third clock signal clk3 having the same frequency as cik2 and having a time delay (refer to FIG. 8(a)). A first signal to be tested After datal enters a sample-and-hold circuit 51, it cooperates with the high and low levels of clk3 to convert datal into a second signal to be tested data2 having a pulse width of ~2. Figure 10(a) discloses a sample-and-hold circuit 51 utilizing datal& The input signal of clk3 is used to generate a second signal to be tested data2. In the preferred embodiment of the sample and hold circuit 51, the size of the inverter a is larger than that of the inverter b, S39958 107364 005017439-2 - 14 - 1282860 to improve the stability of the operation. The mode of operation of the sample-and-hold circuit 5 is as follows: When clk3 is the clamp level, the output signal of the sample-and-hold circuit 5 (ie, data2) is equivalent to datal. When clk3 is low-level, the output signal of the sample-and-hold circuit 51 maintains the level of 4" at the time. Figure 1〇(b) is the timing diagram of the signals of clkl, Clk2, clk3, datal and data2. When the digital signal is high or low When switching the level, it is not a simple switch (refer to Figure 1). 1 (a)), in fact, the data signal is from "〇" to "丨" (or from "丨, to "〇π), as shown in Figure 11 (b) (Figure 11 (a) The “Μ” part enlarges the map), and the slope of its change will affect the slope of the pulse rise and fall of the corresponding eye diagram, which will also affect the magnitude of the loop jitter. The general voltage is from “〇” to “quot” , or the sampling point from "丨" to π〇" can be set at the high and low boundary detection thresholds (b〇undary detecti〇n threshold) 511 and 512. The output signal data2 of the sample and hold circuit 51 is first processed by a pulse width modulation unit 52 to generate a third signal to be measured data3 having a third pulse width w3. FIG. 12(a), 12(b) are pulse widths. Two embodiments of modulation unit 52. The circuit of Figure 12(a) is designed to have a boundary detection threshold of 5 11 equal to 90% of the power supply core voltage value, and the circuit of Figure 12(b) adopts a low boundary detection threshold of 512. A design equal to ten percent of the magnitude of the power supply Vdd voltage. The settings of the general boundary detection thresholds 511, 512 are often greater than 8〇% of the power supply Vdd voltage value and less than 20% of the power supply Vdd voltage value. Comparing the signal timing diagrams of the two circuit designs, the same signal si input is known, and the output value S4 obtained by the latter has a wider pulse width. Generally, the jitter of the signal we want to measure is in the order of picoseconds (i 〇-12 seconds), etc. S39958 107364 005017439-2 -15-1282860' and the information of the signal jitter is the rise and fall of the signal, so the pulse width is utilized. The reducing unit 53 reduces the pulse width of the output signal (ie, data3) from the pulse width modulation unit 52 to a fourth signal to be tested data4 having a fourth pulse width w4, wherein the data4 only retains the pulse containing the signal jitter information. width. Figure 13 (a) is an embodiment of a pulse reduction unit 53. The pulse width reduction unit 53 is sequentially connected in series by an even number of inverters to generate a signal with a time delay from data3.
data3 ’ ’之後將訊號data3 ’與data3接至一反互斥或邏輯閘 (XNOR gate)以產生訊號 data4。圖 13(b)為 data3、data3,及 data4各訊號之時序圖，圖i3(c)則為圖i3(b)iN部位放大 圖。data4之脈寬明顯小於data3之脈寬，因此之後在輸入該 時間數位轉換裝置1時，可減少其中縮寬胞1〇i之數目，不僅 可加速訊號抖動的量測，也可降低硬體之成本。 訊號data4(相當於圖3之a〇)接著進入時間數位轉換裝置 1(其工作原理已詳敍於前，在此不再贅敍），被轉換成至少 一第二數位輸出碼bi。該第二數位輸出碼匕係以溫度計編碼 方式呈現，再經該優先編碼器4〇將該等第二數位輸出碼h 轉換成至少一個第三數位輸出碼為丨至m之正整數），並 由該輸出栓鎖單以〇控制輸出的時機。該優先編碼器4〇及 輸出栓鎖單元50之詳細運作方式如前所述，在此加以省略。 圖14揭示clkl、Clk2、clk3、如⑹、、輸出重置訊 齡_及觸發訊號吨之時序圖。該閃鎖控制器55接收來 自輸入控制H、54之,fL^；elk2後產生輸出重置訊號以如並傳 送至時間數位轉換裝置1内之縮t閃鎖胞2〇1(參圖9及圖 3)。該等縮寬閃鎖胞20i以複數個〇型正反器為實施例時， S39958 107364 〇〇5〇17439-2 1282860 輸：重置訊號Reset係傳送至D型正反器之咖埠，用以主 除岫一週期存留在D型正反 久斋甲之A唬貝枓。請同時參照圖 )及13(c)，訊號data3經該脈寬縮減單元53處理後，於時 間點 Tl、丁 4、τ$、τβ··女》 •產生之訊號data4帶有訊號data3 升緣之抖動資訊。同理於時間點丁2、丁3、了6、了7··· 產生之訊號data4即帶有訊號data3下降緣之抖動資訊。訊號 d咖經時間數位轉換裝以處理後，經優先編碼㈣之後儲 存在輸m鎖單元5〇。此時儲存在輸㈣鎖單元Μ中之資 耗至少—個第三數位輸出碼，也可解讀成-二進位數 =待來自閃鎖控制器55之觸發訊號Tdg傳送至輸出閃鎖 早7050時，該等第三數位輸出碼（二進位數字）即立刻被送 出。此時該二進位數字乘以該解析量r即表示訊號如⑽在該 寺間』的脈a ’亦即訊號data4在該時間點之循環抖動的時 間寬度。 圖15為本發明所揭示之一種訊號抖動量測裝置y之第二 貝施例之系統方塊圖，其係利用前述之時間數位轉換裝置1 和一輸入控制器54,來達成計算該訊號之循環抖動的功能， 其中於本實施例中不需使用到時脈訊號（參圖9之clkl)，而 疋直接利用一第一待測訊號datal來取代在訊號抖動量測裝 置5之第一時脈訊號。]^。且於本實施中所使用之時間數位 轉換裝置1、優先編碼器4〇、輸出閂鎖單元5〇、取樣保持電 路51、脈寬調變單元52及閂鎖控制器55均與第一實施例中 相同。孩第一待測訊號datal進入輸入控制器54，後，該輸入 控制器54將該第一待測訊號datal之頻率降低一奇數倍 S39958 107364 〇〇5〇17439-2 -17- 1282860 k(本實施例k=9)並產生具一時間延遲之一取樣保持控制訊 號ctd。同時，該第一待測訊號datal進入一取樣保持電路5丄 後，配合該取樣保持控制訊號ctd(於本實施例中係將圖1〇(勾 中之clk3以ctd取代）’將datal轉換成具一脈寬W2之一第二 待測訊號data2。取樣保持電路51之輸出訊號data2*經由一 脈寬調變單元52(參圖12(a)或圖12(b))之處理而產生具一第 三脈寬w3之一第三待測訊號data3。之後，利用一可調整脈 寬縮減單兀53f將來自脈寬調變單元52之輸出訊號（即為 data3)之脈寬縮減成具一第四脈寬w4之一第四待測訊號 data4,其中data4只保留含有訊號抖動資訊之脈寬。圖16顯 示第二實施例中 ctd、datal、data2、data3、data4、輸出重 置訊號Reset及觸發訊號Trig之時序圖，其中輸出重置訊號 Reset及觸發訊號Trig之上升緣均會緊隨著訊號data3之上 升緣移動。 圖17(a)為可調整脈寬縮減單元53,之一實施例之示音、 圖，圖17(b)則為圖17(a)之一實施例電路圖。該可調整脈寬 縮減單元53f由偶數個反相器串接（其中包含置於前後之兩 個固定式反相器531及置於中間之偶數個可調式反相器532) 用以產生一與data3具一時間延遲之訊號data3，，其中該時間 延遲可利用一第二控制訊號Vs來調整大小。之後將訊號 data3’與data3接至一反互斥或邏輯閘（XN〇R gate)以產生訊 號data4，因此藉由調整該第二控制訊號％之大小即可調整 訊號data4之第四脈寬w4之大小。其中連接接點a、b之排線 Bus係將一第一控制訊號Ctr連接至一閂鎖控制器55(參圖15) S39958 107364 005017439-2 -18- I282860 中以產生一觸發訊號Trig，而位於接點a、b之間之可調式反 相器532數目必㈣奇數，以降低脈寬縮減時所造成的誤 差。於本實施例中，該排線Bus僅包含兩條訊號線，然而可 视需要增加訊號線數目（意即增加連接點數目）。 複參圖，訊號細4(相當於圖3之a〇)接著進人時間數位 轉換裝置1，被轉換成至少一第二數位輸出碼^為…之 正整數）。在此實施例中，解析量續受一第三控制訊號^參 圖4所調整）。該第二數位輸出碼卜係以溫度計編碼方式呈 現’再經該優先編碼器4〇將該等第二數位輸出碼哺換成至 第三數位輸出％⑽1至"之正整數），並由該輸出 裎鎖早疋50控制輸出的時機。該閃鎖控制器Μ接收來自該 可调整脈寬縮減單元53,之第—控制訊號⑸後產生一輸出 重置訊號Reset並傳送至時間數位轉換裝置丨内之縮寬問鎖 胞2〇i(參圖15及圖3)。該等縮寬閃鎖胞冰以複數個d型正反 4實施例時’輪出重置訊號Reset係傳送至D型正反器之 用以清除前一週期存留在d型正反器中之訊號資 :°復翏圖16’訊號data3經該可調整脈寬縮減單元奸處理 卜於時間點T1、T4產生之訊號_帶有訊號_上升緣 ^斗動資訊。同理於時間點丁2、丁3產生之訊號_帶有訊 儿a3下降緣之抖動資訊。訊號如㈣經時間數位轉換裝置 ^理經優先編碼器做後儲存在輸㈣鎖單元％。此 出:!輸出！鎖單元5°中之資訊係至少-個第三數位輸 觸成進位數字。待來㈣鎖控制器55之 “儿ng傳以輸㈣鎖單元辦，該等第三數位輸 S39958 107364 005017439-2 -19- 1282860 出碼（二進位數字）即立刻被輸出。此時該二進位數字乘以該 解析量r即表示訊號data4在該時間點的脈寬，亦即訊號 data4在該時間點之循環抖動的時間寬度。 上述訊號抖動量測裝置之二實施例均為了達到降低硬體 成本，使用了脈寬縮減單元53(參圖9)或可調整脈寬縮減單 凡53’（參圖15)，先將待訊號（即data3)之脈寬縮短之後再行 處理。然因脈寬縮減單元53或可調整脈寬縮減單元53，的加 入，會產生誤差訊號。該誤差訊號產生說明如下。參圖 18(a) (c)，將一固定週期（Tfix)之測試訊號a輸入可調整脈 寬縮減單元53’，其中該測試訊號A之脈寬長度係以上升下 降時間（Trf)表示，且該測試號八之下降上升時間定義為 Tfix與Trf之差值。測試訊號A經可調整脈寬縮減單元53，之處 理後，其輸出訊號依所使用的第二控制訊號Vs大小而有所 不同。輸出訊號B及C係分別為Vs= IV及1·5 V之輸出訊號。 其中脈寬bl(cl)相應於Trf，而脈寬b2(c2)相應於Tfr (參考 圖13(c))。經可調整脈寬縮減單元53,處理後相應於Trf之脈 覓（例如· bl及cl)以T’rf表示；同理，相應於Tfr之脈寬（例如： b2及C2)以T’fr表示。理論上，bl與b2應該相等且^與^應該 相等，然實際上卻如圖18(b)所示，在許多的第二控制訊號 Vs情況下，其（T’rf_T’fr)值均不為〇(理論上應為〇)。另，參圖 18(c)，在第二控制訊號Vs固定在isv的情況下，輸入1〇個 週期的測试號A至可調整脈寬縮減單元5 3 ’後，可發現其 輸出訊號C各週期之（T，rf-T，id)值均不為〇，其中丁、表示輸出 訊號C上責任週期（duty cycle)為50%之時間長度。為消除因 S39958 107364 〇〇5〇17439-2 -20- 1282860 加入脈寬縮減單元53或可調整脈寬縮減單元53，所引入的誤 差，本發明提出以下之訊號抖動分析方法對循環抖動的時 間寬度（以下稱第五待測訊號）進行分析。 假η又4弟五待測訊號包含隨機抖動（Rancj〇in jitter，·尺了) 及定ϊ性抖動（Deterministic Jitter; DJ)。針對RJ部分，可 以一卩現機變數jR ·· { jRi I jRi，jR2，"jRn}(亦可稱隨機抖動流） 及一常態分佈N( //，cr )來表示，即Jr〜n( #，σ )，其中#表 示該常態分佈之平均值，σ表示該常態分佈之標準差。該 第五待測訊號之脈寬流W: {Wi | Wi，W2，"，Wn}為已知，且 理想訊號之一理想脈寬Wid亦為已知。根據定義 jR2-jRl-W1-Wid? jR3-jR2 = W2-Wid5 · · ·。因此可推出 wid。又以訊號觀點而言，心及1、具有相同的統計 特性’故其相關係數（correlation c〇efficientM i且進一步可 推出 W〜N( _wid，V^2+c2+2_)=N(-Wid，2 σ )。因為該第 五待測號之脈寬流W為已知，故可計算出其標準差σ，， 因此可推传σ· ’=2 σ。意即隨機抖動RJ之標準差σ可藉由已 知之該第五待測訊號之脈寬流W之標準差σ，乘以二分之一 而出。 針對DJ部分，先說明圖19(勾及19〇3)之關係。假設該第五 待測訊號之DJ波形如圖19(a)所示為一正弦函數，其振幅為 Am為一未知數。其中jl5 J2, js · · ·為每一取樣點之取樣值， 其取樣頻率為第一待測訊號data 1之頻率除以一降頻係數 k(即為本發明之訊號抖動量測裝置5之第一實施例中之k 值）。圖19(b)中之各箭頭長度W*i係圖19(a)中各相鄰取樣值 S39958 107364 005017439-2 -21 - 1282860 之差值λ¥，ί( = υΜ) 〇而圖 ^ # w 不 弦函數圖形係根據 該差值Wi利用曲線順應（curve制ng)所得出，其 d下為本發明之訊號抖動分析方法分請之步驟。首 先針對違第五待測訊號進行_快速傅立葉轉換加如 hnsform)得出數個特徵頻率“，意即表示該第五待測訊 號包含有複數個㈣特徵頻率。之後根據每一個特 徵頻率“形成一振幅為i之第一正弦函數訊號。隨後以第 一待測訊號datal之頻率除以該降頻係數^^為取樣頻率 f_P ’針對每該第-正弦函數訊號進行取樣，形成複數個 取樣值Ji。針對每該第一正弦函數訊號所得出之取樣值乃， 將其相鄰兩取樣值相減（即JrJM)後，再利用曲線順應形成 一具一第二振幅Ka之第二正弦函數訊號，其圖形類似圖 iVb)之訊號圖形，但其振幅為Ka，而非a、。因此振幅八爪、 A’^^Ka之間可推得以下之關係：Am/A，m=1/Ka。又因為A，m 即為該第五待測訊號之振幅（可由I FFT(fDy丨求出）且第 二振幅Ka亦可求得，因此DJ的振幅Am=A，m/Ka即可根據上 述方法求出。意即，根據每該第二振幅Ka及其相應之該特 徵頻率fD;i，可計算出該第五待測訊號之一以之振幅。 另’關於總抖動（total jitter; TJ)之峰對峰值及均方根值 也可藉由上述方法來估計。總抖動峰對峰值及總抖動 均方根值7Vr心可分別經由以下式（1)及式（3)而求得。After data3 '', the signal data3' and data3 are connected to an anti-mutation or XNOR gate to generate a signal data4. Figure 13(b) is a timing diagram of the signals of data3, data3, and data4, and Figure i3(c) is an enlarged view of the iN of Figure i3(b). The pulse width of data4 is significantly smaller than the pulse width of data3. Therefore, when the digital conversion device 1 is input, the number of cells 1i can be reduced, which not only accelerates the measurement of signal jitter but also reduces the hardware. cost. The signal data4 (corresponding to a〇 of Fig. 3) is then entered into the time digital conversion device 1 (the operation of which has been described in detail above, which will not be described herein), and is converted into at least a second digital output code bi. The second digital output code is presented in a thermometer coded manner, and the second digital output code h is converted into a positive integer of at least one third digital output code from 优先 to m by the priority encoder 4,, and The timing of the output is controlled by the output latch. The detailed operation of the priority encoder 4 and the output latch unit 50 is as described above and will be omitted herein. Figure 14 shows the timing diagrams for clkl, Clk2, clk3, (6), output reset age_ and trigger signal ton. The flash lock controller 55 receives the output reset signal from the input control H, 54 and fL^;elk2 to be transmitted to the flash lock cell 2〇1 in the time digit conversion device 1 (refer to FIG. 9 and image 3). When the plurality of 闪-type flip-flops 20i are in the form of a plurality of 〇-type flip-flops, S39958 107364 〇〇5〇17439-2 1282860: reset signal Reset is transmitted to the D-type flip-flop, used A 唬 唬 存 存 存 存 主 主 主 主 主 主 主 主 主 主 主 主 主 主 主Referring to FIG. 3 and 13(c), the signal data3 is processed by the pulse width reduction unit 53 at the time point T1, D4, τ$, τβ···· The generated signal data4 carries the signal data3 rising edge. Jitter information. The same reason at the time point D2, Ding 3, 6, 7, 7··· The generated signal data4 is the jitter information with the falling edge of the signal data3. After the signal d is converted by the time digital conversion, it is stored after the priority encoding (4) and stored in the m lock unit 5〇. At this time, the power stored in the input (four) lock unit 至少 is at least a third digit output code, which can also be interpreted as a binary digit = the trigger signal Tdg from the flash lock controller 55 is transmitted to the output flash lock early 7050. The third digit output code (binary digit) is sent immediately. At this time, the binary digit is multiplied by the resolution amount r to indicate the time width of the signal jitter such as (10) between the temples, that is, the signal jitter of the signal data4 at the time point. 15 is a system block diagram of a second embodiment of a signal jitter measuring device y according to the present invention, which utilizes the aforementioned time digital conversion device 1 and an input controller 54 to achieve a cycle for calculating the signal. The function of the jitter, wherein the clock signal is not used in the embodiment (see clkl in FIG. 9), and the first signal to be tested is directly replaced by the first signal to be tested, datal1, in the first clock of the signal jitter measuring device 5. Signal. ]^. The time digital conversion device 1, the priority encoder 4, the output latch unit 5, the sample and hold circuit 51, the pulse width modulation unit 52, and the latch controller 55 used in the present embodiment are all the same as the first embodiment. Same in the middle. After the first signal to be tested datal enters the input controller 54, the input controller 54 reduces the frequency of the first signal to be tested datal by an odd multiple S39958 107364 〇〇5〇17439-2 -17-1282860 k ( This embodiment k = 9) and generates a sample hold control signal ctd with a time delay. At the same time, the first signal to be tested datal enters a sample-and-hold circuit 5, and cooperates with the sample-and-hold control signal ctd (in the present embodiment, the datal is converted into FIG. 1 (the clk3 in the hook is replaced by ctd)' The second signal to be tested, data2, has a pulse width W2. The output signal data2* of the sample and hold circuit 51 is generated by processing a pulse width modulation unit 52 (refer to FIG. 12(a) or FIG. 12(b)). a third pulse width w3 is a third signal to be measured data3. Thereafter, the pulse width of the output signal (ie, data3) from the pulse width modulation unit 52 is reduced to one by an adjustable pulse width reduction unit 53f. The fourth pulse width w4 is the fourth signal to be tested data4, wherein the data4 only retains the pulse width of the signal jitter information. FIG. 16 shows the ctd, datal, data2, data3, data4, output reset signal Reset and the second embodiment. The timing diagram of the trigger signal Trig, wherein the rising edge of the output reset signal Reset and the trigger signal Trig will move along the rising edge of the signal data3. FIG. 17(a) is an adjustable pulse width reduction unit 53, an embodiment. Fig. 17(b) is a circuit diagram of an embodiment of Fig. 17(a). The adjustable pulse width reduction unit 53f is connected in series by an even number of inverters (including two fixed inverters 531 placed in front and rear and an even number of adjustable inverters 532 placed in the middle) for generating one and data3 A time delay signal data3, wherein the time delay can be adjusted by using a second control signal Vs. Then the signal data3' and data3 are connected to an anti-mutation or logic gate (XN〇R gate) to generate a signal. Data4, so the size of the fourth pulse width w4 of the signal data4 can be adjusted by adjusting the size of the second control signal %. The cable Bus connecting the contacts a and b connects the first control signal Ctr to the first control signal Ctr. Latch controller 55 (see Figure 15) S39958 107364 005017439-2 -18- I282860 to generate a trigger signal Trig, and the number of adjustable inverters 532 between contacts a, b must be (four) odd number to reduce The error caused by the pulse width reduction. In this embodiment, the cable Bus includes only two signal lines, but the number of signal lines can be increased as needed (ie, the number of connection points is increased). (equivalent to the a〇 of Figure 3) Digital conversion apparatus 1, is converted into at least a second digital output code ^ ... of positive integer). In this embodiment, the resolution is continued by a third control signal (as adjusted in Figure 4). The second digital output code is presented in a thermometer coded manner, and then the second digital output code is fed to the third digital output code (10) 1 to a positive integer of the third digit output code by the priority encoder 4 The output locks the timing of the output control as early as 50. The flash lock controller Μ receives the first control signal (5) from the adjustable pulse width reduction unit 53, and generates an output reset signal Reset and transmits the narrowed lock cell 2〇i to the time digital conversion device ( See Figure 15 and Figure 3). When the plurality of d-type positive and negative 4 embodiments are used, the round-off reset signal Reset is transmitted to the D-type flip-flop to clear the previous period and remains in the d-type flip-flop. Signaling: °Reconstruction Figure 16' Signal data3 is processed by the adjustable pulse width reduction unit. The signal generated at time points T1 and T4 is transmitted with the signal_rise edge. The same reason is that at the time point D2, Ding 3 generated signal _ with the news a3 falling edge of the jitter information. The signal is as follows: (4) The time-digit conversion device is processed by the priority encoder and stored in the input (four) lock unit %. This out:! Output! The information in the lock unit 5° is at least a third digit that is input as a carry digit. Waiting for (4) lock controller 55 "child ng pass to lose (four) lock unit, the third digit loses S39958 107364 005017439-2 -19- 1282860 out code (binary digit) is immediately output. At this time the second Multiplying the carry digit by the resolution r indicates the pulse width of the signal data4 at the time point, that is, the time width of the cyclic jitter of the signal data4 at the time point. The second embodiment of the signal jitter measuring device achieves a reduction in hard Body cost, using the pulse width reduction unit 53 (refer to Figure 9) or adjustable pulse width reduction single 53' (refer to Figure 15), first reduce the pulse width of the signal (data3) and then process. The addition of the pulse width reduction unit 53 or the adjustable pulse width reduction unit 53 generates an error signal. The error signal is generated as follows. Referring to Fig. 18(a) and (c), a test signal of a fixed period (Tfix) is used. The input pulse width reduction unit 53' is input, wherein the pulse width length of the test signal A is represented by a rising and falling time (Trf), and the falling rise time of the test number eight is defined as a difference between Tfix and Trf. Test signal A Adjustable pulse width reduction unit 53, After processing, the output signal varies according to the size of the second control signal Vs used. The output signals B and C are output signals of Vs=IV and 1·5 V, respectively, wherein the pulse width bl(cl) corresponds to Trf, and the pulse width b2(c2) corresponds to Tfr (refer to Fig. 13(c)). The adjustable pulse width reduction unit 53 is processed by T'rf corresponding to the pulse of Trf (for example, bl and cl). Similarly, the pulse width corresponding to Tfr (for example: b2 and C2) is represented by T'fr. Theoretically, bl and b2 should be equal and ^ and ^ should be equal, but actually as shown in Figure 18(b) In the case of many second control signals Vs, the value of (T'rf_T'fr) is not 〇 (theoretically 〇). In addition, referring to Fig. 18(c), the second control signal Vs is fixed at In the case of isv, after inputting the test number A of one cycle to the adjustable pulse width reduction unit 5 3 ', it can be found that the (T, rf-T, id) values of the output signals C are not 〇. , wherein D, indicating the duty cycle of the output signal C is 50% of the length of time. To eliminate the addition of the pulse width reduction unit 53 or the adjustable by S39958 107364 〇〇5〇17439-2 -20-1282860 The error reduction unit 53 introduces the error. The present invention proposes the following signal jitter analysis method to analyze the time width of the cyclic jitter (hereinafter referred to as the fifth signal to be tested). The false η and the 4th fifth test signal include random jitter ( Rancj〇in jitter, · feet) and Deterministic Jitter (DJ). For the RJ part, you can see the current machine variable jR ·· { jRi I jRi, jR2, "jRn} (also known as random The jitter stream) and a normal distribution N( //,cr) are expressed, that is, Jr~n(#,σ), where # represents the average of the normal distribution, and σ represents the standard deviation of the normal distribution. The pulse width W of the fifth signal to be tested is: {Wi | Wi, W2, ", Wn} is known, and one ideal pulse width Wid is also known. According to the definition jR2-jRl-W1-Wid? jR3-jR2 = W2-Wid5 · · ·. Therefore, wid can be launched. From the signal point of view, the heart and 1, have the same statistical characteristics 'so its correlation coefficient (correlation c〇efficientM i and further can be derived W~N( _wid,V^2+c2+2_)=N(-Wid , 2 σ ). Since the pulse width W of the fifth to-be-measured number is known, the standard deviation σ can be calculated, so that σ· '=2 σ can be derived. That is, the standard deviation of the random jitter RJ σ can be multiplied by one-half of the standard deviation σ of the pulse width flow W of the known fifth signal to be measured. For the DJ part, the relationship of Fig. 19 (hook 19〇3) will be explained first. The DJ waveform of the fifth signal to be tested is a sinusoidal function as shown in Fig. 19(a), and the amplitude is Am is an unknown number, wherein jl5 J2, js · · · is the sampling value of each sampling point, and the sampling frequency thereof The frequency of the first signal to be tested data 1 is divided by a down-conversion coefficient k (that is, the k value in the first embodiment of the signal jitter measuring device 5 of the present invention). The length of each arrow in FIG. 19(b) W*i is the difference between each adjacent sample value S39958 107364 005017439-2 -21 - 1282860 in Fig. 19(a) λ¥, ί( = υΜ) 〇 and ^^ #w not the string function is based on the difference W i is obtained by curve compliance (curve system ng), and d is the step of the signal jitter analysis method of the present invention. First, for the violation of the fifth signal to be tested, _ fast Fourier transform plus hnsform is used to obtain several features. The frequency ", meaning that the fifth signal to be tested contains a plurality of (four) characteristic frequencies. Then, according to each characteristic frequency, a first sinusoidal function signal of amplitude i is formed. Then, the frequency of the first signal to be tested, datal, is divided by the frequency-down coefficient, and the sampling frequency f_P' is sampled for each of the first-sine function signals to form a plurality of sample values Ji. For each sample value obtained by the first sinusoidal function signal, after subtracting the adjacent two sample values (ie, JrJM), the curve compliant is used to form a second sinusoidal function signal having a second amplitude Ka. The graph is similar to the signal pattern of Figure iVb), but its amplitude is Ka, not a. Therefore, the following relationship can be derived between the amplitude octagonal and A'^^Ka: Am/A, m = 1/Ka. Moreover, since A, m is the amplitude of the fifth signal to be tested (which can be obtained by I FFT (fDy 丨) and the second amplitude Ka can also be obtained, the amplitude of the DJ Am=A, m/Ka can be determined according to the above The method is obtained, that is, according to each of the second amplitude Ka and its corresponding characteristic frequency fD; i, one of the amplitudes of the fifth signal to be tested can be calculated. The other is about total jitter (TJ) The peak-to-peak value and the root mean square value can also be estimated by the above method. The total jitter peak to peak value and the total jitter root mean square value of 7 Vr can be obtained by the following equations (1) and (3), respectively.
TJ - + 2xYdDJi ^Ρ-Ρ-2χ(Σ^χ^) (1) (2) 2 ρ-ρ' S39958 107364 005017439-2 -22- 1282860 X[w, -E{Wt)f ^- (3) 八中，妒”為s亥第二正弦函數訊號中差值之 峰對峰值（peak-to-peak)，叫為該第五待測訊號中所包含的 複數個DJ之振幅值，Kai為其相應之即之第二振幅值，^ 為該第二正弦函數訊號中之差值(=J山）（參圖 19(b))，E(Wi)表示該第五待测訊號之脈寬流i '%，.·.，TJ - + 2xYdDJi ^Ρ-Ρ-2χ(Σ^χ^) (1) (2) 2 ρ-ρ' S39958 107364 005017439-2 -22- 1282860 X[w, -E{Wt)f ^- (3 "八中,妒" is the peak-to-peak value of the difference in the second sine function signal of shai, called the amplitude value of the plurality of DJs included in the fifth signal to be tested, Kai is Correspondingly, the second amplitude value, ^ is the difference in the second sinusoidal function signal (=J mountain) (refer to FIG. 19(b)), and E(Wi) represents the pulse width of the fifth signal to be tested. Stream i '%,..,,
wn}之平均值（mean)。因此藉由定量性抖動之振幅⑽心該 第二振幅⑽)及該第二正弦函㈣號之差值（…之峰對峰 值，可求出總抖動峰對峰值（7Vpp广另，藉由該總抖動峰對 峰值叫-p)及該第二正弦函數訊號之差值（w，i)之峰對峰 值’可得出一總抖動均方根值。 本發明之技術内容及技術特點已揭示如上，然而熟悉本 項技術之人士仍可能基於本發明之教示及揭示而作種種不 背離本發明精神之替換及修飾。因此，本發明之保護範圍 應不限於實施例所揭示者，而應包括各種不背離本發明之 替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡單說明】 圖1係習知之眼狀圖； 圖2顯示習知之訊號抖動之量測方法； 圖3係本發明之時間數位轉換裝置之示意圖； 圖4係本發明之時間數位轉換裝置之縮寬胞之電路示意 圆， 圖5係待測訊號經各級縮寬胞後之脈寬縮減示意圖； 1282860 圖6係控制訊號與解析量之關係圖； 圖7係本發明之時間數位轉換裝置進一步包含之優先編 碼為及輸出閂鎖單元示意圖； 圖8(a)係本發明之時間數位轉換裝置之輸入控制器之訊 號時序圖； 圖8(b)係輸入控制器之一實施例之電路示意圖； 圖9係本發明之訊號抖動量測裝置之第一實施例之系統 方塊圖； 圖10(a)係係本發明之訊號抖動量測裝置之取樣保持電路 之電路示意圖； 圖10(b)係本發明之訊號抖動量測裝置之取樣保持電路 各訊號之時序圖； 圖11(a)及（b)顯示資料訊號之邊界偵測閥值； 圖12(a)及（b)係本發明之訊號抖動量測裝置之脈寬調變 單元之兩種電路實施例及其訊號時序圖； 圖13(a)係本發明之訊號抖動量測裝置之脈寬縮減單元之 一電路實施例； 圖13(b)係本發明之訊號抖動量測裝置之脈寬縮減單元 中各訊號之時序圖及其局部放大圖； 圖13(c)係圖13(b)中N區塊之放大圖； 圖14係本發明之訊號抖動量測裝置之第一實施例中各訊 號之時序圖； 圖15為本發明之訊號抖動量測裝置之第二實施例之夺、統 方塊圖； S39958 107364 〇〇5〇17439·2 -24- 1282860 圖16係本發明之訊號抖動量測裝置之第二實施例中各訊 號之時序圖； 圖17(a)係可調整脈寬縮減單元之一實施例示意圖；以及 圖17(b)係圖i7(a)之一實施例之電路圖； 圖18(a)例示可調整脈寬縮減單元之輸出入訊號； 圖1 8(b)及1 8(c)顯示因可調整脈寬縮減單元所引起的謨 差訊號； ％ 圖19(a)例示待測訊號中之定量性抖動訊號；以及 及19(b)係圖19(a)經取樣及相減處理後之訊號。 【主要元件符號說明】 1 時間數位轉換裝置 5、51訊號抖動量測裝置 10 縮寬胞群 10广 l〇n 縮寬胞 l〇ia 第一互補式金氧半導體反向器 i〇ib 第二互補式金氧半導體反向器 i〇ic 調整單元 l〇i( cl 第一端點 i〇ic. 2 第二端點 l〇i, c-3 第三端點 i〇ic- 4 第四端點 l〇i, c-5 第五端點 l〇ic. 6 第六端點 11 升、降緣 12 遮罩 15 眼狀圖 20 縮寬閂鎖胞群 2〇ι 〜20n 縮寬閂 1282860 40 優先編碼器 50 輸出閂鎖單元 51 取樣保持電路 52 脈寬調變單元 53 脈寬縮減單元 53! 可調整脈寬縮減單元 54、 54’ 輸入控制器 55 閂鎖控制器 531 固定式反相器 532 可調式反相器 511 高邊界偵測閥值 512 低邊界偵測閥值 542 D型正反器 S39958 107364 005017439-2 -26-The average of wn} (mean). Therefore, by the amplitude (10) of the quantitative jitter (10) and the difference between the second sine (4) and the peak of the second sine (4), the total jitter peak to the peak value can be obtained (7Vpp is wide, by the The total jitter peak versus peak value -p) and the peak-to-peak value of the difference (w, i) of the second sinusoidal function signal can result in a total jitter rms value. The technical content and technical features of the present invention have been disclosed. As above, the person skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention, and the scope of the present invention should not be limited to those disclosed in the embodiments, but should include The various alternatives and modifications of the present invention are not to be construed as being included in the following claims. FIG. 1 is a conventional eye diagram; FIG. 2 shows a conventional method for measuring signal jitter; 4 is a schematic diagram of a circuit of a widened cell of the time digital conversion device of the present invention, and FIG. 5 is a schematic diagram of a pulse width reduction of a signal to be measured after being narrowed by various stages; 6 series FIG. 7 is a schematic diagram of a priority encoding and output latching unit further included in the time digital conversion device of the present invention; FIG. 8(a) is an input controller of the time digital conversion device of the present invention; Figure 8(b) is a circuit diagram of an embodiment of an input controller; Figure 9 is a system block diagram of a first embodiment of the signal jitter measuring device of the present invention; Figure 10(a) is a system diagram FIG. 10(b) is a timing diagram of signals of the sample-and-hold circuit of the signal jitter measuring device of the present invention; FIG. 11(a) and (b) show data. The boundary detection threshold of the signal; FIG. 12(a) and (b) are two circuit embodiments of the pulse width modulation unit of the signal jitter measuring device of the present invention and its signal timing diagram; FIG. 13(a) FIG. 13(b) is a timing chart of each signal in the pulse width reduction unit of the signal jitter measuring device of the present invention and a partial enlarged view thereof; Figure 13 (c) is the N block in Figure 13 (b) Figure 14 is a timing chart of signals in the first embodiment of the signal jitter measuring device of the present invention; Figure 15 is a block diagram of the second embodiment of the signal jitter measuring device of the present invention; S39958 107364 〇〇5〇17439·2 -24- 1282860 FIG. 16 is a timing chart of signals in the second embodiment of the signal jitter measuring device of the present invention; FIG. 17(a) is an implementation of an adjustable pulse width reducing unit Figure 17 (b) is a circuit diagram of an embodiment of Figure i7 (a); Figure 18 (a) illustrates the input and output signals of the adjustable pulse width reduction unit; Figure 1 8 (b) and 1 8 (c) ) shows the coma signal caused by the adjustable pulse width reduction unit; % Figure 19(a) illustrates the quantitative jitter signal in the signal to be tested; and 19(b) shows the sample and subtraction in Figure 19(a) The signal after processing. [Main component symbol description] 1 Time digital conversion device 5, 51 signal jitter measurement device 10 Widened cell group 10 wide l〇n Widened cell l〇ia First complementary MOS inverter i〇ib Second Complementary MOS inverter i〇ic adjustment unit l〇i ( cl first end point i〇ic. 2 second end point l〇i, c-3 third end point i〇ic- 4 fourth end Point l〇i, c-5 fifth end point l〇ic. 6 sixth end point 11 liter, falling edge 12 mask 15 eye pattern 20 narrowing latch cell group 2〇ι 〜20n shrinking latch 1282860 40 Priority encoder 50 output latch unit 51 sample hold circuit 52 pulse width modulation unit 53 pulse width reduction unit 53! adjustable pulse width reduction unit 54, 54' input controller 55 latch controller 531 fixed inverter 532 Adjustable Inverter 511 High Boundary Detection Threshold 512 Low Boundary Detection Threshold 542 D-type Positive and Negative S39958 107364 005017439-2 -26-