TWI279880B - Manufacture method for semiconductor device having field oxide film - Google Patents

Manufacture method for semiconductor device having field oxide film Download PDF

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Publication number
TWI279880B
TWI279880B TW095103133A TW95103133A TWI279880B TW I279880 B TWI279880 B TW I279880B TW 095103133 A TW095103133 A TW 095103133A TW 95103133 A TW95103133 A TW 95103133A TW I279880 B TWI279880 B TW I279880B
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Taiwan
Prior art keywords
oxide film
region
mask
layer
lamination
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TW095103133A
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English (en)
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TW200631128A (en
Inventor
Syuusei Takami
Hiroaki Fukami
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Yamaha Corp
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Priority claimed from JP2005028699A external-priority patent/JP2006216815A/ja
Priority claimed from JP2005078628A external-priority patent/JP2006261487A/ja
Application filed by Yamaha Corp filed Critical Yamaha Corp
Publication of TW200631128A publication Critical patent/TW200631128A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0638—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layer, e.g. with channel stopper
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Description

127^&003133 號專利申請案 中文申請專利範圍更正本(96年7月） 十、申請專利範圍： 1. 一種半導體裝置製造方法’其包含下列步驟： 製備一具有至少一導電類型之一區域之矽基板； 將一第一氧化矽膜、一氮化矽膜及一第二氧化矽膜按 所述次序自底部層壓於該矽基板之一主表面上； 根據一所要的裝置開口圖案將一包括該第一氧化矽 膜、該氮化矽膜及該第二氧化矽膜中之至少該氮化矽膜 及該第二氧化矽膜之疊層圖案化； 形成一由氛化矽製成並覆蓋該疊層之一側面的侧間隔 物； 藉由使用該疊層及該侧間隔物作為一遮罩，將該一導 電類型之雜質離子植入該矽基板之該主表面中以形成一 通道截斷離子摻雜區；及 在移除該側間隔物之後’藉由使用該疊層作為一遮罩 之選擇性氧化’於該矽基板之該主表面上形成—具有一 對應於該疊層之裝置開口的場氧化膜，且基於該離子換 雜區來形成該一導電類型之一通道截斷區。 2. 如請求項1之半導體裝置製造方法， 其中該第二氧化矽膜為一藉由熱氧化一沈積於該說化 矽膜上之多晶矽膜而形成之氧化矽膜。 3_如請求項2之半導體裝置製造方法， 其中在將該多晶矽膜沈積於該氮化矽膜上以前，藉由 熱處理使該氮化矽膜變得密實。 4·如請求項1之半導體裝置製造方法， 104880-960703.doc 1279880 其中該第二氧化石夕膜為一沈積於該氮化石夕膜上且其後 藉由熱處理而變得密實之氧化矽膜。 5.-種半導體《置製造方法，^含下列步驟： (a)製備在一裝置形成區中一具有一主表面及至少一 導電類型之矽基板； ⑻於該發基板之該主表面上形成—覆蓋該裝置形成區 之氧化遮罩材料層； ⑷根據-對應於該裝置形成區之—部分之第—裝置開 口圖案於該氧化遮罩材料層上形成H触劑層； ⑷使用該第—抗#劑層作為—遮罩，藉由將該一導電 類型之雜質離子經由該氧化遮罩材料層植入該石夕基板之 主表面中而形成一用於一通道截斷之第一離子摻雜 區； 在形成該第—離子摻雜區之後，各向同性地钕刻該 第抗姓劑層以使該第一抗蝕劑層之厚度及平面尺寸減 少一預定數量； ()在該各向同性蝕刻以後，藉由使用該第一抗蝕劑層 作為遮罩之蝕刻來圖案化該氧化遮罩材料層，以形成 由該氧化遮罩材料層之一剩餘部分製成的第一氧化遮 罩；及 (g)在移除該第—抗蝕劑層以後，藉由使用該第一氧化 遮罩之選擇性氧化’於該石夕基板之該主表面上形成一具 有對應於5亥第—氧化遮罩之裝置開口的場氧化膜，並 /成對應於該第一離子摻雜區之該一導電類型之一第一 104880-960703.doc 1279880 通道截斷區。 6. 導電類型相反 如請求項5之半導體裝置製造方法，其中： 於該矽基板之該主表面上形成—與該— 之一導電類型的井區； 該步驟（b)形成亦覆蓋該井區之該氧化遮罩材料層； 該步驟⑷根據-對應於該井區之—部分的第二裝置開 口圖案亦形成一第二抗蝕劑層； ★該步驟⑷亦使用該第二抗㈣層作為—遮罩而形成該 第一離子摻雜區； 人 該步驟（e)亦各向同性地蝕刻該第二抗蝕劑層以使該第 二抗敍劑層之厚度及平面尺寸減少—預定數量； 該步驟（f)亦使用該第二抗蝕劑層作為—遮罩來圖案化 該氧化遮罩材料層，以形成一由對應於該第二抗蝕劑層 之該氧化遮罩材料層之一剩餘部分製成之第二氧化遮 罩， 、、' 在δ亥步驟（f)後及在該步驟（g)之前，該半拿體裝置製造 方法進一步包含下列步驟： (W形成一覆蓋該裝置形成區及該第一抗蝕劑層之第三 抗餘劑層，並形成一第四抗姓劑層，該第四抗蚀劑層未 覆蓋一作為該第一離子摻雜區之一部分的存在於該井區 中之離子摻雜區，而是覆蓋該第二氧化遮罩之一側面及 該第一抗钱劑層；及 (i)藉由使用該第三及第四抗蝕劑層作為一遮罩，將與 該一導電類型相反之該導電類型之雜質離子植入該井區 104880-960703.doc 1279880 中’以藉由補償作為該第一離子摻雜區之一部分的存在 於該井區中之該離子摻雜區而形成一用於一通道截斷之 第—離子換雜區； 在移除该.第二及第四抗姓劑層及該第一及第二抗钱劑 層以後’該步驟（g)藉由使用該第一及第二氧化遮罩之選 擇性氧化’於該石夕基板之該主表面上形成一具有對應於 該第一及第二氧化遮罩之第一及第二裝置開口的場氧化 > 膜、一具有該一導電類型且對應於該第一離子摻雜區之 第一通道截斷區及一具有與該一導電類型相反之該導電 類型且對應於該第二離子摻雜區之第二通道截斷區。 7. 一種半導體裝置製造方法，其包含下列步驟： 製備一具有一主表面及一導電類型之—裝置形成區及 一與該一導電類型相反的一相反導電類型之井區的矽基 板； 於該矽基板之該主表面上形成一覆蓋該裝置形成區及 | 該井區之氧化遮罩材料層； 根據一對應於該裝置形成區之一部分的第一裝置開口 圖案及一對應於該井區之一部分的第二裝置開口圖案於 該氧化遮罩材料層上形成第一及第二抗蝕劑層； 使用該第一及第二抗蝕劑層作為一遮罩，藉由將該— 導電類型之雜質離子經由該氧化遮罩材料層植入該矽基 板之該主表面中形成一用於一通道截斷之第一離子摻雜 區； 在形成該第一離子摻雜區以後，各向同性地蝕刻該第 104880460703.doc -4- 1279880 一及第二抗蝕劑層以將該第一及第二抗蝕劑層之厚度及 平面尺寸減少一預定數量； 形成一覆蓋該裝置形成區及該第一抗蚀劑層之第三抗 餘劑層，並形成一第四抗蚀劑層，該第四抗钕劑層未覆 蓋一作為該第一離子捧雜區之一部分的存在於該井區中 之離子換雜區’而是覆蓋該第二氧化遮罩之一側面及該 第二抗蝕劑層； 使用該第三及第四抗餘劑層作為一遮罩，將該相反導 電類型之雜質離子植入該井區中，以藉由補償作為該第 一離子摻雜區之一部分的存在於該井區中之該離子播雜 區而形成一用於一通道截斷之第二離子摻雜區； 在移除該第三及第四抗蝕劑層及該第一及第二抗姓劑 層後’藉由使用該第一及第二氧化遮罩之選擇性氧化， 於該石夕基板之該主表面上形成一具有對應於該第—及第 二氧化遮罩之第一及第二裝置開口的場氧化膜、—具有 該一導電類型且對應於該第一離子摻雜區的第—通道截 斷區及一具有該相反導電類型且對應於該第二離子摻雜 區的第二通道截斷區。 104880-960703.doc
TW095103133A 2005-02-04 2006-01-26 Manufacture method for semiconductor device having field oxide film TWI279880B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005028699A JP2006216815A (ja) 2005-02-04 2005-02-04 フィールド酸化膜形成法
JP2005078628A JP2006261487A (ja) 2005-03-18 2005-03-18 フィールド酸化膜形成法

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TW200631128A TW200631128A (en) 2006-09-01
TWI279880B true TWI279880B (en) 2007-04-21

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070218629A1 (en) * 2006-03-15 2007-09-20 Infineon Technologies Ag Method of fabricating an integrated memory device
US8080452B2 (en) * 2006-08-01 2011-12-20 Nxp, B.V. Effecting selectivity of silicon or silicon-germanium deposition on a silicon or silicon-germanium substrate by doping
US9418864B2 (en) * 2008-01-30 2016-08-16 Infineon Technologies Ag Method of forming a non volatile memory device using wet etching
US9478989B2 (en) 2012-01-17 2016-10-25 Infineon Technologies Austria Ag Power converter circuit with AC output
US9401663B2 (en) 2012-12-21 2016-07-26 Infineon Technologies Austria Ag Power converter circuit with AC output
US9425622B2 (en) 2013-01-08 2016-08-23 Infineon Technologies Austria Ag Power converter circuit with AC output and at least one transformer
US9461474B2 (en) 2012-01-17 2016-10-04 Infineon Technologies Austria Ag Power converter circuit with AC output
US9484746B2 (en) 2012-01-17 2016-11-01 Infineon Technologies Austria Ag Power converter circuit with AC output
CN103915341B (zh) * 2013-01-08 2016-12-28 中芯国际集成电路制造(上海)有限公司 晶体管及其形成方法
US9490316B2 (en) * 2014-11-17 2016-11-08 United Microelectronics Corp. Semiconductor structure with silicon oxide layer having a top surface in the shape of plural hills and method of fabricating the same
US9905672B2 (en) * 2016-05-23 2018-02-27 Samsung Electronics Co., Ltd. Method of forming internal dielectric spacers for horizontal nanosheet FET architectures
RU2761426C2 (ru) * 2019-12-27 2021-12-08 федеральное государственное бюджетное образовательное учреждение высшего образования Московский педагогический государственный университет Способ размещения наноалмазов с nv-центрами на нитриде кремния

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60180158A (ja) 1984-02-27 1985-09-13 Yokogawa Hokushin Electric Corp 半導体装置の製造方法
JPS63133645A (ja) 1986-11-26 1988-06-06 Matsushita Electronics Corp 半導体素子分離領域の形成方法
JPS63144543A (ja) 1986-12-09 1988-06-16 Nec Corp 半導体素子間分離領域の形成方法
JPH03220748A (ja) 1990-01-25 1991-09-27 Mitsubishi Electric Corp 半導体装置における素子分離方法
JPH04267335A (ja) 1991-02-22 1992-09-22 Seiko Instr Inc 半導体装置の製造方法
JPH05129282A (ja) 1991-11-01 1993-05-25 Sharp Corp 半導体装置およびその製造方法
JPH05136123A (ja) 1991-11-15 1993-06-01 Sharp Corp 素子分離方法
JPH065588A (ja) 1992-06-16 1994-01-14 Sony Corp 半導体装置の製造方法
JPH0685053A (ja) 1992-09-04 1994-03-25 Nippon Semiconductor Kk 半導体集積回路の製造方法
JPH07321193A (ja) 1994-05-27 1995-12-08 Nippon Steel Corp 半導体装置の製造方法
JPH10284479A (ja) 1997-04-07 1998-10-23 Nittetsu Semiconductor Kk 半導体集積回路の製造方法
JP2000012789A (ja) 1998-06-18 2000-01-14 Matsushita Electron Corp 半導体装置
US6232648B1 (en) * 1998-07-27 2001-05-15 Shye-Lin Wu Extended self-aligned crown-shaped rugged capacitor for high density DRAM cells
US6933192B1 (en) * 2004-05-07 2005-08-23 International Business Machines Corporation Method for fabricating a trench having a buried dielectric collar

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TW200631128A (en) 2006-09-01
US7687367B2 (en) 2010-03-30
US20080003776A1 (en) 2008-01-03
US20060189106A1 (en) 2006-08-24
KR100693962B1 (ko) 2007-03-12
KR20060089675A (ko) 2006-08-09

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