Ι278ι·_ 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體結構及其製程，且特別是 有關於一種晶圓結構與其製作方法、晶片的製作方法以及 晶片封裝結構。 【先前技術】 近幾年來，隨著攜帶式(portable)電子產品、手持式通 訊以及及消費性電子產品之成長性已凌駕於傳統個人電腦 (pc)產品之上，電子元件不斷地朝向高容量 '窄線寬的高 密度化、高頻、低耗能、多功能整合方向發展。而在積體 電路(Integrated Circuit，“1C”)封裝技術方面，為配合高輸入 /輸出（I/O)數、尚散熱以及封裝尺寸縮小化的要求下，使得 相關的封裝技術亦朝輕薄短小、以及低成本方向發展。 在光電產業蓬勃發展的今曰，光電元件之製程亦已結 合漸趨成熟的半導體製程技術，不斷朝著微型化的方向發 展’其中這些光電元件之種類諸如為電荷耦合 (Charge-Coupled Device，CCD)晶片、CMOS 影像感測 (CMOS Image Sensor，CIS)晶片、太陽能電池(Solar Cdl)及 生化晶片（Bio-Chip)等。此外，光電元件更可藉由晶圓級封 裝技術(wafer level package)進行量產，以降低光電元件之 製作成本並提高其生產效率。一般而言，習知之光電元件 在進行晶圓級之封裝製程時，通常會在晶圓上配置一透光 基板(例^如玻璃基板”並分別藉由一膠框使透光基板與晶 ，上之每一晶片的元件區域接合，以在膠框、透光基板及 每-晶片之間形成一密閉空間。其後，再對晶圓及透光基 1278982 14642twf.doc/m 板進行切割的動作，以得到多顆獨立的晶片封裝結構。 請參考圖1，其繪示習知一種應用於光電元件之晶片 封裝結構的示意圖。如圖i所示，晶片110係配置於:線 路基板120上，其中晶片110之主動表面110a外圍具有多 個銲墊112，且這些銲墊112係分別藉由導線13〇 =連接 至線路基板120上的多個接點122,以使得晶片11〇可透 過線路基板120與外部線路電性連接。此外，線路基板12〇 上更配置有一透明蓋板140,用以覆蓋晶片110與導線 130’並可避免外界之灰塵或水氣進入晶片封裝結構内，且 外界之光線亦可透過透明蓋板14〇照射至晶片11〇之主動 表面110a上，而與主動表面110a上之主動元件(未繪示 產生作用。 m 除上述之以打線接合(wire bonding)方式來接合晶片 與線路基板之晶片封裝結構之外，f知更可藉由覆曰脚 chlP)、軟片自動接合(tape automatic bonding，TAB)等封裝 技，來達到使晶片與外部線路電性連接之目的。然而，^ 論藉由上述何種封裝技術，皆須經過繁複之製程步驟(如打 線製程或凸塊製程等），且亦無法有效縮小晶片封裝結構之 體積。 【發明内容】 本發明的目的就是在提供-種晶片封裝結構，並且 較小之體積與較為簡化之製程步驟。 的再-目的是提供—種晶圓結構，其有助於縮 小曰曰片封裝結構之體積，並可簡化封裝製程。 l2789i§^wf.doc/m 、 本發明的又一目的是提供一種晶圓結構的製作方 去，其適於形成上述之晶圓結構，以縮小晶片封裝結構之 體積，並簡化封裝製程。 、y本發明的另一目的是提供一種晶片的製作方法，其適 於^/成新型之晶片，用以縮小封裝結構之體積，並可 封裝製程。 基於上述或其他目的，本發明提出一種晶片封裝結 構，其包括一線路基板以及一晶片，其中晶片係配置於^ 路基板上，且晶片包括一基底、多個銲墊、多個導電柱、 圖案化保護層以及一重配置線路。銲墊係配置於基底 上，導電柱係貫穿基底，並位於基底之外圍，且導電柱係 耦接至線路基板。此外，圖案化保護層係配置於基底上， 並暴露出銲墊與導電柱。另外，重配置線路係配置於圖案 化保護層上，並耦接於銲墊與導電柱之間。 、 本發明之晶片封裝結構例如更包括一透明蓋板，其係 1置，晶片上。此外，此透明蓋板之材質例如是玻璃。另 夕，晶片封裝結構例如更包括一框膠，其係配置於透明 板與晶片之間。 本發明之晶片封裝結構例如更包括多個銲球，其係配 置於線路基板上，並透過線路基板耦接至晶片。 本發明之晶片封裝結構例如更包括一導電材，盆係配 2導電柱與線路基板之間。此外，此導電材例如是鲜料 或導電膠。 在本發明之晶片封裝結構中，導電柱之材質例如是鋁 1278982 14642twf· doc/m 或銅。 々在本發明之晶片封l结構中，圖案化保護層例如包括 一第-圖案化保護層以及n案化保護層，且第二圖 案化保，層係配置於第__化保護層上。此外，第一圖 案化保護層之材質例如是氮化石夕(silicon nitride)。另外，第 一圖案化保護層之材質例如是苯併環丁烯 (zocycl〇butene，BCB)或聚亞驢胺(p〇iyimide, pi)。 本發明另提出一種晶圓結構，其包括一基底、多個銲 塾、多個導電柱、一圖案化保護層以及多個重配置線路。 其^，基底係劃分出多個元件區，而銲墊係職配置於元 件區内之基底上，且導電柱係嵌置於元件區邊 緣之基底内。此外，圖案储護層係配置於元件區内之基 底上’，暴露it{銲墊與導餘，而重配置線路係配置於圖 ^化保縣上，其巾每—重配置線路層制應位於元件區 八中之一内，並耦接於其所對應之銲墊與導電柱之間。 在本發明之晶圓結構中，導電柱之材質例如是鋁 銅。 1 在本發明之晶圓結構中，圖案化保護層例如包括一第 -圖案化保護層以及一第二圖案化保護層，其中第二圖案 化保護層係配置於第一圖案化保護層上。此外，第一圖案 化保護層之材質例如是氮化矽(silicon nitride)。另外，第二 囷案化保‘層之材質例如疋笨併環丁烯(Benz〇qCi〇butene， BCB)或聚亞酿胺(poiyimi^ pi)。 本么明更提出一種晶圓結構的製作方法。首先，提供 14642twf.doc/m 1278982 2底，其巾基底上具有錢元魏，時—元件區 基底上係配置有多個銲墊以及—第—圖案化保護層， -圖:化:護層係暴露出銲塾。接著，形成多個盲孔於: 一几件區邊緣之基仙。織，形成—導電柱於每^ ，。之後’形成多健配置線路於圖案絲護層上， 母一重配置線路層係對應位於元件區其中之叙 於其所對應之銲墊與導電柱之間。 耦接 在本發明之晶圓結構的製作方法中，在提供基 後，並且在形成盲孔之前，更包括 mZ^ ^ 層於第-_絲護層上。柄成—紅圖案化保護 —iif明之晶圓結構的製作方法中，形成盲孔的方法 例如是雷射鑽孔。 ^ ^ 在本發明之晶圓結構的製作方法中，形成 法例如是電鍍一導電材質於盲孔内。 、 ^明再提出-種晶片的製作方法。首先’提供一基 底，/、中基底上具有多個元件區，而二 上係配置有多個銲墊以及一第一圖化 楚土氐 案化保護層係暴露出銲塾。接著：幵二且圖 C。然後’形成-導電柱於每-盲孔内。 要t重配置線路於_化保護層上，其中每- 所對應之銲塾盘導電柱之門=中之—内，並搞接於其 J W電柱。然後，進行—單體化製程，以得到多個晶 1278982 14642twf.doc/m ’在提供基底之後，並 一第二圖案化保護層於 在本發明之晶片的製作方法中 且在形成些盲孔之前，更包括形成 弟圖案化保護層上。 在本發明之晶片的製作方法中，形成導電柱的方法例 如是電鍍一導電材質於盲孔内。 7在本發明之晶片的製作方法中，在研磨基底之底面之 後，並且在進行單體化製程之前，更包括配置一透明基板 於基底上方。此外，在配置透明基板於基底上方之前，更 包括开> 成一框膠於透明基板與基底之間。 基於上述，本發明係於晶片（晶圓）基底内形成導電 柱以在與線路基板接合時，晶片上之銲墊可透過重配置 線路，並直接藉由導電柱向下耦接至線路基板上。如此一 ^，不僅可省去習知之打線接合或覆晶接合等製程，降低 製程時間触本，亦可有雜小“封驗狀體積，進 而提昇產品之競爭力。 ▲為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 _請參考圖2A〜2H，其中圖2A〜2E繪示為本發明之 二種晶圓結構的製作流程^賴，而® 2A〜Μ緣示為結 合上述之晶圓結構的製作方法之一種晶片的製作方法。 I278^§2wf.doc/m 首先，如圖2A所示，提供一基底200，其例如是一 夕基底且基底200上係劃分有多個元件區2〇〇a以及圍繞 元件區200a之切割區2〇〇b。每一元件區2〇〇a内之基底2〇〇 上分別配置有多個銲墊2〇2以及一第一圖案化保護層 204a，其中元件區2〇〇a内例如可具有主動元件(未繪示）， 而知墊202係耦接至這些主動元件。此外，第一圖案化保 濩層20如之材質例如是氮化石夕(silicon nitride)，其具有多 個第一開口 206a，用以暴露出銲墊202。 、接著，如圖2B所示，於第一圖案化保護層2〇如上形 成一第二圖案化保護層204b，其材質例如是苯併環丁烯 (Benzocydobutene，BCB)或聚亞醯胺(p〇lyimide，ρι)。此 外，第二圖案化保護層204b中例如具有多個第二開口 2〇6b，用以暴露出銲墊202(甚至部分之第一圖案化保護層 204a)。值得注意的是，形成此第二圖案化保護層2〇4b之 步驟係為選擇性之一步驟，在本發明之其他實施例中，亦 可不需形成第二圖案化保護層204b，而直接進行下一道步 驟。 然後，如圖2C所示，形成多個盲孔208於每一元件 區200a邊緣之基底200内，其中這些盲孔208例如具有高 深寬比(high aspect ratio)，而於基底200上形成盲孔2〇8 的方法例如是雷射鑽孔(laser drilling)或其他加工技術。 之後，如圖2D所示，形成一導電柱21〇於每一盲孔 208内，其中形成導電柱210的方法例如是藉由電鍍製程， 而於盲孔208内填入鋁(A1)、銅(Cu)等導電性較佳之金屬 11 1278982 14642twf.d〇c/m 或其他導電材質。 接者，如圖2E所示，於每一元件區2〇〇a内形成 H 12，其中重配置線路212係位於第—圖案化^ f 204a與第二圖案化保護層⑽上，並耗接於盆所對 H㈣2,電柱21〇之間。此外，形成重配置線路 Mja、方法例如疋先於基底2〇0上全面性地形成一導電材 ^ d未繪示），再藉由微影蝕刻等步驟來圖案化此導電材 料層（未繪示），以得到多個重配置線路以】。BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a semiconductor structure and a process thereof, and more particularly to a wafer structure and a method of fabricating the same, a method of fabricating the wafer, and a chip package structure. [Prior Art] In recent years, as the growth of portable electronic products, handheld communication, and consumer electronics has surpassed traditional personal computer (PC) products, electronic components are constantly moving toward high capacity. 'Narrow line width, high density, high frequency, low energy consumption, multi-functional integration direction. In terms of integrated circuit ("1C") packaging technology, in order to meet the requirements of high input/output (I/O), heat dissipation and package size reduction, the related packaging technology is also light and thin. And the development of low cost. In the future of the photovoltaic industry, the process of optoelectronic components has been combined with the increasingly mature semiconductor process technology, and is constantly developing towards miniaturization. 'The types of these optoelectronic components are such as Charge-Coupled Device (CCD). ) wafer, CMOS image sensor (CIS) wafer, solar cell (Solar Cdl) and bio-Chip. In addition, the photovoltaic elements can be mass-produced by a wafer level package to reduce the fabrication cost of photovoltaic elements and increase their production efficiency. In general, conventional wafer components are usually provided with a light-transmissive substrate (such as a glass substrate) on the wafer during the wafer-level packaging process, and the transparent substrate and the crystal are respectively formed by a plastic frame. The component regions of each of the wafers are bonded to form a sealed space between the plastic frame, the transparent substrate and each of the wafers. Thereafter, the wafer and the transparent substrate 1278982 14642 twf.doc/m plate are cut. The operation is performed to obtain a plurality of independent chip package structures. Referring to Figure 1, there is shown a schematic diagram of a conventional chip package structure applied to a photovoltaic element. As shown in Figure 1, the wafer 110 is disposed on the circuit substrate 120. The active surface 110a of the wafer 110 has a plurality of pads 112 on the periphery thereof, and the pads 112 are connected to the plurality of contacts 122 on the circuit substrate 120 by wires 13 〇 = respectively, so that the wafers 11 〇 permeable lines The substrate 120 is electrically connected to the external circuit. Further, the circuit substrate 12 is further provided with a transparent cover 140 for covering the wafer 110 and the wire 130' and preventing external dust or moisture from entering the chip package structure, and the outside It The wire can also be irradiated onto the active surface 110a of the wafer 11 through the transparent cover 14 ,, and the active component on the active surface 110a (not shown to function. m is joined by wire bonding in addition to the above). In addition to the chip package structure of the chip and the circuit substrate, it is also possible to electrically connect the wafer to the external line by encapsulating techniques such as a cover pinchp) and a tape automatic bonding (TAB). However, it is necessary to go through complicated process steps (such as wire bonding process or bump process, etc.) by the above-mentioned packaging technology, and it is also impossible to effectively reduce the volume of the chip package structure. [The present invention] In providing a chip package structure, and a smaller volume and a more simplified process step. The re-purpose is to provide a wafer structure that helps to reduce the size of the chip package structure and simplify the package process A further object of the present invention is to provide a fabrication of a wafer structure suitable for forming the above-described wafer structure to reduce wafer package junctions. The volume of the structure is simplified, and the packaging process is simplified. y Another object of the present invention is to provide a method for fabricating a wafer, which is suitable for forming a novel wafer for reducing the volume of the package structure and packaging the process. Or other purposes, the present invention provides a chip package structure including a circuit substrate and a wafer, wherein the wafer is disposed on the substrate, and the wafer includes a substrate, a plurality of pads, a plurality of conductive pillars, and patterned protection The layer is disposed on the substrate, the conductive pillars are penetrated through the substrate, and are located at the periphery of the substrate, and the conductive pillars are coupled to the circuit substrate. Further, the patterned protective layer is disposed on the substrate and exposed Solder pads and conductive posts. In addition, the reconfiguration circuit is disposed on the patterned protective layer and coupled between the pad and the conductive post. The chip package structure of the present invention further includes, for example, a transparent cover plate disposed on the wafer. Further, the material of the transparent cover is, for example, glass. In addition, the chip package structure further includes, for example, a sealant disposed between the transparent plate and the wafer. The chip package structure of the present invention further includes a plurality of solder balls, which are disposed on the circuit substrate and coupled to the wafer through the circuit substrate. The chip package structure of the present invention further includes, for example, a conductive material between the pot and the 2 conductive posts and the circuit substrate. Further, the conductive material is, for example, a fresh material or a conductive paste. In the wafer package structure of the present invention, the material of the conductive pillar is, for example, aluminum 1278982 14642 twf·doc/m or copper. In the structure of the wafer package of the present invention, the patterned protective layer includes, for example, a first-patterned protective layer and a n-type protective layer, and the second pattern is protected, and the layer is disposed on the first protective layer. Further, the material of the first patterned protective layer is, for example, silicon nitride. Further, the material of the first patterned protective layer is, for example, benzocyclobutene (BCB) or polydecylamine (pi). The present invention further provides a wafer structure including a substrate, a plurality of solder bumps, a plurality of conductive pillars, a patterned protective layer, and a plurality of reconfiguration lines. The substrate is divided into a plurality of component regions, and the pads are disposed on the substrate in the component region, and the conductive pillars are embedded in the substrate of the edge of the component region. In addition, the pattern storage layer is disposed on the substrate in the component region, exposing it{pads and leads, and the reconfiguration circuit is disposed on the map of Huabao County, and the towel per-reconfiguration line layer system should be It is located in one of the eight regions of the component region and is coupled between the corresponding pad and the conductive pillar. In the wafer structure of the present invention, the material of the conductive pillar is, for example, aluminum copper. In the wafer structure of the present invention, the patterned protective layer includes, for example, a first patterned protective layer and a second patterned protective layer, wherein the second patterned protective layer is disposed on the first patterned protective layer. Further, the material of the first patterned protective layer is, for example, silicon nitride. In addition, the material of the second defragmentation layer is, for example, Benz〇qCi〇butene (BCB) or polyiamine (poiyimi^pi). Benming also proposed a method of fabricating a wafer structure. Firstly, the 14642twf.doc/m 1278982 2 bottom is provided, and the towel base has Qian Yuanwei, and the time-element area is provided with a plurality of pads and a -patterned protective layer on the substrate, - Figure: The solder joint is exposed. Then, a plurality of blind holes are formed on: a base of a few pieces of the edge of the zone. Weaving, forming - a conductive column at every ^. Thereafter, a multi-configuration line is formed on the pattern wire sheath, and the mother-re-distribution line layer is located between the pad and the conductive post corresponding to the element region. Coupling In the fabrication method of the wafer structure of the present invention, after the substrate is provided, and before the formation of the blind via, the mZ^^ layer is further disposed on the first-silicon layer. Handle-red patterning protection—In the method of fabricating a wafer structure, the method of forming a blind hole is, for example, a laser drilling. ^ ^ In the method of fabricating the wafer structure of the present invention, the formation method is, for example, plating a conductive material into the blind via. , Ming Ming proposed - the production method of the wafer. First, a substrate is provided, and a plurality of component regions are provided on the middle substrate, and a plurality of solder pads are disposed on the second substrate, and a first patterned etched protective layer exposes the solder bumps. Then: 幵二 and Figure C. Then the 'forming-conductive pillars are in each-blind hole. It is necessary to reconfigure the line on the _ protective layer, where each of the corresponding soldering pad conductive column gates is in the middle, and is connected to its J W column. Then, a singulation process is performed to obtain a plurality of crystals 1278982 14642 twf.doc/m ' after the substrate is provided, and a second patterned protective layer is used in the fabrication method of the wafer of the present invention and some blind holes are formed. Previously, it also included the formation of a pattern on the protective layer. In the method of fabricating the wafer of the present invention, the method of forming the conductive pillar is, for example, electroplating a conductive material into the blind via. 7 In the method of fabricating a wafer of the present invention, after polishing the bottom surface of the substrate, and before performing the singulation process, further comprising arranging a transparent substrate over the substrate. In addition, before the transparent substrate is disposed on the substrate, it is further included to form a sealant between the transparent substrate and the substrate. Based on the above, the present invention forms a conductive pillar in a wafer (wafer) substrate. When bonding with the circuit substrate, the pad on the wafer can pass through the reconfiguration line and directly coupled to the circuit substrate by the conductive pillar. . Such a ^, not only can save the conventional wire bonding or flip chip bonding process, reduce the process time touch, can also have a small "sealed inspection volume, and thus enhance the competitiveness of the product. ▲ To make the above of the present invention The other objects, features and advantages will be more apparent and understood. The following detailed description of the preferred embodiments, together with the accompanying drawings, will be described in detail below. [Embodiment] _ Please refer to Figures 2A to 2H, wherein Figures 2A to 2E The fabrication process of the two wafer structures of the present invention is shown, and the ® 2A~ Μ 示 is shown as a method for fabricating a wafer in combination with the above-described fabrication method of the wafer structure. I278^§2wf.doc/m First As shown in FIG. 2A, a substrate 200 is provided, which is, for example, an eve substrate and the substrate 200 is divided into a plurality of element regions 2a and a dicing region 2b surrounding the element region 200a. A plurality of pads 2〇2 and a first patterned protective layer 204a are disposed on the substrate 2 of the second layer, wherein the element region 2〇〇a may have an active component (not shown), for example. The known pad 202 is coupled to the active components. In addition, the first pattern The material of the protective layer 20 is, for example, silicon nitride having a plurality of first openings 206a for exposing the pads 202. Next, as shown in FIG. 2B, the first patterning protection The layer 2 is formed as a second patterned protective layer 204b, such as benzooctodoene (BCB) or polydecylamine (p〇lyimide, ρι). In addition, the second patterned protective layer 204b For example, there are a plurality of second openings 2〇6b for exposing the pads 202 (even a portion of the first patterned protective layer 204a). It is noted that the step of forming the second patterned protective layer 2〇4b In another embodiment of the present invention, the second patterned protective layer 204b may be formed without directly forming the next step. Then, as shown in FIG. 2C, a plurality of blind vias 208 are formed. In the substrate 200 at the edge of each element region 200a, wherein the blind holes 208 have, for example, a high aspect ratio, and the method of forming the blind holes 2〇8 on the substrate 200 is, for example, laser drilling. ) or other processing techniques. After that, as shown in Figure 2D A conductive pillar 21 is formed in each of the blind vias 208. The method of forming the conductive pillars 210 is, for example, by an electroplating process, and the conductive holes of the aluminum (A1) and copper (Cu) are filled in the blind vias 208. Good metal 11 1278982 14642twf.d〇c/m or other conductive material. As shown in Fig. 2E, H 12 is formed in each element region 2〇〇a, wherein the reconfiguration line 212 is located in the first patterning ^ f 204a and the second patterned protective layer (10), and are consumed between the basin H (four) 2, the electric pole 21 。. In addition, the reconfiguration line Mja is formed, for example, a conductive material is not formed on the substrate 2〇0, and the conductive material layer is patterned by photolithography etching or the like (unpainted) Show) to get multiple reconfiguration lines to].
值，一提的是，本實施例之圖示僅於每一元件區2〇〇& 内繪不單一銲墊202及其所對應之重配置線路212與導電 柱210。當然，在實際的情形下，基底2〇〇上之其他銲墊 202例如是分別藉由其所對應之重配置線路212耦接至元 件區20〇a周圍之其他導電柱21〇。 在形成上述之晶圓結構之後，本發明更可藉由下述之 步驟得到單體化之晶片。It is to be noted that the illustration of the present embodiment depicts only a single pad 202 and its corresponding reconfiguration line 212 and conductive post 210 in each of the component regions 2 & Of course, in the actual case, the other pads 202 on the substrate 2 are coupled to other conductive posts 21A around the element region 20A, respectively, by their corresponding reconfiguration lines 212. After forming the above-described wafer structure, the present invention can further obtain a singulated wafer by the following steps.
如圖2F所示，配置一透明基板220於晶圓200上方， 其中此透明基板220例如是一玻璃基板，而接合此透明基 板220與基底200的方法例如可於透明基板220或於基底 200之每一元件區200a外圍形成一框膠(sealant)23〇 ,以形 成密閉之空間，進而避免外界之灰塵或水氣進入元件區 200a 内。 然後，如圖2G所示，研磨基底200之底面，以暴露 出嵌置於基底200内之導電柱210，其中目前較為常見的 研磨方法例如是化學機械研磨（chemical mechanical 12 ：twf.doc/m polishing，CMP)等。 之後’如圖2H所示，進行一單體化製程，而As shown in FIG. 2F, a transparent substrate 220 is disposed above the wafer 200. The transparent substrate 220 is, for example, a glass substrate, and the method of bonding the transparent substrate 220 and the substrate 200 can be performed, for example, on the transparent substrate 220 or the substrate 200. A sealant 23 形成 is formed on the periphery of each of the component regions 200a to form a sealed space, thereby preventing external dust or moisture from entering the component region 200a. Then, as shown in FIG. 2G, the bottom surface of the substrate 200 is ground to expose the conductive pillars 210 embedded in the substrate 200. The most common grinding method is, for example, chemical mechanical polishing (chemical mechanical 12: twf.doc/m). Polishing, CMP), etc. Thereafter, as shown in FIG. 2H, a singulation process is performed, and
區2嶋對基底與透明基板22〇進行切割 個J 相互分離之晶片250。 卞巧夕個 =上述，本發明係於製作晶圓結構時，於元件區外 圍的基底内形成盲孔，並於盲孔内形成導電柱，以 面電柱將晶片與外部線路之嶽置(_轉 意圖請如參圖考 3圖所3干= 曰曰片250係配置於一線路基板260上， 且暴路於晶片250背面之每一導電柱21()可直接藉由 ，材270而對應轉接至線路基板26〇上的第 ·， 例如是銲料或導電膠。此外，線路基板26〇 且、士此姑日日片細之另—面例如具有多個第二接點264， ^接點264上例如分別配置有銲球，以供晶 震、、告構與外界電性連接之用。 、 封装或覆晶接合之晶片 亦板，因此不僅在封裝後具有較小之體積， ^乍^為簡化之製程步驟。藉由本發明之晶圓結構與其 產，、晶片的製作方法以及晶片封袭結構不僅可使得 :加微型化’更可降低製程時間與製作 幵產品之競爭力。 捉 雖然本發明已以較佳實施例揭露如上，然其並非用以 13 I2789^d〇c/m 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 _圖^示為習知之—種顧於找元件之⑼封裝結 構的不意圖。 亍j 本發明之—種晶圓結_製作流程 =圖’而圖2A〜2H綠示為結合上述之晶圓結構的製作 方法之一種晶片的製作方法。 圖3繪示為本發明之一種晶 【主要元件符號說明】 了衣、、、。構的不思圖。 110 :晶片 110a ·主動表面 112 :銲墊 120 :線路基板 122 :接點 130 :導線 140 :透明蓋板 200 :基底 200a ··元件區 200b :切割區 202 :銲墊 204a :第一圖案化保護層 204b·弟二圖案化保護層 Ι278982_ 206a ··第一開口 206b :第二開口 208 :盲孔 210 :導電柱 212 :重配置線路 220 :透明基板 230 :框膠 250 :晶片 260 :線路基板 270 :導電材 262 ··第一接點 264 :第二接點 280 :銲球The substrate 2 and the transparent substrate 22 are cut to form a wafer 250 separated from each other. In the above, when the wafer structure is fabricated, a blind hole is formed in the substrate outside the component region, and a conductive pillar is formed in the blind hole, and the wafer is placed on the external circuit with the surface electrode (_ For the purpose of the transfer, please refer to Figure 3: The dry film 250 is disposed on a circuit substrate 260, and each conductive post 21 () that blasts on the back surface of the wafer 250 can directly correspond to the material 270. Transferring to the circuit board 26, for example, solder or conductive paste. In addition, the circuit board 26 and the other side of the board have a plurality of second contacts 264, for example At the point 264, for example, solder balls are respectively arranged for crystal shock, and the structure is electrically connected to the outside. The package or the flip chip is also used for the wafer, so that it has a small volume not only after packaging, ^ ^ The process steps for simplification. The wafer structure and the production thereof, the wafer fabrication method and the wafer encapsulation structure can not only make the miniaturization process, but also reduce the process time and the competitiveness of the product. The present invention has been disclosed above in the preferred embodiment, The present invention is not limited to 13 I2789^d〇c/m, and any person skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. The scope of the patent application is subject to the definition of the patent application. [Simplified description of the drawing] _ Figure ^ shows the conventional design - the purpose of looking at the component (9) package structure is not intended. 亍j The invention of the wafer junction _ production Fig. 2A to Fig. 2H are diagrams showing a method of fabricating a wafer in combination with the above-described method for fabricating a wafer structure. Fig. 3 is a view showing a crystal [main element symbol] of the present invention. 110: Wafer 110a · Active surface 112: Pad 120: Circuit substrate 122: Contact 130: Conductor 140: Transparent cover 200: Substrate 200a · Component area 200b: Cutting area 202: Solder pad 204a The first patterned protective layer 204b·the second patterned protective layer Ι278982_206a··the first opening 206b: the second opening 208: the blind hole 210: the conductive pillar 212: the reconfiguration line 220: the transparent substrate 230: the sealant 250: Wafer 260: circuit substrate 270: conductive material 262 ··First contact 264 : Second contact 280 : Solder ball