TWI278752B - Disk array controller and fast method of executing stripped-data operations in disk array controller - Google Patents
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1278.752 "}..., ： -,, / '〜.一...’(1)... 玖、發明說明 【發明所屬之技術領域】 本發明關於數位資料儲存系統，具體來說，是關於數 位資料儲存及取還之碟片陣列控制器技術的改良。 [先前技術】 小型電腦系統之典型RAID控制器包含至主系統之介 面及至碟片控制器陣列之介面。圖1爲碟片陣列控制器 1 〇之簡化方塊圖，提供主介面1 6與主匯流排1 2之交互 作用’及碟片控制器介面2 2與多個連接碟片控制器1 4之 交互作用。控制器包含控制處理器20及緩衝記憶體】8以 暫存從主匯流排至碟片控制器間移動的資料。 實體埠如同碟片控制器對於系統爲連接巨量儲存裝置 之必要條件。雖然有些介面可以支援並行資料傳送至多數 裝置，但貫體ί阜有成爲瓶頸的傾向。因此，高效率RAID 控制器如圖2A所示每一巨量儲存裝置皆有—實體焊。圖 2A也顯示映射暫存器對應之內容，接下來將參考圖4來 詳細描述。 R AID效率優勢之一來自於資料條狀化穿過陣列碟片 控制器。舉例來說，同時從四個碟片控制器讀取資料，比 起從單一碟片控制器所傳送之速率快上四倍。在圖2A之 例子中，從四個碟片控制器所傳達之十六位元資料以邏輯 碟片控制器次序合倂成爲六十四位元資料傳送到緩衝器（ 圖1中〗8 )。使用者資料被條狀化，即逐—分割成片段 -4- 121875¾23^ (2)1278.752 "}..., : -,, / '~.一...'(1)... 玖, invention description [Technical field of invention] The present invention relates to a digital data storage system, in particular, It is an improvement on the technology of disc array controller for digital data storage and retrieval. [Prior Art] A typical RAID controller for a small computer system includes an interface to the main system and an interface to the disc controller array. 1 is a simplified block diagram of a disc array controller 1 that provides interaction between the main interface 16 and the main bus 12 and the interaction of the disc controller interface 22 with a plurality of connected disc controllers 14. effect. The controller includes a control processor 20 and a buffer memory 8 for temporarily storing data moving from the main bus to the disc controller. The physical port is like a disc controller for the system to connect to a huge amount of storage. Although some interfaces can support parallel data transfer to most devices, there is a tendency to become a bottleneck. Therefore, the high-efficiency RAID controller has physical storage as shown in Figure 2A for each of the massive storage devices. Figure 2A also shows the contents of the mapping register, which will be described in detail below with reference to Figure 4 . One of the advantages of R AID efficiency comes from the striping of data across the array disc controller. For example, reading data from four disc controllers at the same time is four times faster than transferring from a single disc controller. In the example of Fig. 2A, the sixteen bit data conveyed from the four disc controllers are merged in the order of the logical disc controller into sixty-four bits of data to be transferred to the buffer (Fig. 1). User data is stripped, that is, segmented into segments -4- 1218753⁄423^ (2)
(例如，1 6位元字）再以預定順序穿過碟片控制器陣列 。我們判定順序從邏輯碟片控制器#0開始，再進行至邏 輯碟片控制器#n-l，其中n爲陣列中碟片控制器的編號。 重複這個條狀順序以使第k個使用者資料片段對應於邏輯 碟片控制器（K m 〇 d η )。如此，我們以邏輯碟片控制器 編碼來反映條狀次序。因此，圖中所示之四個一組的邏輯 埠簡單地表示四個條狀片段之次序組合。每個、、邏輯埠" 對應於一個條狀片段，而整組對應於四個片段的次序組合 每個碟片控制器之傳送速率100MBPS在到緩衝器時 會變成傳送速率400MBPS。虛線框26槪念上表示一資料 路徑開關。資料路徑開關2 6提供邏輯資料埠與實體資料 埠間動態可規劃之資料路徑。 圖2 Α中邏輯資料埠與實體資料瑋間直接的連接只是 一槪念圖。在實際的應用上，可用實體資料埠數量會比邏 輯資料埠數量來的多。可能會有一些埠保留作爲、、熱備用 秦(for example, 16-bit words) pass through the array of disc controllers in a predetermined order. We determine that the sequence starts from logical disc controller #0 and then proceeds to logical disc controller #n-l, where n is the number of the disc controller in the array. This strip order is repeated such that the kth user profile corresponds to the logical disc controller (K m 〇 d η ). So, we use the logical disc controller encoding to reflect the strip order. Therefore, the logical group of the four groups shown in the figure simply represents the order combination of the four strip segments. Each , logical 埠 " corresponds to a strip segment, and the entire group corresponds to the order of the four segments. The transfer rate of each disc controller 100 MBPS becomes a transfer rate of 400 MBPS when it reaches the buffer. The dashed box 26 represents a data path switch. The data path switch 26 provides a logically programmable data path between the logical data and the physical data. Figure 2 The direct connection between the logical data and the physical data is only a commemorative map. In practical applications, the amount of available physical data will be more than the number of logical data. There may be some 埠 reserved as, hot spare Qin
〃或實體埠可能聚集成不同的獨立存取子陣列。圖2 B爲 四個邏輯資料埠（邏輯埠# 〇 -邏輯璋# 3 )至可用的五個實 體資料璋（實體埠㈣_實體璋料）之可能分配其中一個例 子。例如，大型箭頭3 0簡單表示邏輯埠# 1到實體埠#2之 分配。圖2B也顯示對應於映射暫存器24的內容。在此， I 暫存器右邊數來第二個欄位對應邏輯璋#1，且包含表示實 體埠#2之數値'、2 〃，如箭頭3 〇所表示。接下來會完整 的敘述資料路徑開關2 6實現邏_至實體埠之分配。 -5- I,8f52_| (3)〃 or entities may be aggregated into different independent access subarrays. Figure 2B shows one of the possible assignments of four logical data 埠 (logic 埠 # 〇 - Logic 璋 # 3 ) to the available five physical data 埠 (entity 埠 (4) _ entity data). For example, the large arrow 30 simply represents the assignment of logical 埠 #1 to entity 埠#2. FIG. 2B also shows the content corresponding to the mapping register 24. Here, the second field on the right side of the I register corresponds to the logical 璋#1, and contains the number 値', 2 表示 indicating the actual 埠#2, as indicated by the arrow 3 〇. Next, the data path switch 26 will be fully described to realize the allocation of the logical_to entity. -5- I,8f52_| (3)
圖2 C顯示兩個碟片控制器陣列中每個碟片控制器分 配至五個其中一個可用實體資料埠之例子’稱爲實體埠# 1 及實體埠#2。爲了要匯編一 64位元字以提供給緩衝器， 每1 6位元碟片控制器必須重複讀取兩次’在第一次讀取 時，邏輯埠# 〇及# 1各別由實體埠# 2及# 1所取得。在第二 次讀取時，邏輯埠#2及#3各別由實體埠#2及#1所取得。 這些運算皆由控制器2 0所組織。再次地，映射暫存器顯 示實體埠#1及#2之分配。 圖2 D顯示單一碟片控制器連接至實體埠# 3之陣列的 例子。在這個規劃中，邏輯埠# 〇到邏輯埠# 3的資料是由 重複讀取同一個碟片控制器四次所取得。Figure 2C shows an example in which each of the two disc controller arrays is assigned to one of five available physical data, called Entity #1 and Entity #2. In order to assemble a 64-bit word to be supplied to the buffer, every 16-bit disc controller must be read twice. 'At the first reading, the logical 埠# 〇 and #1 are each by the entity 埠# 2和# 1 obtained. At the second reading, the logical 埠#2 and #3 are each acquired by the entities 埠#2 and #1. These operations are all organized by the controller 20. Again, the map register displays the assignments of entities 埠#1 and #2. Figure 2D shows an example of a single disc controller connected to an array of physical 埠 #3. In this plan, the data from the logical 埠#〇 to 埠#3 is obtained by repeatedly reading the same disc controller four times.
美國專利號碼6，0 1 8，7 7 8中描述其中一個同步冗餘資 料傳送特性爲它允許冗餘資料如美國專利號碼6,23 7，〇52 中描述以飛快地速度處理。圖3A顯示圖2A中四個碟片 控制器陣列加上邏輯3 6以使存入連接至實體埠#4碟片控 制器之冗餘資料模式完整。雖然各種算術及邏輯運算可用 於製造一冗餘模式，但從邏輯資料埠取得資料對應位元間 之邏輯互斥或，在算術運算上因爲互斥或運算不用傳送一 進位而有優勢。由於互斥或的使用，通常會把第五個碟片 控制器稱作''冗餘〃碟片控制器或''同位〃碟片控制器。 圖中所示1 6位元寬之緩衝器互斥或等同於十六個互斥或 閘，都各有四個輸入。如圖3B可見，互斥或功能在碟片 控制器讀取與碟片控制器寫入的運用上也很對稱。圖3 B 顯示與圖3 A所定義相同之四個碟片控制器陣列，而資料 -6- (4) 路徑40，42等顯示碟片控制器讀取方向。在此例子中， 連接於實體埠#2之碟片控制器爲無效。因此，所對應無 功能之資料路徑4 4以虛線顯示。互斥或功能是從現存的 資料碟片控制器（實體埠# 〇，# 1及# 3 )及冗餘碟片控制 器實體埠#4計算而得。此計算修復了存於無效碟片控制 器之資料且結果經由資料路徑4 6直接傳送到邏輯埠# 2以 取代從無效碟片控制器之無用資料。 前段具體說明一些可能存在於RAID控制器中一組邏 輯埠與一組實體裝置埠間各種關係之例子。一般來說，高 效率RA ID控制器被迫處理由連接到實體埠巨量儲存裝置 各種子群組所組成之多數陣列。就本發明一方面來看，使 用了一新穎的映射暫存器並關聯邏輯以使儲存裝置陣列之 軟體規劃可行，且改良了效率，這將在接下來進一步解釋 【發明內容】 本發明提供一種碟片陣列控制器’其包括：連接主系 統之主介面；儲存讀取及寫入資料之緩衝器；及包含多個 用以附加碟片控制器的實體埠之碟片介面；碟片介面另外 包含實現介於實體埠與緩衝器間可選取資料路徑之開關； 及儲存映射資料之映射暫存器，其中開關爲可動態規劃的 ，以回應存入映射暫存器的映射資料’來實現所需碟片陣 列0 1278752 / (5) 【實施方式】 映射暫存器 小型電腦系統之典型RAID控制器包含至主系統之介 面及至碟片控制器陣列之介面。圖1爲碟片陣列控制器 1 〇之簡化方塊圖，提供主介面1 6與主匯流排1 2之交互 作用，及碟片控制器介面22與多個連接碟片控制器1 4之 交互作用。控制器包含控制處理器20及緩衝記憶體1 8以 暫存從主匯流排至碟片控制器間移動的資料。 φ 實體埠如同碟片控制器對於系統爲連接巨量儲存裝置 之必要條件。雖然有些介面可以支援並行資料傳送至多數 裝置，但實體ί阜有成爲瓶頸的傾向。因此，高效率 RAID 控制器如圖2A所示每一巨量儲存裝置皆有一實體埠。圖 2A也顯示映射暫存器對應之內容，接下來將參考圖4來 詳細描述。 RAID效率優勢之一來自於資料條狀化穿過陣列碟片 控制器。舉例來說，同時從四個碟片控制器讀取資料，比 | 起從單一碟片控制器所傳送之速率快上四倍。在圖2 A之 例子中，從四個碟片控制器所傳達之十六位元資料以邏輯 碟片控制器次序合倂成爲六十四位元資料傳送到緩衝器（ 圖I中1 8 )。使用者資料被條狀化，即逐一分割成片段 (例如，1 6位元字）再以預定順序穿過碟片控制器陣列 。我們判定順序從邏輯碟片控制器# 〇開始，再進行至邏-輯碟片控制器#n-1，其中n爲陣列中碟片控制器的編號。 重複這個條狀順序以使第k個使用者資料片段對應於邏輯 冬 观 / (6) 碟片控制器（Κ m ο d η )。如此’我們以邏輯碟片控制器 編碼來反映條狀次序。因此，圖中所示之四個一組的邏輯 璋簡單地表示四個條狀片段之次序組合。每個 ''邏輯埠〃 對應於一個條狀片段’而整組對應於四個片段的次序組合 〇 每個碟片控制器之傳送速率 100MBPS在到緩衝器時 會變成傳送速率4 〇 〇 Μ B P S。虛線框2 6槪念上表示一資料 路徑開關。資料路徑開關2 6提供邏輯資料埠與實體資料 埠間動態可規劃之資料路徑。 圖2Α中邏輯資料埠與實體資料埠間直接的連接只是 一槪念圖。在實際的應用上，可用實體資料埠數量會比邏 輯資料埠數量來的多。可能會有一些埠保留作爲、、熱備用 〃或實體埠可能聚集成不同的獨立存取子陣列。圖2Β爲 四個邏輯資料埠（邏輯埠# 0 -邏輯埠# 3 )至可用的五個實 體資料埠（實體埠#0-實體埠#4 )之可能分配其中一個例 子。例如，大型箭頭3 0簡單表示邏輯埠# 1到實體埠# 2之 分配。圖2 Β也顯示對應於映射暫存器2 4的內容。在此， 暫存器右邊數來第二個欄位對應邏輯埠#1，且包含表示實 體埠#2之數値'' 2〃 ，如箭頭30所表示。接下來會完整 的敘述資料路徑開關2 6實現邏輯至實體璋之分配。 圖2 C顯示兩個碟片控制器陣列中每個碟片控制器分 配至五個其中一個可用實體資料埠之例子，稱爲實體璋# ! 及實體埠#2。爲了要匯編一 64位元字以提供給緩衝器， 每1 6位兀碟片控制器必須重複讀取兩次，在第〜次讀取 (2f87i52i (7) 時，邏輯埠#0及# 1各別由實體埠#2及# 1所取得。在第二 次讀取時，邏輯埠#2及#3各別由實體埠#2及#1所取得。 這些運算皆由控制器2 0所組織。再次地’映射暫存器顯 示實體埠#1及#2之分配。 圖2 D顯示單一碟片控制器連接至實體瑋# 3之陣列的 例子。在這個規劃中，邏輯埠# 〇到邏輯埠# 3的資料是由 重複讀取同一個碟片控制器四次所取得。One of the synchronous redundant data transfer characteristics described in U.S. Patent No. 6,0 1,8,7,8 8 is that it allows redundant data to be processed at a rapid rate as described in U.S. Patent No. 6,23,. Figure 3A shows the four disc controller arrays of Figure 2A plus logic 36 to complete the redundant data pattern stored in the physical port #4 disc controller. Although various arithmetic and logic operations can be used to create a redundant mode, the logical mutual exclusion between the corresponding bits of the data is obtained from the logical data, or it is advantageous in arithmetic operations because the mutual exclusion or operation does not need to transmit a carry. Due to the exclusive use or use, the fifth disc controller is usually referred to as a 'redundant disc controller or a 'co-located disc controller. The 16-bit wide buffers shown in the figure are mutually exclusive or equivalent to sixteen mutually exclusive or gates, each with four inputs. As can be seen in Figure 3B, the mutual exclusion or function is also symmetrical in the use of the disc controller read and the disc controller write. Figure 3B shows the same four disc controller arrays as defined in Figure 3A, while the data -6-(4) paths 40, 42 etc. show the disc controller reading direction. In this example, the disc controller connected to entity 埠#2 is invalid. Therefore, the corresponding non-functional data path 4 4 is shown by a broken line. Mutual exclusions or functions are calculated from existing data disc controllers (Entity 〇# 〇, #1 and #3) and Redundant Disc Controller Entity 埠#4. This calculation fixes the data stored in the invalid disc controller and the result is transferred directly to the logical port #2 via the data path 46 to replace the useless data from the invalid disc controller. The previous paragraph specifies some examples of some of the relationships between a set of logic and a set of physical devices that may exist in a RAID controller. In general, the high efficiency RA ID controller is forced to process a majority of the arrays consisting of various subgroups connected to the physical mass storage device. In one aspect of the invention, a novel mapping register is used and associated logic to make software planning of the array of storage devices feasible, and efficiency is improved, which will be further explained below. [Invention] The present invention provides a The disc array controller includes: a main interface connected to the main system; a buffer for storing read and write data; and a disc interface including a plurality of physical boards for attaching the disc controller; the disc interface additionally Included is a switch that implements a data path selectable between the entity and the buffer; and a mapping register that stores the mapping data, wherein the switch is dynamically planable, in response to the mapping data stored in the mapping register. Disc Array 0 1278752 / (5) [Embodiment] A typical RAID controller for mapping a small computer system includes an interface to the main system and an interface to the disc controller array. 1 is a simplified block diagram of a disc array controller 1 that provides interaction between the main interface 16 and the main bus 12, and the interaction of the disc controller interface 22 with a plurality of connected disc controllers 14. . The controller includes a control processor 20 and a buffer memory 18 for temporarily storing data moving from the main bus to the disc controller. The φ entity is like a disc controller for the system to connect to a huge storage device. While some interfaces can support parallel data transfer to most devices, there is a tendency for entities to become bottlenecks. Therefore, the high-efficiency RAID controller has a physical port for each of the massive storage devices shown in Figure 2A. Figure 2A also shows the contents of the mapping register, which will be described in detail below with reference to Figure 4 . One of the advantages of RAID efficiency comes from the striping of data through the array disc controller. For example, reading data from four disc controllers at the same time is four times faster than a single disc controller. In the example of Figure 2A, the sixteen-bit data conveyed from the four disc controllers are combined in the order of the logical disc controllers into sixty-four bits of data to be transmitted to the buffer (1 in Figure 1). . The user data is striped, i.e., segmented into segments (e.g., 16-bit words) and passed through the array of disk controllers in a predetermined order. We determine that the sequence starts from the logical disc controller #〇 and then proceeds to the logical disc controller #n-1, where n is the number of the disc controller in the array. This strip order is repeated such that the kth user data segment corresponds to the logical winter view / (6) disc controller (Κ m ο d η ). So we use the logical disc controller code to reflect the strip order. Therefore, the logical group of the four groups shown in the figure simply represents the order combination of the four strip segments. Each ''logic 埠〃 corresponds to one strip segment' and the entire group corresponds to the order of four segments. The transfer rate of each disk controller is 100 MBPS and becomes the transfer rate when it reaches the buffer. 4 〇〇Μ BPS . The dashed box 2 6 represents a data path switch. The data path switch 26 provides a logically programmable data path between the logical data and the physical data. The direct connection between the logical data and the physical data in Figure 2 is only a commemorative map. In practical applications, the amount of available physical data will be more than the number of logical data. There may be some 埠 reserved, hot spares, or entities that may be aggregated into different independent access subarrays. Figure 2 shows an example of the possible assignment of four logical data 埠 (logic 埠 # 0 - 埠 埠 # 3 ) to the available five physical data 埠 (entity 埠 #0 - entity 埠 #4). For example, the large arrow 30 simply represents the assignment of logical 埠 #1 to entity 埠#2. Figure 2 Β also shows the content corresponding to the mapping register 24. Here, the second field on the right side of the register corresponds to the logical 埠#1, and contains the number 实'' 2〃 indicating the actual 埠#2, as indicated by the arrow 30. The data path switch 26 is then fully described to implement the logical to physical allocation. Figure 2C shows an example of each of the two disc controller arrays assigned to one of five available physical data, called Entity !# ! and Entity 埠#2. In order to assemble a 64-bit word to be supplied to the buffer, every 16-bit 兀 disc controller must be read twice, at the first reading (2f87i52i (7), logic 埠#0 and #1 Each is obtained by entities 埠#2 and #1. At the second reading, logic 埠#2 and #3 are each obtained by entities 埠#2 and #1. These operations are all performed by controller 20 Organization. Again, the mapping of the scratchpad display entities 埠#1 and #2. Figure 2D shows an example of a single disc controller connected to the array of entities 玮# 3. In this plan, the logic 埠# The data of logic #3 is obtained by repeatedly reading the same disc controller four times.
美國專利號碼6,018,778中描述其中一個同步冗餘資 料傳送特性爲它允許冗餘資料如美國專利號碼6,23 7,0 52 中描述以飛快地速度處理。圖3 A顯示圖2 A中四個碟片 控制器陣列加上邏輯3 6以使存入連接至實體璋#4碟片控 制器之冗餘資料模式完整。雖然各種算術及邏輯3算可用 於製造一冗餘模式，但從邏輯資料埠取得資料對應位元間 之邏輯互斥或，在算術運算上因爲互斥或運算不用傳送一 進位而有優勢。由於互斥或的使用，通常會把第五個碟片 控制器稱作、'冗餘〃碟片控制器或 '、同位〃碟片控制器。 圖中所示丨6位元寬之緩衝器互斥或等同於十六個互 斥或閘，都各有四個輸入。如圖3B可見，互斥或功能在 碟片控制器讀取與碟片控制器寫入的運用上也很對稱。圖 3 B顯示與圖3 A所定義相同之四個碟片控制器陣列，而資 料路徑4 0，4 2等顯示碟片控制器讀取方向。在此例子中 ，連接於實體埠# 2之碟片控制器爲無效。因此’所對應 無功能之資料路徑4 4以虛線顯示。互斥或功能是從現存 的資料碟片控制器（實體埠# 0，# I及# 3 )及冗餘碟片控 -10- 1278752: 1 - „ ·.., ' ------- -I ..…, (8) 制器實體埠#4計算而得。此計算修復了存於無效碟片控 制器之資料且結果經由資料路徑46直接傳送到邏輯埠#2 Μ耳又代從無效碟片控制器之無用資料。 前段具體說明一些可能存在於RAID控制器中一組邏 輯埠與一組實體裝置埠間各種關係之例子。一般來說，高 效率RAI D控制器被迫處理由連接到實體埠巨量儲存裝置 各種子群組所組成之多數陣列。就本發明一方面來看，使 了一新穎的映射暫存器並關聯邏輯以使儲存裝置陣列之 軟體規劃可行，且改良了效率，這將在接下來進一步解釋 依據發明之一實施例，圖4顯示一映射暫存器24之 結構，控制了邏輯與實體資料埠間資料路徑之規劃。（此 映射暫存器也有其他後續將描述之特性及優勢。）在此實 施例中，映射暫存器由五個欄位所組成，各給五個邏輯資 料埠，在此例子中爲 L0-L4。每個暫存器中邏輯資料埠對 應之欄位由所連結實體資料埠之編號所載入。邏輯資料埠 〇欄位之資料，以符號PP_LO代表來表示實體埠關聯邏輯 埠 0。接著四個欄位之値各爲 PP_L1、PP_L2、PP_L3及 PP一L4。第五個邏輯資料埠爲一假埠。PP一値是用於分 配一實體資料埠給同位碟片控制器。 映射暫存器欄位幾乎可以是任何尺寸。以八位元欄位 爲例，可以支援到2 5 6個實體埠之陣列。對於只有五個實 體埠之實施例，三位元之欄位就足夠。五個欄位巧妙地湊 成十六位元暫存器，其中備用一位元在圖中標記爲'' r 〃 -11 - (9) 1278^ 即''保留〃之意。任何形式之非易失記憶體皆可用來儲存 映射暫存器資料。 爲了具體說明映射暫存器的功能，我們將簡短地複習 每個目則曾描述之規劃。圖2 A顯不一映射暫存器2 4。 PP_LO之値爲〇表示邏輯資料埠#0連接到實體埠#〇。接 著三個値爲1、2及3表示接著三個邏輯資料埠連接到接 著三個實體資料埠。PP_L4之値爲7。在此例子中這不是 法定之實體埠編號。'' 7 〃之値是爲了表示在此規劃中沒 有同位碟片控制器。對於選取特定値並無嚴格要求，只要 它不是實際的實體埠編號即可。 再次提及圖2B，存於映射暫存器之値表示實體資料 埠1、2、4及0各別支援邏輯埠0 g[J 3。再次地，' Ί” 表示並未使用同位碟片控制器。 圖2 C顯示映射暫存器爲兩個碟片控制器陣列規劃。 邏輯資料埠#2及#3與邏輯碟片控制器#〇及# 1關聯相同的 實體埠。前面兩個邏輯埠在第一個實體埠循環時傳送資料 | 而後面兩個邏輯埠則在第二個實體埠循環時傳送資料。 圖2D顯示映射暫存器爲單一碟片控制器規劃。邏輯 埠#〇到#3連續循環傳送資料至實體埠#3。所有圖2之變 化皆爲不同資料路徑規劃顯示獨立於冗餘資料邏輯。 圖3 A顯示互斥或邏輯在與圖2 A相同資料碟片控制 器規劃之碟片寫入方向。互斥或由四個邏輯資料埠之資料 計算取得。結果存入連接在映射暫存器邏輯埠#4欄位所 指定實體埠之碟片控制器中。在此例子中，PP_L4之値爲 、12- '' 4 〃而非w 7 〃表示有一同位碟片控制器連接在#4埠。 圖3 B顯示互斥或邏輯在碟片讀取方向除了連接在實 體埠#2之碟片控制器現爲無效外，與圖2A及3 A有相同 的資料路徑。邏輯資料埠2欄位內容由P P_L2被置換成 '' 5 〃 。法定的實體璋.編號爲〇到4。 、、5 〃爲一保留値用 以表示碟片控制器無效。任何邏輯資料埠進入編號5之假 實體埠將從互斥或輸出取得資料。 資料路徑開關 在之前的討論中，我們具體說明載入於映射暫存器欄 位之四個値可用於代表四個邏輯資料埠間所有的可能規劃 ，及連接在五個實體埠上不論是否有冗餘碟片控制器之1 ' 2或4碟片控制器陣列；及具冗餘碟片控制器且不論是 否有無效碟片控制器之陣列。接下來會描述如何利用映射 暫存器內容來規劃硬體塊及資料路徑。接下來之討論，換 句話說，介紹目前首選資料路徑開關2 6實施型態細節， 及它是如何被映射暫存器內容所規劃。 現在參考圖5 A，四個邏輯資料埠每個必須能接收從 實體資料埠五個當中任一個之資料，但若碟片控制器無效 ，則必須從碟片讀取互斥或取得。六個可能資料來源使每 個實體資料ί阜有一個十六位兀寬對應之六對一多工器50 。圖5Α顯示邏輯埠1之多工器50，但其他（給邏輯埠#〇 、#2及#3 )爲相同的。多工器選取器或'、S〃之輸入連接 到映射暫存器邏輯埠#1欄位一'' PP —L1 〃 。PP —L] 0到 4 -13-One of the synchronous redundant data transfer characteristics described in U.S. Patent No. 6,018,778 is that it allows redundant data to be processed at a rapid rate as described in U.S. Patent No. 6,237,052. Figure 3A shows the four disc controller arrays in Figure 2A plus logic 3 6 to make the redundant data pattern stored in the physical port #4 disc controller complete. Although various arithmetic and logic 3 calculations can be used to create a redundant mode, the logical mutual exclusion between the corresponding bits of the data is obtained from the logical data, or it is advantageous in arithmetic operations because the mutual exclusion or operation does not need to transmit a carry. Due to the exclusive use or use, the fifth disc controller is usually referred to as a 'redundant 〃 disc controller or ', a co-located disc controller. The 丨6-bit wide buffers shown in the figure are mutually exclusive or equivalent to sixteen mutually exclusive or gates, each with four inputs. As can be seen in Figure 3B, the mutual exclusion or function is also symmetrical in the operation of the disc controller read and the disc controller write. Figure 3B shows the same array of four disc controllers as defined in Figure 3A, while the data path 40, 4 2, etc. shows the disc controller read direction. In this example, the disc controller connected to entity 埠# 2 is invalid. Therefore, the corresponding non-functional data path 4 4 is shown by a broken line. Mutually exclusive or function is from the existing data disc controller (entity 埠# 0, # I and # 3) and redundant disc control -10- 1278752: 1 - „ ·.., ' ------ - -I ....., (8) Controller entity 埠 #4 calculated. This calculation fixes the data stored in the invalid disc controller and the result is directly transferred to the logic 埠#2 via the data path 46. The useless data from the invalid disc controller. The previous paragraph specifies some examples of the various relationships between a set of logic and a set of physical devices that may exist in a RAID controller. In general, high-efficiency RAI D controllers are forced to process A plurality of arrays consisting of various subgroups of entities connected to a mass storage device. In one aspect of the invention, a novel mapping register is associated with logic to make software planning of the storage device array feasible, and The efficiency is improved, which will be further explained below. According to an embodiment of the invention, Figure 4 shows the structure of a mapping register 24, which controls the planning of the data path between the logical and physical data. (The mapping register also has Other features and advantages that will be described later.) Here In the embodiment, the mapping register is composed of five fields, each of which gives five logical data, in this case L0-L4. The logical data corresponding to each field in the register is connected to the entity. The number of the data is loaded. The data of the logical data field is represented by the symbol PP_LO to represent the entity 埠 associated logic 埠 0. Then the four fields are PP_L1, PP_L2, PP_L3 and PP-L4. The five logical data is a false alarm. PP is used to allocate a physical data to the same-level disc controller. The mapping register field can be almost any size. For example, the octet field can be used. Supports an array of 256 entities. For an embodiment with only five entities, the three-bit field is sufficient. The five fields are cleverly made into a six-bit scratchpad, with one spare The element is marked as '' r 〃 -11 - (9) 1278^ in the figure. ''Retained 。. Any form of non-volatile memory can be used to store the mapping register data. To specify the mapping temporary storage For the function of the device, we will briefly review the plan described in each project. 2 A is not mapped to the register 2 4. The PP_LO is 〇 indicates that the logical data 埠#0 is connected to the entity 埠#〇. Then three 値1, 2 and 3 indicate that the next three logical data are connected to the next Three entity data 埠. The difference between PP_L4 is 7. In this example, this is not a legal entity 埠 number. '' 7 〃 値 is to indicate that there is no co-located disc controller in this plan. Strictly required, as long as it is not the actual entity number. Referring again to Figure 2B, stored in the map register indicates that the entity data 埠 1, 2, 4 and 0 support logic 埠 0 g [J 3 . Again, 'Ί' means that the co-located disc controller is not being used. Figure 2C shows the mapping register for two disc controller array plans. The logical data 埠#2 and #3 are associated with the same physical entity as the logical disk controllers #〇 and #1. The first two logics transmit data when the first entity loops, while the next two logics transmit data when the second entity loops. Figure 2D shows the mapping register as a single disc controller plan. Logic 〇#〇 to #3 continuously transfers data to entity 埠#3. All of the changes in Figure 2 are independent of redundant data logic for different data path planning displays. Figure 3A shows the disc write direction of the mutual exclusion or logic in the same data disc controller as in Figure 2A. Mutually exclusive or calculated from the data of four logical data. The result is stored in the disc controller connected to the entity specified by the mapping register logic 埠#4 field. In this example, PP_L4 is 、, 12-'' 4 〃 instead of w 7 〃 indicates that there is a co-located disc controller connected to #4埠. Figure 3B shows that the mutual exclusion or logic has the same data path as Figures 2A and 3A except that the disc controller connected to the actual 埠#2 is now invalid in the disc reading direction. The logical data 埠 2 field content is replaced by P P_L2 as '' 5 〃 . The legal entity 编号 is numbered 〇 to 4. , , 5 〃 is a reserved 以 to indicate that the disc controller is invalid. Any logical data entered into the number 5 false entity will obtain data from the exclusive or output. Data Path Switch In the previous discussion, we specified that the four fields loaded in the Map Register field can be used to represent all possible plans between the four logical data, and connected to five entities, whether or not there is A 1 '2 or 4 disc controller array for redundant disc controllers; and an array with redundant disc controllers and with or without an invalid disc controller. Next, we will describe how to use the map scratchpad content to plan hardware blocks and data paths. The discussion that follows, in other words, introduces the details of the current preferred data path switch implementation and how it is planned by mapping the contents of the scratchpad. Referring now to Figure 5A, each of the four logical data must be capable of receiving data from any of the five physical data, but if the disc controller is invalid, the mutual exclusion or acquisition must be read from the disc. The six possible sources of data provide a six-to-one multiplexer 50 for each entity data. Figure 5 shows the multiplexer 50 of logic 埠1, but the others (for logic 埠#〇, #2, and #3) are the same. The multiplexer selector or the input of ', S〃 is connected to the mapping register logic 埠 #1 field one '' PP — L1 〃 . PP —L] 0 to 4 -13-
(11) 之値各別選取從實體埠#〇到#4之資料，然而、' 5 〃之値則 選取碟片讀取互斥或之輸出。 圖5B顯示碟片讀取互斥或邏輯52。碟片讀取互斥或 5 2爲一五個輸入之互斥或電路，在此首選實施例中爲十 六位元寬.（對應於連接之碟片控制器資料路徑）。（這等 同於十六個互斥或，每個有五個輸入）。五個輸入每個皆 被對應之及閘所邏輯性地符合或、、攔住〃，及閘5 4爲例 也是十六位元寬。（這等同於十六個反及閘，每個有兩個 輸入）。五個反及閘被對應之五個實體埠選取訊號所符合 ，PP〇_SEL至PP4_SEL。下面將描述這些訊號的產生。 實體埠每個資料路徑可從四個邏輯資料埠當中任一個 而來，或從碟片寫入互斥或而來。參考圖 2A-2D來顯示 此例子。雖然映射暫存器欄位具體說明了每個邏輯資料埠 之資料來源，但我們沒有一個欄位可以提供每個實體埠對 應之資料。此資訊可由我們所具有之欄位來取得。映射暫 存器每個三位元二進位編碼欄位利用 '、一對八〃解碼器來 解碼。圖6顯示邏輯埠# 1欄位之解碼器6 6。P P _ L 1之値 解碼成L1_P0、LI—PI、L1_P2…L1_P7，而名表示從起源 至終點之路徑。以L1__P2爲例’表示從邏輯埠#1至實體 埠#2之路徑。 現在參考圖7A ’顯示從邏輯資料埠到實體資料埠（ #0^4 )多路傳輸資料路徑70之電路圖例子。圖中顯示實 體埠#2之多工器72，其餘四個埠之多工器（無顯示）爲 相同的。每個多工器72包含一個及/或陣列及五個及閘74 - 14- 1278752 (12) ，全部皆爲十六位元寬，及一個對應或閘76。（每個及 閘等同於十六個及閘，每個皆有兩個輸入。而或閘等同於 十六個或閘，每個皆有五個輸入。）對於實體埠#2多工 器’從邏輯資料埠之及閘被對應之五個解碼器輸出所符：# ，即如所示爲 L0_P2 、 LI—P2 、 L2—P2 、 L3—P2 ，及 L4 P2 在這個點上，有兩個開放性問題要解決。在一兩個|碟 片控制器陣列中，指定實體埠透過不同的循環接收從兩個 不同的邏輯ί阜而來的資料。再回去參考圖6，每個解碼器 6 6都有一符合所有它的輸出之起動輸入'' ΕΝ 〃 。而對於 兩個碟片控制器規劃，只有邏輯資料埠#〇及# 1之解碼器 在第一循環時可使用，且只有邏輯資料埠#2及#3之解碼 器在第二循環時可使用。爲此，圖7Α之及閘每次只有一 個可符合。換句話說，只有從指定邏輯璋之資料（依據映 射暫存器）被輸入到對應的實體埠。 在單一實體埠從所有四個邏輯埠（見圖2D )接收資 料之單一碟片控制器中，每次只有一個解碼器6 6可使用 以使及閘74在每次選取特定資料來源（邏輯埠）時只有 一個可使用。另一個開放性問題爲圖5Β之''PPn_SEL" 訊號來源。當主電腦實體埠與任何邏輯埠間有資料路徑時 ，圖6顯示可確立實體埠'' PPn_SEL訊號之五個輸 入或閘68的應用。這表示實體埠爲可用的且可參與圖5B 之碟片讀取互斥或。 -15- (13) 整體讀取&寫入 依照 ATA/ATAPI之詳述，傳送指令到碟片控制器需 要利用已程式設計對於只能支援P I 0型態0之裝置每次存 取速度可能會慢到600nS，而對於支援型態4之裝置，則 每次存取速度亦不超過120n S之10或PIO型態。單獨一 個指令需要八或更多的存取次數。如果所有的碟片控制器 需要依序地控制，則時間將與碟片控制器數目成倍數且在 整個過程中增加相當多的潛在因素。此指令可由每個埠之 獨立控制器所同時發出，但這也在複雜性及價格上增加相 當多。 當資料被碟片控制器陣列切成條狀後，部分指定條會 在每個碟片控制器相對同樣的位置上。這使每個碟片控制 器資料的位址即邏輯緩衝器位址或LBA相同。因此，對 於所有碟片控制器陣列讀取指定條的指令皆相同。且寫入 指定條的指令也一樣爲相同的。這使邏輯控制器（例如， 圖1中2 0 )不用花費比傳送指令給單一碟片控制器所需 時間更多就可以'' 播放〃共通的指令。 如之前所述，——碟片控制器陣列包含連接之碟片控制 器子集。（本發明其中一項優勢爲可以輕易地利用儲存適 當的位元到映射暫存器來規劃或重新規劃連接之碟片控制 器組織並將之變成淸晰的陣列。）在一陣列包含連接之碟 片控制器子集情況下，指令（如同讀取與寫入）只會 '、播 放〃到選取之子集。碟片控制器必須 逐一被控制，不然提供一些手段來''僞裝〃現行陣列 •16-(11) The data from the entity 埠#〇 to #4 is selected separately. However, the '5 〃 选取 selects the disc to read the exclusive or the output. Figure 5B shows disc read exclusive or logic 52. Disc read mutexes or 52 is a mutexes or circuit of five inputs, which in this preferred embodiment is sixteen bits wide (corresponding to the connected disc controller data path). (This is equivalent to sixteen mutually exclusive or each with five inputs). Each of the five inputs is logically matched or blocked by the corresponding gate, and the gate is also hexadecimal. (This is equivalent to sixteen anti-gates, each with two inputs). The five inverse gates are matched by the corresponding five entities 埠 selection signals, PP〇_SEL to PP4_SEL. The generation of these signals will be described below. Entity 埠 Each data path can be from any of the four logical data, or from the disc writes to each other. This example is shown with reference to Figures 2A-2D. Although the mapping register field specifies the source of each logical data, we do not have a field to provide information for each entity. This information can be obtained from the fields we have. Each three-bit binary encoding field of the mapping register is decoded using a ', a pair of gossip decoders. Figure 6 shows the decoder 66 of the logical 埠#1 field. P P _ L 1 is decoded into L1_P0, LI_PI, L1_P2...L1_P7, and the name represents the path from the origin to the end. Taking L1__P2 as an example, the path from logical 埠#1 to entity 埠#2 is indicated. Referring now to Figure 7A', there is shown a circuit diagram example of a multiplexed data path 70 from a logical data to a physical data # (#0^4). The figure shows the multiplexer 72 of the actual 埠#2, and the remaining four multiplexers (not shown) are identical. Each multiplexer 72 includes one and/or an array and five and gates 74 - 14 - 1278752 (12), all of which are sixteen-bit wide and one corresponding or gate 76. (Each gate is equivalent to sixteen gates, each with two inputs. The gate is equivalent to sixteen or gates, each with five inputs.) For entities 埠#2 multiplexer' From the logical data, the gate is corresponding to the output of the five decoders: #, as shown as L0_P2, LI-P2, L2-P2, L3-P2, and L4 P2. At this point, there are two Open issues need to be resolved. In one or two | disc controller arrays, the specified entity receives data from two different logics through different loops. Referring back to Figure 6, each decoder 66 has a start input '' ΕΝ 符合 that matches all of its outputs. For the two disc controllers, only the logic data 埠#〇 and #1 decoders can be used in the first loop, and only the logic data 埠#2 and #3 decoders can be used in the second loop. . For this reason, only one of the gates in Figure 7 can be met at a time. In other words, only the data from the specified logic (in accordance with the mapping register) is input to the corresponding entity. In a single disc controller that receives data from all four logical ports (see Figure 2D) in a single entity, only one decoder 6 6 can be used at a time to cause the gate 74 to select a particular data source each time (logic 埠Only one can be used. Another open question is the ''PPn_SEL" signal source in Figure 5. When there is a data path between the host computer entity and any logic, Figure 6 shows the application of five inputs or gates 68 that can establish the entity 埠'' PPn_SEL signal. This means that the entity is available and can participate in the disc read exclusive or of Figure 5B. -15- (13) Overall read & write According to the details of ATA/ATAPI, the transfer of instructions to the disc controller needs to be programmed. For devices that can only support PI 0 type 0, each access speed may be It will be as slow as 600nS, and for a device with support type 4, the access speed will not exceed 10% of the 120n S or PIO type. A single instruction requires eight or more accesses. If all of the disc controllers need to be controlled sequentially, the time will be multiplied by the number of disc controllers and considerable potential factors will be added throughout the process. This instruction can be issued simultaneously by each of the individual controllers, but this adds a significant amount of complexity and price. When the data is cut into strips by the disc controller array, some of the specified strips will be in the same position for each disc controller. This makes the address of each disc controller data the same as the logical buffer address or LBA. Therefore, the instructions for reading the specified bar for all disc controller arrays are the same. The instructions for writing to the specified bar are also the same. This allows the logic controller (e.g., 20 in Figure 1) to "play" the common command without spending more time than transferring the command to a single disc controller. As mentioned earlier, the disc controller array contains a subset of the connected disc controllers. (One of the advantages of the present invention is that it can be easily utilized to store the appropriate bits to the map register to plan or re-plan the connected disc controller organization and turn it into a clear array.) In the case of a subset of disc controllers, the instructions (like reading and writing) will only be 'played' to the selected subset. The disc controllers must be controlled one by one, otherwise provide some means to ''camouflage the current array.
wWmE (14) 所未參與之實體資料埠。圖8顯示一討論此議題之實施型 態。 參考圖8，顯示實體埠五個當中前面兩個（Ρ0及Ρ1 )的位址、脈衝.、晶片選取訊號 CSO、CS1、DAO、DA1 、D Α2、DIOW及DIOR。要注意到這些位址及脈衝訊號在 所有五個埠中爲共通的。它們被獨立緩衝以使指定碟片控 制器之無效不會阻擋這些訊號傳播到其他碟片控制器。見 緩衝器8〇、82。指定裝置兩個晶片選取訊號CSO#、CS1# 之輸出碟片控制器被該埠之Pn_SEL訊號所符合；見閘84 、8 6。任何不被映射暫存器現行內容所選取之埠的晶片選 取將不被確立且因此會忽略讀取與寫入脈衝。 整體讀取〃意味著潛在衝突資料値被共匯流排所回 送似乎會顯得不合乎常理。在現行實施例中，、、整體讀取 "會造成一讀取脈衝，圖8 Pn_DIOR#，被、'播放々到所 有實體資料埠。那些被晶片選取（Pn —CSO#、Pn —CS1# ) 所符合之連接儲存裝置會回送資料到Pn_D I OR#脈衝後緣 鎖定處之實體埠。這個讀取循環結果並無意圖將資料値會 送到局部控制器。 局部控制器會在不造成Pn_DI0R#脈衝循環重複及任 何鎖定資料改變的情況下利用不同位址來逐一讀取每個填 。這些循環允許局部控制器取出存入每個資料閂鎖中的潛 在獨特値。需要600Ns之 Pn_DIOR#循環只實施過一次。 鎖定於每個埠中.之値各可以藉由重複五次p n_ D !〇R #循環 來顯著節省時間地在1 5 n S內取出。 -17- 1278752 / (15) ''整體讀取〃及 ''整體寫入〃設備允許局部控制器在 可能的最短時間內傳送指令及接收從現行選取陣列之狀態 。當一不同的子陣列藉由載入一新的値到映射暫存器來被 選取時，控制器介面會在不改變其他代碼的情況下自動更 新。 狀態排序 先前討論到許多實體埠輸出之產生及顯示它們是如何 被映射暫存器所操縱。這些埠每個也都有好幾個輸入訊號 。再一次，將這些訊號與邏輯碟片控制器關聯可以減少軟 體支出。舉例來說，每個碟片控制器都有一岔斷輸出以發 出控制器檢修需求之訊號。圖9顯示利用受映射暫存器 PP-LO値控制之多工器90來選取實體埠關聯邏輯資料埠 零之岔斷。每個邏輯資料埠都有一利用相對應PP_Ln値 來定位岔斷之相同多工器（在此未顯示）。在圖9中，緩 衝器92取得從各邏輯資料埠多工器（90等）選取之岔斷 。當局部控制器（圖1中2 0 )透過此緩衝器讀取岔斷狀 態，而岔斷會以邏輯資料埠順序從位元零位置之邏輯資料 埠零開始呈現。相同的技術可用於排序從實體資料埠包含 碟片控制器電纜ID訊號及內部FIFO狀態訊號所取得之 內部及外部訊號。此特性使本機韌體可以利用不同實體埠 數量多個陣列之共通次序代碼。一旦載入岔斷緩衝器92 ，所需狀態位元經常是任何選取陣列 ''已排序〃暫存器內 最不顯著的位元。位元的數目可掩蔽成實際埠的數量。 -18- 1278752-/ (16)wWmE (14) Entity data not involved. Figure 8 shows an implementation of this topic. Referring to FIG. 8, the address, pulse, and chip selection signals CSO, CS1, DAO, DA1, D Α2, DIOW, and DIOR of the first two (Ρ0 and Ρ1) of the five entities are displayed. It should be noted that these addresses and pulse signals are common to all five turns. They are buffered independently so that the invalidation of the specified disc controller does not prevent these signals from propagating to other disc controllers. See buffers 8〇, 82. The output disc controllers of the two wafer selection signals CSO#, CS1# of the designated device are matched by the Pn_SEL signal of the chirp; see gates 84 and 86. Any wafer selection that is not selected by the current contents of the mapped scratchpad will not be asserted and therefore the read and write pulses will be ignored. The overall read 〃 means that the potential conflict data is returned by the common stream, which seems to be unreasonable. In the current embodiment, , the overall read " will cause a read pulse, Figure 8 Pn_DIOR#, is, 'played to all physical data埠. Those connected to the memory device that are selected by the chip (Pn-CSO#, Pn-CS1#) will return the data to the physical port of the Pn_D I OR# pulse trailing edge lock. The result of this read cycle is not intended to send data to the local controller. The local controller will use a different address to read each fill one by one without causing Pn_DI0R# pulse loop repetition and any lock data changes. These loops allow the local controller to remove the potentially unique flaws stored in each data latch. The Pn_DIOR# loop that requires 600Ns has only been implemented once. Locked in each .. Each can be taken out in 15 n S with significant time savings by repeating the p n_ D !〇R # cycle five times. -17- 1278752 / (15) ''Overall read and ''integrated writes' devices allow the local controller to transmit instructions and receive status from the current selection array in the shortest possible time. When a different subarray is selected by loading a new port to the map register, the controller interface automatically updates without changing other code. State Sorting Previously, the generation of many entities' output and how they were manipulated by the mapped scratchpad were discussed. Each of these has several input signals. Once again, correlating these signals with a logical disc controller can reduce software expenditure. For example, each disc controller has a broken output to signal the controller's maintenance needs. Figure 9 shows the multiplexer 90 controlled by the mapped register PP-LO値 to select the entity 埠 associated logic data 零 zero. Each logical data has the same multiplexer (not shown here) that uses the corresponding PP_Ln値 to locate the break. In Fig. 9, the buffer 92 obtains a cut from each logical data multiplexer (90, etc.). When the local controller (20 in Figure 1) reads the interrupted state through this buffer, the interrupt will be presented in the logical data sequence starting from the logical data zero of the zero position of the bit. The same technique can be used to sort the internal and external signals obtained from the physical data, including the disc controller cable ID signal and the internal FIFO status signal. This feature allows the native firmware to utilize a common order code of multiple entities in multiple arrays. Once loaded into the burst buffer 92, the required status bits are often the least significant bits in the selected array ''scheduled' registers). The number of bits can be masked into the actual number of turns. -18- 1278752-/ (16)
岔斷ANY及ALL 從邏輯資料埠選取之岔斷可如同圖9所示可邏輯性地 進行及 94與或96以提供訊號''Interrupt ALL"及、、Breaking ANY and ALL from the logical data 岔 can be logically performed as shown in Figure 9 and 94 or 96 to provide the signal ''Interrupt ALL" and,
Interrupt A N Y 〃 。當局部控制器發出指令，且在任何資 料尙未被傳送之前，可能會想要知道關於從任何碟片控制 器之岔斷，因爲一或多個碟片控制器可能會駁回指令或有 —些其他錯誤。一旦碟片控制器開始傳送資料後，局部控 馨 制器會想要知道所有的碟片控制器何時確立岔斷訊號，因 爲這意味著指令的完整性。要知道這樣的實施型態使軟體 獨立於碟片控制器之數目。（以一兩個碟片控制器陣列來 ， 說，從每個裝置來的岔斷訊號在單一碟片控制器陣列中出 _ 現兩次，而在相同的碟片控制器中出現四次。and及 all訊號仍然正確地運作。） 邏輯位址映射 Φ 雖然大量的運轉時間軟體利用上述之整體指令及狀態 ，但對於存取個體裝置來初始化及處理特定裝置之錯誤仍 然有其必要條件。爲此，每個實體資料埠呈現在局部控制 器位址空間內特定位置上。在初始化的過程中，映射暫存 器以''身分〃模式載入，即邏輯裝置〇指向實體埠0，邏 輯裝置1指向實體埠1等。這使實體埠以控制器位址空間 內第一實體埠位置爲開始的次序呈現。一般操作時，邏輯 及實體碟片控制器映射會載入映射暫存器內。若從邏輯埠 -19-Interrupt A N Y 〃 . When the local controller issues an instruction and before any data is transmitted, you may want to know about the disconnection from any of the disc controllers, because one or more disc controllers may reject the instructions or have some Other errors. Once the disc controller begins transmitting data, the local controller will want to know when all disc controllers have established a break signal, as this means the integrity of the instructions. It is to be understood that such an implementation allows the software to be independent of the number of disc controllers. (In one or two disc controller arrays, it is said that the chopping signal from each device appears twice in the single disc controller array and four times in the same disc controller. The and and all signals still function correctly.) Logical Address Mapping Φ Although a large amount of runtime software utilizes the above-described overall instructions and states, it is still necessary to access individual devices to initialize and process specific device errors. To this end, each entity data is presented at a specific location within the local controller address space. During the initialization process, the mapping register is loaded in the ''identity mode'), that is, the logical device 〇 points to the entity 埠 0, the logical device 1 points to the entity 埠 1 , and so on. This causes the entities to be presented in the order beginning with the location of the first entity in the controller address space. In normal operation, the logical and physical disc controller maps are loaded into the map register. If from the logic 埠 -19-
YllWtW^r^^ 一一一 — i (17) 2接收一岔bi ’局部控制器會透過身分映射載入時存取實 體埠2之特定位址空間來存取岔斷碟片控制器。這使邏輯 碟片控制器檢修獨立於它們所連接之實體資料埠。 圖1 〇顯示一邏輯位址特色之硬體實施型態。當控制 器存取裝置埠空間之位址區域，一對八解碼器1 〇 〇會將控 制器位址五到七列解碼，並對各裝置定義三十二位元空間 。各空間的解碼會將對應埠N之解碼訊號即pn_DEC排序 。編碼七實際埠之解碼提供整體讀取之訊號。P7_DEC訊 號與各個其他解碼訊號1 02被OR使爲了該埠特定存取及 整體存取兩個原因而確立結果埠選取訊號Pn_SEL ( n = 0-4 ) 〇 各埠選取訊號被映射暫存器PP^Ln値所控制。一對 八解碼器104將P2_SEL訊號依據映射暫存器PP_L2値發 送，並產生一組L2_P0-CS形式的訊號以表示從邏輯埠2 到實體埠零之晶片選取。其他四個邏輯埠的一對八解碼器 也相同（在此未顯示）。 每個實體埠有五個輸入或閘，例如1 0 6。在此有顯示 實體埠#2之閘106。將晶片選取實體埠#2之五個不同來 源進行或在一起。單一碟片控制器子陣列之晶片選取會被 全部四個邏輯裝置所確立，而雙碟片控制器子陣列之晶片 選取會被兩個邏輯裝置所確立。 前面所述及圖示具體說明了一種形式映射暫存器之數 個不同例子；可稱之爲邏輯映射暫存器。如所述，提供定 義陣列每個邏輯碟片控制器一欄位，且在該欄位中之値表 -20- Ι27_23Γ -.-,.一，，...^.-^=-. 二·? ..·,.、，.,、.,w..,·,.—..r ., ... ,,^ . - 4 0〇) 示對應的實體埠編號。在另一個稱之爲實體映射的實施例 中，一暫存器提供每個實體埠或連接之碟片控制器一欄位 ，且在各欄位中之値表示對應的邏輯埠編號。這另一個映 射暫存器在接下來例子中有具體介紹。 假定四個碟片控制器爲了條狀資料定義一陣列。整塊 的條狀寬度以一特定順序存入各個可利用的碟片控制器中 。接下來重複著這個過程。舉例來說，第一塊資料（第5 、第9等也是）存入連接到實體埠#1之碟片控制器中。 第二塊資料（第6、第1 0等也是）存入連接到實體瑋#2 之碟片控制器中。第三塊資料（第7、第11等也是）存 入連接到實體埠#4之碟片控制器中。第一塊資料被放置 在邏輯碟片控制器0，第二塊資料被放置在邏輯碟片控制 器1，第三塊資料被放置在邏輯碟片控制器2，而第四塊 資料被放置在邏輯碟片控制器3。在此情況下，映射暫存 器之兩種型態如下述： -21 - 1278752 ” / (19) 邏輯映射： 邏輯璋# 3 2 1 0 値（實體 i阜） 0 4 2 1 實體埠# 4 3 2 1 0 値（邏輯 埠#) 2 - 1 0 3YllWtW^r^^ One-to-one — i (17) 2 Receive a bi ’ local controller accesses the defragmentation disc controller by accessing the specific address space of the 埠 2 when the identity map is loaded. This allows the logical disc controller to be serviced independently of the physical data to which they are connected. Figure 1 shows a hardware implementation of a logical address feature. When the controller accesses the address area of the device space, a pair of eight decoders 1 解码 解码 decodes the controller address five to seven columns and defines thirty-two bit space for each device. The decoding of each space sorts the decoded signal corresponding to 埠N, that is, pn_DEC. The decoding of the code seven actual 提供 provides the overall read signal. The P7_DEC signal and each of the other decoded signals 102 are ORed to establish a result for the two reasons of the specific access and the overall access. The selected signal Pn_SEL (n = 0-4) 〇 each selected signal is mapped to the register PP ^Ln値 is controlled. The one-to-eight decoder 104 transmits the P2_SEL signal according to the mapping register PP_L2 and generates a set of signals in the form of L2_P0-CS to indicate the wafer selection from the logical 埠2 to the physical zero. The other four logical 埠 pairs of eight decoders are also the same (not shown here). There are five inputs or gates per entity, such as 1 0 6 . Here, there is a gate 106 showing the entity 埠#2. Five different sources of wafer selection entities 埠#2 are taken together or together. The wafer selection of a single disc controller sub-array is established by all four logic devices, and the wafer selection of the dual disc controller sub-array is established by two logic devices. The foregoing and the illustrations illustrate several different examples of a formal mapping register; it can be referred to as a logical mapping register. As described, a column defining each logical disc controller of the array is provided, and in the field, the table -20- Ι27_23 Γ -.-,.1,,...^.-^=-. ·?..,.,.,.,.,w..,·,.—..r ., ... ,,^ . - 4 0〇) shows the corresponding entity number. In another embodiment, referred to as entity mapping, a scratchpad provides a field for each entity or connected disc controller, and the corresponding logical number in each field. This other mapping register is described in detail in the next example. Assume that the four disc controllers define an array for the strip data. The strip widths of the individual blocks are stored in a specific order in each of the available disc controllers. This process is repeated next. For example, the first piece of data (5th, 9th, etc.) is also stored in the disc controller connected to entity #1. The second piece of data (6th, 1st, etc.) is also stored in the disc controller connected to entity 玮#2. The third piece of data (7th, 11th, etc.) is also stored in the disc controller connected to entity #4. The first piece of data is placed in the logical disc controller 0, the second piece of data is placed in the logical disc controller 1, the third piece of data is placed in the logical disc controller 2, and the fourth piece of data is placed in the Logical Disc Controller 3. In this case, the two types of mapping registers are as follows: -21 - 1278752 ” / (19) Logical mapping: Logic 璋# 3 2 1 0 値(Entity i阜) 0 4 2 1 Entity 埠# 4 3 2 1 0 値(Logic 埠#) 2 - 1 0 3
本發明得由熟悉技藝之人任施匠思而爲諸般修飾，然 皆不脫如申請專利範圍所需的保護者。 [圖式簡單說明】 圖1爲一碟片陣列控制器的簡化方塊圖，該碟片陣列 控制器提供與主匯流排交互作用之主介面，及與多個附加 碟片控制器交互作用之碟片控制器介面。 圖2A爲一槪念圖，說明邏輯資料埠與實體資料埠之 間的直接連接；且顯示對應之映射暫存器內容。 圖2B爲一槪念圖，說明四個邏輯埠分配至可用的五 個實體資料埠例子；且顯示對應之映射暫存器pg g。 圖2 C爲兩個碟片控制器陣列之槪念圖，其中每個碟 片控制器分配至五個可用的實體資料埠之一；| @ 0 之映射暫存器內容。 圖2 D爲單一碟片控制器系統之槪念圖，其中邏輯土阜 -22- Γ*> 十.:* I278f5f (20) 0-3連續循環傳送資料至實體埠#3 ;且顯示對應之映射暫 存器內容。 圖3 A說明互斥或邏輯在圖2 a碟片控制器規劃之碟 片寫入方向；且顯示對應之映射暫存器內容。 圖3B顯示互斥或邏輯在與圖2A及3A相同資料路徑 之碟片讀取方向，除了附加在實體埠#2之碟片控制器現 爲無效外；且同樣地顯示對應之映射暫存器內容。The present invention has been modified by those skilled in the art, without departing from the scope of the claimed invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a simplified block diagram of a disc array controller that provides a main interface for interacting with a main bus and a disc that interacts with a plurality of additional disc controllers. Slice controller interface. Figure 2A is a commemorative diagram illustrating the direct connection between the logical data and the physical data; and the corresponding mapping register contents are displayed. Figure 2B is a commemorative diagram showing four logical 埠 assigned to the five available physical data ; examples; and the corresponding mapping register pg g is displayed. Figure 2C is a conceptual diagram of two disc controller arrays, where each disc controller is assigned to one of five available physical data; | @ 0 maps the scratchpad contents. Figure 2D is a commemorative diagram of a single disc controller system, in which the logical band -22- Γ*> X.:* I278f5f (20) 0-3 continuously transmits data to the entity 埠#3; Map the contents of the scratchpad. Figure 3A illustrates the mutual exclusion or logic in the disc write direction planned by the disc controller of Figure 2a; and the corresponding mapped register contents are displayed. Figure 3B shows the disc read direction of the same data path as the mutual exclusion or logic in the same data path as in Figures 2A and 3A, except that the disc controller attached to the entity 埠#2 is now invalid; and the corresponding map register is similarly displayed. content.
圖4爲映射暫存器結構的一個例子；陣列控制器中一 實施例之映射暫存器控制邏輯與實體資料璋間資料路徑之 規劃。 圖5 A爲邏輯璋# 1讀取資料路徑之多工器電路槪念圖 圖5 B說明陣列控制器中一實施例之碟片讀取互斥或 圖6說明對於陣列控制器中一實施例之映射暫存器邏 輯埠#1 ( PP_L1 )欄位之解碼器邏輯。 · 圖7 A爲陣列控制器中一實施例之邏輯璋至實體埠資 料路徑。（只適用於實體埠#2 ) 圖7 B說明陣列控制器中一實施例之碟片寫入互斥或 邏輯。 圖8說明碟片位址，選通及晶片選擇邏輯，使整體存 取指令可以存取目前選取之陣列。 圖9說明用於關聯邏輯碟片控制器之岔斷訊號邏輯。 圖1 〇說明邏輯定址之硬體實施型態。 -23- 1278753 (21) 【主要元件符號說明】4 is an example of a structure of a map register; a map register control logic of an embodiment of an array controller and a data path of an entity data. 5A is a logic 璋#1 multiplexer circuit for reading a data path. FIG. 5B illustrates a disk read repulsion of an embodiment of the array controller or FIG. 6 illustrates an embodiment for an array controller. The decoder logic that maps the scratchpad logic 埠#1 ( PP_L1 ) field. Figure 7A is a logical to physical data path for an embodiment of the array controller. (Applicable only to entity 埠 #2) Figure 7B illustrates disc write mutexes or logic in an embodiment of the array controller. Figure 8 illustrates the disc address, strobe and wafer selection logic so that the overall access instruction can access the currently selected array. Figure 9 illustrates the chopping signal logic for associating a logical disc controller. Figure 1 shows the hardware implementation of logical addressing. -23- 1278753 (21) [Key component symbol description]
10 碟片陣列控制器 12 主匯流排 14 碟片控制器 16 主介面 18 緩衝記億體 20 控制處理器 22 碟片控制器介面 2 4 映射暫存器 26 資料路徑開關 30 箭頭 5 0 多工器 52 碟片讀取互斥或邏輯10 Disc Array Controller 12 Main Bus 14 Disc Controller 16 Main Interface 18 Buffered Billion 20 Control Processor 22 Disc Controller Interface 2 4 Map Register 26 Data Path Switch 30 Arrow 5 0 Multiplexer 52 disc read mutual exclusion or logic
5 4 及鬧 66 解碼器 6 8 或閘 7 0 資料路徑 72 多工器 7 4 及閘 7 6 或閘 80 緩衝器 82 緩衝器 閘 •24- 845 4 and alarm 66 decoder 6 8 or gate 7 0 data path 72 multiplexer 7 4 and gate 7 6 or gate 80 buffer 82 buffer gate • 24-84
8 6 鬧 9 0 多工器 92 緩衝器 94 及閘 96 或閘 10 0 一對八解碼益 1 0 2解碼訊號8 6 闹 9 0 multiplexer 92 buffer 94 and gate 96 or gate 10 0 pair of eight decoding benefits 1 0 2 decoding signal
1 〇 4 —對八解碼器 1 0 6或閘 -25-1 〇 4 — to eight decoders 1 0 6 or gates -25-
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