1276939 九、發明說明： 【發明所屬之技術領域】 本舍明係關於一種調整倉.驻要批/ 古、土* 门正員載U執行效能之系統及其 万法，其可依據負载訊號，使季 b便糸統此於穩定狀態下動態調 整負載裝置之執行效能。 【先前技術】1276939 IX. Description of the invention: [Technical field to which the invention belongs] This book is about a system for adjusting the warehouse. The resident batch/the ancient and the soil* are carrying the U performance and its method, which can be based on the load signal. The season b is adjusted to dynamically adjust the performance of the load device under steady state conditions. [Prior Art]
10 15 、如圖1所不，在習知負載裝置執行效能的領測電路中， 電源供應器17係用以輸入高電壓準位（例如：i職特）之交 流電，並輸出低電壓準位(例如：12伏特)之直流電，以供應 負載裝置(例如：中央處理器u)運作時所需之電力，由於中 央處理nil消耗電力所需之電M準位（例如·· 13伏特）較電 源供應ϋΠ所提供之電壓準位為低，故藉由儲能電感财 儲能電容19之儲能能力，並配合pWM控制器15控制高間極 控制訊號Ugate及低閘極控制訊號Lgate，以分別控制開關器 161及開關器162之開啟/閉合狀態，使電源供應器17可提供 电力至中央處理器1丨。其中，開關器i 6丨所汲取之電力係由 電源供應器17所提供，PWM控制器15可依據中央處理器u 所汲取之電力大小而調整開關器161及開關器162之切換速 度，以滿足中央處理器i i於重負載或輕負載下之電力消耗。 由於中央處理器11的執行效能皆經由BI0S直接對調 整裝置12做設定，此調整裝置12可為頻率調整器或電壓調 整器，進而去控制時脈產生器Π及電壓控制器14對中央處 理為11進行超壓超頻或降頻降壓的執行效能調整動作，如 20 1276939 10 15 20 圖2a所不，習知技術欲對中央處理器n進行超頻時，由於 為了配合中央處理器“本身需穩定超頻的特性，所以必須 $對此中央處理器1](進行超壓然後再超頻，因此習知技術 常於系、統開始的同時就已由BIOS設定為超壓，以此預先超 壓的動作來配合後續超頻的需求，但由於系統開機後其電 壓即處於超壓狀態，因而此習知做法會造成不必要的功率 祕’且就算此中央處理器u不進行超頻之動作，電壓仍 :法IV回未超壓的狀態’再者此習知技術做法為單一超壓 ，頻杈式’所以無法在同一系統下，丨中央處理器η不同 :間的系統執行需求而改變其執行效能，除造成無法減少 能源的消耗外’且長時間的超壓更容易造成 的損毁率上昇，實造成制上之不便。 °σ11 /圖2b所述為習知技術於價測中央處理器u的負載狀態 後’欲對其中央處理11 11進行降頻之效能調整動作，且^ =合中央處理器im定降頻的特性，所以必須先降頻再降 D旦習知技術為了保護未降頻前系統可以穩定執行，因 彺在在系統開機的同時，則會經由㈣s設定電壓不做任 :調整’因為如果降壓後，中央處理器"尚未降頻或是才 :降頻時’將可能造成系統不穩定或當機，而無法達到 % ^而K U此白知技術無法對中央處理器丄丄 動態降頻降壓的動作，且若僅以降頻的方式來達成省 :，的、’其效果也有限’進而無法滿足使用者使用上之需 並造成使用上之困擾。 6 1276939 L發明内容】 本發明之目的係提供一 法，係依據實際負載所相對裝置執行效能之方 負載裝置之執行效能，此牛^號而動態地調整 置之負載狀態，並依據負載裝= 2:(A)偵測負載裝 況，判斷負載訊號是否大於一二=::負載狀 表示負載裝置欲執行超頻之動作 ^品界值’如成立則 供-控制訊號控制 執仃步驟(c);(c)提 10 15 20 羅，彳士㈣ 工制态，以對負載裝置進行升 反，亚U控制訊號控制一 仃开 負載裝置；(D)提供—超…°°停止供應時脈訊號至 日守脈產生态執行超頻之 從 ^ P ^ , 乍，以及（E)偵測時脈產生器是 至時脈產生器，以重斩J 运—啟動時脈供應訊號 Μ M、/ 重新供應時脈訊號至負《置。因此， 猎由此方法可經由超頻 之倉箭『炉… 设定’來偵測當負載裝置 1及^又為《進行超頻時，則進行負載裝置之工作 I:目的“訊號之調整，以達到動態調整負載裳置執行效 之方—目^'提供—種調整負載裝置執行效能 地，：負St:實際負載所相對應之-負載訊號，而動態 ===行效能，其包括步驟:⑷侧載 、、心、亚依據負載裝置之負載狀態而測得負載 =;二判斷負載訊號是否小於一降頻臨界值，如成= =表示負«置欲執行降頻之動作，並執行步㈣）；（c)提 ，控制訊號控制至—時脈產生器，以停止供應時脈訊號 7 25 1276939 至負載裝置；（D)提供一 使時脈產生哭勃—^ 、仃5至時脈產生器，以 已完成降頻之動作“⑹偵測時脈產生器是否 時脈產生+ β 傳啟動時脈供應訊號至 屋生^以重新供應時脈訊號 供一降壓勃耔#% … 戟衣置，以及（F)捻 〇 ^，以控制一電壓控制器對負載f置進行 ㈣之動作。因此，藉由此方 衣置進订 來禎測告自# # π j '、工甶F牛頻臨界點的設定， 行負载梦罟夕丫从兩、 义文局奴進仃降頻時，則進 整負葡奘罟拥… m虎之凋整，以達到動態調 正貞戟衣置執行效能之目的。 上述負载裝置較佳為一中.虛 顯千曰H 土 甲央處理杰（cpu)，但亦可為如 …、日日、南北橋晶片、記憶體等相關之負載裝置。 【實施方式】 有關本發明之調整負載裝置執行效能之方法之第 15 =施例’請先參照圖3所示之系統方塊圖，其係用來搭配 為明之方法使用’如圖3所示，電流負載偵測裝置”可依 據負載訊號，如：PWM工作週期訊號、高閉極控制訊號 Ugate《低閘極控制訊號Lgate之變化來調整負載裝置（例 如：中減理器311)的效能執行，本實施例係以pwM工作 週期訊號為例，PWM控制器35會依據中央處理器3ιι的負載 狀態之改變，而輸出-請社作週期訊號至電流負載侦測 裝置32’於本實施例中，此pWM工作週期訊號是由pwM控 制器35依據中央處理器311之負載狀態之改變，而調整？侧 訊號高/低準位維持時間所得來，再者電流負載偵測裝置Μ 1276939 會依據PWM工作週期訊號之變化，進而調整時脈產生器^ 及電壓控制器34之運作，其可用來增加或降低中央處理哭 3 11之日可脈汛號及工作電壓。此外，為了強化高閘極控制訊 號Ugate及低閘極控制訊號Lgate之驅動能力，使用者亦可於 5電源供應器37内之PWM控制器35之後端加入緩衝裝置％，' 其中，緩衝I置3 8可為正向器、反向器、緩衝器、或上述 元件之結合。 ^ 15 如圖4所示，電流負載偵測裝置32由準位取樣器、 頻率產生器322、計時器323、計數器324、暫存器％^以 及比較器326所組成。頻率產生器322是用來產生一高頻訊 號，例如：100K Hz之高頻訊號，並輸出高頻訊號至計時器 323。準位取樣器321可用來對pWM工作週期訊號進行取 樣’並輸出取樣訊號至計數器324。計時器切是於一單位 時間内計數高頻訊號之次數，例如：計數⑽個高頻訊號， 亚輸出單位時間訊號至計數器324。計數器似可用以 取樣訊號之次數，並於接收單位時間訊號之㈣，輸出累 加訊號至比較器326。比較器326接收到計數器似傳來之累 =號時，則會將此累加訊號與儲存於暫存器325内的臨界 =對’於本實施例中，暫存器325儲存有—超頻臨界 頻Γ界值，且此超頻臨界值與降頻臨界值除於本 儲存裝：：ΪΓ2? ’其亦可儲存在SRAM、記憶體等 抑Ϊ值^ Γ，超頻臨界值所相對應之效㈣大於降 机界值所相對應之效能，並依比對結果（超頻或降頻）來控 20 1276939 制時脈產生器33及電壓控制器34運作，以達到動態調整中 央處理器3 11之執行效能。 5 10 15 有關本發明之實施方法，請參照圖5所示之流程圖並— 併芩妝圖3所示之系統方塊圖，首先，於步驟S5〇丨中， 控制器35會铺測中央處理器3 11之負載狀態，並依據中央處 理器311之負載狀態而輸出pWM工作週期訊號至電流負載 偵測t置32，負載狀態示意圖請參照圖6所示，此時電流負 載偵測裝置32則會判斷PWM工作週期訊號是否大於超頻臨 界值A1，A2或降頻臨界值B1，B2(步驟S5〇2)，於本實施例中 超頻及降頻之判斷方法如下所述，將中央處理器3ιι之執行 效能區分成複數效能階、級’並設定每—效能階級所對應之 作頻率、工作電麼、臨界值以及反磁)帶值。如圖7所示， 較佳係將中央處理器311之執行效能區分成五效能階級，分 別為超高效能I階、高效能Π階、正常效能職（預設值）、 低效能IV階、以及超低效能¥階，且其工作頻率分別為預 設頻率提升1G%、預設頻率提升6%、預設頻率、預設頻率 降低6。/。、以及預設頻率降㈣％，卫作Μ分別為14” 1.35v、l.3v、my以及! 2〇v，臨界值較佳分別為d、 25以及15，反磁滯值較佳分別為47、23以及.由上 述中可知’如果工作頻率被提升者，則其反磁滞值將大於 U ;相反地’如果卫作頻率被降低者，則其反磁滞值 將小於臨界值，此乃因為中央處理器311之工作頻率改變將 造成令央處理器311之執行效能改變，而此執行效能之改變 所產生之負載與中央處理器311因運算處理（例如··執行大 20 1276939 型應用程式）所產生之負載無關，為了使中央處理哭叫之 執行效能的切換置於相同之比對基礎上，故需以反磁滞值 以進行相關之比對’使中央處理器311之執行效能之切換更 5 15 20 符合現實之狀況。可想而知地，使用者可依其需求而將執 仃ί能之效能階級數予以增加或減少，或改變臨界值與反 磁命值之值，或改變每一效能階級所對應之工作頻率或工 作電壓，並不以上述為限。 請一併參照圖6所示之超頻及降頻相關元件狀態示意 -於本貝施例中以臨界值A1來做為超頻操作之臨界值， 其臨界值A2判斷方式與臨界值A1相同，在此則不多加描 $，例如超頻臨界值^之負載狀態為35%，則當中央處理 益叫之負載狀態程度超過35%時，則表示中央處理哭叫 需=超塵超頻以調整執行效能，則電流負載偵測裝置％ 則昼輸出-控制訊號來控制電壓控制器34,對中央處理哭 ’並以此控制訊餘制時脈產生器3 3停止供應 =«至令央處理器311(步驟_)，因時脈訊號之頻率 右處於變動的狀況下使之達到超頻的頻率時，容易造成盆 哭 、 y、先兮止供應打脈訊號給中央處理 ::11、他相關元件，並提供一超頻執行訊號至時脈產生 以讓時脈產生器33將時脈訊號之頻率調至欲超頻之 目^頻率（步驟S504)，並持續㈣頻率是否已目 ^^5)，#時脈產生器33之時脈訊號頻率已達超頻^ 不”，則傳送—啟動時脈供應訊號至時脈產生器^ 11 1276939 5 10 15 20 =重新供應時脈訊號至中央處理器3ιι(步驟测），如此便 凡成中央處理益311超頻之動作（步驟S512)。 免再者’於步驟S5〇2中，於本實施例中以臨界值β2來做 间，牛^呆作之臨界值，其臨界值m判斷方式與臨界值扣相 於μ/ΓΙ不多加士描述’又如中央處理器311之負載狀態低 卢牛ν、品I值Β2時’例如臨界值扣為18%時，則表示中央 3器3U須進行降頻㈣之執行效能調整，此時為防止中 3=1若：降頻期間持續接收時脈產生器3職 置32會提供載偵測裝 哭价“J _時脈產生器％，以控制時脈產生 时33停止供應時脈訊號 電流負㈣測带置32二1 (步驟S5〇7)’然後 哭33貞f衣置32會再提供-降頻執行訊號至時脈產生 二二制時脈產生器33執行時脈訊號頻率下降之動作 (v知S508)，並持續偵測頻率 ⑽），並^㈣^ 周至降頻目標值（步驟 目把值日士田 之時脈訊號頻率已達降頻頻率的 訊Γ 流負载偵測裝置32會傳送一啟動時脈供應 ;;:u %脈產生器33 ’以重新供應時脈訊： 311(步驟S510)，當中央處 〒央處理益 則雷法自， 时·311已重新接收時脈訊號時， 則电，巩負载偵測裝置32會接著提 電虔控制器34對中央處理哭，川.隹 執订心虎來控制 ss丨丨、t 處益311進行降麼之動作（步驟 ，如此才完成中央處理器3 11降壓/降Λ 整（步驟S512)e 頻之執行效能調 作mr測裝置32除可由觸控制器35接收p购 …號外，如圖8所示’更可先由―緩衝裝置38來輸 工 12 127693910 15 , as shown in FIG. 1 , in the lead-test circuit of the performance of the conventional load device, the power supply 17 is used to input the alternating current of the high voltage level (for example, i), and output the low voltage level. The DC power (for example: 12 volts) is used to supply the power required to operate the load device (for example, the central processing unit u), and the power M level (for example, 13 volts) required for the central processing of nil to consume power is higher than that of the power supply. The voltage level provided by the supply unit is low, so the energy storage capacity of the energy storage capacitor 19 is stored, and the high-level control signal Ugate and the low-gate control signal Lgate are controlled by the pWM controller 15 to respectively The open/close state of the switch 161 and the switch 162 is controlled so that the power supply 17 can supply power to the central processing unit 1 . The power drawn by the switch i 6丨 is provided by the power supply 17, and the PWM controller 15 can adjust the switching speed of the switch 161 and the switch 162 according to the power drawn by the central processing unit u to meet the switching speed of the switch 161 and the switch 162. The power consumption of the central processing unit ii under heavy load or light load. Since the execution performance of the central processing unit 11 is directly set by the BI0S, the adjusting device 12 can be a frequency adjuster or a voltage regulator, and then the clock generator and the voltage controller 14 are controlled to be centrally processed. 11 Performing performance adjustment actions for over-voltage overclocking or down-conversion step-down, such as 20 1276939 10 15 20 Figure 2a does not, the conventional technology wants to overclock the central processor n, because it needs to be stable in order to cooperate with the central processing unit. Overclocking characteristics, so it must be $ for this CPU 1] (overvoltage and then overclocking, so the conventional technology is often set by the BIOS to overpressure at the same time as the system starts, the pre-overpressure action To meet the needs of the subsequent overclocking, but since the voltage of the system is in an overpressure state after the system is turned on, this conventional practice will cause unnecessary power secrets. And even if the central processing unit u does not perform the overclocking action, the voltage is still: IV back to the state of no overpressure 'again, this conventional technical practice is a single overpressure, frequency ' ' so can not be under the same system, 丨 central processor η is different: system execution needs In order to change the performance of the system, in addition to the inability to reduce the energy consumption, and the long-term overpressure is more likely to cause an increase in the damage rate, which is inconvenient to make. °σ11 / Figure 2b is the conventional technology at the price After measuring the load state of the central processor u, 'the performance adjustment action of the central processing 11 11 is to be down-converted, and ^=the central processor is sure to reduce the frequency characteristics, so it is necessary to first reduce the frequency and then reduce the D-day knowledge. In order to protect the system before the frequency reduction, the system can be stably executed, because when the system is powered on, the voltage will be set via (4) s: adjust 'because if the CPU is down, the CPU has not been down or : When the frequency is down, it may cause the system to be unstable or crash, but it cannot reach % ^. However, this technology cannot be used to dynamically reduce the frequency of the CPU, and if it is only down-converted. Province:, 'the effect is limited' and thus can not meet the user's needs and cause problems. 6 1276939 L content of the invention The object of the invention is to provide a method based on the actual load relative to the device Execution performance of the performance of the load device, dynamically adjust the load state, and according to the load installation = 2: (A) to detect the load condition, determine whether the load signal is greater than one or two =:: load The figure indicates that the load device is to perform the overclocking action. If the value is set, the control signal control execution step (c); (c) mention 10 15 20 Luo, the gentleman (4) the work state, to carry out the load device. Raise the reverse, sub-U control signal control to open the load device; (D) provide - super... ° ° stop supplying the clock signal to the day spur generation state to perform overclocking from ^ P ^, 乍, and (E) detection The clock generator is a clock generator that restarts the clock supply signal Μ M, / re-supplies the clock signal to negative. Therefore, this method can be used to detect when the load device 1 and ^ are "overclocking, then carry out the work of the load device I: the purpose" signal adjustment through the overclocking bin arrow "Settings" The dynamic adjustment of the load is performed by the effect--providing the performance of the load device: negative St: the actual load corresponding to the load signal, and dynamic === line performance, which includes the steps: (4) Side load, heart, and sub-measurement load according to the load state of the load device; second, determine whether the load signal is less than a down-conversion threshold, such as == indicates negative «destination to perform the down-converting action, and perform step (4) (c), control signal control to - clock generator to stop supplying clock signal 7 25 1276939 to the load device; (D) to provide a clock to generate a cry - ^, 仃 5 to clock generation The action of the frequency reduction has been completed. (6) Detect whether the clock generator generates the clock or the β pulse to start the clock supply signal to the house to re-supply the clock signal for a buck rash #% ... Set, and (F) 捻〇 ^ to control a voltage controller The action of the load f is set to (4). Therefore, by setting the square clothes to the order, the setting of the threshold point of the ## π j ', the work 甶 F 牛 频 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Then the whole negative Portuguese ... ... m m m m m m m m m m m m m m m m m m m m m m Preferably, the load device is a medium-sized virtual device (cpu), but may be a load device such as a day, a north-south bridge chip, a memory, or the like. [Embodiment] Regarding the 15th embodiment of the method for adjusting the performance of the load device of the present invention, please refer to the system block diagram shown in FIG. 3, which is used to match the method of the method as shown in FIG. The current load detecting device can adjust the performance of the load device (for example, the middle loader 311) according to the load signal, such as the PWM duty cycle signal and the high gate control signal Ugate. In this embodiment, taking the pwM duty cycle signal as an example, the PWM controller 35 outputs a periodic signal to the current load detecting device 32' according to the change of the load state of the central processing unit 3, in this embodiment, The pWM duty cycle signal is obtained by the pwM controller 35 according to the change of the load state of the central processing unit 311, and the side signal high/low level maintaining time is adjusted, and the current load detecting device Μ 1276939 operates according to the PWM. The change of the periodic signal, in turn, adjusts the operation of the clock generator ^ and the voltage controller 34, which can be used to increase or decrease the central processing pulse and the operating voltage. In addition, in order to enhance the driving capability of the high gate control signal Ugate and the low gate control signal Lgate, the user can also add the buffer device % at the rear end of the PWM controller 35 in the 5 power supply 37, where the buffer I is placed. 3 8 may be a forward converter, an inverter, a buffer, or a combination of the above components. ^ 15 As shown in FIG. 4, the current load detecting device 32 is composed of a level sampler, a frequency generator 322, a timer 323, The counter 324, the register %^ and the comparator 326 are formed. The frequency generator 322 is configured to generate a high frequency signal, for example, a high frequency signal of 100 kHz, and output a high frequency signal to the timer 323. The device 321 can be used to sample the pWM duty cycle signal and output a sampling signal to the counter 324. The timer cut is the number of times the high frequency signal is counted in one unit time, for example: counting (10) high frequency signals, sub output unit time signals Up to the counter 324. The counter seems to be used to sample the number of signals, and in the receiving unit time signal (4), the accumulated signal is output to the comparator 326. When the comparator 326 receives the accumulating number of the counter The accumulator signal is stored in the buffer 325 in the critical value = pair. In this embodiment, the register 325 stores an overclocking critical frequency threshold, and the overclocking threshold and the down threshold are In addition to this storage::ΪΓ2? 'It can also be stored in SRAM, memory and other suppression values ^ Γ, the corresponding effect of the overclocking threshold (4) is greater than the corresponding performance of the lower limit, and compare As a result (overclocking or down-conversion), 20 1276939 clock generator 33 and voltage controller 34 are operated to dynamically adjust the execution performance of the central processing unit 3 11. 5 10 15 For the implementation method of the present invention, please refer to the figure. The flowchart shown in FIG. 5 is the same as the system block diagram shown in FIG. 3. First, in step S5, the controller 35 will test the load state of the central processing unit 3 11 and according to the central processing unit 311. In the load state, the output pWM duty cycle signal to the current load detection t is set to 32. The load state diagram is shown in FIG. 6. At this time, the current load detecting device 32 determines whether the PWM duty cycle signal is greater than the overclocking threshold A1. A2 or down-frequency threshold B1, B2 ( Step S5〇2), in the present embodiment, the method for judging overclocking and down-converting is as follows: the execution performance of the central processing unit 3 ιι is divided into a plurality of performance levels, levels 'and the frequency corresponding to each performance level, Working power, threshold and diamagnetic). As shown in FIG. 7, the performance of the central processing unit 311 is preferably divided into five performance classes, namely, an ultra-high performance I-order, a high-performance level, a normal performance (preset value), and a low-performance IV stage. And the ultra-low performance ¥ step, and its working frequency is 1G% of the preset frequency, 6% of the preset frequency, the preset frequency, and the preset frequency are reduced by 6. /. And the default frequency drop (four)%, Wei Zuo is 14" 1.35v, l.3v, my and ! 2〇v, the critical values are preferably d, 25 and 15, respectively, the anti-hysteresis values are preferably 47, 23 and . As can be seen from the above, 'if the operating frequency is increased, the anti-hysteresis value will be greater than U; conversely, if the operating frequency is lowered, the anti-hysteresis value will be less than the critical value. Because the operating frequency of the central processing unit 311 changes, the execution performance of the central processing unit 311 is changed, and the load generated by the change of the execution performance is processed by the central processing unit 311 (for example, the implementation of the large 20 1276939 type application) The load generated by the program is irrelevant. In order to make the switching of the execution performance of the central processing crying on the same basis, the inverse hysteresis value is needed to perform the correlation comparison to make the performance of the central processing unit 311 Switching more 5 15 20 is in line with the reality. It is conceivable that the user can increase or decrease the number of performance levels of the 仃 能 energy, or change the value of the critical value and the diamagnetic value according to his needs. Or change the level of each performance class The operating frequency or operating voltage should not be limited to the above. Please refer to the state of overclocking and down-converting related components as shown in Figure 6 - in the example of this embodiment, the critical value A1 is used as the critical value of overclocking operation. The value of the threshold A2 is determined in the same manner as the threshold A1. Here, the value of the threshold A2 is not increased. For example, if the load state of the overclocking threshold is 35%, then when the load state of the central processing benefit is more than 35%, then It means that the central processing crying needs to be super-dust overclocking to adjust the performance. Then, the current load detecting device % outputs the control signal to control the voltage controller 34, and the central processing is crying, and the control system generates the clock. The device 3 3 stops supplying = «to the central processor 311 (step _), because the frequency of the clock signal is in a state of being changed to the frequency of overclocking, it is easy to cause the basin to cry, y, first stop the supply The pulse signal is sent to the central processing unit::11, its related component, and provides an overclocking execution signal to the clock generation to cause the clock generator 33 to adjust the frequency of the clock signal to the target frequency to be overclocked (step S504), and Continue (four) whether the frequency has been met ^^5 ), #脉脉器33's clock signal frequency has reached overclocking ^ No", then transmit - start clock supply signal to the clock generator ^ 11 1276939 5 10 15 20 = re-supply the clock signal to the central processor 3 ιι (step measurement), so that the central processing benefits 311 overclocking action (step S512). In the case of step S5〇2, in the present embodiment, the critical value β2 is used as the threshold value, and the critical value m is determined by the threshold value and the critical value is deducted from the μ/ΓΙ不多加士The description 'again, if the load state of the central processing unit 311 is low, and the value of the product I is Β2', for example, when the threshold value is 18%, it means that the central 3 device 3U has to perform the performance adjustment of the frequency reduction (4). Prevent the middle 3=1: If the continuous receiving period of the clock generator 3 is set during the down frequency, it will provide the load detection and crying price “J _clock generator % to control the clock generation 33 to stop supplying the clock signal current. Negative (four) tape set 32 2 1 (step S5 〇 7) 'then cry 33 贞 f clothes set 32 will be provided again - down frequency execution signal to clock generation two two system clock generator 33 to perform clock signal frequency drop Action (v know S508), and continuously detect the frequency (10)), and ^ (four) ^ Zhou to down frequency target value (steps to measure the value of the clock signal frequency of the Shishitian has reached the frequency reduction frequency of the stream load detection device 32 will transmit a start clock supply;;: u% pulse generator 33' to re-supply the pulse: 311 (step S510), when the center The central processing benefit is that when the time 311 has re-received the clock signal, the electric power, the gravity load detecting device 32 will then raise the power controller 34 to the central processing to cry, and the 隹. Ss丨丨, t 益 311 to perform the action (step, so complete the CPU 3 11 buck / down ( (step S512) e frequency execution performance tuning mr measuring device 32 in addition to the touch controller 35 receiving the p purchase number, as shown in Figure 8, 'more can be first used by the buffer device 38 to transport 12 1276939
入PWM控制器35依據中央處理器3丨丨之負載狀態之改變而 調整之高/低準位維持時間，且此緩衝裝置38接收pwM訊號 後並輸出一高閘極控制訊號Ugate，則電流負載偵測裝置32 亦可擷取此高閘極控制訊號11以化為PWM工作週期訊號，此 5 實施例僅訊號擷取點與上述實施例不同，其操作方式與上 述貝知例相同，故不再詳述。又如圖9所示，緩衝裝置3 $接 收PWM訊號後，亦可輸出一低閘極控制訊號乙料化，且電流 丨 負載偵測裝置32亦可擷取此低閘極控制訊號Lgau為pwM 工作調期訊號，此實施例此操作方式與達成功效皆與上述 10 實施例相同，在此則不多加描述。 再者，中央處理為311之負載狀態除了可藉由pWM訊 號測得，如圖10所示，中央處理器311之負載狀態亦可藉由 電流偵測電路91來偵測中央處理器311之汲取電流，並以所 測得之汲取電流而得知中央處理器311之負載狀態，並進而 15調整中央處理器311之執行效能，此實施例此操作方式與達 成功效皆與上述實施例相同，在此則不多加描述。又如圖 11所示，中央處理為3 11之負載狀態亦可藉由電壓偵測電路 92來偵測中央處理器311之工作電壓，並以此工作電壓而得 知中央處理器3 11之負載狀態，並進而調整中央處理器3丄丄 2〇之執行效能，此實施例此操作方式與達成功效皆與上述實 施例相同，在此則不多加描述。 、 如上所述，本發明利用負载訊號偵測來使負載裝置能 穩定地進行動態超壓超頻或降頻降壓的執行效能調整，並 以超頻及降頻臨界值的設定來達成動態調整執行效能之目 13 1276939 ☆使n统在執行超頻或㈣貞 行相對應之調整，除使負载裝置能發揮最大的 更可降低能源的耗損。 7執仃效月巨， 上述實施例僅係為了方便說明而舉例而已 主張之權利範圍自應以^專利所料準，=月所 於上述實施例。 _僅限 • 【圖式簡單說明】 圖1係習知技術之系統方塊圖。 10圖2a，圖几係習知技術之狀態示意圖。 圖3係本發明第一較佳實施例之流程圖。 圖4係本發明第一較佳實施例之狀態示意圖。 圖5係本發明第一較佳實施例之系統方塊圖。 圖6係本發明電流負載偵測裝置之功能方塊圖。 15圖7係本發明負載量化值、臨界值、工作電壓以及反磁滯值 之不意圖。 圖8係本發明第二較佳實施例之系統方塊示意圖。 圖9係本發明第三較佳實施例之系統方塊示意圖。 • 圖10係本發明第四較佳實施例之系統方塊示意圖。 .20 圖11係本發明第五較佳實施例之系統方塊示意圖。 【主要元件符號說明】 11中央處理器 12調整裝置 13時脈產生器 14電壓控制器 17電源供應器 18儲能電感 14 1276939 19儲能電容 15 PWM控制器 32電流負载偵測裝 34電壓控制器 323計時器 3 2 6比較器 91電流偵測電路 161開關器 3 5 PWM控制器 置311中央處理器 321準位取樣器 324計數器 38緩衝裝置 92電壓偵測電路 162開關器 33時脈產生器 322頻率產生器 325暫存器 3 7電源供應器The PWM controller 35 adjusts the high/low level maintenance time according to the change of the load state of the central processing unit 3, and the buffer device 38 receives the pwM signal and outputs a high gate control signal Ugate, then the current load The detecting device 32 can also capture the high gate control signal 11 to be converted into a PWM duty cycle signal. The signal extraction point of the fifth embodiment is different from the above embodiment, and the operation mode is the same as the above-described example, so More details. As shown in FIG. 9, after receiving the PWM signal, the buffer device 3$ can also output a low gate control signal, and the current load detection device 32 can also capture the low gate control signal Lgau as pwM. The operation timing signal, this operation mode and the achievement effect are the same as the above 10 embodiment, and will not be described here. In addition, the load state of the central processing unit 311 can be measured by the pWM signal. As shown in FIG. 10, the load state of the central processing unit 311 can also be detected by the current detecting circuit 91 to detect the CPU 311. The current is measured by the measured current, and the load state of the central processing unit 311 is known, and then the performance of the central processing unit 311 is adjusted. In this embodiment, the operation mode and the effect are the same as in the above embodiment. This is not much to describe. As shown in FIG. 11, the central processing unit 3 11 can also detect the operating voltage of the central processing unit 311 by the voltage detecting circuit 92, and know the load of the central processing unit 31 by using the operating voltage. The state and the performance of the central processing unit are adjusted. The operation mode and the effect of the implementation are the same as those of the above embodiment, and will not be described here. As described above, the present invention utilizes load signal detection to enable the load device to stably perform dynamic over-voltage over-frequency or down-conversion step-down performance adjustment, and achieve dynamic adjustment execution performance by setting overclocking and frequency reduction threshold values. Head 13 1376939 ☆ Make the n system perform the overclocking or (4) 贞 line corresponding adjustment, in addition to making the load device can maximize the energy consumption. The above-mentioned embodiments are merely exemplified for convenience of explanation, and the claimed scope of rights is to be determined by the patent, and the month is the above embodiment. _Only • [Simplified description of the drawings] Fig. 1 is a system block diagram of a conventional technique. Figure 2a is a schematic view of the state of the prior art. Figure 3 is a flow chart of a first preferred embodiment of the present invention. Figure 4 is a schematic view showing the state of the first preferred embodiment of the present invention. Figure 5 is a block diagram of a system in accordance with a first preferred embodiment of the present invention. Figure 6 is a functional block diagram of the current load detecting device of the present invention. Figure 7 is a schematic illustration of the load quantized value, threshold value, operating voltage, and anti-hysteresis value of the present invention. Figure 8 is a block diagram of a system in accordance with a second preferred embodiment of the present invention. Figure 9 is a block diagram showing the system of a third preferred embodiment of the present invention. Figure 10 is a block diagram of a system in accordance with a fourth preferred embodiment of the present invention. Figure 20 is a block diagram of a system in accordance with a fifth preferred embodiment of the present invention. [Main component symbol description] 11 central processing unit 12 adjustment device 13 clock generator 14 voltage controller 17 power supply 18 energy storage inductor 14 1276939 19 storage capacitor 15 PWM controller 32 current load detection device 34 voltage controller 323 timer 3 2 6 comparator 91 current detection circuit 161 switch 3 5 PWM controller set 311 central processor 321 level sampler 324 counter 38 buffer device 92 voltage detection circuit 162 switch 33 clock generator 322 Frequency generator 325 register 3 7 power supply
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