12744 ^(^twf.doc/g 九、發明說明： 【發明所屬之技術領域】 本毛明疋有關於半導體元件之一種熔絲結構，特別是 關於半導體元件中1具有至少-個熱緩衝區塊之炫絲結 構。 【先前技術】 隨著持'續增加的尺寸，半導體元件變得更容易受矽晶 體中缺陷或雜質所影響。單—二極體或電晶體的失效往往 ，成整個晶片的缺陷。為解決這個問題，在半導體元件中 常形成一些包括連接熔絲的冗餘電路。如果在製程之後發 現-個電路具有缺陷’可以用—贿絲轉換以將其禁能， 亚至能一冗餘電路。對於記憶體元件，缺陷記憶胞可以在 其位址重新設置-個好的記憶胞。在顏電路巾使用溶絲 的另一個理由是可以將例如是辨識碼的控制字元永久地程 式化至晶片中。 通常，熔絲是由複晶矽或金屬線所形声的，但是，熔 絲又可依知、其被燒斷(blown)成斷路(open)之方式，而分為 雷射熔絲(Laser fuse)，乃利用雷射而以雷射光束來割斷熔 絲，與電子熔絲(Electronic fuse)，經由電流通入燒炫或燒 斷熔絲而成斷路；電子熔絲多應用於如EEPROM之記憶元 件中，而雷射、熔絲多應用於如DRAM之記憶元件中。 對於雷射溶絲之設計而言，首先，一般的積體電路最 上層都覆蓋有氮化矽、二氧化矽或兩者堆疊而成的保護 層，在以雷射燒熔複晶矽熔絲或金屬熔絲時，為避免損及 12744 li)2twf.d〇c/g 該保護層，故以雷射方式燒熔熔絲通常需要在頂層令形成 一開口，且雷射需準確對準熔絲而不得摧毁其他鄰近元 件，但是，仍常常因能量過強而對上下層之保護層形成凹 洞等損傷。 對於複Ba石夕k絲而言，需施予一電墨而通入一足夠大 的電流以使其加熱，並使熔絲斷裂開來(rupture)，但是這 種技術需要施予相當大的電壓以燒熔熔絲；而隨著積體電 路的尺寸日漸縮小，則能提供之電壓也日益變小，所以設 • 計於複晶矽熔絲上添加一矽化金屬層（Silicidelayer)，而僅 . 冑外加—足夠電壓，即可造成斷路之效果。其機制是利用 • 通入電流加熱而加速電子遷徙，進而使熔絲上之矽化金屬 - 層與複晶矽產生凝聚作用，而造成矽化金屬層燒熔，並導 • 致複晶矽晶粒再成長。 而所谓燒斷溶絲成為斷路，可代表實際上將炫絲燒斷 裂開，造成熔絲結構不連續（斷裂）而為斷路，也可能是 僅將炫絲上之石夕化金屬層燒熔，或造成複晶石夕溶絲之燒斷 φ 後電阻(P〇St-burn resistance)增加至一相當高的地步，而被 視為斷路。 但疋，隨著製程條件與電壓範圍之變動，常在施予電 壓賴溶絲後，卻發現仍有殘餘炫融溶絲，或溶絲燒斷後 電阻並不穩定，而影響元件可靠性、降低整體電性表現。 此外，溶絲通入電流時產生之高熱，也常會導致周圍其他 元件結構過熱，而降低元件穩定性。 【發明内容】 12744102twfdoc/g 因此’需要一個可以低電壓燒溶，穩定且不會造成過 熱而損壞到周圍元件的溶絲結構。 本發明之—目的在提供半導體元射-種具熱緩衝 區塊之熔絲結構，避免過熱而提高熔絲結構可靠性。 、本發明之另-目的在提供—種可以以相#低的電壓/ 電流燒炫的炫絲結構，其中之熱緩衝區塊可有效分散^ %所產生之過熱現象，而在被入電流或燒炼時不會負面與 響周圍半導體結構的電性表現，提升半導體元件穩定声二 依照本發明一較佳實施例，提供一種炫絲結構，形成ς Ζ體兀件或是-積體電路中，輯結構包括：—第— 二：在二半導體基底上形成；—熔絲層’形成於第-絕緣 二/中溶絲層係具有多數個區塊，包括—第一區塊、 ::二二塊、一第三區塊、一第四區塊以及連接第 連結區塊，其中第二區塊與第三區塊係= 」 I、相區塊之間，連結區塊位於第二區塊與第 =之間，但與第二區塊與第三區塊並不相連，而除 相連，·一第-…ί 塊外’其他區塊彼此並不 声包人”1::ί 成在熔絲層上，其中第二絕緣 塞；以及一頂部層’形成在第二絕緣 塊，而基相連接’其中頂部層包括—熱緩衝區 Hi 塊透過多數個介層插塞與第二區塊與第： 為讓本發明之上、:;二與第四區塊並繼。 易隱’下文特舉較佳實施例，並配合所附圖式，作 7 12744 l^)2twfd〇c/^ 明如下。 【實施方式】 复施例 下例實施例將苓考附圖做一詳細說明，以使習知此技 藝者得以充分暸解，並可在不脫離本發明之精神及保護範 圍下加以修改，以下之說明其非本發明之限制，本發明的 保護範圍僅由申請專利範圍所定義。 圖1乃是一種熔絲結構之剖面示意圖，其乃是沿著圖 2所示之上視圖中Ι·Ι，方向所得之剖面結構。以下將^述圖 1所繪示之熔絲結構ίο及其相關製造流程，复士 構Η)乃形成於-半導體元件中或一積體電路中;其:= 一半導體基底100之上’該基底⑽更可包括冑半導體元 =(未繪示）形成於其中。接著，於該基底i⑻之上形成 -下絕緣層110。下絕緣層110包括一氧化層，例如是氧 ^石夕層或是旋塗式朗層的組合。然後再於下絕緣層110 土形成-料層12G。！！常娜絲層12G可以為複晶石夕斑 二屬石夕化合物之複合層，金財化合物包括㈣鈦、石夕化 八μ石夕化錄或碎化翻，也可是一金屬層或一金屬合金層， ί敕包括鈦、鶴、銘或銅等，而該炫絲層12G之厚度係可 t，事實上本發明情絲層的電阻係數可以藉著改變其 料’長度’寬度或厚度而調整。—般 較其他金屬線及内連線為高，以做為： ''Ό不霉 〇 然後，形成一上絕緣層13〇覆蓋該熔絲層12〇，而該 12744 i j緣層13G包括-氧化層，例如是氧切層歧旋塗式 ，璃層的組合。接著，形成_光阻 出介層洞135的位置。介層洞Si 目及大小可依據貫際所需而決定。多數 於上絕緣層η",用錢接後 = ::=Γ20。接著，移除未被光= 刀上、％緣層13G後’形成介層插塞140於介層洞135中。 二之=包括以濺鑛法形成填充介層洞的一金 屬層（未^韻著⑽餘以 ，介層插塞。然後，再形成一二 f4〇一f二頂部金屬塾層⑽於上絕緣層130及介職塞 丄4D上。 人則 電流於該第—頂部金屬墊層15G，電流經過 "層插基而進入炫絲層120，再經介層插塞140而傳 導至該第二頂部金屬墊層⑽；而電流亦可反向傳導，端 視半導體兀件之設計。圖2所示奸魏絲層之上視圖， 溶絲層12G係具有兩邊寬中間窄的形狀，也就是包含兩個 較寬區域122a、122b與介於其間之—個較窄區域124; 當電流（以虛線箭頭表示）由較寬區域122&經由其間之乾、 窄區域124而流向較寬區域mb時，由於較窄區域^ =積較為狹小，而導致其單位面積⑽通過之電流密度 較尚。而若電流反方向由較寬區域122b經由其間之較窄區 ，124而流向較寬區域122a時’同樣地，較窄區域124 單位面積内所通過之電流密度較高。 12744 因此相對於兩端較寬的區域122a、122b，其中間窄的 部分124可視為一個高阻抗的窄通道，使得在此區通過之 電流密度提高，而造成局部溫度增加，得以使局部區域之 電子遷移加速，該局部區域也就是燒熔點，故熔絲層120 之細窄部分124會燒熔斷裂，或是該局部區域之燒斷後電 阻增高至一程度，而造成斷路使電性中斷。由於上述熔絲 層的形狀設計，只需要一相對較小的電流/電壓即可燒熔熔 絲之局部。 但此種形狀設計仍有其他問題，包括在窄通道區域， 因此區通過之電流密度甚高（大電流）而使局部溫度升高， 而有過熱之情況發生，並使熔絲因高熱斷裂開來(thermal rupture) 〇 因此，本發明發展出一種具熱缓衝區塊之熔絲結構， 可在不增加整體熔絲結構電阻之情況下，避免熔絲過熱或 燒熔情況之產生。 在一較佳實施例中，熔絲結構乃形成p—半導體元件 中或一積體電路中，但是熔絲結構之設計乃包括一具熱緩 衝區塊之熔絲層。 圖3所示乃是依照另一較佳實施例所形成熔絲結構中 一具有熱緩衝區之炫絲層的上視圖。如圖3所示，溶絲層 300包括一第一區塊310、一第二區塊320、一第三區塊 330、一第四區塊340與連接第一區塊310與第四區塊340 之一連結區塊315，其中第二區塊320與第三區塊330係 位於第一區塊310與第四區塊340之間，連結區塊315位 12744 l^)2twfdoc/g 於弟一區塊320與弟二區塊330之間，但與第二區塊320 與第三區塊330並不相連，而除了連結區塊315連接第一 區塊310與第四區塊340外，其他區塊彼此並不相連。而 第二區塊320與第三區塊33〇透過介層插塞（未顯示）與 一熱緩衝區塊350相耦接，該熱緩衝區塊35()係與該熔絲 層300位於不同層’其僅透過介層插塞與第二區塊320與 第二區塊330耦接，而與第一區塊31〇與第四區塊34〇並 不相連或耦接。 • 大體上，依照此一較佳實施例所形成熔絲結構，若是 沿著圖3所示上視圖中剖面線14，所得之剖面結構，則與 ' 圖1所示大致相同，而製程步驟亦大致類似，故在此省略 • 而不贅述。而圖4所示乃是依照一較佳實施例所形成熔絲 - 結構之剖面圖，其乃是沿著圖3所示之上視圖中剖面線 II-II所得之剖面結構，熔絲結構4〇乃位於一半導體基底 400之上，包括一下絕緣層41〇覆蓋於基底之上，一熔絲 層300位於該下絕緣層41〇上，以及一上絕緣層43〇覆蓋 φ 該熔絲層300，其中該熔絲層300可以例如微影蝕刻方式 形成所需之圖案，並可依照製程設計所需調整其尺寸大 小。通常該熔絲層300可以為複晶矽與金屬矽化合物之複 合層，金屬石夕化合物包括石夕化鈦、石夕化钻、石夕化鎳或石夕化 在白，也可是-金屬層或一金屬合金層，金屬包括鈦、鎢、 鋁或銅等，而該溶絲層3〇〇之厚度係可調整；事實上本發 明中溶絲層的電阻係數可以藉著改變其材料，長度，寬度 或厚度而调整。-般而言，該炫絲詹之電阻係數較其他金 12744 屬線及内連線為高，以做為_理想之熔絲結構。該上絕緣 層430中並包括介層洞435，以例如微影製程而定義出其 位置，並在介層洞435中形成介層插塞44〇。介層插塞44() 所，用的材質可以是鈦、鎢或銅等，插塞數目及大小可依 據貫際所需而決定。如圖4所示，多數個介層插塞44〇是 位於上絕緣層430中，用來連接其上之一熱緩衝區塊35〇 與其下之該熔絲層300。該熱緩衝區塊35〇係位於該上絕 緣層430及介層插塞440上。該熱緩衝區塊35〇之形成方 法，包括形成一頂部金屬層45〇於該上絕緣層43〇及介層 插塞44〇上，再以例如微影侧方式圖案化該頂部金屬^ 450,而形成包括該熱緩衝區塊35〇與其他頂部金屬墊^ (未顯示）之圖案；該頂部金屬層450所使用之金屬材二 包括鈦、鎢、鋁或銅等，而該頂部金屬層之厚度係可調整， 而其圖案可依縣程設計所需調整其尺寸大小。該熱緩衝 區塊3如相較於該熔絲層之材質，具有較良好之熱傳導能 力，而幫助熱的傳導而散熱，而其他頂部金屬墊層（如圖 1 可作為熔絲結構之電流輸人墊’或連結溶絲結構 至積體電路之其他元件。 、、=參見圖3,當電流通人時’電流（以虛線箭頭表示） 之&動路徑為由第一區塊310經該連結區塊315，而流至 第：土塊340 ;由於該連結區塊315之面積遠較其所:接 之弟一與第四區塊來的狹小，而導致其單 之電流密度較高。所以相對於兩端較寬的區塊:所=" 其中間連接較窄的連結區塊315視為—個高阻抗的㈣ 12 12744 W2twfdoc/g 道，使得在連結區塊通過之電流密度提高 :得：穩定綱絲之局部或導致局部之燒斷二 二Ξ局也就是所謂之燒炫點。而若電流反方 向由弟四區塊340經由其間之該連結區塊315㈣向第一 區塊310時，同樣地，中間連接較窄的連結區塊仍之單 位面=内所通過之電流密度較高，而形成所謂之燒料。 由於熔絲通入電流時常會產生高熱，常會導致周 他兀件結構過熱，而降低元件穩定性。故相較於圖2之:: 計，此-較佳實施例之炼絲層·由於 _又 塊，其與電流路徑並不輕接’但與第一、第; 連之第H區塊_接，而提供—條新㈣= 徑，以4助通入電流時所產生高熱能有效地發散I、故 積杈狹窄的該連結區塊315因為流經電流密度較高而: 熱之虞時’由該熱緩衝區塊35G與其相輪之第 t Γί之效率之熱傳導路徑，可將燒溶點附近ί 產生之熱均勻7刀佈，而有助於散熱。 在另-較佳實施例中，炫絲結構同樣可形成於 或一積體電路中，但是熔絲結構之設計乃包括Ϊ 有至個熱緩衝區塊之炫絲層，較佳的是 ^ 緩衝區塊之熔絲層。 、 数個熱 -具= 广較佳實施例所形成熔絲結構中 於第一區塊51〇 ^第塊5r以及介 ，、弟一區塊520之間的一第一内區塊 13 12744120^砲崎12744 ^(^twf.doc/g IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a fuse structure of a semiconductor element, and in particular to a semiconductor element having at least one thermal buffer block [Historical Technology] [Prior Art] With the continued increase in size, semiconductor components become more susceptible to defects or impurities in the crystal. Failure of the single-diode or transistor tends to be the entire wafer. Defects. In order to solve this problem, redundant circuits including connecting fuses are often formed in semiconductor components. If a circuit is found to have defects after the process, it can be used to disable it. For the memory component, the defective memory cell can be reset at its address - a good memory cell. Another reason for using the melted wire in the Yan circuit towel is that the control character such as the identification code can be permanently programmed. Usually, the fuse is shaped by a polysilicon or a metal wire, but the fuse can be divided into an open circuit by means of knowledge, and it is blown into an open manner. Laser fuse, which uses a laser to cut the fuse with a laser beam, and an electronic fuse (Electronic fuse), which is opened by a current to burn or blow the fuse; the electronic fuse is more It is applied to memory components such as EEPROM, and lasers and fuses are mostly used in memory components such as DRAM. For the design of laser-dissolved filaments, first, the uppermost layer of a general integrated circuit is covered with tantalum nitride. a protective layer formed by stacking cerium oxide or both, in order to avoid damage to the protective layer of 12744 li) 2 twf.d 〇 c / g when using a laser to fuse a fuse or a metal fuse Laser-fired fuses usually require an opening in the top layer, and the laser needs to be accurately aligned with the fuse without destroying other adjacent components. However, the protective layer of the upper and lower layers is often concave due to excessive energy. Holes and other damage. For the complex Ba stone, it is necessary to apply an electric ink to pass a large enough current to heat it and break the fuse, but this technique needs to be applied to a considerable amount. The voltage is to melt the fuse; and as the size of the integrated circuit is gradually reduced, the voltage that can be supplied is also becoming smaller, so it is necessary to add a silicide layer to the polysilicon fuse, and only胄 Plus - enough voltage to create an open circuit effect. The mechanism is to use electric current to accelerate the migration of electrons, thereby causing coagulation of the deuterated metal layer and the polycrystalline silicon on the fuse, causing the deuterated metal layer to melt and lead to the recrystallization of the crystal grains. growing up. The so-called burnt-dissolved filament becomes an open circuit, which may actually break the skein of the skein, causing the fuse structure to be discontinuous (fracture) and being broken, or it may be only melting the stellate metal layer on the skein. Or the P 〇 St-burn resistance is increased to a relatively high level and is considered as an open circuit. However, with the change of process conditions and voltage range, it is often found that there is still residual fused filament after the voltage is applied to the dissolved filament, or the resistance is unstable after the filament is blown, which affects the reliability and lowering of the component. Overall electrical performance. In addition, the high heat generated when the filament passes through the current also often leads to overheating of other surrounding components and reduces component stability. SUMMARY OF THE INVENTION 12744102twfdoc/g therefore requires a filament structure that can be burned at a low voltage, stable, and does not cause excessive heat to damage surrounding components. SUMMARY OF THE INVENTION The object of the present invention is to provide a fuse structure for a semiconductor element-injection thermal buffer block to avoid overheating and improve fuse structure reliability. Another object of the present invention is to provide a sleek structure that can be ignited with a low voltage/current of a phase #, wherein the thermal buffer block can effectively dissipate the overheating phenomenon generated by the current, or During the smelting, the electrical performance of the surrounding semiconductor structure is not adversely affected, and the semiconductor element is stabilized. In accordance with a preferred embodiment of the present invention, a snagging structure is formed to form a Ζ 兀 body or an integrated circuit. The structure includes: - the second - is formed on the two semiconductor substrates; the - fuse layer 'formed in the first - insulating two / medium-soluble layer has a plurality of blocks, including - the first block, :: two Two blocks, a third block, a fourth block, and a connection block, wherein the second block and the third block are between the I and the phase blocks, and the link block is located in the second block. Between the second and the third, but not connected to the second and third blocks, except for the connection, · a -... ί block, 'other blocks are not accommodating each other' 1:: a fuse layer, wherein the second insulating plug; and a top layer 'formed on the second insulating block, and the base phase is connected' The middle top layer includes a thermal buffer Hi block through a plurality of via plugs and a second block and a first: for the present invention, the second and fourth blocks are succeeded. The preferred embodiment, in conjunction with the drawing, is made as follows: 7 12744 l^) 2twfd〇c/^ is as follows. [Embodiment] The following example embodiment will be described in detail with reference to the accompanying drawings. It is to be understood by those skilled in the art that the invention can be modified without departing from the spirit and scope of the invention. The following description is not to be construed as limiting the scope of the invention. A cross-sectional view of a fuse structure, which is a cross-sectional structure obtained in the direction of the top view shown in FIG. 2. The fuse structure ίο and its related manufacturing process are shown in FIG. , in the semiconductor device or in an integrated circuit; it: = above a semiconductor substrate 100 'the substrate (10) may further comprise a germanium semiconductor element = (not shown) formed therein. Forming a lower-under insulating layer 110 over the substrate i (8). The lower insulating layer 110 The oxide layer is, for example, a combination of an oxygen layer or a spin-on layer. Then, a layer 12G is formed on the lower layer 110. The normal layer 12G can be a polycrystalline stone. The second is a composite layer of Shixi compound, and the gold compound includes (4) titanium, Shi Xihua, 8μ Shi Xihua recorded or shredded, or a metal layer or a metal alloy layer, including titanium, crane, Ming or Copper or the like, and the thickness of the dazzling layer 12G is t. In fact, the resistivity of the inventive layer can be adjusted by changing the 'length' width or thickness of the material. Generally, other metal wires and interconnects are High, as: ''Ό不〇, then, an upper insulating layer 13 is formed to cover the fuse layer 12〇, and the 12744 ij edge layer 13G includes an oxide layer, such as an oxygen-cut layer spin coating , the combination of glass layers. Next, the position of the photoresist spacer layer 135 is formed. The size and size of the via hole can be determined according to the needs of the cross. Most of the upper insulation layer η", after the money is connected = ::=Γ20. Next, the interlayer plug 140 is formed in the via hole 135 by removing the uncovered light, the upper edge layer 13G. 2. The second layer consists of forming a metal layer filled with a via hole by sputtering. (There is no more than (10), the interlayer plug. Then, a second f4〇-f top metal layer (10) is formed to be insulated. The layer 130 and the dielectric plug 4D. The current flows in the first-top metal pad 15G, and the current passes through the layer to enter the skein layer 120, and then conducts to the second through the via plug 140. The top metal underlayer (10); and the current can also be reversed, looking at the design of the semiconductor element. Figure 2 shows the top view of the filth layer, the lyotropic layer 12G has a narrow width in both sides, that is, including Two wider regions 122a, 122b and a narrower region 124 therebetween; when current (indicated by a dashed arrow) flows from a wider region 122& through a dry, narrow region 124 therebetween to a wider region mb, Since the narrower region ^ = product is narrower, the current density per unit area (10) is higher. If the current is reversed from the wider region 122b via the narrower region 124, the flow to the wider region 122a is the same. Current, the current density passed through a narrow area 124 per unit area Therefore, 12744, therefore, the narrow portion 124 can be regarded as a high-impedance narrow channel with respect to the wider regions 122a, 122b at both ends, so that the current density in this region is increased, and the local temperature is increased, so that the local portion is increased. The electron migration in the region is accelerated, and the local region is also the melting point of the melting point. Therefore, the narrow portion 124 of the fuse layer 120 is melted and fractured, or the resistance of the local region is increased to a certain extent after the blow, thereby causing the electrical interruption of the circuit. Due to the shape design of the above fuse layer, only a relatively small current/voltage is required to burn a part of the fuse. However, there are still other problems in the shape design, including in the narrow channel region, so the current through the region The density is very high (high current) and the local temperature rises, and the overheating occurs, and the fuse is thermally ruptured. Therefore, the present invention develops a melting with a heat buffer block. The wire structure can avoid the occurrence of overheating or melting of the fuse without increasing the resistance of the overall fuse structure. In a preferred embodiment, the fuse structure forms p In a semiconductor device or in an integrated circuit, but the fuse structure is designed to include a fuse layer of a thermal buffer block. Figure 3 shows a fuse structure formed in accordance with another preferred embodiment. A top view of the silk layer of the thermal buffer. As shown in FIG. 3, the lysate layer 300 includes a first block 310, a second block 320, a third block 330, and a fourth block 340. One of the first block 310 and the fourth block 340 is connected to the block 315. The second block 320 and the third block 330 are located between the first block 310 and the fourth block 340. 315 bits 12744 l^) 2twfdoc/g is between the first block 320 and the second block 330, but is not connected to the second block 320 and the third block 330, except that the connection block 315 is connected first. Outside the block 310 and the fourth block 340, the other blocks are not connected to each other. The second block 320 and the third block 33 are coupled to a thermal buffer block 350 through a via plug (not shown), and the thermal buffer block 35 is different from the fuse layer 300. The layer 'couples with the second block 320 and the second block 330 only through the via plug, and is not connected or coupled with the first block 31〇 and the fourth block 34〇. • In general, the fuse structure formed in accordance with this preferred embodiment, if it is along the section line 14 in the upper view shown in FIG. 3, the resulting cross-sectional structure is substantially the same as that shown in FIG. 1, and the process steps are also It is roughly similar, so it is omitted here and will not be described. 4 is a cross-sectional view of a fuse-structure formed in accordance with a preferred embodiment, which is a cross-sectional structure taken along line II-II of the top view shown in FIG. 3, and the fuse structure 4 The semiconductor layer 400 is disposed on a semiconductor substrate 400, and includes a lower insulating layer 41 covering the substrate, a fuse layer 300 on the lower insulating layer 41, and an upper insulating layer 43 covering the φ. The fuse layer 300 can be formed into a desired pattern by, for example, photolithography etching, and can be adjusted in size according to the process design. Generally, the fuse layer 300 may be a composite layer of a polycrystalline germanium compound and a metal germanium compound, and the metal stone compound includes a stone of the earth, a stone, a stone, a stone, a stone, a stone, or a metal layer. Or a metal alloy layer, the metal comprises titanium, tungsten, aluminum or copper, and the thickness of the lyotropic layer 3 可 can be adjusted; in fact, the resistivity of the lyotropic layer in the present invention can be changed by the material, the length Adjust for width or thickness. In general, the resistance coefficient of the Hyun silk is higher than that of other gold 12744 lines and interconnects, as an ideal fuse structure. The upper insulating layer 430 includes a via 435, defines its position by, for example, a lithography process, and forms a via plug 44 in the via 435. The dielectric plug 44() can be made of titanium, tungsten or copper, and the number and size of the plugs can be determined according to the requirements. As shown in FIG. 4, a plurality of via plugs 44A are located in the upper insulating layer 430 for connecting one of the thermal buffer blocks 35'' to the underlying fuse layer 300. The thermal buffer block 35 is located on the upper insulating layer 430 and the via plug 440. The method for forming the thermal buffer block 35 includes forming a top metal layer 45 on the upper insulating layer 43 and the via plug 44, and patterning the top metal 450 by, for example, lithography. Forming a pattern including the thermal buffer block 35 and other top metal pads (not shown); the metal material used in the top metal layer 450 includes titanium, tungsten, aluminum or copper, and the top metal layer The thickness can be adjusted, and the pattern can be adjusted according to the design of the county. The thermal buffer block 3 has better thermal conductivity than the material of the fuse layer, and helps heat conduction and heat dissipation, while other top metal pads (as shown in FIG. 1 can be used as a fuse structure for current transmission). The human pad 'or joins the filament structure to the other components of the integrated circuit. ·, = see Figure 3, when the current is on, the current (indicated by the dashed arrow) & the path is the first block 310 The block 315 is connected to the first block: 340; since the area of the connecting block 315 is much smaller than that of the first block and the fourth block, the current density of the single block is high. Relative to the wider block at both ends: =" The concatenated block 315 with a narrow connection is considered to be a high-impedance (four) 12 12744 W2twfdoc/g channel, resulting in an increase in current density through the junction block: It is obtained that the part of the stabilizing wire or the partial burning of the second wire is the so-called burning point. If the current is reversed from the fourth block 340 via the connecting block 315 (four) to the first block 310 In the same way, the connection block with the narrow connection in the middle still has a unit surface = The current density passed through is higher, and the so-called burning material is formed. Since the fuse often generates high heat when it is passed into the current, it often causes the structure of the other parts to overheat and lower the stability of the element. Therefore, compared with Figure 2 :: The wire layer of the preferred embodiment is not lightly connected to the current path due to the _ block, but is connected to the first and the second block H, and provides a new (4) = diameter, the high thermal energy generated by the 4 assist current is effectively diverged I, so the connection block 315 with narrow accumulation is because the current density is high: when the heat is blocked The heat conduction path of the efficiency of the 35G and the phase wheel of the phase wheel can uniformly heat the heat generated in the vicinity of the melting point to 7 knives, thereby contributing to heat dissipation. In another preferred embodiment, the skein structure can also be formed in Or in an integrated circuit, but the design of the fuse structure includes a bristles layer having a thermal buffer block, preferably a fuse layer of the buffer block. Several heat tools = wide The fuse structure formed by the preferred embodiment is between the first block 51 and the block 5r and the block 520. a first inner block 13 12744120^Guazaki
Tr1；f 550 5 -肉塊0較靠近第-區塊510，第 於笛二肉/。較#近第二區塊52〇 ’而第三内區塊550介 ； 品塊530與第二内區塊540之間。 八母内區塊之形狀為兩端寬大而中間段細 Ϊ口亞=^ ΐ~内區塊530、、550是由三個區塊所組 第内區塊530是由兩端較寬之第一端區塊Tr1;f 550 5 - Meat block 0 is closer to the first block 510, and is the same as the flute. The second inner block 550 is adjacent to the second block 52 ; and the second inner block 540 is between the block 530 and the second inner block 540. The shape of the inner block of the eight mothers is the width of the two ends and the middle section is fine. The inner block 530, 550 is composed of three blocks. The inner block 530 is widened by the two ends. One end block
a、弟二端區塊53〇c與連接第一端區塊兄如與第二端 :A 〇C之第一連結區塊530b所組成，第二内區塊540 是^兩端較寬之第三端區塊5術、細端區塊遍與連 接第三端區塊54Ga與第四端區塊5條之第二連結區塊 540b所組，，而第三内區塊55〇是由兩端較寬之第五端區 塊55〇a、第六端區塊550c與連接第五端區塊550a與第六 女而區塊550c之第二連結區塊5通所組成。各端區塊之开） 狀可為多邊形’而不—定限為方形，且各連結區塊相對於 其連結之各端區塊較為窄細，但是其長度&寸係可調整。 而雖然各内區塊之形狀可類似啞鈴形，但各連結區塊與端 區塊之連接相對位置亦不一定要位於中間，而可視設計需 要任意調整。 雖然第一區塊510、第二區塊520以及介於第一區塊 510與第二區塊520之間的第一内區塊530、第二内區塊 540與苐三内區塊550彼此並不相連，但是有位於另一層 之多數個熱緩衝區塊會透過介層插塞（未顯示）耦接到炼 絲層的各區塊，因此電性連接到熔絲層的各區塊。亦即， 14 1274410 12112twf.doc/g 如圖5所示，一第一熱緩衝區塊515連接第一區塊5l〇與 第一内區塊530之第一端區塊530a，一第二熱緩衝區塊525 連接弟一内區塊530之第二端區塊530c與第三内區塊550 之第六端區塊550c，一第三熱緩衝區塊535連接第三内區 塊550之第五端區塊550a與第二内區塊54〇之第三端區塊 540a，以及一第四熱緩衝區塊545連接第二内區塊54〇之 第四端區塊540c與第二區塊520。各區塊係透過介層插塞 (未顯示）與不同層之熱緩衝區塊515、525、535、545 相耦接，該些熱緩衝區塊515、525、535、545係與該熔絲 層500位於不同層。 圖5A所示乃是依照另一較佳實施例所形成熔絲結構 中一具有多數個熱緩衝區之熔絲層的上視圖。請參照圖 5A，在另一實施例中，熔絲層5〇〇,包括一第一區塊51〇、 一第二區塊520及沈基在第一區塊51〇與第二區塊之間的 一内區塊530’，而各區塊彼此並不相連。其中，内區塊53〇, 是由三個區塊所組成，且其形狀例如是啞鈴形等具有一頸 部或腰部的矩形或橢圓形。此内區塊53〇，是由第一端區塊 530a、第二端區塊530c與連接第一端區塊530a與第二端 區塊530c之連結區塊530b所組成，而兩端的第一端區塊 530a及第二端區塊比連結區塊53〇b寬。同樣地，不同層 的熱緩衝區塊會透過介層插塞（未顯示）耦接到熔絲層的 各區塊，因此電性連接到熔絲層的各區塊。 接著，請繼續參考圖5A，一第一熱緩衝區塊515，連 接第一區塊510與第一内區塊53〇，之第一端區塊53〇，a， 15 1274410 12112twf.doc/s =-第二熱緩衝區塊525’連接第—内區塊蕭之第 塊530’c與第二區塊52〇。 °° 槿，著圖5所示上視圖中14,方向所得之剖面結 ’6. ’乃是依照另—魏實施綱 t之剖面圖’炫絲結構60乃位於一半導體基底_之^ =括-下_層61G錢於絲之上，-騎JI _位於 ;=層610上，以及-上絕緣層⑽覆蓋該二 Γ宏 料層谓可以例如微刻方式形成所需之 圖案，亚可依照製程設計所需調整其尺寸大小。通常該炼 絲層50G可以為複晶石讀金屬魏合物 化合物包括石夕化鈦，谈 金屬層或-金屬合金層，金屬包括鈦、鎢、紹或銅等，而 該炫絲層5GG之厚度係可調整；事實上本發明中溶絲層的 包阻係數相藉著改變其龍，長度，寬度或厚度而調整。 二般而言，該熔絲層之電阻係數較其他金屬線及内連線為 咼以做為理想之熔絲結構。該上絕緣層630中並包括 介層洞635，以例如微影製程而定義出其位置，並在介層 洞635中形成介層插塞64〇。介層插塞64〇所使用的材^ 可以是鈦、鎢或銅等，插塞數目及大小可依據實際所需而 決定。如圖6所示，多數個介層插塞640是位於上絕緣層 630中，用來連接其上之熱緩衝區塊與其下之熔絲層。例 如··該些熱緩衝區塊係位於該上絕緣層63〇及介層插塞64〇 上°亥些熱缓衝區塊之形成方法，包括例如··形成一項部 層660於違上、纟e緣層630及介層插塞640上，再以微影餘 16 1274410 12112twf.doc/g 刻方式圖案化該頂部層 如525、535與其他頂部 括該些熱緩衝區塊 Ληβ .. 屬墊Μ (未顯不）之圖案；該頂 口Ρ層660所使用之例如是金屬， 是可為多晶石夕。而該頂部層_之厚4可:ί 案可依照製程設計所需娜1 ’而/、圖 a 乃正其尺寸大小。該些熱緩衝區塊 才軏於抓4狀材f，具錄^ =傳導而散熱，而其他頂部金屬塾層:二：a, the second end block 53〇c is connected with the first end block brother and the second end: A 〇C first connection block 530b, and the second inner block 540 is ^ both ends wider The third end block 5, the thin end block is connected with the second connecting block 540b connecting the third end block 54Ga and the fourth end block 5, and the third inner block 55 is composed of The fifth end block 55A, the sixth end block 550c, which is wider at both ends, and the second connection block 5, which is connected to the fifth end block 550a and the sixth female block 550c, are formed. The opening of each end block may be a polygon 'not limited to a square shape, and each connecting block is narrower than the end blocks to which it is connected, but the length & inch can be adjusted. Although the shape of each inner block may be similar to a dumbbell shape, the relative positions of the connecting blocks and the end blocks are not necessarily located in the middle, and the visual design needs to be arbitrarily adjusted. The first block 510, the second block 520, and the first inner block 530, the second inner block 540, and the third inner block 550 between the first block 510 and the second block 520 are mutually They are not connected, but a plurality of thermal buffer blocks located in another layer are coupled to the respective blocks of the wire layer through a via plug (not shown), and thus are electrically connected to the respective blocks of the fuse layer. That is, as shown in FIG. 5, a first thermal buffer block 515 is connected to the first block 51a and the first end block 530a of the first inner block 530, a second heat. The buffer block 525 is connected to the second end block 530c of the inner block 530 and the sixth end block 550c of the third inner block 550. The third hot buffer block 535 is connected to the third inner block 550. The fifth end block 550a and the third end block 540a of the second inner block 54A, and a fourth thermal buffer block 545 are connected to the fourth end block 540c and the second block of the second inner block 54A. 520. Each block is coupled to a thermal buffer block 515, 525, 535, 545 of a different layer via a via plug (not shown), and the thermal buffer blocks 515, 525, 535, 545 are coupled to the fuse Layer 500 is located at a different layer. Figure 5A is a top plan view of a fuse layer having a plurality of thermal buffers in a fuse structure formed in accordance with another preferred embodiment. Referring to FIG. 5A, in another embodiment, the fuse layer 5〇〇 includes a first block 51〇, a second block 520, and a sink base in the first block 51〇 and the second block. An inner block 530', and the blocks are not connected to each other. Here, the inner block 53A is composed of three blocks, and its shape is, for example, a dumbbell shape or a rectangular or elliptical shape having a neck portion or a waist portion. The inner block 53A is composed of a first end block 530a, a second end block 530c and a connecting block 530b connecting the first end block 530a and the second end block 530c, and the first ends are The end block 530a and the second end block are wider than the link block 53〇b. Similarly, the thermal buffer blocks of the different layers are coupled to the respective blocks of the fuse layer through via plugs (not shown) and are thus electrically connected to the various blocks of the fuse layer. Next, referring to FIG. 5A, a first thermal buffer block 515 is connected to the first block 510 and the first inner block 53A, and the first end block 53A, a, 15 1274410 12112twf.doc/s The second thermal buffer block 525' connects the first block 530'c and the second block 52'. ° ° 槿, in the upper view shown in Figure 5, the resulting profile of the section '6. ' is in accordance with another - Wei implementation of the profile of the section of the 'throwing wire structure 60 is located in a semiconductor substrate _ ^ ^ - the lower layer 61G is on the wire, the - riding JI _ is located on the = layer 610, and the upper insulating layer (10) covers the two-dimensional macro layer to form the desired pattern, for example, in a micro-engraving manner, The process design needs to be resized. Generally, the wire layer 50G may be a polycrystalline stone read metal compound compound including a shixi titanium, a metal layer or a metal alloy layer, the metal includes titanium, tungsten, sho or copper, and the skein layer 5GG The thickness can be adjusted; in fact, the coefficient of resistance of the lyophilized layer in the present invention is adjusted by changing its length, length, width or thickness. In general, the fuse layer has a higher resistivity than other metal lines and interconnects as an ideal fuse structure. The upper insulating layer 630 includes a via 635, defines its position by, for example, a lithography process, and forms a via plug 64 介 in the via 635. The material used for the interlayer plug 64 can be titanium, tungsten or copper, and the number and size of the plugs can be determined according to actual needs. As shown in FIG. 6, a plurality of via plugs 640 are located in the upper insulating layer 630 for connecting the thermal buffer block thereon and the underlying fuse layer. For example, the thermal buffer blocks are located on the upper insulating layer 63 and the via plugs 64, and the method for forming the thermal buffer blocks includes, for example, forming a layer 660. The 纟e edge layer 630 and the via plug 640 are patterned by the lithography 16 1274410 12112 twf.doc/g pattern, such as 525, 535 and other tops including the thermal buffer blocks Ληβ.. It is a pattern of mats (not shown); the top layer 660 is made of, for example, metal, which may be polycrystalline. The thickness of the top layer _ can be: ί can be designed according to the process design Na 1 ' / / Figure a is the size of its size. The hot buffer blocks are only caught in the 4th material f, which has a heat transfer, while the other top metal layer is:
==構之電流輪入塾’或連_絲結構至積體電 ^ ^見圖5或圖5Α，當電流通入時，電流（以虛線 則頭、不）之流動路徑，例如為由第一區塊训經該些熱 緩衝區塊與該些内區塊，而流至第二區塊52();由於該些 内區塊之該些連結區塊53〇b、通、5條及53〇，b之面 積遠較其所連接之該麵區塊之馳顧塊來的狹小，而 導致其單位面積_通過之f流密度較高。所以相對於兩 端較寬的端區塊 530a、530c、550c、55〇a、540a、540c， 各内區塊之中間連接較窄的連結區塊⑽、55仙、M〇b 及530 b視為一個尚阻抗的窄通道，使得在連結區塊通過 之電度長：咼，局部溫度增加而導致局部之燒斷後電阻 變咼，該局部區域530b、550b、540b及530，b也就是所 谓之燒熔點。而若電流反方向由第二區塊52〇經由其間之 該些熱緩衝區塊與該些内區塊，而流向第一區塊51〇時， 同樣地’中間各内區塊之連接較窄的連結區塊53〇b、 550b、540b及530’b之單位面積内所通過之電流密度較 17 1274410 121 l2twf.doc/g 向，而形成所謂之燒熔點。 此外，基於製程設計需要，任何熱緩衝區塊的形狀也 可進行調整。因此，流過熱緩衝區塊之特定區域(例如是較 乍區域)的電流密度較高，則熱緩衝區塊之特定區域成為燒 熔點。另一方面，用以連接的介層插塞的電阻會被小心地 進行設計，因此，如果有必要的話，也可成為燒熔點。 由於熔絲通入電流時常會產生高熱而常有過熱之 • 虞，並降低元件穩定性。故相較於圖2之設計，圖5中的 熔絲層500由於具有多數個内區塊，並透過多數個熱緩衝 區塊與第一與第二區塊連接而形成一條較長且曲折之電流 - 途徑。因此，本發明之設計將電流途徑拉長，可使流經熔 • 絲結構之電流較小於圖2之設計，且具有多個燒熔點。而 由於流經之電流較小（中電流），若熔絲層為複晶矽與金屬 矽化合物之複合層，本發明此一較佳實施例中熔絲結構之 燒熔點多僅發生電子遷徙，造成石夕化金屬層燒、熔而使燒斷 φ 後電阻增加至一相當高的地步，而被視為斷路。而較不會 如，2有大電流流過而使局部溫度升高，而過熱並使熔絲 因π熱斷裂開來。若熔絲層為一金屬層結構，則更可容許 通過較大之電流，使燒熔點局部溫度升高而熔絲因高熱斷 裂開來。而多個燒溶點更可使溶絲結構之敏感度升高，並 提高熔絲結構之可信賴度。 一此外，由於具有多數個熱、緩衝區塊，其粞接第一與第 -區塊與各内區塊，而形成電流路徑，而該電流路徑上、 位於另-層之熱緩衝區域可視為一條新的熱傳導路徑，幫 1274410 12n2twf.d〇c/g 助，入電流時所產生高熱能有效地發散 ，•故當各内區塊之 面積，狹窄的該連結區塊因為流經電流密度較高而有過熱 虞日寸與其輕接之該些熱緩衝區塊，則提供一高效率之 熱傳導路徑，可將燒熔點附近所產生之熱均勻分佈，甚至 傳導致另一層，而有助於散熱。 斤X本叙明之丈谷絲結構由於具有一或多個熱緩衝區 =與多個互相分離的區塊，而得續供更有效之熱傳導路 從’不但改善散熱率，戦賴，更可降健絲過熱造成 if 響，而對於周圍其他元件而言，降低過熱之風險， 了使/、製程餘裕增大。 限定;^ΐ 實關揭露如上，_並非用以 =明丄任何熟習此技藝者，在不脫離本發明之精神 i乾圍内，當可作些許之更動與潤飾，因此本發明之伴： 關當視_之中請專職_界定者鱗。保5又 【圖式簡單說明】 圖1為熔絲結構的剖面圖。 圖2為圖1之熔絲結構之熔絲層的上視囷 緩衝例輸之_結構中具熱 圖4為圖3之溶絲結構的剖面圖 出之具有熱緩衝區 不出之具有熱緩衝 圖5為依照本發明一實施例所繪示 塊之熔絲結構的剖面圖。 圖5A為依照本發明一實施例所繪 區塊之溶絲結構的剖面圖。 19 1274410 12112twf.doc/g 圖6為圖3之熔絲結構沿著剖面線Ι-Γ的頗面圖。 【主要元件符號說明】 10、40 :熔絲結構 100、400、600 :基底 110、410 :下絕緣層 120、300、500、500’ ：熔絲層 122a、122b :較寬區域 124 :較窄區域 130、430 :上絕緣層 135、435 :介層洞 . 140、440 :介層插塞 . 150 :第一頂部金屬墊層 160 :第二頂部金屬墊層 300 ··熔絲結構 310、510、510’ ：第一區塊 315 :連結區塊 _ # 320、520、520, ··第二區塊 330 ··第三區塊 340 ··第四區塊 350 :熱緩衝區塊 450 :頂部金屬層 515、515’ ：第一熱緩衝區塊 525、525’ ：第二熱緩衝區塊 530、530’ ··第一内區塊 20 1274410 12112twf.doc/g 530a、530’a :第一端區塊 530b、530’b :第一連結區塊 530c、530’c :第二端區塊 535 :第三熱缓衝區塊 540 :第二内區塊 540a :第三端區塊 540b :第二連結區塊 540c :第四端區塊 • 545 :第四熱緩衝區塊 . 550 :第三内區塊 - 550a ··第五端區塊 : 550b :第三連結區塊 550c :第六端區塊==Construction of the current wheel into the 塾' or even _ wire structure to the integrated body ^ ^ See Figure 5 or Figure 5 Α, when the current is flowing, the flow path of the current (headed, not dotted), for example, by the first The block trains the hot buffer blocks and the inner blocks, and flows to the second block 52(); because of the connecting blocks 53〇b, 通, 5, and 53 of the inner blocks 〇, the area of b is much narrower than the block of the face block to which it is connected, resulting in a higher flow density per unit area. Therefore, with respect to the end blocks 530a, 530c, 550c, 55〇a, 540a, 540c which are wider at both ends, the connection blocks (10), 55 sen, M 〇 b and 530 b are connected in the middle of each inner block. It is a narrow channel that is still impedance, so that the electric energy passing through the connecting block is long: 咼, the local temperature increases and the electric resistance changes after the local burning, and the local regions 530b, 550b, 540b and 530, b are also called Burn the melting point. If the current flows in the opposite direction from the second block 52 through the heat buffer blocks and the inner blocks, and flows to the first block 51, the connection between the inner blocks is narrower. The current density per unit area of the connecting blocks 53〇b, 550b, 540b, and 530'b is higher than that of 17 1274410 121 l2twf.doc/g, and a so-called melting point is formed. In addition, the shape of any thermal buffer block can be adjusted based on process design needs. Therefore, the current density of a particular region of the flow overheating buffer block (e.g., a helium region) is higher, and a particular region of the thermal buffer block becomes a melting point. On the other hand, the resistance of the via plug to be connected is carefully designed so that it can also be a melting point if necessary. Due to the high heat generated by the fuse current, it often has overheating and reduces component stability. Therefore, compared with the design of FIG. 2, the fuse layer 500 in FIG. 5 has a long and tortuous shape because it has a plurality of inner blocks and is connected to the first and second blocks through a plurality of thermal buffer blocks. Current - the route. Thus, the design of the present invention elongates the current path so that the current flowing through the fuse structure is less than the design of Figure 2 and has multiple firing melting points. However, since the current flowing through is small (medium current), if the fuse layer is a composite layer of a polycrystalline germanium and a metal germanium compound, in the preferred embodiment of the present invention, the melting point of the fuse structure only undergoes electron migration. The metal layer of the Shi Xihua is burned and melted so that the resistance increases to a relatively high level after being blown, and is regarded as an open circuit. It is less likely that, for example, 2 has a large current flowing to cause the local temperature to rise, and the overheating causes the fuse to break due to π heat. If the fuse layer is a metal layer structure, it is more allowable to pass a large current, so that the local temperature of the burning melting point rises and the fuse is broken by high heat. The plurality of melting points can increase the sensitivity of the filament structure and improve the reliability of the fuse structure. In addition, since there are a plurality of heat and buffer blocks, which are connected to the first and the first blocks and the inner blocks, a current path is formed, and the thermal buffer region located on the other layer in the current path can be regarded as A new heat conduction path helps 1274410 12n2twf.d〇c/g, and the high heat generated by the current is effectively diverged. Therefore, when the area of each inner block is narrow, the connected block is flowed through the current density. The high thermal buffer block with high temperature and overheating provides a high-efficiency heat conduction path, which can evenly distribute the heat generated near the melting point and even lead to another layer, which helps to dissipate heat. . Because of having one or more heat buffers = multiple separated blocks, it is necessary to continue to supply more efficient heat conduction paths from 'not only improving heat dissipation rate, but also reducing The overheating of the silk wire causes an if, and for other components around it, the risk of overheating is reduced, and the margin of the process is increased.限定 ΐ 实 实 实 实 ΐ , , , , , , , _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ When viewing _ among the full-time _ define the scales.保五又 [A brief description of the drawings] Figure 1 is a cross-sectional view of the fuse structure. 2 is a top view of the fuse layer of the fuse structure of FIG. 1 and has a heat buffer. FIG. 3 is a cross-sectional view of the filament structure of FIG. 3 with a thermal buffer. FIG. 5 is a cross-sectional view showing a fuse structure of a block according to an embodiment of the invention. Figure 5A is a cross-sectional view showing a dissolved filament structure of a block in accordance with an embodiment of the present invention. 19 1274410 12112twf.doc/g Figure 6 is a cross-sectional view of the fuse structure of Figure 3 taken along the section line Ι-Γ. [Description of main component symbols] 10, 40: Fuse structure 100, 400, 600: Substrate 110, 410: Lower insulating layer 120, 300, 500, 500': Fuse layer 122a, 122b: Wide area 124: Narrow Regions 130, 430: upper insulating layers 135, 435: vias. 140, 440: via plugs. 150: first top metal pad layer 160: second top metal pad layer 300 · fuse structures 310, 510 510': first block 315: link block _ # 320, 520, 520, · · second block 330 · · third block 340 · · fourth block 350: hot buffer block 450: top Metal layer 515, 515': first thermal buffer block 525, 525': second thermal buffer block 530, 530' · first inner block 20 1274410 12112twf.doc / g 530a, 530'a: first End block 530b, 530'b: first connection block 530c, 530'c: second end block 535: third hot buffer block 540: second inner block 540a: third end block 540b: Second connection block 540c: fourth end block • 545: fourth hot buffer block. 550: third inner block - 550a · · fifth end block: 550b: third link block 550c: sixth End block
21twenty one