1272704 08374tw〇.d〇c/006 95.5-19 玖、發明說明 (發明說明應敘明.發明所屬之技術領域、先前技術、內容、奮施方式及圖式簡 單說明） ~ 本發明是有關於一種覆晶封裝結構（flip-chip package )，且特別是有關於一種藉由凸塊將散熱塊（heat sink )與晶片背面連接之覆晶封裝結構。 覆晶接合技術主要是在晶片上的焊墊上進行凸塊的 製作，然後將其翻覆並利用凸塊直接於承載器（ carrier )連 接。覆晶封裝有別於傳統的打線方式（wire bonding )，覆晶 封裝中的晶片上的焊墊可以作任意的配置，如陣列排列、 交錯排列等。由於覆晶封裝具有封裝體積小、高腳數、路 徑短、低電感以及雜訊容易控制等優點，十分符合現代產 品高速度、高效能且輕薄短小的要求。覆晶封裝就型態而 目可以區分爲覆晶式構裝（flip chip in package )以及覆晶 式組裝（flip chip on board )兩種。其中，覆晶式構裝是先將 晶片翻覆與承載基材連接後，再藉由承載基材與印刷電路 板連接，而覆晶式組裝則是將晶片翻覆後，直接與印刷電 路板接合。 首先請參照第1圖，其繪示爲習知覆晶式組裝之剖面 示意圖。習知覆晶式組裝主要係由晶片1〇〇、球底金屬層 106、凸塊108、印刷電路板11〇以及散熱塊us所構成。 1272704 08374twf2.doc/006 95-5-19 印刷電路板110上配置有多個接點112。而晶片100 配置於印刷電路板110上方，且晶片100具有一主動表面 與一背面。其中，晶片100之主動表面上具有多個焊墊102 以及一保護層104,保護層104例如覆蓋於晶片100之主動 表面上並將焊墊102暴露。 晶片1〇〇與印刷電路板Π〇之間例如配置有多個球底 金屬層106以及凸塊108，以使得晶片100上的焊墊102 藉由球底金屬層106以及凸塊108與印刷電路板110上的 接點112電性連接。 散熱塊Π8配置於晶片100的背面上方。散熱塊118 與晶片1〇〇的背面之間例如配置有導熱膠Π6,藉由導熱膠 Π6達到散熱塊118與晶片100之間的連接。 接著請參照第2圖，其繪示爲習知覆晶式構裝之剖面 示意圖。習知覆晶式構裝主要係由晶片200、球底金屬層 206、凸塊208、承載基材210、焊球216、印刷電路板218 以及散熱塊224所構成。 晶片200配置於承載基材210上方，且晶片200具有 一主動表面與一背面。其中，晶片200之主動表面上具有 多個焊墊202以及一保護層204,保護層204例如覆蓋於晶 片200之主動表面上並將焊墊202暴露。 1272704 083 74twf2. doc/006 95-5-19 承載基材210上的一表面上配置有多個接點212，而 承載基材210上的另一表面上配置有多個接點214。其中， 承載基材210上的接點212係藉由球底金屬層206以及凸 塊208而與晶片200上之焊墊202電性連接，而承載基材 210上的接點214係藉由焊球216而與印刷電路板218上之 接點22〇電性連接。 散熱塊224配置於晶片200的背面上方。散熱塊224 與晶片200的背面之間例如配置有導熱膠222,藉由導熱膠 222達到散熱塊224與晶片200之間的連接。 然而’習知的覆晶式封裝結構中，以導熱膠作爲散熱 塊與晶片之間的傳導路徑，其散熱特性仍有改善的空間。 此外’習知的覆晶封裝結構中，以導熱膠作爲散熱塊與晶 片之間的連接媒介，其接合性不如預期的良好，進而影響 到封裝體的信賴性。 因此，本發明的目的在提出一種覆晶封裝結構，其具 有良好的封裝信賴性以及散熱特性。 爲達本發明之上述目的，提出一種覆晶封裝結構主要 係由一印刷電路板、一晶片、多個第一球底金屬層、多個 第一凸塊、一散熱塊、多個第二球底金屬層以及多個第二 凸塊所構成。其中，印刷電路板上配置有複數個接點，而 1272704 08374twf2.doc/006 95-5-19 接點係與第一凸塊電性連接。晶片配置於印刷電路板上 方，晶片具有一主動表面與一背面，其中主動表面上具有 多個焊墊以及一保護層，保護層覆蓋於主動表面上並將焊 墊暴露。第一球底金屬層配置於焊墊上。第一凸塊配置於 第一球底金屬層與接點之間。散熱塊配置於晶片的背面 上。第二球底金屬層配置於晶片背面上。而第二凸塊則配 置於第二球底金屬層與散熱塊之間，以將晶片及散熱塊連 接。 爲達本發明之上述目的，提出一種覆晶封裝結構主要 係由一承載基材、一晶片、多個第一球底金屬層、多個第 一凸塊、一散熱塊、多個第二凸塊、第二球底金屬層、一 印刷電路板以及多個焊球（solder ball )所構成。其中，承載 基材具有一第一表面與一第二表面，第一表面上具有多個 第一接點，而第二表面上具有多個第二接點。晶片配置於 承載基材上方，晶片具有一主動表面與一背面，其中主動 表面上具有多個焊墊以及一保護層，保護層覆蓋於主動表 面上並將焊墊暴露。第一球底金屬層配置於焊墊上。第一 凸塊配置於第一球底金屬層與第一接點之間。散熱塊配置 於晶片背面上方。而第二凸塊配置於晶片與散熱塊之間， 1272704 08374twf2.doc/006 95^^ ^ 凸塊與晶片背面之間。印刷電路板配置於承載基材下$， 印刷電路板上配置有多個第三接點。而焊球則配置於承g 基材與印刷電路板之間，以將第二接點與第三接點電 接。 本發明中，印刷電路板與晶片之間例如配置有一__ (Underfill )，此塡膠係用以將上述第一凸塊包覆。 本發明中，第一凸塊、第二凸塊以及焊球例如爲各_ 錫/鉛比之錫鉛凸塊。 本發明中，散熱塊之熱膨脹係數例如與晶片之熱膨_ 係數相同。 爲讓本發明之上述目的、特徵、和優點能更明_易 懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 圖式之簡單說明： 第1圖繪示爲習知覆晶式組裝之剖面示意圖； 第2圖繪示爲習知覆晶式構裝之剖面示意圖； 第3圖繪示爲依照本發明一較佳實施例於散熱塊上製 作凸塊而與覆晶晶片背面連接之示意圖； 第4圖繪示爲依照本發明一較佳實施例於覆晶晶片背 面製作凸塊而與散熱塊連接之示意圖； 8 1272704 08374twf2.doc/006 95-5-19 第5圖繪示爲依照本發明一較佳實施例覆晶晶片藉由 凸塊而與散熱塊連接之示意圖； 第6圖繪示爲依照本發明一較佳實施例覆晶式組裝之 剖面示意圖；以及 第7圖繪示爲依照本發明一較佳實施例覆晶式構裝之 剖面示意圖。 圖式之標示說明： 100、200 :晶片 1G2、202 :焊墊 104、204 :保護層 106、206 :球底金屬層 108、208 :凸塊 110、218 :印刷電路板 112、212、214、220 :接點 114、207 :塡膠 116、222 :導熱膠 118、224 :散熱塊 210 :承載基材 216 :焊球 3 0 0 :晶片 9 1272704 08374twf2.doc/006 95-5-19 300a :背面 300b :主動表面 3 02 :焊墊 304 :保護層 306、308 :球底金屬層 310、312 :凸塊 314 :印刷電路板 316 :接點 318a、318b :塡膠 320 :散熱塊 322 :承載基材 324、326 :接點 328 :焊球 較佳實施例 首先請參照第3圖，其繪示爲依照本發明一較佳實施 例於散熱塊上製作凸塊而與覆晶晶片背面連接之示意圖。 晶片300具有一主動表面300a以及一背面300b。其中，晶 片300之主動表面300a上例如配置有多個球底金屬層306 (繪示於第6圖），球底金屬層306上例如配置凸塊310。 而晶片300背面300b上例如配置有多個球底金屬層308。 10 1272704 08374twf2.doc/0〇6 95-5-19 同樣請#照第3圖，接著提供一散熱塊32〇，散熱塊 32〇的熱膨脹俤數例如與晶片300的熱膨脹係數相同，以使 得晶片3〇〇與飮熱塊uo之間不會有熱膨脹係數差異（CTE mismatch )的問題。散熱塊320的其中一袠面上配置多個凸 塊3 12,凸塊312的位置例如係對應於球底金屬層3〇8的位 置。接著將晶片3〇〇與散熱塊32〇接合（b〇nding )，藉由位 置相對應之凸塊312及球底金屬層3〇8達到接合的目的。 接著請參照第4圖，其繪示爲依照本發明一較佳實施 例於覆晶晶片背面製作凸塊而與散熱塊連接之示意圖。由 第4圖可清楚得知，凸塊312不僅可以配置於散熱塊32〇 上（如第3圖），其亦可配置於晶片300背面300b的球底 金屬層308上。 接著請參照第5圖，其繪示爲依照本發明一較佳實施 例覆晶晶片藉由凸塊而與散熱塊連接之示意圖。晶片300 與散熱塊320藉由凸塊3 12連接之後，位於晶片3〇〇與散 熱塊320之間的凸塊312與球底金屬層3〇8便成爲二者之 間的熱傳導路徑。由於凸塊312與球底金屬層308皆爲金 屬材質，其熱傳導的特性十分良好。此外，晶片300藉由 凸塊312將熱傳導至散熱塊320時的傳導路徑很短，因此 對於封裝體散熱能力的提升有很大的助益。 11 1272704 08374twf2.doc/006 95^19 覆晶封裝就型態而言可以區分爲覆晶式構裝（flip chip in package )以及覆晶式組裝（flip chip on board )兩 種。其中，覆晶式構裝是先將晶片翻覆與承載基材連接後， 再藉由承載基材與印刷電路板連接，而覆晶式組裝則是將 晶片翻覆後直接與印刷電路板接合。 接著請參照第6圖，其繪示爲依照本發明一較佳實施 例覆晶式組裝之剖面示意圖。覆晶式組裝主要係由一印刷 電路板314、一晶片300、多個球底金屬層3〇6、多個凸塊 310、一散熱塊320、多個球底金屬層308以及多個312凸 塊所構成。 印刷電路板314上配置有多個接點316。而晶片300 配置於印刷電路板314上方，且晶片300具有一主動表面 3〇〇a與一背面300b。其中，晶片3〇〇之主動表面300a上 具有多個焊墊302以及一保護層304，保護層304例如覆蓋 於主動表面300a上並將焊墊暴露。 印刷電路板314上的接點316係藉由凸塊310及球底 金屬層306而與晶片上的焊墊302電性連接。此外，印刷 電路板314與晶片300之間例如配置有一塡膠3 18a，此塡 膠318a具有應力緩衝、保護凸塊310的作用。 散熱塊320配置於晶片3〇〇的背面3〇〇b上方。散熱 12 1272704 08374twf2.doc/006 95-5-19 塊320與晶片300的背面300b之間例如配置有球底金屬層 308以及凸塊312。藉由球底金屬層308以及凸塊312達到 散熱塊320與晶片300之間的連接。 上述凸塊310與凸塊312例如爲各種錫/鉛比之錫鉛凸 塊，而散熱塊320之熱膨脹係數例如與晶片300之熱膨脹 係數相同，以避免晶片300與散熱塊320之間熱膨脹係數 差異的問題。 最後請參照第7圖，其繪示爲依照本發明一較佳實施 例覆晶式構裝之剖面示意圖。覆晶式構裝主要係由一承載 基材322、一晶片300、多個球底金屬層306、多個凸塊310、 一散熱塊320、多個凸塊312、多個球底金屬層308、一印 刷電路板314以及多個焊球328所構成。 承載基材322具有一第一表面與一第二表面，第一表 面上具有多個第一接點324,而第二表面上具有多個第二接 點 326。 晶片300配置於承載基材322上方，且晶片300具有 一主動表面300a與一背面300b。其中，晶片300之主動表 面300a上具有多個焊墊302以及一保護層304,保護層304 例如覆蓋於主動表面300a上並將焊墊302暴露。 承載基材322上的接點324係藉由凸塊310及球底金 13 1272704 95-5-19 08374twf2.d〇c/006 屬層306而與晶片上的焊墊302電性連接。此外，承載基 材322與晶片300之間例如配置有一塡膠318b，此塡膠318b 具有應力緩衝、保護凸塊310的作用。此外，承載基材322 上的接點326係藉由焊球328而與印刷電路板314上之接 點316電性連接。 散熱塊320配置於晶片3〇〇的背面300b上方。散熱 塊320與晶片300的背面3〇〇b之間例如配置有球底金屬層 以及凸塊312。藉由球底金屬層以及凸塊312達到 散熱塊320與晶片300之間的連接。 上述凸塊310、凸塊312以及焊球328例如爲各種錫/ 鉛比之錫鉛凸塊，而散熱塊320之熱膨脹係數例如與晶片 3〇〇之熱膨脹係數相同，以避免晶片300與散熱塊320之間 熱膨脹係數差異的問題。 綜上所述，本發明之覆晶封裝結構至少具有下述優 點： 1·本發明之覆晶封裝結構中係以凸塊作爲散熱塊與晶 片之間的傳導路徑，因凸塊材質大多爲金屬（合金），故使 得封裝體的散熱十分良好。 2·本發明之覆晶封裝結構中’凸塊與散熱塊、晶片背 面上的球底金屬層之間的接合性十分良好，進一步增進了 14 1272704 08374twf2.doc/006 95-5-19 封裝的信賴性。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍內，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者爲準。 151272704 08374tw〇.d〇c/006 95.5-19 玖, invention description (invention description should be stated. The technical field, prior art, content, mode of operation and schematic description of the invention) ~ The present invention relates to a A flip-chip package, and in particular, a flip chip package structure in which a heat sink is connected to a back surface of a wafer by bumps. The flip chip bonding technique is mainly to make bumps on the pads on the wafer, then flip them over and connect them directly to the carrier by bumps. The flip chip package is different from the conventional wire bonding. The pads on the wafer in the flip chip package can be arranged in any arrangement, such as array arrangement, staggered arrangement, and the like. Since the flip chip package has the advantages of small package size, high number of pins, short path, low inductance, and easy control of noise, it is in line with the requirements of high speed, high efficiency, light weight and shortness of modern products. The flip chip package can be divided into two types: a flip chip in package and a flip chip on board. The flip-chip package is characterized in that the wafer is flipped over the carrier substrate and then connected to the printed circuit board by the carrier substrate. In the flip chip assembly, the wafer is flipped over and directly bonded to the printed circuit board. Referring first to Figure 1, a cross-sectional view of a conventional flip-chip assembly is shown. The conventional flip chip assembly is mainly composed of a wafer 1 , a ball metal layer 106 , a bump 108 , a printed circuit board 11 , and a heat sink us . 1272704 08374twf2.doc/006 95-5-19 A plurality of contacts 112 are disposed on the printed circuit board 110. The wafer 100 is disposed above the printed circuit board 110, and the wafer 100 has an active surface and a back surface. The active surface of the wafer 100 has a plurality of pads 102 and a protective layer 104. The protective layer 104 covers, for example, the active surface of the wafer 100 and exposes the pads 102. For example, a plurality of ball-bottom metal layers 106 and bumps 108 are disposed between the wafer 1 and the printed circuit board, such that the pads 102 on the wafer 100 pass the ball-bottom metal layer 106 and the bumps 108 and the printed circuit. The contacts 112 on the board 110 are electrically connected. The heat sink block 8 is disposed above the back surface of the wafer 100. Between the heat dissipating block 118 and the back surface of the wafer 1 is disposed, for example, a thermal conductive adhesive tape 6, and the thermal conductive adhesive tape 6 reaches the connection between the thermal dissipating block 118 and the wafer 100. Referring to Figure 2, there is shown a schematic cross-sectional view of a conventional flip-chip package. The conventional flip-chip package is mainly composed of a wafer 200, a ball-bottom metal layer 206, bumps 208, a carrier substrate 210, solder balls 216, a printed circuit board 218, and a heat sink block 224. The wafer 200 is disposed above the carrier substrate 210, and the wafer 200 has an active surface and a back surface. The active surface of the wafer 200 has a plurality of pads 202 and a protective layer 204. The protective layer 204 covers, for example, the active surface of the wafer 200 and exposes the pads 202. 1272704 083 74twf2. doc/006 95-5-19 A plurality of contacts 212 are disposed on one surface of the carrier substrate 210, and a plurality of contacts 214 are disposed on the other surface of the carrier substrate 210. The contacts 212 on the carrier substrate 210 are electrically connected to the pads 202 on the wafer 200 by the ball-bottom metal layer 206 and the bumps 208, and the contacts 214 on the carrier substrate 210 are soldered. The ball 216 is electrically connected to the contact 22 on the printed circuit board 218. The heat dissipation block 224 is disposed above the back surface of the wafer 200. Between the heat dissipating block 224 and the back surface of the wafer 200, for example, a thermal conductive paste 222 is disposed, and the thermal conductive paste 222 reaches the connection between the heat dissipating block 224 and the wafer 200. However, in the conventional flip-chip package structure, the heat conduction adhesive is used as a conduction path between the heat dissipation block and the wafer, and the heat dissipation characteristics still have room for improvement. Further, in the conventional flip chip package structure, the thermal conductive adhesive is used as the connection medium between the heat dissipating block and the wafer, and the bonding property is not as good as expected, thereby affecting the reliability of the package. Accordingly, it is an object of the present invention to provide a flip chip package structure which has good package reliability and heat dissipation characteristics. In order to achieve the above object of the present invention, a flip chip package structure is mainly provided by a printed circuit board, a wafer, a plurality of first ball bottom metal layers, a plurality of first bumps, a heat sink block, and a plurality of second balls. The bottom metal layer and the plurality of second bumps are formed. Wherein, a plurality of contacts are arranged on the printed circuit board, and the 1272704 08374twf2.doc/006 95-5-19 contact is electrically connected to the first bump. The wafer is disposed on the printed circuit board. The wafer has an active surface and a back surface. The active surface has a plurality of pads and a protective layer covering the active surface and exposing the pads. The first ball bottom metal layer is disposed on the pad. The first bump is disposed between the first ball bottom metal layer and the joint. The heat slug is disposed on the back side of the wafer. The second ball bottom metal layer is disposed on the back surface of the wafer. The second bump is disposed between the second ball bottom metal layer and the heat sink block to connect the wafer and the heat sink block. In order to achieve the above object of the present invention, a flip chip package structure is mainly provided by a carrier substrate, a wafer, a plurality of first ball bottom metal layers, a plurality of first bumps, a heat sink block, and a plurality of second bumps. The block, the second ball bottom metal layer, a printed circuit board, and a plurality of solder balls are formed. The carrier substrate has a first surface and a second surface, the first surface having a plurality of first contacts and the second surface having a plurality of second contacts. The wafer is disposed above the carrier substrate, the wafer having an active surface and a back surface, wherein the active surface has a plurality of pads and a protective layer covering the active surface and exposing the pads. The first ball bottom metal layer is disposed on the pad. The first bump is disposed between the first ball bottom metal layer and the first contact. The heat slug is placed above the back of the wafer. The second bump is disposed between the wafer and the heat sink block, and is between the bump and the back surface of the wafer. The printed circuit board is disposed under the carrier substrate, and a plurality of third contacts are disposed on the printed circuit board. The solder ball is disposed between the substrate and the printed circuit board to electrically connect the second contact to the third contact. In the present invention, for example, an __ (Underfill) is disposed between the printed circuit board and the wafer, and the silicone is used to coat the first bump. In the present invention, the first bump, the second bump, and the solder ball are, for example, tin-lead bumps of different tin/lead ratios. In the present invention, the thermal expansion coefficient of the heat sink block is, for example, the same as the thermal expansion coefficient of the wafer. The above described objects, features, and advantages of the present invention will become more apparent from the following description of the preferred embodiments. FIG. 2 is a schematic cross-sectional view showing a conventional flip-chip assembly; FIG. 3 is a cross-sectional view showing a conventional flip-chip package; FIG. 3 is a view showing a bump on a heat dissipation block according to a preferred embodiment of the present invention; FIG. 4 is a schematic view showing a bump formed on the back surface of the flip chip and connected to the heat sink block according to a preferred embodiment of the present invention; 8 1272704 08374twf2.doc/006 95-5 -19 is a schematic view showing a flip chip bonded to a heat sink block by bumps according to a preferred embodiment of the present invention; FIG. 6 is a flip-chip assembly according to a preferred embodiment of the present invention. A schematic cross-sectional view; and FIG. 7 is a schematic cross-sectional view of a flip-chip package in accordance with a preferred embodiment of the present invention. Description of the drawings: 100, 200: wafer 1G2, 202: pads 104, 204: protective layer 106, 206: ball metal layer 108, 208: bumps 110, 218: printed circuit boards 112, 212, 214, 220: contact 114, 207: silicone 116, 222: thermal paste 118, 224: heat sink 210: carrier substrate 216: solder ball 3 0 0: wafer 9 1272704 08374twf2.doc / 006 95-5-19 300a: Back surface 300b: active surface 302: solder pad 304: protective layer 306, 308: ball bottom metal layer 310, 312: bump 314: printed circuit board 316: contact 318a, 318b: silicone 320: heat sink 322: carrying Substrate 324, 326: Contact 328: Preferred embodiment of the solder ball. Referring first to FIG. 3, a bump is formed on the heat dissipating block to be connected to the back surface of the flip chip according to a preferred embodiment of the present invention. schematic diagram. The wafer 300 has an active surface 300a and a back surface 300b. For example, a plurality of ball-bottom metal layers 306 (shown in FIG. 6) are disposed on the active surface 300a of the wafer 300, and bumps 310 are disposed on the ball-bottom metal layer 306, for example. On the back surface 300b of the wafer 300, for example, a plurality of ball-bottom metal layers 308 are disposed. 10 1272704 08374twf2.doc/0〇6 95-5-19 Similarly, according to FIG. 3, a heat dissipating block 32 is provided, and the thermal expansion coefficient of the heat dissipating block 32 is, for example, the same as the thermal expansion coefficient of the wafer 300, so that the wafer There is no problem with the difference in thermal expansion coefficient (CTE mismatch) between the 3 〇〇 and the hot block uo. A plurality of bumps 3 12 are disposed on one of the top faces of the heat sink block 320, and the positions of the bumps 312 correspond to, for example, the positions of the ball bottom metal layers 3〇8. Then, the wafer 3 is bonded to the heat sink block 32, and the bump 312 and the ball bottom metal layer 3〇8 corresponding to the position are joined for the purpose of bonding. Next, please refer to FIG. 4, which is a schematic view showing the bumps on the back side of the flip chip and the heat sinks according to a preferred embodiment of the present invention. As is clear from Fig. 4, the bumps 312 can be disposed not only on the heat sink block 32A (as shown in Fig. 3) but also on the ball bottom metal layer 308 on the back surface 300b of the wafer 300. Next, please refer to FIG. 5, which is a schematic diagram of a flip chip connected to a heat sink block by bumps according to a preferred embodiment of the present invention. After the wafer 300 and the heat sink block 320 are connected by the bumps 3 12 , the bumps 312 and the ball bottom metal layer 3 〇 8 between the wafer 3 〇〇 and the heat sink block 320 become a heat conduction path therebetween. Since both the bump 312 and the ball-bottom metal layer 308 are made of a metal material, the heat conduction characteristics are very good. In addition, the conduction path of the wafer 300 when the heat is conducted to the heat sink block 320 by the bumps 312 is short, so that the heat dissipation capability of the package body is greatly improved. 11 1272704 08374twf2.doc/006 95^19 The flip chip package can be divided into two types: flip chip in package and flip chip on board. The flip-chip package is characterized in that the wafer is flipped over the carrier substrate and then connected to the printed circuit board by the carrier substrate. In the flip chip assembly, the wafer is flipped over and directly bonded to the printed circuit board. Referring to Figure 6, there is shown a cross-sectional view of a flip-chip assembly in accordance with a preferred embodiment of the present invention. The flip chip assembly is mainly composed of a printed circuit board 314, a wafer 300, a plurality of ball bottom metal layers 3〇6, a plurality of bumps 310, a heat sink block 320, a plurality of ball bottom metal layers 308, and a plurality of 312 convex portions. The block is composed. A plurality of contacts 316 are disposed on the printed circuit board 314. The wafer 300 is disposed above the printed circuit board 314, and the wafer 300 has an active surface 3A and a back 300b. The active surface 300a of the wafer 3 has a plurality of pads 302 and a protective layer 304. The protective layer 304 covers, for example, the active surface 300a and exposes the pads. The contacts 316 on the printed circuit board 314 are electrically connected to the pads 302 on the wafer by the bumps 310 and the ball-bottom metal layer 306. In addition, between the printed circuit board 314 and the wafer 300, for example, a silicone 3 18a is disposed, and the silicone 318a has a stress buffering function and a protective bump 310. The heat sink block 320 is disposed above the back surface 3〇〇b of the wafer 3〇〇. Heat Dissipation 12 1272704 08374twf2.doc/006 95-5-19 A ball-bottom metal layer 308 and bumps 312 are disposed between the block 320 and the back surface 300b of the wafer 300, for example. The connection between the heat slug 320 and the wafer 300 is achieved by the bottom metal layer 308 and the bumps 312. The bumps 310 and the bumps 312 are, for example, tin-lead bumps of various tin/lead ratios, and the thermal expansion coefficient of the heat-dissipating block 320 is the same as the thermal expansion coefficient of the wafer 300, for example, to avoid the difference in thermal expansion coefficient between the wafer 300 and the heat-dissipating block 320. The problem. Finally, please refer to FIG. 7, which is a cross-sectional view showing a flip-chip structure according to a preferred embodiment of the present invention. The flip-chip package is mainly composed of a carrier substrate 322, a wafer 300, a plurality of ball-bottom metal layers 306, a plurality of bumps 310, a heat-dissipating block 320, a plurality of bumps 312, and a plurality of ball-bottom metal layers 308. A printed circuit board 314 and a plurality of solder balls 328 are formed. The carrier substrate 322 has a first surface and a second surface, the first surface having a plurality of first contacts 324 and the second surface having a plurality of second contacts 326. The wafer 300 is disposed above the carrier substrate 322, and the wafer 300 has an active surface 300a and a back surface 300b. The active surface 300a of the wafer 300 has a plurality of pads 302 and a protective layer 304. The protective layer 304 covers, for example, the active surface 300a and exposes the pads 302. The contact 324 on the carrier substrate 322 is electrically connected to the pad 302 on the wafer by the bump 310 and the ball gold 13 1272704 95-5-19 08374 twf2.d〇c/006 layer 306. In addition, a silicone 318b is disposed between the carrier substrate 322 and the wafer 300. The silicone 318b has a stress buffering function and a protective bump 310. In addition, the contacts 326 on the carrier substrate 322 are electrically connected to the contacts 316 on the printed circuit board 314 by solder balls 328. The heat sink block 320 is disposed above the back surface 300b of the wafer 3. A ball-bottom metal layer and bumps 312 are disposed between the heat dissipation block 320 and the back surface 3b of the wafer 300, for example. The connection between the heat slug 320 and the wafer 300 is achieved by the bottom metal layer and the bumps 312. The bumps 310, the bumps 312, and the solder balls 328 are, for example, tin-lead bumps of various tin/lead ratios, and the thermal expansion coefficient of the heat-dissipating block 320 is the same as the thermal expansion coefficient of the wafer 3, for example, to avoid the wafer 300 and the heat-dissipating block. The problem of the difference in thermal expansion coefficient between 320. In summary, the flip chip package structure of the present invention has at least the following advantages: 1. The flip chip package structure of the present invention uses a bump as a conduction path between the heat sink block and the wafer, since the bump material is mostly metal. (Alloy), so the heat dissipation of the package is very good. 2. The junction between the bump and the heat slug and the bottom metal layer on the back side of the wafer in the flip chip package structure of the present invention is very good, further enhancing the package of 14 1272704 08374twf2.doc/006 95-5-19 Trustworthiness. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. 15