TWI270331B

TWI270331B - Circuit board with multi circuit layers and method for fabricating the same

Info

Publication number: TWI270331B
Application number: TW93114393A
Authority: TW
Inventors: Bin-Yang Chen; Chih-Liang Chu; Xian-Zhang Wang; Hsin-Ku Huang
Original assignee: Phoenix Prec Technology Corp
Priority date: 2004-05-24
Filing date: 2004-05-24
Publication date: 2007-01-01
Also published as: TW200539772A

Abstract

A circuit board with multi circuit layers and a method for fabricating the same are proposed, wherein a plurality of core substrates formed with metal layers on the surfaces thereof are provided. A plurality of vias are formed on one surface of the core substrate to expose the metal layer on the other surface of the core substrate. A first circuit layer and a plurality of conductive vias are formed on the surface of the core substrate with vias formed thereon by a pattern process. A multi-layer circuit board is formed by integrating the core substrates with an insulating layer formed between the core substrates on their surfaces having conductive vias. After a plurality of holes are formed in the multi-layer circuit board, a second circuit layer and a plurality of conductive holes are formed on the multi-layer circuit board by a pattern process, wherein a plurality of pads are defined in the second circuit layer and at least a pad is formed on the bottom end of the conductive via, so as to improve the layout flexibility and area.

Description

1270331 五、發明說明（1) " ~一 -- 【發明所屬之技術領域】·· 、匕本發明係關於一種具多層線路層之電路板及其製法，尤指一種可提高線路之佈線空間與靈活性之具多層線之電路板及其製法。曰【先前技術】：隨著電子產業的蓬勃發展，電子產品亦逐漸邁入多功能、高性能的研發趨勢。為滿足半導體封裝件高積集度（ Integration)及微型化（Miniaturizati〇n)的封裝需求，以供更多主被動元件及線路載接，電路板亦逐漸由單層板雙層板〉秀變成多層板（Multi-layer board)，俾在有限的工間下’運用層間連接技術（I n t e r 1 a y e r c 〇 n n e c t丨〇 η )來擴大電路板上可供利用的線路佈局面積，藉此配合高電子密度之積體電路（Integrated circuit)需要，降低電路板的厚度，以在相同電路板單位面積下容納更多數量的線路及元件。另因應微處理器、晶片組與繪圖晶片等高效能晶片之運算需要，佈有導線之電路板亦需提昇其傳遞晶片訊號、改善頻寬、控制阻抗等功能，來成就高I /0數封裝件的發展。然而，為符合半導體封裝件輕薄短小、多功能、高速度及高頻化的開發方向，電路板已朝向細線路及小孔徑發你展0 因此為提高電路板之佈線精密度，業界發展出一種增層技術（Build_up)’亦即在一核心電路板（Core circuit board)表面利用電路增層技術交互堆疊多層絕緣層及線1270331 V. DESCRIPTION OF THE INVENTION (1) " ~1 - [Technical Fields of the Invention] The present invention relates to a circuit board having a multilayer circuit layer and a method of manufacturing the same, and more particularly to improving wiring space of a line A multi-layer circuit board with flexibility and its manufacturing method.曰 [Prior Art]: With the rapid development of the electronics industry, electronic products have gradually entered a multi-functional, high-performance research and development trend. In order to meet the packaging requirements of semiconductor package high integration and miniaturization, for more active and passive components and lines to be connected, the circuit board is gradually changed from single-layer board to double-layer board. Multi-layer board, which uses the interlayer connection technology (I nter 1 ayerc 〇nnect丨〇η) to expand the layout area available on the board for a limited number of workspaces. Density integrated circuits are required to reduce the thickness of the board to accommodate a larger number of lines and components per unit area of the same board. In addition, in response to the computing needs of high-performance chips such as microprocessors, chipsets, and graphics chips, circuit boards with wires need to be upgraded to transmit chip signals, improve bandwidth, and control impedance to achieve high I / 0 packages. The development of the pieces. However, in order to meet the development direction of thin, versatile, high-speed and high-frequency semiconductor packages, the circuit board has been extended to thin lines and small apertures. Therefore, in order to improve the wiring precision of the board, the industry has developed a Build_up] is the use of circuit build-up technology to alternately stack multiple layers of insulation and wires on the surface of a core circuit board.

17661全懋.ptd 第9頁 1270331 五、發明說明（2) -- 路層’並於該絕緣層中開設導電盲孔（c〇nductive ha)以· 供上下層線路之間電性連接。其中，電路增層製程係影變電路板線路密度的關鍵，依照現行技術，辈二呆有夕以平加成法（Senu-additive process，SAP)與線路電鍍法（pattern plating method)來製作電路增層。請參閱第1 A至1 C圖’所謂半加成法係提供一核心電路板1 0，並在其表面形成一絕緣層11，利用雷射鑽孔（L a s㊀^ dr i 1 1 i ng)技術於該絕緣層11上形成開孔丨丨〇，以連通該核心電路板1 0之内層線路層1 2中作為電性導通之電性連^妾墊1 6 (如第1 A圖所示）。接著，於該絕緣層1 1上形成_導電層1 3，並在該導電層1 3上施加一圖案化阻層1後進行電鍵’以於6亥導電層1 3上形成圖案化線路層i5(如第1 b圖所示）。之後’剝離該阻層1 4並移除先前覆蓋於阻層1 4下之導電層1 3 (如第1C圖所示）；如此，運用此等步驟重複形成絕緣層及增層線路層，即製成一具有多層線路層之電路板。另外，線路電鍍法如第2A至2C圖所示，亦先提供一核心電路板2 0，並於該核心電路板2 0表面形成一例如樹脂壓合銅箔（Resin coated copper, RCC)之覆有金屬層211 之壓合絕緣層2 1，再利用雷射鑽孔等方式在該絕緣層2 1上形成開孔2 1 0 ’俾以連通邊核心電路板2 0之内層線路層2 2 中作為電性導通之電性連接墊2 6 (如第2 A圖所示）。而後，於該覆有金屬層211之絕緣層21上形成一導電層23，並在導電層2 3上施加一圖案化阻層2 4後進行電錢，以於該導電17661 全懋.ptd Page 9 1270331 V. Inventive Note (2) -- The road layer 'and a conductive blind hole (c〇nductive ha) in the insulating layer to electrically connect the upper and lower lines. Among them, the circuit-adding process is the key to the line density of the shadow-changing circuit board. According to the current technology, the second generation has a Senu-additive process (SAP) and a pattern plating method. Circuit buildup. Please refer to Figures 1A to 1C. The so-called semi-additive method provides a core circuit board 10 and forms an insulating layer 11 on its surface, using laser drilling (L a s - ^ dr i 1 1 i ng The technique forms an opening 丨丨〇 on the insulating layer 11 to communicate with the inner layer of the core circuit board 10 as an electrically conductive electrical connection pad 16 (as shown in FIG. 1A) Show). Next, a conductive layer 13 is formed on the insulating layer 11, and a patterned resist layer 1 is applied on the conductive layer 13 to perform a key bond to form a patterned wiring layer i5 on the 6-well conductive layer 13. (as shown in Figure 1 b). Thereafter, the resist layer 14 is stripped and the conductive layer 13 previously covered under the resist layer 14 is removed (as shown in FIG. 1C); thus, the insulating layer and the build-up wiring layer are repeatedly formed by using these steps, that is, A circuit board having a plurality of wiring layers is formed. In addition, as shown in FIGS. 2A to 2C, the line plating method first provides a core circuit board 20, and a surface of the core circuit board 20 is formed with, for example, a resin-coated copper foil (RCC). The laminated insulating layer 2 1 having the metal layer 211 is further formed with an opening 2 1 0 '俾 on the insulating layer 2 1 by means of laser drilling or the like to connect the inner layer circuit layer 2 2 of the edge core circuit board 20 As an electrical connection of the electrical connection pad 2 6 (as shown in Figure 2A). Then, a conductive layer 23 is formed on the insulating layer 21 covered with the metal layer 211, and a patterned resist layer 24 is applied on the conductive layer 23, and then electricity is applied to the conductive layer.

1270331 五、發明說明（3) 一' 層2 3上形成圖案化線路層25 (如第2B圖所示）。之後，剝- 離該阻層2 4並移除先前覆蓋在阻層2 4下之金屬層部分（= 第2C圖所示）。接著’可重複實施以上步驟而形成絕緣層及增層線路層’俾完成一具有多層線路層之電路板。惟，前述習知製程均係在核心電路板上利用如壓合等方式形成絕緣層’然後再於該些絕緣層之同一側藉由雷射鑽孔方式形成複數盲孔，後續再形成複數導電盲孔以^性導接電路板内之層間線路結構，然而，如此一來便需額多佈設電性連接墊16,26以承接該些導電盲孔，俾透過該些電性連接墊與導電盲孔之連結，來電性連接該電路板内. 之各層線路結構。因此’習知技術不僅增加電性連接墊之設置量，浪費電路板最外線路層及其他線路面之佈線面積，除了不利於微f化封裝趨勢之外’更會在線路佈局時受到導電盲孔之佔没空間及與導電盲孔相對應之電性連接墊所左右，從而 =專電路板之線路佈線密度，亦不利於電路板之佈線靈活更甚者，於該電墊後’需額外佈線以墊’再由後者之電性内層線路，如此，將接墊以承接導電盲孔利於佈線之靈活性。路板外層之導電盲孔處形成電性連接將該電性連接墊連結至另一電性連接連接墊承接一導電盲孔以電性連接至造成佈線複雜，且需額外多設電性連 ’造成製程步驟與成本之提升，且不1270331 V. DESCRIPTION OF THE INVENTION (3) A patterned wiring layer 25 is formed on a layer 2 (as shown in Fig. 2B). Thereafter, the resist layer 24 is stripped off and the portion of the metal layer previously covered under the resist layer 24 is removed (= Figure 2C). Then, the above steps can be repeatedly performed to form an insulating layer and a build-up wiring layer, and a circuit board having a plurality of wiring layers can be completed. However, the conventional processes are formed on the core circuit board by forming an insulating layer by a method such as pressing, and then forming a plurality of blind holes by laser drilling on the same side of the insulating layers, and subsequently forming a plurality of conductive holes. The blind hole is used to guide the interlayer circuit structure in the circuit board. However, in this way, the electrical connection pads 16, 26 are required to be disposed to receive the conductive blind holes, and the conductive pads are electrically conductive. The connection of the blind holes is electrically connected to the circuit structure of each layer in the circuit board. Therefore, the conventional technology not only increases the amount of electrical connection pads, but also wastes the wiring area of the outermost circuit layer and other circuit surfaces of the circuit board. In addition to the disadvantage of micro-foil packaging, it will be exposed to conductive blindness during line layout. The hole occupies no space and the electrical connection pad corresponding to the conductive blind hole is left and right, so that the circuit wiring density of the special circuit board is not conducive to the flexible wiring of the circuit board, and after the electric pad, 'extra extra The wiring is padded with the latter's electrical inner layer wiring, so that the pads can be used to receive conductive blind holes to facilitate wiring flexibility. An electrical connection is formed at the conductive blind hole of the outer layer of the circuit board, and the electrical connection pad is connected to another electrical connection connection pad to receive a conductive blind hole to be electrically connected to cause complicated wiring, and an additional electrical connection is required. Causing process steps and cost increases, and not

此外，該些導電盲孔通常係由增層線路層朝向核心電In addition, the conductive blind holes are usually made up of a layered wiring layer toward the core.

第11頁 1270331 五、發明說明（4) 路板開設，且後續需在該導電盲孔中充填滿如銅之材料，以提供該電路板後續佈線之電性導接使用，如此將使用較多材料而提高電路板之製造成本及製程步驟。【發明内容】：鑒於以上所述習知技術之缺點，本發明之主要目的在於提供一種具多層線路層之電路板及其製法，藉以增加電路板線路·之佈局面積，從而提高線路佈局靈活性。本發明之另一目的在於提供一種具多層線路層之電路板及其製法，藉以降低成本。為達成上述及其他目的，本發明揭露一種具多層線路 f 層之電路板，係包括：複數芯層板，該芯層板之一表面上形成有第一圖案化線路層及複數導電盲孔，而於該芯層板之另一表面上形成有第二圖案化線路層；至少一絕緣層，係夾置於該些芯層板之第一圖案化線路層及導電盲孔間；以及多數形成於該些芯層板中之導電通孔，以供電性導接該些芯層板。其中，該芯層板之第二圖案化線路層具有複數電性連接墊，且至少一電性連接墊係可選擇性對應至該芯層板之第一圖案化線路層同側之導電盲孔底部，另，該導電通孔係可選擇貫穿多數芯層板之電鐘導通孔結構，亦可選擇部分貫穿該多數芯層板之導電盲孔結構。此外，各 # 該芯層板間亦可間隔有絕緣層及另一電路板來相互進行接合。本發明之具多層線路層之電路板之製法則包括：提供複數芯層板，該芯層板表面上形成有金屬層；於該芯層板Page 11 1270331 V. Description of the invention (4) The board is opened, and the conductive blind hole is filled with copper-filled material to provide electrical connection for the subsequent wiring of the board, so that it will be used more. Materials improve the manufacturing cost and process steps of the board. SUMMARY OF THE INVENTION In view of the above disadvantages of the prior art, the main object of the present invention is to provide a circuit board having a multi-layer circuit layer and a method for manufacturing the same, thereby increasing the layout area of the circuit board, thereby improving the layout flexibility. . Another object of the present invention is to provide a circuit board having a multilayer wiring layer and a method of manufacturing the same, thereby reducing cost. In order to achieve the above and other objects, the present invention discloses a circuit board having a multi-layered circuit f layer, comprising: a plurality of core layer plates having a first patterned circuit layer and a plurality of conductive blind holes formed on one surface thereof; And forming a second patterned circuit layer on the other surface of the core layer; at least one insulating layer is sandwiched between the first patterned circuit layer and the conductive blind hole of the core layer; and most of the formation The conductive vias in the core sheets are electrically connected to the core sheets. The second patterned circuit layer of the core board has a plurality of electrical connection pads, and at least one of the electrical connection pads selectively corresponds to the conductive blind holes on the same side of the first patterned circuit layer of the core layer. At the bottom, the conductive vias may select a conductive via structure of the plurality of core sheets, or may select a conductive blind via structure partially extending through the plurality of core sheets. In addition, each of the core layers may be separated from each other by an insulating layer and another circuit board. The method for manufacturing a circuit board with a multilayer circuit layer of the present invention comprises: providing a plurality of core plates, wherein a metal layer is formed on a surface of the core plate;

17661全懋.ptd 第12頁 1270331 五、發明說明（5) 之一表面形成有複數盲孔，藉以使該芯層板另一表面之金屬層顯露於該盲孔底端；進行線路圖案化製程，以在該芯層板中具有盲孔之表面上形成第一圖案化線路層與複數導電盲孔；將該些芯層板形成有導電盲孔之一側間隔有絕緣層以相互接合形成一多層板；於該多層板中開設有複數通孔；進行線路圖案化製程，以於該多層板之表面上及通孔中形成第二圖案化線路層及複數導電通孔，其中該第二圖案化線路層具有複數電性連接墊，且至少一電性連接墊係形成在該芯層板之導電盲孔底部。此外，該芯層板間係可間隔有絕緣層及另一電路板來相互進行接合，而該導電通 b 孔可為例如導電盲孔或電鍍導通孔，藉以電性導接該些芯層板之線路層。17661 全懋.ptd Page 12 1270331 V. Invention Description (5) One surface is formed with a plurality of blind holes, so that the metal layer on the other surface of the core plate is exposed at the bottom end of the blind hole; Forming a first patterned circuit layer and a plurality of conductive blind vias on a surface having a blind via in the core layer; forming the core vias with one of the conductive vias spaced apart by an insulating layer to form a bonding layer a multi-layer board; a plurality of through holes are formed in the multi-layer board; and a circuit patterning process is performed to form a second patterned circuit layer and a plurality of conductive via holes on the surface of the multi-layer board and the through holes, wherein the second The patterned circuit layer has a plurality of electrical connection pads, and at least one electrical connection pad is formed on the bottom of the conductive blind holes of the core layer. In addition, the core plates may be separated from each other by an insulating layer and another circuit board, and the conductive vias may be, for example, conductive blind holes or plated via holes, thereby electrically connecting the core plates. The circuit layer.

因此，本發明之具多層線路層之電路板及其製法係可在複數芯層板之一側形成有導電盲孔後，再於該些電路板間形成有導電盲孔之一側夾置絕緣層，之後於該電路板之另一側形成具多數電性連接墊之圖案化線路層，以使該導電盲孔底端可選擇性形成有電性連接墊之直接電性傳導路徑，避免習知技術需在一電性連接墊處額外佈線以將其連結至承接於導電盲孔開孔處之電性連接墊，藉以減少製程步驟及複雜性，同時避免佔用線路佈局空間。 D 另，本發明之具多層線路層之電路板及其製法係使線路層之電性連接墊直接設置於導電盲孔底部，且無須考慮導電盲孔之佔設空間及開設位置’精以增加電路板之線路佈局面積，並提高電路板之線路佈局靈活性，藉以解決習Therefore, the circuit board with the multi-layer circuit layer of the present invention and the manufacturing method thereof can be formed with a conductive blind hole on one side of the plurality of core layers, and then one side of the conductive blind hole is formed between the circuit boards. a layer, and then forming a patterned circuit layer having a plurality of electrical connection pads on the other side of the circuit board, so that the bottom end of the conductive blind hole can selectively form a direct electrical conduction path of the electrical connection pad, avoiding It is known that an additional wiring is required at an electrical connection pad to connect it to an electrical connection pad that is received at the opening of the conductive blind hole, thereby reducing process steps and complexity while avoiding occupation of the wiring layout space. Further, the circuit board with the multi-layer circuit layer of the present invention and the manufacturing method thereof enable the electrical connection pads of the circuit layer to be directly disposed at the bottom of the conductive blind hole, and it is not necessary to consider the occupied space and the opening position of the conductive blind hole. The circuit layout area of the circuit board, and improve the circuit layout flexibility of the circuit board, thereby solving the problem

17661 全懋.ptd 第13頁 1270331 五、發明說明（6) ____ 知技術之種種缺失。再者，未菸 T %明之且冬；板及其製法毋須額外多設置電性二 I、、杲路層之電路接，便可進行電路板各線路層之 : ’毛盲孔作承曰心敗向電性導接，Μ 減少電性連接墊之設置量，以降低製程之成本稭此相對亦不受導電盲孔開孔之佔設空間所=广從而擴2且本發明外層線路佈局面積，令線路佈局更具靈活性^ 電路板之路板之導電盲孔底端表面形成圖案二G路層及2 2，於電時，亦無須將諸如銅之填充材料充填於導電盲Ζ性連接墊更加降低製程之成本並減少製程步驟。中’亦【實施方式】：以下係藉由特定的具體實施例說明本發明之余熟習此技藝之人士可由本說明書所揭示之内容U地^ 解本，明之其他優點與功效。本發明亦可藉由其他不同的具體貫施例加以施行或應用，亦即，本說明書中的各項細節亦可基於不同觀點與應用，而在不悖離本發明之^神^ 進行各種修飾與變更。请蒼閱第3 Α至第3 J圖，係用以說明本發明之具多層線路層之電路板製法之較佳實施例。其中，須注意的是，該等圖式均為簡化之示意圖，僅以示意方式說明本發明之電路板架構。惟該等圖式僅顯示與本發明有關之元件，其所择頁示之元件非為實際實施時之態樣，其實際實施時之元件數目、形狀及尺寸比例為一種選擇性之設計，I其元件佈局型態可能更行複雜。如第3A圖及第3B圖所示，首先，提供複數芯層板30,17661 懋.ptd Page 13 1270331 V. Description of invention (6) ____ Known techniques are missing. Furthermore, the unsmoke T% is clear and winter; the board and its method do not need to be provided with additional electrical circuit I, and the circuit layer of the circuit layer can be used to carry out the circuit layer of the circuit board: 'Mao blind hole for the heart and soul Electrically conductive connection, 减少 reduce the setting amount of the electrical connection pad to reduce the cost of the process, and the relative space of the conductive blind hole opening is not widened and expanded, and the outer circuit layout area of the present invention is The layout of the circuit is more flexible. ^ The bottom surface of the conductive blind hole of the circuit board forms a pattern of two G-layers and 22, and it is not necessary to fill the conductive padding material such as copper with the filling material. Reduce process costs and reduce process steps. [Embodiment] The following is a description of the present invention by way of specific specific embodiments. Those skilled in the art can understand the advantages and effects of the present invention. The present invention may also be implemented or applied by other different specific embodiments, that is, the details in the present specification may also be based on different viewpoints and applications, and various modifications may be made without departing from the invention. With changes. Please refer to the third to third J drawings for explaining a preferred embodiment of the circuit board manufacturing method having the multilayer wiring layer of the present invention. It should be noted that these drawings are simplified schematic diagrams, and the circuit board architecture of the present invention is only illustrated in a schematic manner. However, the drawings only show the components related to the present invention, and the components of the selected pages are not actual implementation, and the actual number of components, shape and size ratios are a selective design. The layout of its components may be more complicated. As shown in FIGS. 3A and 3B, first, a plurality of core sheets 30 are provided,

17661 全懋.ptd17661 full 懋.ptd

1270331 五、發明說明（7) 3 1，該芯層板3 0，3 1係於表面形成有金屬層3 0 1，3 11 ’並以雷射鑽孔方式於該怒層板30, 31中鑽設複數盲孔3 0 2，312 (如第3 B圖所示），以使該盲孔3 0 2，3 1 2底端外露出該怒層板30，31另一表面之金屬層3〇1，311。其中’該芯層板30， 3 1之絕緣部分可為環氧樹脂（E P 0χ Υ r e s丨n)、聚乙醢胺 (Polyimide)、氰酯（Cyanate Ester)、玻璃纖維、雙順丁稀二酸酿亞胺/三氮阱（Bismaleimide Triazine，BT )或混合環氧樹脂與玻璃纖維之FR5材質等所製成。該金屬層30 1—般係以導電性較佳之銅（Cu)為主，且該金屬層3 0 1，3 1 1可先壓合或沈積於該絕緣芯層上，或使用樹脂 # 壓合銅箔（Resin coated copper， RCC)形成。如第3C圖所示，選擇利用物理氣相沈積（PVD)、化學氣相沈積（CVD )、無電鍍或化學沈積等技術，例如濺鍍 (Sputtering)、蒸鍵（Evaporation)、電弧蒸氣沈積（Arc vapor deposition)、离隹子束濺鏟(Ion beam sputtering) 、雷射炫散沈積（Laser ablation deposition)、電漿促進之化學氣相沈積或無電鍍等方法，於該芯層板3 0，3 1具有盲孔302, 31 2之表面上及盲孔302, 31 2中形成有一導電層 (未圖示）以作為電流傳導路徑，俾利用電鍍製程以在該芯層板30, 31表面金屬層301及盲孔3 0 2, 3 1 2中形成一具足 ❸ 夠厚度之電鍍金屬層3 0 3，3 1 3。然後，在該芯層板3 0，3 1形成有盲孔3 0 2，3 1 2之一側利用蝕刻等方式進行該電鍍金屬層3 0 3，3 1 3之圖案化製程，以在該芯層板3 〇，3 1之一表面上形成第一圖案化線路層303a，313 a與導電盲孔302a，31 2a，1270331 V. INSTRUCTION DESCRIPTION (7) 3 1. The core layer 3 0, 3 1 is formed with a metal layer 3 0 1, 3 11 ' on the surface and is laser-drilled in the anger layer 30, 31 Drilling a plurality of blind holes 3 0 2, 312 (as shown in FIG. 3B) so that the bottom layer of the blind holes 3 0 2, 3 1 2 exposes the metal layer 3 on the other surface of the anger layer 30, 31 〇 1,311. The insulating portion of the core layer 30, 31 may be epoxy resin (EP 0χ Υ res丨n), polyimide, cyanoate (Cyanate Ester), glass fiber, double-butadiene It is made of Bismaleimide Triazine (BT) or mixed epoxy resin and FR5 material of glass fiber. The metal layer 30 1 is generally made of copper (Cu) which is preferably electrically conductive, and the metal layer 3 0 1, 31 1 may be pressed or deposited on the insulating core layer first, or may be laminated using a resin # Copper foil (Resin coated copper, RCC) is formed. As shown in Figure 3C, techniques such as physical vapor deposition (PVD), chemical vapor deposition (CVD), electroless plating, or chemical deposition, such as sputtering, evaporation, and arc vapor deposition, are selected. Arc vapor deposition, Ion beam sputtering, laser ablation deposition, plasma-promoted chemical vapor deposition or electroless plating, on the core plate 30, 3 1 has blind holes 302, 31 2 on the surface and blind holes 302, 31 2 formed a conductive layer (not shown) as a current conduction path, using an electroplating process to surface metal on the core plate 30, 31 A layer 301 and a blind via 3 0 2, 3 1 2 form a plated metal layer 3 0 3, 3 1 3 of sufficient thickness. Then, the core layer 30, 31 is formed with a blind hole 3 0 2, and one side of the 3 1 2 is patterned by etching or the like to perform the patterning process of the plated metal layer 3 0 3, 3 1 3 Forming a first patterned circuit layer 303a, 313a and conductive blind holes 302a, 31 2a on one of the core plates 3 〇, 31

17661 全懋.ptd 第15頁 1270331 五、發明說明（8) 如第3D圖所示。當然，前述之線路圖案化製程亦可以電鐘_ 方式形成，可在形成導電層後覆蓋一圖案化電錢阻層（未圖示），並進行電鍍以形成該第一圖案化線路層303a，313a 與導電盲孔3 0 2 a，3 1 2 a，然後再予以移除該電鑛阻層與覆蓋其下之導電層。如第3E圖所示，而後將上述表面形成有第一圖案化線路層30 3a，31 3a與導電盲孔3 0 2a，31 2a之該些芯層板30, 31 間夾置一絕緣層3 5，該絕緣層3 5可依熱壓、塗佈、或其他適當方式以相對接合該些芯層板3 0，3 1，並使該些芯層板 30,31中形成有第一圖案化線路層3 0 3a， 313a之表面為該❿ 絕緣層3 5所覆蓋，同時使該絕緣層3 5充填至該導電盲孔 3 0 2a，31 2a中，藉以形成一多層板，如第3F圖所示。其中 ’該絕緣層 3 5可為例如 ABF( Ajinomoto Build-up Film，商品名’曰商味之素公司出產）層，當然，該絕緣層3 5亦可選用其他具不同特性之絕緣材料，而非以本實施例中所述者為限。 * 如第3G圖所示，係以例如機械鑽孔方式於該完成接合之多層板中鑽設多凄丈貫穿該多層板之通孔32，並於該通孔 32之孔壁形成一金屬層320 ’並填充—導電或不導電之填充材料3 2 1於該專通孔3 2中’如第3 η圖戶斤_ ' 如第3 I圖所示，接下來，進杆蜱狄不0 構成該多層板之芯層板30, 31表面上’圖案化製程’以於二圖案化線路層3〇3b，313b及電_導=該通孔32中形成第二圖案化線路層3 0 3b，3 13b具有^數^孔33。其中，該第 I數電性連接墊3 0 3c，31317661 懋.ptd Page 15 1270331 V. Description of invention (8) as shown in Figure 3D. Of course, the foregoing circuit patterning process can also be formed by an electric clock, and after forming a conductive layer, a patterned electric money resist layer (not shown) can be covered and electroplated to form the first patterned circuit layer 303a. 313a and the conductive blind hole 3 0 2 a, 3 1 2 a, and then the conductive layer and the conductive layer covering the underlying layer are removed. As shown in FIG. 3E, an insulating layer 3 is interposed between the core sheets 30, 31 of the first patterned circuit layer 30 3a, 31 3a and the conductive blind vias 3 0 2a, 31 2a. 5, the insulating layer 35 may be oppositely bonded to the core sheets 30, 3 1 by heat pressing, coating, or other suitable manner, and the first patterning is formed in the core sheets 30, 31. The surface of the circuit layer 3 0 3a, 313a is covered by the insulating layer 35, and the insulating layer 35 is filled into the conductive blind holes 3 0 2a, 31 2a to form a multilayer board, such as the 3F. The figure shows. The insulating layer 35 may be, for example, a layer of ABF (Ajinomoto Build-up Film), and of course, the insulating layer 35 may also be made of other insulating materials having different characteristics. Not limited to those described in this embodiment. * As shown in FIG. 3G, a plurality of through holes 32 penetrating the multi-layer board are drilled in the completed multi-layer board by, for example, mechanical drilling, and a metal layer is formed on the hole wall of the through hole 32. 320 'and filled - conductive or non-conducting filling material 3 2 1 in the through hole 3 2 'as the 3rd η map _ _ ' as shown in Figure 3, next, enter the rod Di Di 0 Forming a 'patterning process' on the surface of the core sheets 30, 31 of the multilayer board to form a second patterned circuit layer 3 0 3b in the second patterned circuit layers 3〇3b, 313b and the vias , 3 13b has ^ number ^ hole 33. Wherein, the first number of electrical connection pads 3 0 3c, 313

1270331 五、發明說明（9) ~ '~~ -- 之:^性連接墊303。，313祕'形成在該芯層板3〇,3i 2二目L3〇2a，312a底部。其中，由於圖案化製程係屬 ;第=此不再為文贅述。0此，本發明係可分別在弟—圖尔化線路層3 03b， 313b中定義複數電性連接墊1270331 V. Description of the invention (9) ~ '~~ --: The connection pad 303. , 313 secret 'formed on the bottom of the core layer 3〇, 3i 2 binocular L3〇2a, 312a. Among them, because the patterning process is a system; the second = this is no longer a text. 0, the present invention can define a plurality of electrical connection pads in the Brother-Turley circuit layers 3 03b, 313b, respectively.

且令至少一電性連接塾3〇3c，313c形成於上述 j心層板30,31之導電盲孔3〇2a，312a底部，以供形成電性連接之直接傳導路徑，而無須如習知技術於一電性連接墊背面額外佈線以將其連結至承接導電盲孔之電性連接墊。故二本發明可將預先經雷射形成之盲孔作為諸如電性連接，等導電線路之一部份，進而相對減少電性連接墊之設置量’而且，本發明不受導電盲孔之佈設空間之限更可擴大電路板之佈局空間與靈活性。And at least one electrical connection 塾3〇3c, 313c is formed at the bottom of the conductive blind holes 3〇2a, 312a of the j core layer 30, 31 for forming a direct conduction path of the electrical connection, without The technology is additionally wired on the back of an electrical connection pad to connect it to an electrical connection pad that receives the conductive via. Therefore, the present invention can use a blind hole formed in advance by laser as a part of a conductive line such as an electrical connection, thereby relatively reducing the amount of the electrical connection pad. Moreover, the present invention is not provided by the conductive blind hole. The space limit can also expand the layout space and flexibility of the board.

如第3J圖所示，於第二圖案化線路層3〇3b，313b上形成=圖案化拒銲劑層（solder mask) 34，以外露出部分 4第一圖案化線路層3〇3b，313b之電性連接墊3〇3c μ? 且於該電性連接墊3 0 3c，313c上形成有金屬保護層36，例如錄/金金屬層或其他適當之金屬保護層，以保護該電性連接墊3 0 3c，313c，並可提供該電性連接墊3〇3c，313c與其他導，元件良好電性連接。其後復可在該電性連接墊^植接有銲線、錫球、金屬凸塊或其他適當導電元件，俾供後續作用為承載半導體晶片之電路板。明參閱苐3 I圖’透過前述製程本發明亦揭露出一種具多層線路層之電路板，係包括：複數芯層板3 〇，3卜於該芯層板30, 31之一表面上形成有第一圖案化線路層3〇3a，As shown in FIG. 3J, a patterned solder mask 34 is formed on the second patterned wiring layer 3〇3b, 313b, and the first patterned wiring layer 3〇3b, 313b is exposed. a metal connection layer 36, such as a recording/gold metal layer or other suitable metal protection layer, is formed on the electrical connection pads 3 0 3c, 313c to protect the electrical connection pads 3 0 3c, 313c, and the electrical connection pads 3〇3c, 313c can be provided with other conductive components. Thereafter, solder wires, solder balls, metal bumps or other suitable conductive elements are implanted on the electrical connection pads for subsequent operation as a circuit board carrying the semiconductor wafer. The present invention also discloses a circuit board having a multi-layer circuit layer, comprising: a plurality of core layers 3, 3, and a surface of one of the core sheets 30, 31 formed on the surface of the core layer 30, 31 The first patterned circuit layer 3〇3a,

17661 全懋.ptd 第17頁 1270331 五、發明說明（ίο) 3 1 3 a及複數導電盲孔3 0 2 a，3 1 2 a ’而於該芯層板3 〇，3 1之另一表面上形成有第二圖案化線路層3〇3b，313b，以令該第二圖案化線路層303b，313b中至少一電性連接墊303c，313c 係對應至該導電盲孔3 0 2 a，3 1 2 a底部；至少一絕緣層3 5 ’ 係夾置於該些芯層板3 0，3 1之間；以及多數形成於該芯層板3 0，3 1中之電鑛導通孔3 3，以供電性導接該怒層板3 〇，3 1 之線路層。另外，請參閱第4A至第4E圖，係表示本發明具多層線路層之電路板及其製法之另一較佳實施態樣。惟，本實施 φ 例之結構及製法與前述實施例大致上相同，其不同之處僅在於本實施例係於該多層板中形成導電盲孔，而非前述& 實施例中係形成貫穿該多層板之電錢導通孔。故，下列戶斤說明者僅為示例性說明，並非用以限定本發明者，而相同元件符號係用以代表相同之元件，故相同作用及結構之處不再多作敘述，僅就不同之處說明。如第4 A圖所示，提供一已完成接合之多層板。其中該多層板依前述實施例中之第3A至第3F圖所示之製糕而形成者。 ; 如第4B圖所示，係於該多層板之上下兩側分別採用例· 如雷射鑽孔技術鑽設複數盲孔4 1，以外露出該芯層板3 〇 ’ 31之第一圖案化線路3 0 3a，313a。接著，於該多層板及盲，孔4 1表面形成一金屬層4 2，如第4 C圖所示，其係玎選擇用物理氣相沈積（PVD)、化學氣相沈積（CVD)、無电 / 或化學沈積等技術，例如丨賤鍵（S p u 11 e r i n g)、蒸鑛17661 全懋.ptd Page 17 1270331 V. Invention Description (ίο) 3 1 3 a and a plurality of conductive blind holes 3 0 2 a, 3 1 2 a 'and on the other side of the core layer 3 3, 3 1 The second patterned circuit layer 3〇3b, 313b is formed on the second patterned circuit layer 303b, 313b, and the at least one electrical connection pad 303c, 313c corresponds to the conductive blind hole 3 0 2 a, 3 1 2 a bottom; at least one insulating layer 3 5 ' is sandwiched between the core sheets 3 0, 31; and most of the electric ore vias 3 3 formed in the core sheets 3 0, 31 The power layer is connected to the circuit layer of the anger layer 3 〇, 3 1 . Further, referring to Figs. 4A to 4E, there is shown another preferred embodiment of the circuit board having the multilayer wiring layer of the present invention and a method of manufacturing the same. However, the structure and manufacturing method of the embodiment of the present embodiment are substantially the same as those of the foregoing embodiment, except that the present embodiment is formed in the multilayer board to form a conductive blind hole, instead of the above-described embodiment. The electric money conduction hole of the multi-layer board. Therefore, the following descriptions are merely illustrative and are not intended to limit the inventors, and the same component symbols are used to represent the same components, so the same functions and structures are not described more, only different. Description. As shown in Figure 4A, a multi-layer board that has been joined is provided. The multilayer board is formed by the cakes shown in Figs. 3A to 3F of the foregoing embodiment. As shown in FIG. 4B, the first patterning of the core layer 3 〇' 31 is exposed by using a plurality of blind holes 4 1 on the upper and lower sides of the multi-layer board, for example, by laser drilling technology. Line 3 0 3a, 313a. Next, a metal layer 42 is formed on the surface of the multilayer board and the blind hole 4, as shown in FIG. 4C, and the system is selected by physical vapor deposition (PVD), chemical vapor deposition (CVD), or Techniques such as electricity/chemical deposition, such as S pu 11 ering, steaming

17661 全懋.ptd17661 full 懋.ptd

1270331 五、發明說明（Π)1270331 V. Description of invention (Π)

Evaporation)、電弧蒸氣沈積（Arc vapor depositi〇n. )、離子束藏鍍（Ion beam sputtering)、雷射炫散沈積（Laser ablation deposition)、電漿促進之化學氣相沈積或無電鍍等方法，於該芯層板3 0，3 1及盲孔41表面形成有一導電層（未圖示）以作為電流傳導路徑，俾利用電鍍製程以在該芯層板3 0，3 1及盲孔4 1表面形成一具足夠厚度之電鍍金屬層42。如第4D圖所示，進行線路圖案化製程，以於構成該多層板之芯層板3 0，3 1表面上及盲孔4 1中形成第二圖案化線路層303b，313 b及導電盲孔41a。如圖所示，該第二圖案化線路層303b，313 b具有複數電性連接墊303c，313c，且至少一電性連接墊3 0 3 c，3 1 3 c係形成在該芯層板3 〇，3 1之導電盲孔3 0 2 a，3 1 2 a底部。因此，本發明係在該第二圖案化線路層30 3b，3 13b中定義複數電性連接墊3 0 3c，3 13c，且令7至少一電性連接墊3 0 3c，31 3,形成於上述芯層板3〇, 3丨之&電^ 孔3 0 2 a，3 1 2 a底部，毋須額外佈線以將該電性連接墊3 〇 3 2 313c連結至另一電性連接墊，更毋須再由後者之電性連I 塾承接一導電盲孔以電性連接至内層線路，如此將可簡化佈、、泉’且形成直接之傳導路徑。故，本發明可解決習知術之缺失而不受導電盲孔之佈設空間之限，除了可擴大恭路板之線路佈局面積外，更令電路板之線路佈局具靈活2 如第4E圖所示，之後，於該多層板表面形成一拒銲劑層34，藉以外露出部份第二圖案化線路層3^/、Evaporation, arc vapor deposition, arc beam deposition, Ion beam sputtering, laser ablation deposition, plasma-induced chemical vapor deposition, or electroless plating, A conductive layer (not shown) is formed on the surface of the core layer 3 0, 31 and the blind via 41 as a current conduction path, and an electroplating process is used to form the core layer 3 0, 31 and the blind via 4 1 . The surface forms a layer of electroplated metal 42 of sufficient thickness. As shown in FIG. 4D, a line patterning process is performed to form a second patterned circuit layer 303b, 313b and a conductive blind in the surface of the core layer 30, 31 formed in the multilayer board and in the blind via 41. Hole 41a. As shown, the second patterned circuit layer 303b, 313b has a plurality of electrical connection pads 303c, 313c, and at least one electrical connection pad 3 0 3 c, 3 1 3 c is formed on the core layer 3 〇, 3 1 conductive blind hole 3 0 2 a, 3 1 2 a bottom. Therefore, in the second patterned circuit layer 30 3b, 3 13b, the plurality of electrical connection pads 3 0 3c, 3 13c are defined, and at least one of the electrical connection pads 3 0 3c, 31 3 is formed in The core plate 3〇, 3丨&Electrical hole 3 0 2 a, 3 1 2 a bottom, no additional wiring is required to connect the electrical connection pad 3 〇 3 2 313c to another electrical connection pad, Furthermore, it is no longer necessary for the latter to receive a conductive blind via to electrically connect to the inner layer, which will simplify the cloth and spring and form a direct conduction path. Therefore, the present invention can solve the shortcoming of the conventional technique without being limited by the layout space of the conductive blind hole. In addition to expanding the layout area of the Gonggong board, the circuit layout of the circuit board is more flexible, as shown in FIG. 4E. After that, a solder resist layer 34 is formed on the surface of the multilayer board, and a portion of the second patterned circuit layer 3^/ is exposed.

1270331 五、發明說明（12) 3=電性連接墊3 03c，31 3c ’並於該電性連接塾3〇3c，後復其他路板 3 1 3 c上形成有金屬保護層3 6，由該全屬仅崎轻〇 λ ，墊，，仙與其他導電元件接：;；；：：=錫球、金屬凸塊或。彳千俾仏後項忭用為承載半導體晶片之電說雖前述實施例中係以具有四層 …，惟應了解的是，本發明亦路；為例作路板。如第5圖所示，係表示本發Τ應用於其他層數之電板及其製法之另—較佳實施態樣。月复、夕層線路層之電路 30, 31間隔夾置有絕緣層35盥一 ”主要於複數芯層板間俾以形成具更多線路層曰之電路二電路板50進行接合，六層線路層之電路板）。i V如圖中之實施例係為具線路層數或其他之製 ^所完成接合之電路板或孔係可為貫穿該電路接該多層線路層 :線=2電盲％，抑或 =通孔，或部分貫定。 …]所述者所限制，而可因此，本發明之罝夕在複數芯層板之—倒形路層之電路板及其製法係可間形成有導電盲孔 < :電盲孔後，#於該些電路板徑，避免習知技術驚在=性連接墊之直接電性傳導： $[連接墊處額外佈線以將其連1270331 V. INSTRUCTION DESCRIPTION (12) 3=Electrical connection pads 3 03c, 31 3c 'and the electrical connection 塾3〇3c, and the other circuit boards 3 1 3 c are formed with a metal protection layer 3 6 The whole is only 崎〇垫, mat, 仙, and other conductive elements:;;;::= solder balls, metal bumps or. The latter is used to carry the semiconductor wafer. Although the foregoing embodiment has four layers, it should be understood that the present invention is also a road; for example, a circuit board. As shown in Fig. 5, it is another preferred embodiment of the present invention which is applied to other layers of the board and its method of manufacture. The circuit 30, 31 of the monthly complex circuit layer is interposed with an insulating layer 35"" mainly between the plurality of core plates to form a circuit 2 circuit board 50 with more circuit layers, and the six-layer circuit The circuit board of the layer) i V as shown in the embodiment is a circuit board or other system to complete the bonding of the circuit board or hole system can be connected to the circuit layer through the circuit: line = 2 electric blind %, or = through hole, or partially determined. ...] the limitation of the above, and thus, the present invention can be formed between the circuit board of the inverted core layer of the plurality of core sheets and the manufacturing system thereof There are conductive blind holes < : after electric blind holes, # in the circuit board diameter, to avoid the direct electrical conduction of the technical connection in the = sexual connection pad: $ [additional wiring at the connection pad to connect it

17661 全懋.ptd 第20頁 ::側形成具多數電性連：：絕緣層，之後於該電路板之電盲孔底端可選擇十之圖案化線路層，以電性連接墊，藉以減少製程線路佈局空間。層之電路板及其製法係使線導電盲孔底部，且無須考慮置’藉以增加電路板之線路路佈局靈活性，藉以解決習發明之具多層線路層之電路十生連接墊供與導電盲孔作承之縱向電性導接，藉此相對降低製程之成本。且本發明間所限，從而擴大電路板之局更具靈活性。此外，於電圖案化線路層及電性連接墊料充填於導電盲孔中，亦程步驟。限於實施例所述方法，其他效替代步驟，例如改變多層本發明之可實施範圍。上述之原理及其功效，而非用於之人士均可在不違背本發明例進行修飾與變化。因此，後述之申請專利範圍所列。 1270331 五、發明說明（13) 結至承接於導電盲孔開孔處之步驟及複雜性，同時避免佔用另，本發明之具多層線路路層之電性連接墊直接設置於導電盲孔之佔設空間及開設位佈局面積，並提高電路板之線知技術之種種缺失。再者，本板及其製法毋須額外多設置電接，便可進行電路板各線路層減少電性連接墊之設置量，以亦不受導電盲孔開孔之佔設空外層線路佈局面積，令線路佈路板之導電盲孔底端表面形成時，亦無須將諸如銅之填充材更加降低製程之成本並減少製本發明之前揭步驟並未僅電路板製程、設備或材料之尊電路板之製備層數等亦包含於實施例僅為例示性說明本發明限制本發明。任何熟習此技藝之精神及範疇下，對上述實施本發明之權利保護範圍，應如17661 全懋.ptd Page 20:: The side is formed with a plurality of electrical connections:: Insulation layer, then the patterned circuit layer of ten can be selected at the bottom of the electric blind hole of the circuit board to electrically connect the pads, thereby reducing Process line layout space. The circuit board of the layer and the manufacturing method thereof make the bottom of the wire conductive blind hole, and it is not necessary to consider the flexibility of the circuit path layout of the circuit board, so as to solve the circuit of the multi-layer circuit layer of the invention. Kong Zuocheng's longitudinal electrical connection, which reduces the cost of the process. And the invention is limited, thereby expanding the board layout to be more flexible. In addition, the electrically patterned circuit layer and the electrical connection pad are filled in the conductive blind vias, which are also steps. The method described in the examples is limited to other alternative steps, such as changing the range of implementation of the present invention. Modifications and variations can be made without departing from the scope of the invention. Therefore, the scope of the patent application described later is listed. 1270331 V. Description of the invention (13) The step and complexity of the connection to the opening of the conductive blind hole, and avoiding occupation, the electrical connection pad with the multi-layer circuit layer of the invention is directly disposed in the conductive blind hole Set space and open layout area, and improve the lack of circuit board technology. Moreover, the board and the manufacturing method thereof need not be provided with an additional number of electrical connections, so that the circuit board can reduce the setting amount of the electrical connection pads, and the layout area of the empty outer layer is not affected by the conductive blind hole opening. When the bottom surface of the conductive blind hole of the circuit board is formed, it is not necessary to reduce the cost of the process, such as copper, and reduce the manufacturing process of the present invention, which is not only the circuit board process, equipment or material. The number of layers and the like are also included in the examples, which are merely illustrative of the invention and are intended to limit the invention. In the spirit and scope of any skill in the art, the scope of protection of the above-described embodiments of the present invention should be as

17661 全懋.ptd17661 full 懋.ptd

1270331 圖式簡單說明【圖式簡單說明】：第1 A圖至第1 C圖係習知之半加成法製程示意圖；第2 A圖至第2 C圖係習知之線路電鍍法製程示意圖；第3 A圖至第3 J圖係本發明具多層線路層之電路板之第一實施例剖面示意圖；第4A圖至第4E圖係本發明具多層線路層之電路板之第二實施例剖面示意圖；以及第5圖係本發明具多層線路層之電路板之第三實施例剖面示意圖。 (元件符號說明） 10 核心電路板 11 絕緣層 110 開孔 12 内層線路層 13 導電層 14 阻層 15 圖案化線路層 16,26 電性連接墊 20 核心電路板 21 絕緣層 211 金屬層 210 開孔 22 内層線路層 23 導電層1270331 Brief description of the drawing [Simplified description of the drawing]: Fig. 1A to Fig. 1C are schematic diagrams of the conventional semi-additive process; Fig. 2A to Fig. 2C are schematic diagrams of the conventional circuit plating process; 3A to 3J are cross-sectional views showing a first embodiment of a circuit board having a multilayer wiring layer; and FIGS. 4A to 4E are cross-sectional views showing a second embodiment of a circuit board having a multilayer wiring layer of the present invention; And FIG. 5 is a cross-sectional view showing a third embodiment of the circuit board having the multilayer wiring layer of the present invention. (Component symbol description) 10 core circuit board 11 insulation layer 110 opening 12 inner layer circuit layer 13 conductive layer 14 resist layer 15 patterned circuit layer 16, 26 electrical connection pad 20 core circuit board 21 insulation layer 211 metal layer 210 opening 22 inner layer circuit layer 23 conductive layer

17661 全戀.ptd 第22頁 1270331 圖式簡單說明 2 4 阻層 25 圖案化線路層 30, 31 芯層板 301,311 金屬層 302, 312 盲孔 302a，312a導電盲孔 3 0 3,3 1 3 電鍍金屬層 303a，313a第一圖案化線路層 303b，313b第二圖案化線路層 303c, 313c 電性連接墊 35 絕緣層 32 通孔 320 金屬層 321 填充材料 33 電鍍導通孔 34 拒銲劑層 36 金屬保護層 41 盲孔 41a 導電盲孔 42 金屬層 50 電路板17661 全恋.ptd Page 22 1270331 Schematic description 2 4 Resistive layer 25 Patterned circuit layer 30, 31 Core layer 301, 311 Metal layer 302, 312 Blind hole 302a, 312a Conductive blind hole 3 0 3,3 1 3 Plating Metal layer 303a, 313a first patterned circuit layer 303b, 313b second patterned circuit layer 303c, 313c electrically connected pad 35 insulating layer 32 via 320 metal layer 321 filling material 33 plating via 34 solder resist layer 36 metal protection Layer 41 blind hole 41a conductive blind hole 42 metal layer 50 circuit board

17661 全懋.ptd 第23頁17661 懋.ptd第23页

Claims

月％日修(吏)正替換頁 ——ί— 案號93114393 I,j 年&月％日 ^ 六、申請專利範圍 — -- 1 · 一種具多層線路層之電路板製法，係包括：提供複數表面形成有金屬層之芯層板；於該芯層板一表面形成複數盲孔，藉以外芯層板另一表面之金屬層；出讀進行線路圖案化製4 1以在該芯層板具有表面上形成第一圖案化線路層與複數導電盲孔，·之將該些芯層板形成有導電盲孔之一侧間隔有的層以相互接合形成一多層板； β、、、巴緣於該多層板中開設複數通孔；以及進行線路圖案化製程，以於該多層板之表面及董、應通孔處形成弟一圖案化線路層及複數導電通孔 f 該弟二圖案化線路層係具有複數電性連接塾，其中少一電性連接墊係形成在該芯層板之導電盲孔底1至 2 ·如申請專利範圍第1項之具多層線路層之電路板製去其中，該盲孔係以雷射鑽孔方式形成。 & ' ’ 3.如申請專利範圍第1項之具多層線路層之電路板黎】、該通孔中可填充一填充材料。 "去5 4 ·如申請專利範圍第1項之具多層線路層之電路板擎、其中，該導電通孔為電鍍導通孔及導電盲孔之/ /套：者。 ~中〜 5 ·如申請專利範圍第1項之具多層線路層之電路板製、其中，該導電通孔係貫穿多層板，以供後續飛法’ 導通孔。 4成電鍍 6 · 如申請專利範圍第1項之具多層線路層之電政士 %纷叛製法，Month % Daily Repair (吏) is replacing page - ί - Case No. 93114393 I, j year & month % day ^ VI. Patent application scope - 1 · A circuit board method with multiple circuit layers, including: Providing a core layer having a metal layer formed on the plurality of surfaces; forming a plurality of blind holes on one surface of the core layer board, and forming a metal layer on the other surface of the outer core layer; and performing line patterning on the core layer to read the core layer The plate has a first patterned circuit layer and a plurality of conductive blind holes formed on the surface, and the core plates are formed with a layer separated by one side of the conductive blind holes to be joined to each other to form a multilayer board; β, ,, a peripheral hole is formed in the multi-layer board; and a circuit patterning process is performed to form a patterned circuit layer and a plurality of conductive vias on the surface of the multilayer board and the through holes of the board The circuit layer has a plurality of electrical connection ports, wherein one less electrical connection pad is formed on the conductive blind hole bottoms 1 to 2 of the core layer plate. The circuit board system has a multilayer circuit layer according to the first item of the patent application scope. Going to it, the blind hole is laser-drilled The way is formed. & ' ’ 3. The circuit board with a multi-layer circuit layer as claimed in claim 1 can be filled with a filling material. " Go to 5 4 · As claimed in the patent scope, the circuit board with a multi-layer circuit layer, wherein the conductive via is a plating via and a conductive blind hole / / sleeve: . ~中~5 · A circuit board having a multi-layer circuit layer as claimed in claim 1, wherein the conductive vias penetrate the multilayer board for subsequent flying method. 4 into electroplating 6 · If you apply for the multi-layer circuit layer of the first item of patent scope, the economist

17661(修正本）.ptc 第24頁 _頁 θί 年 G 月 βΒ 修正_ 六、Vm丽其中，該導電通孔係未貫穿該多層板，以供後續形成導電盲孔。 7. 如申請專利範圍第1項之具多層線路層之電路板製法，其中，該第二圖案化線路層上係形成一圖案化拒銲層，且係外露出部份該第二圖案化線路層。 8. 如申請專利範圍第1項之具多層線路層之電路板製法，其中，該電性連接墊上形成有金屬保護層，以保護該電性連接墊並供有效電性連接導電元件。 9. 如申請專利範圍第8項之具多層線路層之電路板製法，其中，該導電元件係由銲線、錫球及金屬凸塊所組成之群組之其中一者。 1 0 .如申請專利範圍第8項之具多層線路層之電路板製法，其中，該金屬保護層係為鎳/金金屬層。 11.如申請專利範圍第1項之具多層線路層之電路板製法，其中，該芯層板間係可間隔有絕緣層以與多層電路板進行接合。 1 2. —種具多層線路層之電路板，係包括：複數芯層板，該芯層板之一表面形成有第一圖案化線路層及導電盲孔，而於該芯層板之另一表面形成有第二圖案化線路層，該第二圖案化線路層係具有複數電性連接墊，且至少一電性連接墊係形成在該芯層板之導電盲孔底部；至少一絕緣層，係夾置於該些芯層板之第一圖案化線路層及導電盲孔中；以及17661 (Revised). ptc Page 24 _Page θί年 G 月βΒ Correction _ VI. Vm 丽 Among them, the conductive via does not penetrate the multilayer board for subsequent formation of conductive blind holes. 7. The circuit board method according to claim 1, wherein the second patterned circuit layer forms a patterned solder resist layer, and the second patterned circuit is exposed outside. Floor. 8. The method of manufacturing a circuit board having a multi-layer circuit layer according to claim 1, wherein the electrical connection pad is formed with a metal protective layer to protect the electrical connection pad and to electrically connect the conductive element. 9. The method of manufacturing a circuit board having a multi-layer circuit layer according to claim 8, wherein the conductive element is one of a group consisting of a bonding wire, a solder ball, and a metal bump. A method of manufacturing a circuit board having a multilayer circuit layer according to claim 8 wherein the metal protective layer is a nickel/gold metal layer. 11. The method of manufacturing a circuit board having a multilayer circuit layer according to claim 1, wherein the core sheets are interposed with an insulating layer to be bonded to the multilayer circuit board. 1 2. A circuit board having a multi-layer circuit layer, comprising: a plurality of core plates, a surface of one of the core plates being formed with a first patterned circuit layer and a conductive blind hole, and the other of the core plates Forming a second patterned circuit layer on the surface, the second patterned circuit layer has a plurality of electrical connection pads, and at least one electrical connection pad is formed on the bottom of the conductive blind hole of the core layer; at least one insulating layer, The clip is placed in the first patterned circuit layer and the conductive blind hole of the core sheets;

17661(修正本）.ptc 第25頁修正 127(聯“為魅碰換頁丨你六、申請專利範圍複數導電通孔，係形成於該芯層板中，以供電性導接該些芯層板。 1 3 .如申請專利範圍第1 2項之具多層線路層之電路板，其中，該等盲孔係以雷射鑽孔方式而鑽設形成。 1 4 .如申請專利範圍第1 2項之具多層線路層之電路板，其中，該導電通孔為電鍍導通孔及導電盲孔之其中一者。 1 5 .如申請專利範圍第1 2項之具多層線路層之電路板，其中，該導電通孔係貫穿多層板，以供後續形成電鍍導其導其，，成，層板形板銲路續路拒電後電化之供之案層以層圖。路，路一層線板線成路層層層形線多多多係化具該具上案之穿之層圖項貫項路二 2 2 1未 1線第第係第化該圍孔圍案份範通範圖部利電利二出專導。專第露。請該孔請該外孔申，盲申，係通如中電如中且其電其之，該，成板護板組路保路所電以電塊之，之凸層層。層屬路護件路金線保元線及層屬電層球多金導多錫具有接具、之成連之線項形性項銲 2 8 11 上 11 由第墊效第係。圍接有圍件者範連供範元一利性並利電中專電塾專導其請該接請該之申，連申，組如中性如中群17661 (Revised). ptc Page 25 Amendment 127 (Linked for the charm touch page 丨 you six, the patent application range of multiple conductive through holes, formed in the core layer, to electrically connect the core boards 1 3 . A circuit board having a multi-layer circuit layer as claimed in claim 12, wherein the blind holes are formed by laser drilling. 1 4. If the patent application scope is item 12 a circuit board having a multi-layer circuit layer, wherein the conductive via is one of a plating via and a conductive via. 1 5. A circuit board having a multilayer circuit layer according to claim 12, wherein The conductive vias are penetrated through the multi-layer board for subsequent electroplating to guide them, and the layer-by-layer board line is formed by the layer of the strip-shaped board soldering circuit after the circuit is rejected. The formation of the layered layered line is more than a multi-system with the layer of the above-mentioned case of the project. The project is two 2 2 1 not the first line of the first system of the perforation of the peri-scope case Fan Tong Fan Tu Li Li Er out of the special guide. Specially exposed. Please ask the hole to apply for the outer hole, blind application, the system is like If the electricity is in the middle and the electricity is the same, the plate-protecting plate is protected by the electric block, and the convex layer is layered. The layer is protected by the road gold wire and the layer is the electric layer ball gold. Leading tin has the connection, the connection of the line item shape welding 2 8 11 on the 11th by the first pad effect. Enclosed with the accessories Fan Fan for Fan Yuanyi benefit and interest in the secondary school Please ask the applicant to pick up the application, even the application, the group is as neutral as the group

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:頁气歹年b月义曰修正六、申請專利範圍 2 1 .如申請專利範圍第1 2項之具多層線路層之電路板，其中，該芯層板間係間隔有絕緣層以與多層電路板進行接合。: Page 歹歹 b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b b The board is joined.

17661(修正本）.ptc 第27頁17661 (Revised).ptc Page 27