1270193 ，九.、發明說明： 【發明所屬之技術領域】 本發明係有關於二極體串以及相關之靜電放電防護電路， 尤指具有低漏電流的二極體串以及靜電放電防護電路。 【先前技術】 在所有應用於晶片靜電放電元件與電路中’二極體是一個 結構最簡單的靜電放電防護元件。適當運用該元件順向導通特 性，只需要消耗少量的晶片面積，即可非常有效率地保護晶片 > 避免受到靜電放電的破壞。 傳統的二極體串是單純的利用順向串接數個二極體所組 成。將一傳統的二極體串（diode string)連接於一高電源線(Vhigh) 以及一低電源線（Vi〇w)之間，即可作為一靜電放電防護電路。 然而，由於電路結構中寄生一個由雙極性電晶體（bipolar transistor，BJT)串接組成的達靈頓放大電路（Darlington Amplifier)，造成串接二極體組成的靜電放電防護電路會產生流 向基座（substrate)的基座漏電流（iLeakage，substrate leakage > current)。當晶片正常操作於高溫環境，或是串接二極體的數目 變多，漏電問題將會變的更加嚴重。 傳統的解決漏電問題的方法大致可以歸類為兩個方向，一 個是從電路方面著手’增加部分的電路來降低達靈頓放大電路 的電流增益（gain);另一個是從二極體結構著手，希望完全消除 達靈頓放大電路的存在。 【發明内容】 本發明之-目的是降低提供-二極體串於正常操作時的漏 0821 -A20685CIPTWF(N2) ；P 18930006TWA1 ;edward 5 1270193 .電流。 本發明之一實施例提出一具有低漏電流的二極體串（diode string)。該二極體串包含有複數二極體區、一阻絕區以及一偏壓 電阻。該等二極體區提供複數二極體。每一二極體區包含有一 第一極區（1st polar region)以及一第二極區（2nd polar region)。該 第一極區為一第一導電型，設於一基底上，作為一對應二極體 的一第一電極。該第二極區，為與該第一導電型相反之一第二 導電型，設於該第一極區中，作為該對應二極體的一第二電極。 | 該等二極體係為串接在一起，以提供該二極體串的一主陽極以 及一主陰極。該阻絕區為該第二導電型，用以分隔該等二極體 區。該偏壓電阻連接於該阻絕區以及一第一電源線之間。於正 常操作時，該第一電源線之電壓係不位於該主陽極與該主陰極 之電壓之間。 本發明之另一實施例提供另一具有低漏電流的二極體串 (diode string)。該二極體串包含有複數雙極性接面電晶體以及一 偏壓電阻。每一 BJT包含有一集極（collector) —射極（emitter) 以及一基極（base)。一 BJT的該射極係連接至下一 BJT的該基 ® 極。每一 BJT的集極係連接在一起。第一 BJT的該基極與最後 B JT的該射極係作為該二極體串的二主電極。該偏壓電阻連接 於每一 BJT的集極與一第一電源線之間。於正常操作時，該第 一電源線之電壓係不位於該二主電極之電壓之間。 偏壓電阻可以降低於該正常操作時，該二極體串中寄生之 •達靈頓放大電路中的集極電流，因此可以抑制該二極體串的漏 : 電流。 為使本發明之上述目的、特徵和優點能更明顯易懂，下文 特舉一較佳實施例，並配合所附圖式，作詳細說明如下： 0821 -A20685CIPTWF(N2) ;P 18930006TWA1 ;edward 6 1270193 【實施方式】 第la圖為實施本發明之一二極體串的剖面圖。在第ia圖 中，一二極體串1〇〇形成於一 p型半導體基底（p_type substrate)102的一晶片上“乂一般的三層井作^化,……]^^ 製程所製作。1270193, IX. Invention: TECHNICAL FIELD The present invention relates to a diode string and related electrostatic discharge protection circuit, and more particularly to a diode string having a low leakage current and an electrostatic discharge protection circuit. [Prior Art] In all of the application to the chip electrostatic discharge element and circuit, the 'diode is the simplest electrostatic discharge protection element. By properly applying the component's pass-through characteristics, it is only necessary to consume a small amount of wafer area to protect the wafer very efficiently > to avoid damage from electrostatic discharge. A conventional diode string is simply composed of a plurality of diodes connected in series. A conventional diode string is connected between a high power line (Vhigh) and a low power line (Vi〇w) to act as an ESD protection circuit. However, due to a parasitic Darlington Amplifier consisting of a bipolar transistor (BJT) connected in a circuit structure, an ESD protection circuit composed of a series diode is generated to flow to the pedestal. Substrate leakage current (iLeakage, substrate leakage > current). When the wafer is operating normally in a high temperature environment, or the number of serially connected diodes is increased, the leakage problem will become more serious. The traditional method of solving the leakage problem can be roughly classified into two directions. One is to start from the circuit side to increase the part of the circuit to reduce the current gain of the Darlington amplifier circuit; the other is to start from the diode structure. I hope to completely eliminate the existence of the Darlington amplifier circuit. SUMMARY OF THE INVENTION The object of the present invention is to reduce the leakage of the supply-diode string during normal operation 0821 - A20685CIPTWF(N2); P 18930006TWA1 ; edward 5 1270193 . One embodiment of the present invention provides a diode string with low leakage current. The diode string includes a plurality of diode regions, a resistive region, and a bias resistor. The diode regions provide a plurality of diodes. Each of the diode regions includes a first polar region and a second polar region. The first pole region is of a first conductivity type and is disposed on a substrate as a first electrode of a corresponding diode. The second polar region is a second conductivity type opposite to the first conductivity type, and is disposed in the first polar region as a second electrode of the corresponding diode. The two pole systems are connected in series to provide a main anode of the diode string and a main cathode. The blocking region is the second conductivity type for separating the diode regions. The bias resistor is coupled between the blocking region and a first power line. During normal operation, the voltage of the first power line is not between the voltage of the main anode and the main cathode. Another embodiment of the present invention provides another diode string having a low leakage current. The diode string includes a plurality of bipolar junction transistors and a bias resistor. Each BJT contains a collector-emitter and a base. The emitter of a BJT is connected to the base of the next BJT. The collectors of each BJT are connected together. The base of the first BJT and the emitter of the last B JT serve as the two main electrodes of the diode string. The bias resistor is coupled between the collector of each BJT and a first power line. During normal operation, the voltage of the first power line is not between the voltages of the two main electrodes. The bias resistor can reduce the collector current in the parasitic Darlington amplifier circuit in the diode string during normal operation, thereby suppressing leakage of the diode string: current. In order to make the above objects, features and advantages of the present invention more comprehensible, the following detailed description of the preferred embodiments and the accompanying drawings are described in detail as follows: 0821 -A20685CIPTWF(N2) ;P 18930006TWA1 ;edward 6 1270193 [Embodiment] Fig. 1a is a cross-sectional view showing a diode string of the present invention. In the ia diagram, a diode string 1 is formed on a wafer of a p-type substrate 102 ("a general three-layer well, ...] ^^ process.
二極體串100具有數個二極體區104。每一個二極體區提 供一 一極體，具有一 P型井106以及一個N重掺雜區log，分 別作為一 一極體的陽極（anode)以及陰極（cathode)。N型井 (N_well)110以及深N型井（Deep N_well)112作為一個阻絕區， 除了把P型井106彼此電性分隔之外，也把p型井1〇6與p型 半導體基底102電性分隔。 為了形成良好的電性接觸（electric contact)，P型井j〇6之 表面具有P重摻雜區114, N型井110之表面具有N重換雜區 116,以及P型半導體基底1〇2之表面具有P重摻雜區u 。現 製程的技術不同，重摻雜區的表面可以選擇性的形成金屬石夕化 物（silicide)，以降低表面電阻值。這些重摻雜區可以運用表面上 形成的絕緣物，使他們彼此相互電性隔絕。於第la圖的& 中，該絕緣物是以淺溝隔離（Shallow trench isolation)技％ 成，也可以用局部氧化技術（local oxidation)所形成。 ’ 晶片上的内連線（inter connection)可以提供元件之 的連 的二 接。透過内連線，二極體順向串接在一起。也就是， 極 體的陰極連接到下一個二極體的陽極，而第一個 極體的陽極 以及最後一個二極體的陰極，便分別成為這個二極體串1〇〇 ° 主陽極以及主陰極。二極體串聯的數目可以視二極體串所带的 的起始電壓大小而定。譬如說，假使希望二極體串的起> 電壓 0821 -A20685CIPTWF(N2) ;P 18930006TWA1 ;edward 7 1270193 為4V，且一個二極體的開啟電壓為〇·7ν，則二極體串中串接的 二極體數目至少需要6個（〇·7*6=4·2>4)。 透過内連線，p型半導體基底（P-type substrate) 102耦接到 電源線GND。透過内連線，深N型井112以及N型井11〇連接 到一個偏壓電阻Rb，然後連接到電源線VCC。偏壓電阻Rb， 譬如說，可以為多晶矽電阻（p〇ly resistor)或是井電阻。The diode string 100 has a plurality of diode regions 104. Each of the diode regions provides a pole body having a P-well 106 and an N-doped region log as anodes and cathodes of a single pole body, respectively. The N-well 110 and the Deep N_well 112 serve as a resisting zone. In addition to electrically separating the P-wells 106 from each other, the p-wells 1 and 6 and the p-type semiconductor substrate 102 are also electrically connected. Separation. In order to form a good electrical contact, the surface of the P-type well J 〇 6 has a P heavily doped region 114, the surface of the N-type well 110 has an N-replacement region 116, and a P-type semiconductor substrate 1 〇 2 The surface has a P heavily doped region u. The current process technology is different, and the surface of the heavily doped region can selectively form a silicide to reduce the surface resistance. These heavily doped regions can utilize insulators formed on the surface to electrically isolate them from each other. In & in Figure la, the insulator is formed by shallow trench isolation or by local oxidation. The inter connection on the wafer provides a connection to the components. Through the interconnect, the diodes are connected in series. That is, the cathode of the polar body is connected to the anode of the next diode, and the anode of the first pole body and the cathode of the last diode body become the main anode and the main anode of the diode string respectively. cathode. The number of diodes connected in series can depend on the magnitude of the starting voltage carried by the diode string. For example, if the voltage of the desired diode string is >0821 -A20685CIPTWF(N2);P 18930006TWA1 ;edward 7 1270193 is 4V, and the opening voltage of one diode is 〇·7ν, the string in the diode string The number of connected diodes needs at least six (〇·7*6=4·2>4). A p-type substrate 102 is coupled to the power line GND through an interconnect. Through the interconnect, the deep N-well 112 and the N-well 11 are connected to a bias resistor Rb and then connected to the power supply line VCC. The bias resistor Rb, for example, may be a polysilicon resistor or a well resistor.
在正常操作時（未發生靜電放電，晶片正常連接電源時）， 電源線VCC的電壓不可低於主陽極的電壓。於第ia圖的實施 例中，電源線VCC與電源線GND的電壓可以分別是一晶片之 最1¾以及最低電壓。 第lb圖之左半部為第la圖中的二極體串100之等效電 路，右半部為一對應符號。 對應第lb圖之等效電路至第ia圖，每一個NPN雙極性接 面電晶體（BJT)的集極是深N型井112/N型井110、基極是P型 井106其中之一、以及射極是N重摻雜區ι〇8其中之一。一個 BJT的射極連接到下一個BJT的基極。第一個bJT的基極便是 二極體串100的主陽極’最後一個BJT的射極便是二極體串⑽ 的主陰極。所有的BJT之集極全部連接在一起，然後透 電阻Rb，耦接到電源線VCC。 第lb圖中之等效電路中的串接BJT顯示出_達靈頓放大電 路(Darlington Ampli_。偏壓電阻Rb可以抑制達靈頓放大電 路的集極電流’所以可以抑制二極體串於正常操作時的漏電 流。另一方面，由主陽極到主陰極的電流路徑並沒有串接住何 的電阻，所以二極體串於開啟時（主陽極與主陰極之間的電壓差 大於二極體串的起始電壓），可以有效的導通並釋放電流。因 此，非常適用於靜電放電防護。 0821 -A20685CIPTWF(N2) ;P 18930006TWA1 ;edward 8 1270193 • •為了電路上表達方便，以下以第lb圖中之新定義符號，表 示依據本發明實施之一二極體串。 依據本發明實施之二極體串可以作為一個電壓箝制電路 (voltage clamping circuit)，於一晶片中，提供輸出入埠 (input/output port)或是電源線間的靜電放電防護。 第2圖為依據本發明實施之一靜電放電防護電路。二極體 串可以單獨使用或是與其他的ESD防護元件共同使用，以達到 最佳的ESD防護效果。第2圖中的二極體串所在位置僅為舉 | 例，並不限制二極體串其他可能的運用位置。二極體串S1設於 電源線VH1與輸出入焊墊（I/O pad)之間，二極體串S2輸出入焊 墊(I/O pad)與電源線VL1之間，均作為輸出入埠之靜電放電防 護電路。每個二極體串S3-S6都連接於兩個電源線之間，作為 電源線間的靜電放電防護。於正常操作時，二極體串S1-S6都 是關閉狀態。假設，於正常操作時，電源線VH1的電壓高於電 源線VH0的電壓，電源線VL1的電壓低於電源線VL0的電壓。 那於正常操作時，二極體串S4為逆向偏壓，二極體串S1-S3、 S5-S6為順向偏壓。視電壓配置的條件，電源線VH1與電源線 B VCC可以是相同的電源線。 二極體串也可以運用於靜電放電電路中的觸發電路。第3a 以及3b圖為兩個具有觸發電路的靜電放電防護電路，均設於電 源線VCC與GND之間。在第3a以及3b圖中，二極體串S7與 觸發電阻R0相串聯於電源線VCC與GND之間，作為一個觸發 電路。二極體串S7與觸發電阻R0之間的連接點，連接到一個 主要靜電放電元件的觸發端。主要靜電放電元件可以是一個 BJT(如第3a圖中的BJT B0)，也可以是一個場效電晶體（Field effect transistor)(如第3b圖中的MOS M0)。當一對應於電源線 0821 -A20685C!PTWF(N2) ;P 18930006TWA1 ;edward 9 1270193 GND為正的eSd脈衝出現於電源線vcc時，譬如說，觸發端 的電壓暫時性的升高，可以觸發主要靜電放電元件，以釋放ESD 電流。 依據製程技術以及佈局規劃，依據本發明實施的二極體串 可以有不同的結構，而先前所提的第la圖僅僅是一個例子。第 4-6圖為實施本發明之另三個二極體串的剖面圖。 第4圖中的二極體串也可以用三層井（triple_well)CMOS製 程所製作。相較於第la圖中的單一的深N型井112,第4圖中 | 一極體串具有數個深N型井112以及N型井110，彼此透過内 連線以及N重摻雜區116連接在一起，所以大致具有相同的電 壓。 第5圖中的二極體串可以用具有深溝與淺溝隔絕技術的 BICMOS製程所製作。於第5圖中，n型沉接區（N+ sinker)120 與N型埋藏摻雜層（N+ buried layer)122構成一個阻絕區，把P 型井106彼此電性分隔。n型沉接區（N+ sinker)也可以用一般的 N型井替換。阻絕區的外圍具有一個深溝124以及一個淺溝 126，如第5圖所示。 B 第6圖為第5圖的變形。第5圖中二極體串具有數個N型 埋藏摻雜層（N+ buried layer)122，彼此透過内連線以及N重摻 雜區116連接在一起，所以大致具有相同的電壓。 雖然以上二極體串是以P型基底實施，本發明也可以實施 • 於N型基底。熟悉半導體之人士，於熟讀以上實施例後，可簡 •單的推導出於N型基底的實施例以及相對應的電壓配置，在此 * ^ 不再累述。 本發明雖以較佳實施例揭露如上，然其並非用以限定本發 明，任何熟習此項技藝者，在不脫離本發明之精神和範圍内’ 0821 -A20685CIPTWF(N2I ;P 18930006TWA1 ;edward 10 1270193 •當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之 申請專利範圍所界定者為準。During normal operation (when electrostatic discharge does not occur and the wafer is normally connected to the power supply), the voltage of the power supply line VCC must not be lower than the voltage of the main anode. In the embodiment of the ia diagram, the voltages of the power supply line VCC and the power supply line GND may be the highest and the lowest voltage of a wafer, respectively. The left half of the lb diagram is the equivalent circuit of the diode string 100 in the first diagram, and the right half is a corresponding symbol. Corresponding to the equivalent circuit of the lb diagram to the ia diagram, the collector of each NPN bipolar junction transistor (BJT) is one of the deep N-type well 112/N-type well 110 and the base is the P-type well 106. And the emitter is one of the N heavily doped regions ι〇8. The emitter of one BJT is connected to the base of the next BJT. The base of the first bJT is the main anode of the diode string 100. The emitter of the last BJT is the main cathode of the diode string (10). All the collectors of the BJT are all connected together, and then the resistor Rb is coupled to the power line VCC. The series connection BJT in the equivalent circuit in Figure lb shows the Darlington Amplifier circuit (Darlington Ampli_. The bias resistor Rb can suppress the collector current of the Darlington amplifier circuit) so that the diode string can be suppressed from normal. Leakage current during operation. On the other hand, the current path from the main anode to the main cathode does not have any resistance in series, so when the diode string is turned on (the voltage difference between the main anode and the main cathode is greater than the pole The starting voltage of the body string can effectively turn on and release the current. Therefore, it is very suitable for electrostatic discharge protection. 0821 -A20685CIPTWF(N2) ;P 18930006TWA1 ;edward 8 1270193 • • For the convenience of circuit expression, the following is the first lb A new definition symbol in the figure indicates a diode string according to the implementation of the present invention. A diode string according to the present invention can be used as a voltage clamping circuit to provide an input/output port in a wafer ( Input/output port) or electrostatic discharge protection between power lines. Figure 2 is an electrostatic discharge protection circuit according to an embodiment of the present invention. The diode strings can be used alone or with Other ESD protection components are used together to achieve the best ESD protection. The position of the diode string in Figure 2 is only for the example, and does not limit the other possible positions of the diode string. The string S1 is disposed between the power supply line VH1 and the input/output pad (I/O pad), and the diode string S2 is input and output between the pad (I/O pad) and the power line VL1, and both serve as static electricity for input and output. Discharge protection circuit. Each diode string S3-S6 is connected between two power lines as electrostatic discharge protection between power lines. In normal operation, the diode strings S1-S6 are all off. During normal operation, the voltage of the power line VH1 is higher than the voltage of the power line VH0, and the voltage of the power line VL1 is lower than the voltage of the power line VL0. In normal operation, the diode string S4 is reverse biased, two poles The body strings S1-S3 and S5-S6 are forward biased. Depending on the voltage configuration conditions, the power line VH1 and the power line B VCC can be the same power line. The diode string can also be used for triggering in an electrostatic discharge circuit. Circuits. Figures 3a and 3b show two ESD protection circuits with trigger circuits. It is disposed between the power supply line VCC and GND. In the 3a and 3b diagrams, the diode string S7 and the trigger resistor R0 are connected in series between the power supply line VCC and GND as a trigger circuit. The diode string S7 and the trigger The connection point between the resistors R0 is connected to the trigger end of a main electrostatic discharge element. The main electrostatic discharge element can be a BJT (such as BJT B0 in Fig. 3a) or a field effect transistor (Field effect transistor). ) (such as MOS M0 in Figure 3b). When a corresponding eSd pulse corresponding to the power line 0821 - A20685C! PTWF(N2) ; P 18930006TWA1 ; edward 9 1270193 GND appears on the power line vcc, for example, the voltage at the trigger terminal temporarily rises, which can trigger the main static electricity. Discharge element to release ESD current. Depending on the process technology and layout planning, the diode strings implemented in accordance with the present invention may have different configurations, and the aforementioned first diagram is merely an example. Figures 4-6 are cross-sectional views of another three diode strings embodying the present invention. The diode string in Figure 4 can also be fabricated in a triple-well CMOS process. Compared with the single deep N-type well 112 in FIG. 1a, the first pole series has a plurality of deep N-type wells 112 and N-type wells 110, which are interconnected with each other and N-doped regions. 116 are connected together, so they have roughly the same voltage. The diode string in Figure 5 can be fabricated using a BICMOS process with deep trench and shallow trench isolation techniques. In FIG. 5, the n-type sink region (N+ sinker) 120 and the N-type buried layer 122 form a resistive region that electrically separates the P-wells 106 from each other. The n-type sinking zone (N+ sinker) can also be replaced with a normal N-type well. The periphery of the barrier zone has a deep trench 124 and a shallow trench 126 as shown in FIG. B Fig. 6 is a modification of Fig. 5. In the fifth diagram, the diode string has a plurality of N-type buried layers 122 which are connected to each other through the interconnect and the N-doped region 116, so that they have substantially the same voltage. Although the above diode string is implemented as a P-type substrate, the present invention can also be implemented on an N-type substrate. Those skilled in the art, after reading the above embodiments, can simply derive the embodiment of the N-type substrate and the corresponding voltage configuration, which is not repeated here. The present invention has been disclosed in its preferred embodiments as described above, but is not intended to limit the invention, and any one skilled in the art, without departing from the spirit and scope of the invention, is in the form of '0821 - A20685 CIPTWF (N2I; P 18930006TWA1; edward 10 1270193) • The scope of protection of the present invention is defined by the scope of the appended claims.
0821-A20685CIPTWF(N2);P18930006TWAl;edward 11 1270193 •【圖式簡單說明】 第la圖為實施本發明之一二極體串的剖面圖。 第lb圖為第la圖中的二極體串100之等效電路以及一對 應定義符號。 第2圖為依據本發明實施之一靜電放電防護電路。 第3a以及3b圖為依據本發明之兩個具有觸發電路的靜電 放電防護電路。 第4-6圖為實施本發明之三個二極體串的剖面圖。 > 【主要元件符號說明】 100〜二極體串 102〜P型半導體基底 104〜二極體區 106〜P型井 108〜N重摻雜區 110〜N型井 112〜深N型井 114〜P重摻雜區 ’ 116〜N重摻雜區 118〜P重摻雜區 120〜N型沉接區 122〜N型埋藏摻雜層 ^ 124〜深溝 • 126〜淺溝 # : Rb〜偏壓電阻 S1-S7〜二極體串 R0、RB〜電阻 0821 -A20685CIPTWF(N2) ;P 18930006TWA1 ;edward 120821-A20685CIPTWF(N2); P18930006TWAl; edward 11 1270193 • [Simplified Schematic] FIG. 1a is a cross-sectional view of a diode string embodying the present invention. Figure lb is an equivalent circuit of the diode string 100 in the first diagram and a pair of symbols to be defined. Figure 2 is an electrostatic discharge protection circuit in accordance with an embodiment of the present invention. Figures 3a and 3b show two electrostatic discharge protection circuits with trigger circuits in accordance with the present invention. 4-6 are cross-sectional views of three diode strings embodying the present invention. > [Major component symbol description] 100~diode string 102~P type semiconductor substrate 104~diode region 106~P type well 108~N heavily doped region 110~N type well 112~deep N type well 114 ~P heavily doped region '116~N heavily doped region 118~P heavily doped region 120~N type sinking region 122~N type buried doping layer ^124~deep trench•126~ shallow trench# : Rb~ partial Piezoresistors S1-S7~diode string R0, RB~resistor 0821 -A20685CIPTWF(N2) ;P 18930006TWA1 ;edward 12