TWI267970B

TWI267970B - Interconnect structure and fabricating method thereof

Info

Publication number: TWI267970B
Application number: TW94141091A
Authority: TW
Inventors: Yu-Hao Hsu; Ming-Tsung Chen
Original assignee: United Microelectronics Corp
Priority date: 2005-11-23
Filing date: 2005-11-23
Publication date: 2006-12-01
Also published as: TW200721412A

Abstract

An interconnect structure is described, disposed on a substrate with a conductive part thereon and including a dielectric layer, a composite plug and a conductive line. The dielectric layer is located on the substrate covering the conductive part. The composite plug is located in the dielectric layer electrically connecting with the conductive part. The composite plug includes a first plug and a second plug from bottom to top, wherein the material or the critical dimension of the second plug is different from that of the first plug. The conductive line is disposed on the dielectric layer electrically connecting with the composite plug.

Description

126797A8twf.d〇c/g 九、發明說明：【發明所屬之技術領域】本發明是有關於一種積體電路結構及其製造方法，且特別是有關於一種内連線結構及其製造方法。【先前技術】126797A8twf.d〇c/g IX. Description of the Invention: [Technical Field] The present invention relates to an integrated circuit structure and a method of fabricating the same, and more particularly to an interconnect structure and a method of fabricating the same. [Prior Art]

隨著積體電路產業的蓬勃發展，為了能夠在一塊晶片上製作更多的元件，亦即提高元件的積集度，元件的線寬也必須愈盈縮減。如此一來，會使得半導體後段製程之金屬内連線的製程裕度(Process Window)大幅縮減。尤其是在形成接觸窗/介層窗開口的時候，由於開口的深寬比(Aspat Ratio)相當高，往往會使得内連線的製程產生許多問題。請麥考圖1之習知M0S電晶體接觸窗的剖面示意圖。此接觸窗150位於兩MOS電晶體11〇與12〇之間二且電性連接二者所共用的源/汲極區13G，其中體110與120被介電層14〇所覆蓋，而接觸窗插塞位於介電層140中。當製程的線寬愈小時，接觸窗^口⑷With the booming development of the integrated circuit industry, in order to be able to make more components on a single wafer, that is, to increase the integration of components, the line width of the components must also be reduced. As a result, the process window of the metal interconnects in the semiconductor back-end process is greatly reduced. Especially when the contact window/via window opening is formed, since the aspect ratio of the opening is relatively high, the process of the interconnect is often caused to cause many problems. Please refer to the schematic diagram of the cross section of the M0S transistor contact window of McCaw Chart 1. The contact window 150 is located between the two MOS transistors 11 〇 and 12 二 and is electrically connected to the source/drain region 13G, wherein the bodies 110 and 120 are covered by the dielectric layer 14 ,, and the contact window The plug is located in the dielectric layer 140. When the line width of the process is smaller, the contact window (4)

140, ^ 145的深寬比(Aspect Ratio)會侖芮來，在㈣接觸窗開口 145時，往往會發生接門^ 一 Γ=層140餘刻不完全的現象，而可能會= 二pen)的問題。此外’高深寬比還會導二，杨g)的過程中產生孔洞(偏）。元件的可靠度下降，而降低產品㈣率。W都會造成 126797fl58twf.doc/g 【發明内容】有鑑於此，本發明的目的就是在提供一種内 L:可效解決接觸窗/介層窗開口之高深寬比的問題，使付7G件的可靠度及產品良率得以提升。、本，明的另一目的是提供一種内連線結構的製造方法，其是用來製造上述本發明的内連線結構。140, ^ 145 aspect ratio (Aspect Ratio) will come, in the (four) contact window opening 145, there will often be a door ^ Γ = layer 140 incomplete phenomenon, and may = two pen) The problem. In addition, the 'high aspect ratio will also lead to the hole (bias) in the process of the second, Yang g). The reliability of the component is reduced, and the product (four) rate is lowered. W will cause 126797fl58twf.doc/g [Invention] In view of this, the object of the present invention is to provide an inner L: effective solution to the problem of the high aspect ratio of the contact window/via window opening, which makes the 7G piece reliable. Degree and product yield have been improved. Another object of the present invention is to provide a method of fabricating an interconnect structure for fabricating the interconnect structure of the present invention described above.

本發明的内連線結構位於基底上，此基底上包括一導電部。此㈣線結構至少包括介電層、複合插絲導線。其中’介電層配置於基底上，且覆蓋住導電部。複合插寒配f於介電層中以電性連接導電部，且由下而上包括第二插塞與第二插塞，此第二插塞與第—插塞的材質不同或關鍵尺寸不同。導線配置於介電層上，且電性連接複合插塞。依照本發明的實施例所述之内連線結構，上述第一插塞的深寬比例如小於等於3，其材f例如是銅u、翻、金、翻或其合金。上述第二插塞的材質例如是銅、鎢、 I呂、翻、金、翻或其合金。The interconnect structure of the present invention is located on a substrate including a conductive portion. The (four) wire structure includes at least a dielectric layer and a composite wire. Wherein the dielectric layer is disposed on the substrate and covers the conductive portion. The composite plugging element is electrically connected to the conductive portion in the dielectric layer, and includes a second plug and a second plug from bottom to top. The second plug and the first plug are different in material or different in key dimensions. . The wire is disposed on the dielectric layer and electrically connected to the composite plug. According to the interconnect structure of the embodiment of the present invention, the first plug has an aspect ratio of, for example, 3 or less, and the material f is, for example, copper u, flip, gold, turn or alloy thereof. The material of the second plug is, for example, copper, tungsten, Ilu, turn, gold, turn or alloy thereof.

依照本發明的實施例所述之内連線結構，上述介電層例如是由基底起包括下介電層與上介電層，且第一插塞ς 於下介電層中，第二插塞位於上介電層中，其中上介^層的材質例如是低介電材料。此時上述内連線結構可更包A 一層保護層，配置於下介電層與上介電層之間。此保護層的材質例如是氮化矽、碳化矽、氮氧化矽或碳氮化矽。依照本發明的實施例所述之内連線結構，上塞與介電層、導電部之間更可包括—阻障層，其材質二如 126797e58twf.d〇c/g f^上$成用來定義雙重鑲嵌開叫—硬罩幕層。本發卿插塞分成_階段形成，而各階段中開二見比白大巾晴低’故_與填溝開口的製程裕度得以k局，而可降低斷路發生的機率。因此，本發明可以增加元件可*度，達成提昇產品良率的效果。為讓本發明之±述和其他目的、特徵和優點能更明顯易懂’下文特舉實施例，並配合所附圖式詳細說明如下。【實施方式】圖2疋本發明實施例之内連線結構的剖面示意圖。此内連線結構位於具有隔離結構2〇1與多個半導體元件21〇的基底200上，其中每一個半導體元件21〇例如是包括閘介電層211、閘極213與源/汲極區215的MOS電晶體。閘介電層211與閘極213依序配置於基底200上，其中閘介電層211的材質例如是氧化矽，閘極213的材質例如是摻雜多晶矽或金屬等導體材料。源/汲極區215配置於閘極 213兩側下方之基底2〇〇中，且摻雜有p或N型摻質。閘極213上例如更設有金屬矽化物層217，其材質例如是矽化鈦、矽化鈷、矽化鎳或矽化鉑等。閘極213側壁例如更設有間隙壁219，其材質例如是氧化矽等絕緣材料。半導體元件210上更可包括餘刻中止層220,例如是氮化石夕層。上述結構上設置有一層介電層221，其覆蓋住半導體元件210，且其中設置有複合插塞230與半導體元件210 的導電部電性連接。此處所謂導電部包括源/汲極215與閘極213，而複合插塞230例如是同時連接一源/彡及極區215 12679^〇8twf.doc/g 與一閘極213的共享接觸窗插塞(Share Contact Plug)，如圖 2所示者，或是僅連接源/汲極區215或閘極213的接觸窗。介電層221可以分為下介電層222與上介電層225 ; 同時，複合插塞230例如是分為上下兩部分。其中，下層之弟一插塞231位於下介電層222中，上層之第二插塞235 位於上介電層225中，且第一插塞231與第二插塞235的材質不同或關鍵尺寸不同。在某些實施例中，第二插塞235 的關鍵尺寸小於第一插塞231的關鍵尺寸。另外，第一插塞231、第二插塞235的材質例如是鋁、銅、鶴、鉑、金、翻或其合金。其中，合金除了可以是前述任兩種或更多種金屬的合金(如銘銅合金)之外，也可以疋金屬與非金屬的合金’如推雜梦的銘合金、銅合金或銅銘合金等。第一插塞231與第二插塞235可以具有相同的材質，也可以具有不同的材質。另外，第一插塞231與下介電層222、源/汲極區215、間隙壁219之間例如更設置有阻障層237,且第二插塞235與上介電層225、第一插塞 231之間例如更設置有另一阻障層239。阻障層237、239 的材質例如是鈦、氮化鈦、组、氮化组、嫣、氮化鶴或鈦鎢合金等。下介電層222的材質例如是氧化矽、硼磷矽玻璃等絕緣材料。上介電層225的材質例如是氧化;ε夕或介電常數小於4的低介電材料，如HSQ、FSG、Flare、SILK、碳摻雜氧化石夕（Carbon Doped Oxide，CD0)、氫化非晶石炭 (Hydrogenated Amorphous Carbon)、氟化非晶石炭 I26797^Wf.d〇c/g (Fluorinated Amorphous Carbon) ^ Parylene > PAE (P〇ly(arylene ethers))、Cyclotene、Si〇2 氣凝膠(Aerogel)、According to the interconnect structure of the embodiment of the present invention, the dielectric layer includes, for example, a lower dielectric layer and an upper dielectric layer from the substrate, and the first plug is in the lower dielectric layer, and the second plug The plug is located in the upper dielectric layer, wherein the material of the upper layer is, for example, a low dielectric material. At this time, the above interconnect structure may further comprise a protective layer of A, disposed between the lower dielectric layer and the upper dielectric layer. The material of the protective layer is, for example, tantalum nitride, tantalum carbide, niobium oxynitride or niobium carbonitride. According to the interconnect structure of the embodiment of the present invention, the upper plug and the dielectric layer and the conductive portion may further include a barrier layer, and the material thereof is used as 126797e58twf.d〇c/gf^ Define a dual inlay opening - hard mask layer. The hairpin of this hair is divided into _ stages, and the opening of each stage is lower than that of the white towel. Therefore, the process margin of the opening and filling groove is obtained by k, which can reduce the probability of occurrence of the circuit. Therefore, the present invention can increase the component grading and achieve an effect of improving the yield of the product. The present invention and other objects, features and advantages will be more apparent from the following description. Embodiments Fig. 2 is a schematic cross-sectional view showing an interconnect structure of an embodiment of the present invention. The interconnect structure is located on the substrate 200 having the isolation structure 201 and the plurality of semiconductor elements 21, wherein each of the semiconductor elements 21 includes, for example, a gate dielectric layer 211, a gate 213, and a source/drain region 215. MOS transistor. The gate dielectric layer 211 and the gate electrode 213 are sequentially disposed on the substrate 200. The material of the gate dielectric layer 211 is, for example, tantalum oxide. The material of the gate electrode 213 is, for example, a conductive material such as doped polysilicon or metal. The source/drain regions 215 are disposed in the substrate 2 below the both sides of the gate 213 and doped with p or N type dopants. Further, for example, a metal telluride layer 217 is provided on the gate electrode 213, and the material thereof is, for example, titanium telluride, cobalt telluride, nickel telluride or platinum telluride. The side wall of the gate 213 is further provided with a spacer 219, for example, an insulating material such as ruthenium oxide. The semiconductor component 210 may further include a residual stop layer 220, such as a nitride layer. The above structure is provided with a dielectric layer 221 covering the semiconductor device 210, and a composite plug 230 is disposed therein to be electrically connected to the conductive portion of the semiconductor device 210. The conductive portion here includes a source/drain 215 and a gate 213, and the composite plug 230 is, for example, a shared contact window connecting a source/deuterium and a polar region 215 12679^〇8twf.doc/g and a gate 213. A Share Contact Plug, as shown in FIG. 2, or a contact window connecting only the source/drain region 215 or the gate 213. The dielectric layer 221 can be divided into a lower dielectric layer 222 and an upper dielectric layer 225; at the same time, the composite plug 230 is divided into upper and lower portions, for example. The second plug 235 is located in the lower dielectric layer 222, and the second plug 235 of the upper layer is located in the upper dielectric layer 225, and the materials of the first plug 231 and the second plug 235 are different or critical dimensions. different. In some embodiments, the critical dimension of the second plug 235 is less than the critical dimension of the first plug 231. In addition, the material of the first plug 231 and the second plug 235 is, for example, aluminum, copper, crane, platinum, gold, tumbling or alloy thereof. Wherein, the alloy may be an alloy of any two or more of the foregoing metals (such as a copper alloy), and may also be an alloy of a base metal and a non-metal such as an alloy of a dream, a copper alloy or a copper alloy. Wait. The first plug 231 and the second plug 235 may have the same material or different materials. In addition, a barrier layer 237 is further disposed between the first plug 231 and the lower dielectric layer 222, the source/drain region 215, and the spacer 219, and the second plug 235 and the upper dielectric layer 225 are first. For example, another barrier layer 239 is further disposed between the plugs 231. The material of the barrier layers 237 and 239 is, for example, titanium, titanium nitride, a group, a nitrided group, a tantalum, a nitrided iron or a titanium tungsten alloy. The material of the lower dielectric layer 222 is, for example, an insulating material such as yttrium oxide or borophosphon glass. The material of the upper dielectric layer 225 is, for example, oxidation; a low dielectric material having a dielectric constant of less than 4, such as HSQ, FSG, Flare, SILK, Carbon Doped Oxide (CD0), hydrogenation Hydrogenated Amorphous Carbon, fluorinated amorphous carboniferous I26797^Wf.d〇c/g (Fluorinated Amorphous Carbon) ^ Parylene > PAE (P〇ly (arylene ethers)), Cyclotene, Si〇2 aerogel (Aerogel),

Si〇2乾凝膠(Xerogel)或是前述介電材料的組合等，而下介電層222的材質也可以選自部分的前述低介電材料。上下介電層222與225間例如更設有保護層223，其材質可為氮化矽、碳化矽(sic)、氮氧化矽(Si0N)或碳氮化矽(SiCN)。上介電層225與複合插塞230上更設有介電層24〇，其中設有與複合插塞230電性連接的導線25〇。介電層24〇的材質例如是氧化矽、硼磷矽玻璃或前述低介電材料，而導線250的材質例如是銅、鎢、鋁、鉬、金、鉑或其合金。上述實施例中的複合插塞雖係以連接M〇s電晶體之源/汲極區、閘極的共享接觸窗插塞為例作說明，然而，本發明之複合插塞並不限於是接觸窗插塞，也可以是電性連接至導線的介層窗插塞。由於本發明提出之内連線結構中的複合插塞23〇分為上下兩個部分形成，故可以降低第一插塞231與第二插^ 235各自所對應之開口的深寬比。如此即可提高製程裕& 以利於插塞形成，而能防止斷路發生，增加元件的可靠度= 下面說明本發明實施例之内連線結構的製造方法，其製造流程圖如圖3A至圖3E所繪示。此内連線的製造方法例如是應用於靜態隨機存取記憶體(SRAM)的製程中。/ 請參照圖3A，首先提供基底綱，其上已形成有結構301與多個半導體元件310。隔離結構301例如是汽溝渠隔離(STI)結構’其軸紐縣此領域者所周知。么 126797058twfd〇c/g 半導體元件310例如是MOS電晶體，包括基底300 上的閘介電層311、閘介電層311上的閘極313和位於閘極313兩側之基底300中的源/汲極區315。閘介電層311 的材負例如是氧化石夕，閘極313的材質例如是金屬或摻雜多晶石夕等導體材料，且源/汲極區315摻雜有p型或n型摻質。另外，閘極313上更可設置金屬矽化物層3Π，以降低閘極313的阻值，此金屬矽化物層317的材質例如是 • 梦化欽、秒化錄或碎化銘。閘極313的側壁例如更設置有 ® 間隙壁319，其材質例如是氧化石夕等絕緣材料。請繼續參照圖3A，接著於基底300上形成蝕刻中止層 320覆盍住元件310，其材質例如是氮化石夕，且形成方法例如是化學氣相沈積法。然後，在蝕刻中止層32〇上形成一 f下介電層321覆蓋住元件310，此下介電層321的頂面兩度僅約略高於元件310，且材質例如是氧化矽、硼磷矽玻％專。下介電層321的形成方法例如是先進行化學氣相沈積法沉積介電材料，再以化學機械研磨法將其平坦化。 • 之後，於下介電層321上形成硬罩幕層323，其材質例如是氮化石夕、礙化石夕、氮氧化石夕或碳氮化石夕，且形成方 -法例如是化學氣相沈積法。接著，於硬罩幕層323上形成 • 目案化光阻層325，其形成方法例如u以旋塗方式於硬罩幕層323上形成-層光阻材料(未緣示），並於曝光後進行顯影。此光阻材料例如是一種有機光活化物。請參照圖3A、3B’繼而以圖案化光阻層％進行蝕刻，以移除暴露出之硬罩幕層323與下介電層321， 126797fl58twf.doc/g 而形成開口 327。移除罩幕層323與下介電層321的方法例如是非等向性之反應性離子蝕刻法(Reacdve I〇n Etch); 而依照材質科同’㈣各層所使用的錢產生氣體組成也可有所不同。由於蝕刻中止層32〇與下介電層321的材質不同，因此乾式蝕刻會停在蝕刻中止層32〇上，而可避免閘極313與源/汲極區315被非等向性蝕刻破壞。然後’除去殘留的光阻層325，再移除暴露出之敍刻中止層320 ’其方法例如是濕|虫刻法。開口 m列如是暴露出-閘極313上方之金屬魏物層317及相鄰的一源/ 汲極區315。^然’並不是每個半導體元件31〇上都會形成開口 327,且某些開口 327也可能是只暴露出源/汲極區 315。開口 f27的位置分佈與形狀是依照電路的設計而定。請繼續參照圖犯，接下來於基底細層别與導體層333填滿開口 327,再 :二早導體層333、阻障層331與硬單幕層323二二第-插基335，其方法例如是化學機械研磨法。阻障層別氮化鈦、组、氮化组、鶴、氣化鶴0或鈦 :體=3的材質例如是銅、鎢、銘、銦、金、麵或豆人二學體層333的形成“ 如是小於等於3,而可提高製中例 12 I26797ft8twf.d〇c/i 開口 327的深寬比可小於等於1.5。接著，請參照圖3C，於下介電層321上依序形成保護層337、介電層339、蝕刻中止層341、介電層343、頂蓋層345與硬罩幕層347。保護層337的材質例如是氮化矽、碳化石夕、氮氧化；5夕或碳氮化;5夕，其形成方法例如是化學氣相沈積法。介電層339的材質例如是氧化矽或介電常數小於4的低介電材料，如HSQ、FSG、Flare、SILK、碳推雜氧化矽（Carbon Doped Oxide，CDO)、氫化非晶碳 (Hydrogenated Amorphous Carbon)、氟化鉀(KF)、就化非晶碳（Fluorinated Amorphous Carbon)、Parylene、PAE (P〇ly(arylene ethers))、Cyclotene、Si02 氣凝膠(Aerogel)、The Si〇2 xerogel (Xerogel) is a combination of the foregoing dielectric materials, and the material of the lower dielectric layer 222 may also be selected from a part of the aforementioned low dielectric material. For example, a protective layer 223 is further disposed between the upper and lower dielectric layers 222 and 225, and the material thereof may be tantalum nitride, sic, yttrium oxynitride (SiC) or tantalum carbonitride (SiCN). The upper dielectric layer 225 and the composite plug 230 are further provided with a dielectric layer 24, wherein a wire 25 is electrically connected to the composite plug 230. The material of the dielectric layer 24 is, for example, yttrium oxide, borophosphon glass or the aforementioned low dielectric material, and the material of the wire 250 is, for example, copper, tungsten, aluminum, molybdenum, gold, platinum or an alloy thereof. The composite plug in the above embodiment is described by taking the source/drain region of the M〇s transistor and the shared contact window plug of the gate as an example. However, the composite plug of the present invention is not limited to being in contact. The window plug may also be a via plug electrically connected to the wire. Since the composite plug 23 of the interconnect structure proposed by the present invention is formed by dividing the upper and lower portions, the aspect ratio of the opening corresponding to each of the first plug 231 and the second plug 235 can be reduced. In this way, the process margin can be improved to facilitate the formation of the plug, and the occurrence of the open circuit can be prevented, and the reliability of the component can be increased. The following describes the manufacturing method of the interconnect structure of the embodiment of the present invention. The manufacturing flow chart is shown in FIG. 3A to FIG. 3E is shown. The manufacturing method of the interconnect is, for example, applied to a process of a static random access memory (SRAM). Referring to FIG. 3A, a substrate is first provided, on which a structure 301 and a plurality of semiconductor elements 310 have been formed. The isolation structure 301 is, for example, a trench isolation (STI) structure, which is well known to those skilled in the art. 126797058twfd〇c/g The semiconductor device 310 is, for example, a MOS transistor, including a gate dielectric layer 311 on the substrate 300, a gate 313 on the gate dielectric layer 311, and a source in the substrate 300 on both sides of the gate 313. Bungee area 315. The material of the gate dielectric layer 311 is, for example, oxidized oxide, and the material of the gate 313 is, for example, a metal or doped polysilicon, and the source/drain region 315 is doped with p-type or n-type dopant. . In addition, a metal telluride layer 3 is further disposed on the gate 313 to reduce the resistance of the gate 313. The material of the metal telluride layer 317 is, for example, • Dreaming, Second Recording or Fragmentation. The side wall of the gate 313 is further provided with, for example, a spacer 319 made of an insulating material such as oxidized oxide. Referring to FIG. 3A, an etch stop layer 320 is formed on the substrate 300 to cover the device 310, such as a nitride nitride, and the formation method is, for example, chemical vapor deposition. Then, a lower dielectric layer 321 is formed on the etch stop layer 32 to cover the device 310. The top surface of the lower dielectric layer 321 is only slightly higher than the element 310, and the material is, for example, yttrium oxide or bismuth phosphide. Glass% special. The lower dielectric layer 321 is formed by, for example, depositing a dielectric material by chemical vapor deposition followed by planarization by chemical mechanical polishing. • Thereafter, a hard mask layer 323 is formed on the lower dielectric layer 321 , and the material thereof is, for example, nitrite, phlegm, oxynitride or carbonitride, and forms a square-method such as chemical vapor deposition. law. Next, a filming photoresist layer 325 is formed on the hard mask layer 323, and a forming method thereof, for example, u forms a layer of photoresist material (not shown) on the hard mask layer 323 by spin coating, and exposes it. After development. This photoresist material is, for example, an organic photoactivator. Referring to Figures 3A, 3B', etching is performed with the patterned photoresist layer % to remove the exposed hard mask layer 323 and the lower dielectric layer 321, 126797fl58twf.doc/g to form an opening 327. The method of removing the mask layer 323 and the lower dielectric layer 321 is, for example, an anisotropic reactive ion etching method (Reacdve I〇n Etch); and the gas composition according to the material used in the material layer of the (4) layer may also be used. It is different. Since the etching stop layer 32 is different from the material of the lower dielectric layer 321, the dry etching stops on the etching stop layer 32, and the gate 313 and the source/drain region 315 are prevented from being destroyed by anisotropic etching. Then, the residual photoresist layer 325 is removed, and the exposed stop layer 320' is removed, for example, by wet-wetting. The openings m are as exposed to a metal wafer layer 317 above the gate 313 and an adjacent source/drain region 315. ^Almost no opening 327 is formed on each of the semiconductor elements 31, and some of the openings 327 may also expose only the source/drain regions 315. The position distribution and shape of the opening f27 are determined according to the design of the circuit. Please continue to refer to the figure, and then fill the opening 327 in the base layer and the conductor layer 333, and then: the second early conductor layer 333, the barrier layer 331 and the hard single curtain layer 323 22nd-interposer 335, the method For example, chemical mechanical polishing. Barrier layer Titanium nitride, group, nitride group, crane, gasification crane 0 or titanium: body = 3 material such as copper, tungsten, indium, indium, gold, surface or bean formation "If it is less than or equal to 3, the aspect ratio of the example 12 I26797ft8twf.d〇c/i opening 327 can be increased to 1.5 or less. Next, referring to FIG. 3C, a protective layer is sequentially formed on the lower dielectric layer 321 337, dielectric layer 339, etch stop layer 341, dielectric layer 343, cap layer 345 and hard mask layer 347. The material of the protective layer 337 is, for example, tantalum nitride, carbon carbide, nitrogen oxidation; Nitriding; the formation method is, for example, chemical vapor deposition. The material of the dielectric layer 339 is, for example, yttrium oxide or a low dielectric material having a dielectric constant of less than 4, such as HSQ, FSG, Flare, SILK, carbon push. Carbon Doped Oxide (CDO), Hydrogenated Amorphous Carbon, Potassium Fluoride (KF), Fluorinated Amorphous Carbon, Parylene, PAE (P〇ly (arylene ethers) ), Cyclotene, Si02 aerogel (Aerogel),

Si〇2乾凝膠(Xerogel)或是前述介電材料的組合等，依照 η電層339預定的介電常數而定。介電層339的形成方法例如疋化學氣相沈積法或旋塗法(Spin-coating)。 Ί虫刻中止層341的材質例如是氮化石夕、碳化梦、氮氧化矽或碳氮化矽，其形成方法例如是化學氣相沈積法。介電層343的材質例如是氧化矽或上述介電常數小於4的低介電材料，其形成方法例如是化學氣相沈積法或旋塗法。頂盍層345的材質例如是石夕酸四乙酯(teos)-氧化石夕，且其形成方法例如是化學氣相沈積法。硬罩幕層347的材質例如疋氮化鈦，其形成方法例如是化學氣相沈積法。值知一提的是’上述保護層337、钱刻中止層341、頂盍層345與硬罩幕層347的設置是為了提高對於後續微影、蝕刻製程的控制，使光阻圖案得以準確地移轉，避免 13 I26797ft8twf.d〇c/g 侵蝕其他膜層。惟這些膜層的設置與否或是其他如抗反射層、潤濕層（Wetting Layer)等膜層的增設與否，仍可選擇性地視製程的需要而定。請參照圖3D，然後於保護層337、介電終中止層341、介電層343、頂蓋層祕與石】罩幕層^ 巾形成-雙重鑲嵌開口 350’其包括下暴露出第一插塞335 的介層窗開口 357與上通過其上方之導線溝渠355。雙重 ·· 镶嵌開ϋ 350的形成方法可以是先钕刻出介層窗^ 口參 357，再餘刻出導線溝渠355 ;也可以是先形成侧出導線溝渠355，再蝕刻出介層窗開口 357。蝕刻這些膜層的方法例如是非等向性之反應性離子蝕刻(Reactive l0n ^ch)，其所使用的電聚產生氣體組成可依照各膜層材質作調整。因雙重鑲嵌開口的形成方法為此領域者所周知，故不再費述。接著，請參照圖3E，於硬罩幕層347上形成阻障層 359以及導體層360，再移除介電層343上之導體層36〇、阻障層359、硬罩幕層347及頂蓋層345。其中，阻障層鲁 359的材質例如是鈦、氮化鈦、钽、氮化鈕、鎢、氮化鎢或鈦鎢合金，其形成方法例如是化學氣相沈積法或物理氣相沈積法。導體層36〇的材質例如是銅、鎢、鋁、鉬、金、 • 鉑或其合金，其形成方法例如是化學氣相沈積法或物理氣相沈積法。移除介電層343上之導體層360至頂蓋層345 的方法例如是化學機械研磨法。此時導線溝渠355中的導體層360疋為内連線之導線，其經由介層窗開口 Μ?中的導體層360 (即第二插塞)與第一插塞335電性連接。 12679^08twf.doc/g 綜上所述，由於本發明將插塞分成兩個階段形成，而各階段中開σ的深寬比皆大幅降低，故可防止介電層麵刻不完全的情形，同時可避免溝填(GapFill)的過程中產生孔洞(Void)缺陷，而得以預防斷路等問題，達到提高元可靠度與產品良率的功效。勺雖然本發明已以實施例揭露如上，然其並非用本發明’任何熟習此㈣者，林_本發日狀精，圍内，當可作些許之更動與潤飾，因此本發明 ^車巳當視後附之申請專利範圍所界定者為準。 ’、邊乾圍【圖式簡單說明】圖1是習知MOS電晶體接觸窗的剖面示意圖2是本發明實施例之内連線結構的剖面了音。圖3A〜3E是本發明實施例之内連線製 ^ 【主要元件符號說明】勺不思圖。 100、200、300 :基底 110、120 : MOS 電晶體 130、215、315 :源/汲極區 140、22卜 240、339、343 :介電層 145 :接觸窗開口 9 150 :接觸窗插塞 201、301 ··隔離結構 210、 310 :半導體元件 211、 311 :閘介電層 213、313 :閘極 15 12679^08twf.doc/g 217、317 :金屬矽化物層 219、 319 :間隙壁 220、 320、341 :蝕刻終止層 222、 321 :下介電層 223、 337 :保護層 225 :上介電層 230 :複合插塞 231 :第一插塞 235 :第二插塞 237、239、331、359 ··阻障層 250 :導線 323、347 :硬罩幕層 325 :圖案化光阻層 327 :開口 333、360 :導體層 335 :第一插塞 345 :頂蓋層 350 :雙重鑲嵌開口 355 :導線溝渠 357 :介層窗開口The Si〇2 xerogel (Xerogel) or a combination of the foregoing dielectric materials is determined in accordance with the predetermined dielectric constant of the η electrical layer 339. A method of forming the dielectric layer 339 is, for example, a bismuth chemical vapor deposition method or a spin-coating method. The material of the worm-killing stop layer 341 is, for example, nitriding stone, carbonized dream, cerium oxynitride or lanthanum carbonitride, and its formation method is, for example, chemical vapor deposition. The material of the dielectric layer 343 is, for example, ruthenium oxide or a low dielectric material having a dielectric constant of less than 4, and the formation method is, for example, a chemical vapor deposition method or a spin coating method. The material of the top ruthenium layer 345 is, for example, teosyl-oxidized oxide, and its formation method is, for example, chemical vapor deposition. The material of the hard mask layer 347 is, for example, tantalum titanium nitride, and its formation method is, for example, chemical vapor deposition. It is worth mentioning that 'the above protective layer 337, the money stop layer 341, the top layer 345 and the hard mask layer 347 are arranged to improve the control of the subsequent lithography and etching process, so that the photoresist pattern can be accurately Move to avoid 13 I26797ft8twf.d〇c/g eroding other layers. However, the setting of these layers or the addition of other layers such as anti-reflective layer and Wetting Layer can still be selected depending on the needs of the process. Please refer to FIG. 3D, and then form a double damascene opening 350' on the protective layer 337, the dielectric final stop layer 341, the dielectric layer 343, the cap layer, and the mask layer. The via opening 357 of the plug 335 is connected to the lead trench 355 above it. The double-inlaid opening 350 can be formed by first engraving the via window 357 and then engraving the wire trench 355; or forming the side-out wire trench 355 first, and then etching the via opening 357. The method of etching these layers is, for example, a non-isotropic reactive ion etching (Reactive l0h ^ch), and the electropolymerization gas composition used can be adjusted according to the material of each film layer. Since the formation method of the double damascene opening is well known to the art, it will not be described. Next, referring to FIG. 3E, a barrier layer 359 and a conductor layer 360 are formed on the hard mask layer 347, and the conductor layer 36, the barrier layer 359, the hard mask layer 347, and the top of the dielectric layer 343 are removed. Cover layer 345. The material of the barrier layer 359 is, for example, titanium, titanium nitride, tantalum, nitride button, tungsten, tungsten nitride or titanium tungsten alloy, and the formation method thereof is, for example, chemical vapor deposition or physical vapor deposition. The material of the conductor layer 36 is, for example, copper, tungsten, aluminum, molybdenum, gold, platinum or an alloy thereof, and the formation method thereof is, for example, a chemical vapor deposition method or a physical gas phase deposition method. The method of removing the conductor layer 360 on the dielectric layer 343 to the cap layer 345 is, for example, a chemical mechanical polishing method. At this time, the conductor layer 360 in the wire trench 355 is a wire of the interconnect wire, which is electrically connected to the first plug 335 via the conductor layer 360 (ie, the second plug) in the via opening. 12679^08twf.doc/g In summary, since the present invention divides the plug into two stages, and the aspect ratio of the open σ in each stage is greatly reduced, the dielectric layer can be prevented from being incomplete. At the same time, void defects (Void) defects can be avoided during the process of GapFill, and problems such as disconnection can be prevented, thereby improving the reliability of the element and the yield of the product. Although the present invention has been disclosed in the above embodiments by way of example, it is not intended to be used by any of the inventions of the present invention, and the invention may be modified and retouched. This is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view of a conventional MOS transistor contact window. Fig. 2 is a cross-sectional view of an interconnect structure of an embodiment of the present invention. 3A to 3E are diagrams showing the interconnection method of the embodiment of the present invention. 100, 200, 300: substrate 110, 120: MOS transistor 130, 215, 315: source/drain region 140, 22 240, 339, 343: dielectric layer 145: contact window opening 9 150: contact window plug 201, 301 · isolation structure 210, 310: semiconductor device 211, 311: gate dielectric layer 213, 313: gate 15 12679^08twf.doc / g 217, 317: metal telluride layer 219, 319: spacer 220 , 320, 341 : etch stop layer 222 , 321 : lower dielectric layer 223 , 337 : protective layer 225 : upper dielectric layer 230 : composite plug 231 : first plug 235 : second plug 237 , 239 , 331 359 · barrier layer 250: wires 323, 347: hard mask layer 325: patterned photoresist layer 327: openings 333, 360: conductor layer 335: first plug 345: cap layer 350: double inlaid opening 355: Wire trench 357: via window opening

Claims

12679¾ 8twfl .doc/006 伴昃月箩日修⑻正替坂頁十、申請專利範圍： 1· 一種内連線結構，位於一基底上，該基底上包括一導電部’且該内連線結構包括：一介電層，配置於該基底上，並覆蓋住該導電部；一複合插塞，配置於該介電層中，且電性連接該導電部，該複合插塞由下而上包括一第一插塞與一第二插塞，且該第二插塞與該第一插塞的材質不同或關鍵尺寸不同；以及一導線，配置於該介電層上，且電性連接該複合插塞。 2·如申請專利範圍第1項所述之内連線結構，其中該第一插塞的深寬比小於等於3。 3·如申請專利範圍第1項所述之内連線結構，其中該第一插塞的材質選自銅、鎢、鋁、鉬、金、鉑及其合金。 4·如申請專利範圍第1項所述之内連線結構，其中該第二插塞的材質選自銅、鎢、鋁、鉬、金、鉑及其合金。 5·如申請專利範圍第1項所述之内連線結構，其中該介電層由該基底起包括一下介電層與一上介電層，且該第一插塞位於該下介電層中，該第二插塞位於該上介電層中。 6·如申請專利範圍第5項所述之内連線結構，其中該上介電層的材質包括低介電材料。 7·如申請專利範圍第5項所述之内連線結構，更包括一保護層，配置於該下介電層與該上介電層之間。 8·如申請專利範圍第7項所述之内連線結構，其中該保4層的材質選自氮化矽、碳化矽、氮氧化矽與碳氮化矽。 17 I26797〇8twfi>d〇c/〇〇6 95-8-8 9. 如申請專利範圍第丨項所述之内連線結構 -阻障層’錄該複合插塞與該介㈣、料 10. 如申請專利範圍第9項所述之内連線 ^ =質選自鈦、氮化鈦、一，、氮化;; 11. 如中請專利範圍帛丨項所述之内連線結構，126793⁄4 8twfl .doc/006 昃箩箩 ( ( 8 8 8 8 8 、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、、 The method includes: a dielectric layer disposed on the substrate and covering the conductive portion; a composite plug disposed in the dielectric layer and electrically connected to the conductive portion, the composite plug being included from bottom to top a first plug and a second plug, and the second plug is different in material or key size from the first plug; and a wire disposed on the dielectric layer and electrically connected to the composite Plug. 2. The interconnect structure of claim 1, wherein the first plug has an aspect ratio of less than or equal to three. 3. The interconnect structure of claim 1, wherein the material of the first plug is selected from the group consisting of copper, tungsten, aluminum, molybdenum, gold, platinum, and alloys thereof. 4. The interconnect structure of claim 1, wherein the material of the second plug is selected from the group consisting of copper, tungsten, aluminum, molybdenum, gold, platinum, and alloys thereof. 5. The interconnect structure of claim 1, wherein the dielectric layer comprises a lower dielectric layer and an upper dielectric layer from the substrate, and the first plug is located in the lower dielectric layer The second plug is located in the upper dielectric layer. 6. The interconnect structure of claim 5, wherein the material of the upper dielectric layer comprises a low dielectric material. 7. The interconnect structure of claim 5, further comprising a protective layer disposed between the lower dielectric layer and the upper dielectric layer. 8. The interconnect structure of claim 7, wherein the material of the fourth layer is selected from the group consisting of tantalum nitride, tantalum carbide, niobium oxynitride and niobium carbonitride. 17 I26797〇8twfi>d〇c/〇〇6 95-8-8 9. As shown in the scope of the patent application, the interconnect structure-barrier layer is recorded as the composite plug and the dielectric (4), material 10 The interconnecting line as described in item 9 of the patent application scope is selected from the group consisting of titanium, titanium nitride, one, and nitriding; 11. The interconnect structure as described in the scope of the patent,

導電部為-摻雜區、一閘極、一摻雜區與一閘極的組合了或是一導線。、口 12· —種内連線結構的製造方法，包括：提供一基底，該基底上已形成有一導電部；於該基底上形成一下介電層覆蓋住該導電部；於該下介電層中形成一第一插塞，以電性連接該導電部； … 於戎下介電層與該第一插塞上形成一上介電層；以及於該上介電層中形成一第二插塞與一導線，該第二插The conductive portion is a doped region, a gate, a doped region and a gate, or a wire. The method for manufacturing an interconnect structure includes: providing a substrate having a conductive portion formed thereon; forming a lower dielectric layer over the substrate to cover the conductive portion; and the lower dielectric layer Forming a first plug electrically connected to the conductive portion; forming an upper dielectric layer on the underlying dielectric layer and the first plug; and forming a second plug in the upper dielectric layer Plug with a wire, the second plug

塞位於該第一插塞與該導線之間，且電性連接該導線與該第一插塞。 13·如申請專利範圍第12項所述之内連線結構的製造方法，其中該第一插塞的深寬比小於等於3。 H·如申請專利範圍第12項所述之内連線結構的製造方法’其中邊弟一插基的材質選自銅、鶴、铭、銷、金、鉑及其合金。 15·如申睛專利範圍第12項所述之内連線結構的製造方法，其中該上介電層由下而上包括一第一介電層、一蝕The plug is located between the first plug and the wire, and electrically connects the wire and the first plug. The method of manufacturing an interconnect structure as described in claim 12, wherein the first plug has an aspect ratio of 3 or less. H. The manufacturing method of the interconnect structure as described in claim 12, wherein the material of the mate is selected from the group consisting of copper, crane, Ming, pin, gold, platinum, and alloys thereof. The method of manufacturing an interconnect structure according to claim 12, wherein the upper dielectric layer comprises a first dielectric layer and an etch from bottom to top.

18 I2679H_ 95-8-8 刻中止層與一第二介電層。 16·如申1專利範圍第15項所述之内連線結構的製造方法’其中该第-介電層與該第二介電層的材質包括電材料。、一 17·如申請專利範圍第15項所述之内連線結構的製造方法，其中該蝕刻中止層的材質選自氮化矽、氮化矽:氮乳化梦、碳氮化秒。 18·如申請專利範圍第12項所述之内連線結構的製造方法，其中於該上介電層中形成該第二插塞與該導線法包括：〃於^上介電層中形成一雙重鑲嵌開口，包括暴露出該第一插塞的一介層窗開口與通過其上方之一導線溝渠；於該上介電層上形成一導體層，其填滿該雙重鑲嵌開口，以及移除該雙重鑲嵌開口以外之該導體層。 19·如申請專利範圍第18項所述之内連線結構的製造 • 方法，其中移除該雙重鑲嵌開口以外之該導體層的方法句括化學機械研磨法。 2〇·如申凊專利範圍第18項所述之内連線結構的製造、 #法’ f包括··於該上介電層形成之後、該雙重鑲嵌開Q 形成之别，於該上介電層上形成用來定義該雙重鑲嵌的一硬罩幕層。18 I2679H_ 95-8-8 engraved stop layer and a second dielectric layer. The method of manufacturing an interconnect structure as described in claim 15 wherein the material of the first dielectric layer and the second dielectric layer comprises an electrical material. The method of manufacturing the interconnect structure of claim 15, wherein the material of the etch stop layer is selected from the group consisting of tantalum nitride, tantalum nitride: nitrogen emulsified dream, and carbonitride. 18. The method of fabricating an interconnect structure according to claim 12, wherein the forming the second plug in the upper dielectric layer and the wire method comprises: forming a dielectric layer in the upper dielectric layer a dual damascene opening, comprising a via opening exposing the first plug and a wire trench passing over the upper plug; forming a conductor layer on the upper dielectric layer, filling the dual damascene opening, and removing the The conductor layer other than the double inlaid opening. 19. The method of manufacturing an interconnect structure as described in claim 18, wherein the method of removing the conductor layer other than the dual damascene opening comprises a chemical mechanical polishing method. 2. The manufacture of the interconnect structure as described in claim 18 of the patent scope of the application, the method f includes: after the formation of the upper dielectric layer, the formation of the double damascene opening Q, A hard mask layer is formed on the electrical layer to define the dual damascene.