1261312 九、發明說明： 【發明所屬之技術領域】 - 本發明係在提供一種避免反應室粒子污染的化學氣相 - 沈積方法，尤指一種避免反應室粒子污染的高密度電漿化 學氣相沈積方法。 φ 【先前技術】 在半導體製程中，為了使晶片上各個電子元件之間擁 有良好的隔離，以避免元件相互干擾而產生短路現象，一 般採用區域氧化法(localized oxidation isolation, LOCOS)或 是淺溝槽隔離(shallow trench isolation，STI)方法來進行元 件之隔離與保護。由於LOCOS製程中產生的場氧化層 (field oxide)所佔據晶片的面積太大，而且生成過程會伴隨 鳥嘴(bird’s beak)現象的發生，因此對於線寬250奈米（nm) 以下的半導體製程皆採用STI進行隔離。 請參照第1圖，在典型之STI製程中，係先於半導體 晶圓10之半導體基底4上覆蓋一層氧化層12以做為緩衝 層’避免下層基材4在後績製程中受到熱應力破壞。接著 於氧化層12上形成一氮化矽層2，並於其上覆以圖案化-光 1261312 阻層（未顯示），用來暴露出部分之氮化石夕層2以界定sti 的位置，然後蝕刻該暴露部分之氮化矽層2，進行圖案轉 移，從而形成圖案化之氮化矽層2。接著，以此圖案化之. • 氮化矽層2以作為遮罩，蝕刻未受氮化矽層2遮掩部分之 . 半導體基底4，以形成溝槽8。最後進行氧化矽6之沈積， 以填滿溝槽8’並利用化學機械研磨（CMP)完成STI的製程。 • 然而，隨著製程線寬不斷縮小，若使用一般的化學氣 相沈積（chemical vapor deposition, CVD)，則在沈積過程 中’沈積物可能累積於溝槽8開口，發生懸突(over hang) 現象，進而導致諸如孔洞（void)或接合缝隙（seam)等覆蓋不 均勻及溝槽無法被填滿的問題。因此，在目前的STI製程 中’通常採用高密度電漿氣相沈積(high-density plasma chemical vapor deposition, HDP-CVD)，利用同時進行化學 籲 氣相沈積與物理濺蝕的方式，以順利於溝槽8中填滿氧化 石夕6 〇 然而，在利用HDP-CVD進行氧化物沈積步驟時，反 應室（chamber)内壁會因沈積反應的進行而形成一層氧化層 薄膜，此氧化層薄膜可能在後續製程中剝落造成污染。因 此，目前係藉由先於反應室室壁上形成一定厚度及品質之 1261312 前氧化層（pre-oxide layer)的方式，以避免製程時，反應室 室壁上之氧化層發生剝落的現象，並使後續製程中所形成 之氧化層薄膜得以持續附著於該前氧化層上，從而避免後 續形成之氧化層薄膜因剝落所造成粒子污染。其中，該前 氧化層之製作方法係利用矽曱烷(silane, SiH4)與氧氣(〇2) 之反應，從而於反應室室壁上形成一定厚度與品質之前氧 化層。 在該前氧化層形成後，即可進行主要的HDP-CVD製 程，亦即，藉由在反應室中通入矽曱烷以及氧氣來進行沈 積以填滿淺溝槽’而此時亦會同時於反應室室壁上形成一 氧化層薄膜。然而，由於反應室室壁上已覆有一預先沈積 之前氧化層，因此該伴隨溝槽填充程序產生之氧化層薄膜 將可附著於該前氧化層上。是以，反應室室壁上所形成之 該前氧化層的品質將影響後續製程中氧化層之附著情況， 因此製造品質優良之箣氧化層係防止反應室受到污染的重 要因素。 此外，由於反應室室壁上之氧化層將隨著每一次的製 程而增厚，所以，當反應室室壁上之氧化層累積達到一定 厚度時，必須進行一清潔程序除去反應室室壁上過厚之氧 1261312 化層。一般而言，依據不同之製程需求，大約每進行一到 十片晶圓之HDP-CVD製程即需進行一次的清潔程序。 儘管上述方法在較大線寬之製程中能有效避免粒子污 染，但是在90奈米以下之製程中，為了避免溝槽開口堵 塞，必須使用更大之電漿能量解離反應氣體分子，以增加 填洞能力（gapfill ability)。然而，在使用較大電漿能量的情 況下，較強烈的離子撞擊將肇使反應室内壁的的氧化層更 加谷易剝洛’從而造成嚴重的粒子污染。此時，傳統的 HDP-CVD方法可能無法有效避免上述粒子污染。因此，目 前便需要一種更為有效的方法以避免小線寬製程中因氧化 層剝落所產生之粒子污染。 【發明内容】 本發明提供一種避免反應室粒子污染的高密度電裝化 學氣相沈積方法，以改善習知技藝中反應室粒子污染的問 域本餐明更提供一種在HDP-CVD反應室室壁上形成較 佳品質之前氧化層的方法，以使後續HDP-CVD製程中產 生之氧化層得附著其上，從而避免後續產生之氧化層自反 應室室壁剝落而造成污染。 1261312 根據本發明之申請專利範圍，其係揭露一種避免反應室 粒子污染的化學氣相沈積方法。首先以較高之低頻射頻功 率功率以及較長之製程時間進行一鈍化製程以及一預熱製 程。接著，於反應室室壁形成一前氧化層，並同時於反應 室中提供一高頻射頻功率功率以引導反應室中帶電粒子之 方向，促進前氧化層之沈積。並持續於反應室中提供較高 之低頻射頻功率功率以維持反應室之溫度，最後再開始進 行一主要氧化層沈積。此外，根據本發明所提供之方法， 在進行多次主要氧化層之沈積後，可進行一清潔程序，以 清除反應室室壁上過厚之氧化層。 本發明所提供之方法可形成品質優良之前氧化層，從而 使後續製程中產生之氧化物得以附著其上而不剝離造成粒 子污染。換言之，本發明可有效解決習知CVD反應室中粒 子污染的問題。 【實施方式】 本發明提供一種改良之CVD方法，此種CVD方法可以提 高前氧化層之品質，使其足以承受HDP-CVD之高功率製 程與強烈粒子撞擊而不致自反應室室壁剝離，以減少反應 室中之粒子污染。 11 1261312 5月茶照第2圖’第2圖為本發明之HDP-CVD方法之 較佳具體實施㈣流程圖—。如第2圖所示，本發明所提 供之方法主要由鈍化製程(步驟21())、預熱製程(步驟叫、 前氧化層(pre-〇xidelayer)沈積(步驟214)、提供低頻射頻功 率力率卜驟216)、以及主氧化層（main〇xidela㈣沈積(步 驟218)所構成。而本發明與習知HDp_cvD方法最 同在於，本發明所提供之枝在進㈣氧化層沈積(步驟 218)之前，便將反應室維持於高功率以及高溫的狀態，使 知在反應至室壁上生成前氧化層時，反應室便持續處於類 似主氧化層沈積下之高功率、高溫狀態下，以製備一厚度 及品質較佳之前氧化層，並使此前氧化層穩定於該製程環 境中’從㈣免室壁上之氧化物在進行主氧化層沈積時剝 落。此外，本發明之方法更於反應中提供一偏壓以引導反 應室中之污染粒子，因此可更進一步避免反應室之污染。 請繼續參照第2圖，現將詳細說明本發明之一具體實 施例實施方法。根據本發明之方法，首先於hDP_CvD反 應室中進行一排空反應室之鈍化製程（步驟21〇)。該鈍化製 程係於反應室中通入氫氣以移除反應室中之殘餘氣體，從 而淨空反應室。例如，清潔製程所使用之三氟化氮(NF3)等 氣體即可能殘留於反應室中，因此需要一鈍化程序清除 12 1261312 之。然而，本發明所提供之純化程序與習知技藝之鈍化程 序有所不同。_本發明之献程序絲—不小於主氧化 層沈積(步驟2寧需之低頻射頻功率功率~ radio f卿ency，LFRF)下進行，並持續一較長之製程時間， 以使反應室處於高溫狀態。亦即，必須於反應室中維持大 於或等於主氧化層沈積所需之低頻射頻功率功率，並使反 應室之溫錢到大於或料主氧化層沈積_需之溫度。 例如，-般於90奈米㈣之製程在進行主氧化層沈積（步 驟218)時，所使用之低頻射頻功率功率約為5_瓦(補)， 故本發明可於鈍化製程巾在反應室巾提供6_瓦之低頻 射頻功率功率。歸續進行鈍化轉，直至反應室之溫度 大於或等於主氧化層沈積之溫度，例如，持續鈍化製程⑽ 秒，以使反應室溫度到達攝氏58〇度或更高。 /接著，進行一反應室之預熱製程（步驟212)。該預熱製 程係於反應室中通入氬(Ar)、氦(He)、或氫氣㈣等鈍氣 (inert gas)的狀況下’提高反應室之溫度，以職續化學反 應之進行。亦即，根據本發明所提供之方法，係於預熱反 應室中提供辦大於或等於主氧化層沈積所需功率之倾 射頻功率功率，以及進行較長時間之加熱，以使反應室之 溫度高於或等於主氧化層沈積之溫度。例如，可於反應室 13 1261312 中提供6000瓦之低頻射頻功率功率，並持續加溫18〇秒， 以使反應室溫度達到攝氏攝氏580度或更高。 在完成預熱製程（步驟212)後，隨即進行一前氧化層之 沈積’以於反應室室壁上形成一前氧化層。如前所述，在 沈積主氧化層時將會有部分之氧化物附著於反應室室壁 上，這些附著於反應室室壁上之氧化物可能在後續製程中 剝落，造成污染。因此習知技藝係預先沈積於反應室室壁 上形成一定厚度與品質之氧化層（亦即該前氧化層），以使 後續生成之氧化物得以附著，從而避免氧化物自反應室室 壁上剝落。惟本發明與習知技藝之不同之處在於，本發明 於進行前氧化層沈積時，亦同時於反應室中提供一高頻射 頻功率功率（high frequency radio frequency，HFRF)，以引導 反應室中帶電粒子之移動方向’ 一方面可促進氧化層之沈 積’另一方面又能避免氧化物粒子落於基座上造成污染。 例如，在反應室中維持高功率（例如6000瓦）之低頻射 頻功率的情況下，先利用高頻射頻功率於反應室中提供 2000瓦之偏壓60秒後，再通入矽曱烷(siiane)和氧氣等反 應氣體並維持該偏壓達17〇秒。如此將可在偏壓的辅助下 於反應室室壁表面形成一品質與厚度較佳之前氧化層，且 14 1261312 境與後續製程相仿，因此該前氧化層將可 程中之高功率、高溫環境。此外，必須強調的 二相軸頻功率可由仏咖反應室中餘提供電裝 漳# bombard)騎之電極提供’惟於本發明中該偏邀係將 帶正電之電漿向下料至晶圓基座上，㈣帶有負電之氧 化㈣上^至反應室室壁之上。總之，無_外設置提 ί、偏[之7L件以進仃本發明之方法，因此本發明更有易於 實施之優點。 在^成祕化層之沈積製程（步驟214)後，再於反應室 提供較高之低頻射頻功率以維持反應室之溫度（步驟 216)並進行一主要氧化層沈積（步驟⑽）。例如可於反應 室中提供高功率（例如_瓦）之低頻射頻功率約6〇秒， 使反應室之環境達到較錄態後，接著再進行主要之氧化 層沈積’以完成HDP-CVD製程。值得注意的是，本發明 之方法可適用於各種淺溝隔離(STI)製程、層間介電層 (ILD)、金屬内介電層（IMD)等之HDP-CVD製程上。 由於在進行主氧化層沈積（步驟218)時，亦會同時將部 分氧化物沈積於反應室室壁上，因此在重複多次主氧化層 沈積製程（步驟214)後，將於反應室室壁上形成較厚之氧化 15 1261312 層。此時，本發明可再進行一清潔製程，而於反應室中通 入氟化物等清潔氣體，以清除過厚之氧化層。例如，可在 進行夕-人主氧化層沈積（步驟218)後，例如十次，便於反應 至中通入三氟化氫以去除多餘之氧化物。而多餘之三氟化 氫則可藉由前述鈍化製程（步驟21〇)移除。換言之，無須在 每一次主氧化層沈積（步驟218)前皆進行該鈍化製程(步驟 210) ’僅須在反應室中有殘留氟化物時進行該鈍化製程（步 驟210)即可ό 相較於傳統之hdp_CVd方法，本發明可有效減少反 應至中之粒子污染。例如，相對於一傳統利用4000瓦低頻 射v頁力率之製程’上述實施例可大幅減少反應室中之殘餘 粒子數量，因此，可大幅延長反應室維護的週期。例如， 依知上述之實施例，可在製造三千片以上之晶圓後，再進 行反應至之維護。換言之，利用本發明所提供之方法，不 但可以減少反應室中之粒子污染，提高晶圓之良率，更可 進一步降低反應室之維護成本，增加產能(throughput)。 以上所述僅為本發明之較佳實施例，凡依本發明申請 專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範 圍。 1 16 1261312 【圖式簡單說明】 第1圖為一習知淺溝槽隔離結構之剖面圖。 第2圖為一本發明之具體實施例之流程圖。 【主要元件符號說明】 2 氮化石夕層 210 以較高之LFRF功率及較長之 製程時間進行一鈍化製程 4 半導體基底 212 以較高之LFRF功率以及較長 之製程時間進行一預熱製程 6 氧化梦 214 於反應室提供HFRF偏壓，並於 反應室室壁上形成前氧化層 8 溝槽 216 於反應室中提供較高之LFRF 功率 10 半導體晶圓 218 進行主要氧化層之沈積 12 氧化層 171261312 IX. Description of the invention: [Technical field to which the invention pertains] - The present invention provides a chemical vapor-deposition method for avoiding particle contamination in a reaction chamber, and more particularly to a high-density plasma chemical vapor deposition for avoiding particle contamination in a reaction chamber. method. φ [Prior Art] In the semiconductor process, in order to have good isolation between the electronic components on the wafer to avoid short-circuit phenomenon caused by mutual interference of components, generally used localized oxidation isolation (LOCOS) or shallow trenches The trench trench isolation (STI) method is used to isolate and protect components. Since the area of the wafer occupied by the field oxide generated in the LOCOS process is too large, and the generation process is accompanied by the bird's beak phenomenon, the semiconductor process with a line width of less than 250 nm (nm) is used. All are isolated using STI. Referring to FIG. 1 , in a typical STI process, an oxide layer 12 is applied over the semiconductor substrate 4 of the semiconductor wafer 10 as a buffer layer to prevent the underlying substrate 4 from being damaged by thermal stress in the subsequent process. . A tantalum nitride layer 2 is then formed on the oxide layer 12 and overlaid with a patterned-light 1261312 resist layer (not shown) for exposing a portion of the nitride layer 2 to define the position of sti, and then The exposed portion of the tantalum nitride layer 2 is etched and patterned to form a patterned tantalum nitride layer 2. Then, the silicon nitride layer 2 is used as a mask to etch the portion of the semiconductor substrate 4 that is not covered by the tantalum nitride layer 2 to form the trenches 8. Finally, deposition of yttrium oxide 6 is performed to fill the trench 8' and the process of STI is completed by chemical mechanical polishing (CMP). • However, as the process line width continues to shrink, if general chemical vapor deposition (CVD) is used, the deposit may accumulate in the opening of the trench 8 during the deposition process, and overhang occurs. Phenomenon, which in turn causes problems such as uneven coverage of voids or seams and the inability of the grooves to fill. Therefore, in the current STI process, 'high-density plasma chemical vapor deposition (HDP-CVD) is usually used, and simultaneous chemical vapor deposition and physical sputtering are used to smoothly The trench 8 is filled with oxidized oxide 夕6 〇 However, in the oxide deposition step by HDP-CVD, the inner wall of the chamber forms an oxide film due to the deposition reaction, and the oxide film may be Peeling in subsequent processes causes pollution. Therefore, the pre-oxide layer of a certain thickness and quality is formed on the wall of the reaction chamber to avoid the peeling of the oxide layer on the chamber wall during the process. The oxide film formed in the subsequent process is continuously adhered to the front oxide layer, thereby preventing particle contamination caused by peeling of the subsequently formed oxide film. Among them, the pre-oxidation layer is produced by reacting silane (SiH4) with oxygen (?2) to form a certain thickness and quality of the oxide layer on the chamber wall. After the formation of the front oxide layer, a main HDP-CVD process can be performed, that is, deposition is performed by introducing decane and oxygen into the reaction chamber to fill the shallow trenches. An oxide film is formed on the walls of the reaction chamber. However, since the reaction chamber wall is covered with a pre-deposited oxide layer, the oxide film produced by the accompanying trench filling process will adhere to the front oxide layer. Therefore, the quality of the front oxide layer formed on the wall of the reaction chamber will affect the adhesion of the oxide layer in the subsequent process, and therefore the production of a high quality tantalum oxide layer is an important factor for preventing contamination of the reaction chamber. In addition, since the oxide layer on the wall of the reaction chamber will be thickened with each process, when the oxide layer on the wall of the reaction chamber accumulates to a certain thickness, a cleaning procedure must be performed to remove the chamber wall. Overly thick oxygen 1261312 layer. In general, depending on the process requirements, a cleaning process is required for approximately one to ten wafers of HDP-CVD. Although the above method can effectively avoid particle contamination in the process of larger line width, in the process of 90 nm or less, in order to avoid clogging of the trench opening, it is necessary to use larger plasma energy to dissociate the reaction gas molecules to increase the filling. Gapfill ability. However, in the case of using larger plasma energy, a stronger ion impact will cause the oxide layer in the inner wall of the reaction chamber to be more easily delaminated, resulting in severe particle contamination. At this time, the conventional HDP-CVD method may not effectively avoid the above particle contamination. Therefore, there is a need for a more efficient method to avoid particle contamination caused by oxide flaking in a small line width process. SUMMARY OF THE INVENTION The present invention provides a high-density electrical chemical vapor deposition method for avoiding particle contamination in a reaction chamber to improve the particle contamination of the reaction chamber in the prior art. The present invention provides a room in the HDP-CVD reaction chamber. A method of forming a prior quality oxide layer on the wall is provided to adhere the oxide layer generated in the subsequent HDP-CVD process, thereby preventing contamination of the subsequently generated oxide layer from the reaction chamber wall. 1261312 A method of chemical vapor deposition that avoids particle contamination of a reaction chamber is disclosed in accordance with the scope of the present invention. First, a passivation process and a preheating process are performed with higher low frequency RF power and longer process time. Next, a front oxide layer is formed on the walls of the reaction chamber, and a high frequency RF power is supplied to the reaction chamber to direct the direction of the charged particles in the reaction chamber to promote deposition of the front oxide layer. It continues to provide higher low frequency RF power in the reaction chamber to maintain the temperature of the reaction chamber and finally begins a major oxide layer deposition. Further, in accordance with the method of the present invention, after deposition of a plurality of primary oxide layers, a cleaning procedure can be performed to remove an excessively thick oxide layer on the walls of the reaction chamber. The method provided by the present invention can form a high quality prior oxide layer so that oxides generated in subsequent processes can be attached thereto without peeling off causing particle contamination. In other words, the present invention can effectively solve the problem of particle contamination in a conventional CVD reaction chamber. [Embodiment] The present invention provides an improved CVD method which can improve the quality of a front oxide layer enough to withstand the high power process of HDP-CVD and strong particle impact without peeling off from the reaction chamber wall. Reduce particle contamination in the reaction chamber. 11 1261312 May tea photo 2'' Fig. 2 is a flow chart of a preferred embodiment (4) of the HDP-CVD method of the present invention. As shown in FIG. 2, the method provided by the present invention mainly comprises a passivation process (step 21 ()), a preheating process (step called, pre-〇xide layer deposition (step 214), providing low frequency RF power. The force rate is 216), and the main oxide layer (main 〇 dela) is deposited (step 218). The present invention is the same as the conventional HDp_cvD method, and the branch provided by the present invention is deposited in the (four) oxide layer (step 218). Before, the reaction chamber is maintained at a high power and high temperature state, so that when the reaction forms a front oxide layer on the chamber wall, the reaction chamber continues to be in a high-power, high-temperature state similar to that of the main oxide layer. Preparing a prior thickness and quality of the oxide layer and stabilizing the previous oxide layer in the process environment 'from (4) the oxide on the chamber wall is peeled off during the deposition of the main oxide layer. Further, the method of the present invention is more reactive A bias is provided to guide the contaminating particles in the reaction chamber, so that contamination of the reaction chamber can be further avoided. Referring now to Figure 2, a detailed implementation of one embodiment of the present invention will now be described in detail. In the method of the invention, a passivation process of a row of empty reaction chambers is first performed in the hDP_CvD reaction chamber (step 21A). The passivation process is performed by introducing hydrogen into the reaction chamber to remove residual gas in the reaction chamber, thereby clearing the reaction chamber. For example, a gas such as nitrogen trifluoride (NF3) used in the cleaning process may remain in the reaction chamber, so a passivation procedure is required to remove 12 1261312. However, the purification procedure provided by the present invention and the passivation of the prior art are required. The procedure is different. _ The program of the present invention - not less than the main oxide layer deposition (step 2 is less than the low frequency RF power ~ radio frequency LF, LFRF), and lasts a longer process time, to Keeping the reaction chamber at a high temperature. That is, it is necessary to maintain a low-frequency RF power power greater than or equal to that required for the deposition of the main oxide layer in the reaction chamber, and to make the temperature of the reaction chamber larger than the temperature at which the main oxide layer is deposited. For example, the process of 90 nm (four) is used to perform main oxide layer deposition (step 218), and the low frequency RF power used is about 5 watts (complement), so the present invention can be passivated. The towel provides 6 watts of low frequency RF power in the reaction chamber. The passivation is continued until the temperature of the chamber is greater than or equal to the temperature at which the main oxide layer is deposited, for example, the passivation process is continued for 10 seconds to allow the chamber temperature Reaching 58 degrees Celsius or higher. / Next, performing a preheating process of the reaction chamber (step 212). The preheating process is performed by introducing argon (Ar), helium (He), or hydrogen (four) into the reaction chamber. In the case of an inert gas, 'increasing the temperature of the reaction chamber to proceed with the chemical reaction. That is, the method according to the present invention provides a greater than or equal to the main oxide layer in the preheating reaction chamber. The RF power of the desired power is deposited, and the heating is performed for a longer period of time such that the temperature of the reaction chamber is higher than or equal to the temperature at which the main oxide layer is deposited. For example, a low frequency RF power of 6000 watts can be provided in reaction chamber 13 1261312 and continuously heated for 18 seconds to bring the chamber temperature to 580 degrees Celsius or higher. After the preheating process (step 212) is completed, a deposition of a front oxide layer is performed to form a front oxide layer on the walls of the reaction chamber. As previously mentioned, some of the oxide will adhere to the walls of the reaction chamber during deposition of the main oxide layer. These oxides adhering to the walls of the reaction chamber may peel off during subsequent processes, causing contamination. Therefore, the prior art is deposited on the wall of the reaction chamber to form an oxide layer of a certain thickness and quality (that is, the front oxide layer), so that the subsequently formed oxide is adhered, thereby preventing the oxide from being on the chamber wall of the reaction chamber. Peel off. However, the present invention differs from the prior art in that the present invention provides a high frequency radio frequency (HFRF) in the reaction chamber during the deposition of the front oxide layer to guide the reaction chamber. The moving direction of the charged particles 'on the one hand can promote the deposition of the oxide layer' and on the other hand can prevent the oxide particles from falling on the pedestal and causing pollution. For example, in the case of maintaining high-frequency (for example, 6000 watts) low-frequency RF power in the reaction chamber, the high-frequency RF power is first used to provide a bias of 2000 watts in the reaction chamber for 60 seconds, and then sane is introduced. And a reactive gas such as oxygen and maintain the bias for 17 sec. In this way, an oxide layer with a good quality and thickness can be formed on the surface of the reaction chamber wall with the aid of a bias voltage, and the 14 1261312 environment is similar to the subsequent process, so that the front oxide layer will have a high power and high temperature environment. In addition, the two-phase axial frequency power that must be emphasized can be provided by the electrode of the bomb 反应 反应 bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb bomb On the circular base, (4) with negatively charged oxidation (4) above the chamber wall. In short, there is no way to improve the method of the present invention, so that the present invention has an advantage of being easy to implement. After the deposition process of the secret layer (step 214), a higher low frequency RF power is supplied to the reaction chamber to maintain the temperature of the reaction chamber (step 216) and a primary oxide layer deposition (step (10)). For example, a high power (e.g., watt) low frequency RF power can be provided in the reaction chamber for about 6 seconds, after the reaction chamber environment is brought to a higher state, followed by a major oxide layer deposition to complete the HDP-CVD process. It should be noted that the method of the present invention can be applied to various HDP-CVD processes such as shallow trench isolation (STI) processes, interlayer dielectric layers (ILD), and metal internal dielectric layers (IMD). Since part of the oxide is deposited on the chamber wall at the same time during the main oxide layer deposition (step 218), after repeating the main oxide layer deposition process (step 214), the chamber wall will be A thicker layer of oxidized 15 1261312 is formed. At this time, the present invention can perform a cleaning process by introducing a cleaning gas such as fluoride into the reaction chamber to remove the excessively thick oxide layer. For example, after the eve-human primary oxide layer deposition (step 218), e.g., ten times, the reaction is facilitated to pass hydrogen trifluoride to remove excess oxide. The excess hydrogen trifluoride can be removed by the aforementioned passivation process (step 21). In other words, it is not necessary to perform the passivation process (step 210) before each main oxide layer deposition (step 218). 'The passivation process (step 210) is only required when there is residual fluoride in the reaction chamber. The conventional hdp_CVd method can effectively reduce particle contamination in the reaction. For example, the above embodiment can substantially reduce the amount of residual particles in the reaction chamber relative to a conventional process utilizing a 4,000 watt low frequency shot page rate. Therefore, the cycle of maintenance of the reaction chamber can be greatly extended. For example, in accordance with the above embodiments, the reaction can be maintained after the fabrication of more than three thousand wafers. In other words, by using the method provided by the present invention, not only the particle contamination in the reaction chamber can be reduced, the yield of the wafer can be improved, but also the maintenance cost of the reaction chamber can be further reduced, and the throughput can be increased. The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the invention are intended to be included in the scope of the present invention. 1 16 1261312 [Simple description of the drawings] Fig. 1 is a cross-sectional view of a conventional shallow trench isolation structure. Figure 2 is a flow diagram of a particular embodiment of the invention. [Main component symbol description] 2 The nitride layer 210 performs a passivation process with a higher LFRF power and a longer process time. 4 The semiconductor substrate 212 performs a preheating process with a higher LFRF power and a longer process time. The Oxidation Dream 214 provides an HFRF bias in the reaction chamber and forms a front oxide layer on the chamber wall. The trench 216 provides a higher LFRF power in the reaction chamber. 10 Semiconductor Wafer 218 Performs Primary Oxide Deposition 12 Oxide Layer 17