TWI260714B - Method for forming a metal layer in multiple steps - Google Patents

Method for forming a metal layer in multiple steps Download PDF

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TWI260714B
TWI260714B TW094140473A TW94140473A TWI260714B TW I260714 B TWI260714 B TW I260714B TW 094140473 A TW094140473 A TW 094140473A TW 94140473 A TW94140473 A TW 94140473A TW I260714 B TWI260714 B TW I260714B
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substrate
metal layer
forming
predetermined thickness
reaction chamber
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TW200638484A (en
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Kun-Yu Lin
Chuan-Ping Hou
Keng-Hong Lin
Po-Jen Shih
Hsien-Kuan Chen
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Taiwan Semiconductor Mfg
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    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/18—Electroplating using modulated, pulsed or reversing current
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/10—Electroplating with more than one layer of the same or of different metals
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/60—Electroplating characterised by the structure or texture of the layers
    • C25D5/615—Microstructure of the layers, e.g. mixed structure
    • C25D5/617—Crystalline layers
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    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
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    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H01L21/2885—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition using an external electrical current, i.e. electro-deposition
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32051—Deposition of metallic or metal-silicide layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
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    • H01L2924/01029—Copper [Cu]
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Abstract

A method for forming a metal layer having a predetermined thickness on an underlying material is disclosed. According to the method, the underlying material is electroplated to form the metal layer having a fraction of the predetermined thickness thereon. The step of electroplating is interrupted for a predetermined period of time. The step of electroplating is then resumed to form the metal layer having the predetermined thickness on the underlying material, thereby improving planarity of the metal layer.

Description

1260714 九、發明說明 【發明所屬之技術領域】 本發明係有關於— 種以複合步驟形成金屬 種半導體製程技術，特別是有 層之方法。 關於一 【先前技術】 半導體積體電路（ΙΓ、 、1Cs)有许夕圖案化金屬層之階層， 金屬層的不同階芦夕„π _ t ^ ㈢之間可猎由内連線結構來連接，例如介芦 嵌導電材料之交叉溝渠。形成金屬層之製程通常^ 二：化製程。銅因為其良好的導電性而通常被選擇為形 成金屬層的材料。 & 銅層通常是藉由電鍍製程來形成。薄的種晶層係沉積在 :詈二1如半導體基材或介電層。設置有種晶層之底材係 學電鍍液或化學反應室中。接著，此種晶層會在底 莫雷社$車又厚的銅| °然後’銅層被圖案化以形成想要的 等電結構。 jl：b« 田 * 常合1、、二應用上，需要一些非常厚的銅層，這些厚銅層通 二二埝，小凸起”（HU1〇Ck )的問題。在電鍍製程期間， 母曰顆曰曰粒皆朝著個別的結晶方向成長，當成長進行時，每 上成/真滿匕們之間的間隔空隙並且通常以相似的速度向 、長。然而，一些晶粒找到早先成核位置並且領先開始成 二阳粒沿著可引起較快成長速度之結晶方向來成 長，此種實晳μ > 、、上成長尚度鬲於其鄰近晶粒的晶粒被定義為 1260714 J凸起。當銅層的厚度增加，此“小凸起，，的問題會變得越 嚴重。當銅層的厚度小於13κ埃時，銅的晶粒大小相對較 小，不會對銅層造成嚴重的問題。然而，當銅層的厚度高於 4 〇 κ _ m可能會變成“小凸起’，且對銅層造成嚴重的 問題。 “小凸起，，會造成某些缺點，一個缺點是由於“小凸起” 的緣故’使得銅層表面有不均句的#刻速度，另—個缺點是 • φ f在積體電路封裝製程中使用銅層為結合塾時，“小凸起” 會增加凸塊製程失敗的可能性。 “目此’在半導體製程技術中，非常需要一種不會產生 小凸起’’問題的金屬層形成方法。 【發明内容】 本發明的目的係在於提供一種在底材上形成具有預設 厚度之金屬層的方法’藉以避免產生“小凸起”問題。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a metal semiconductor process in a composite step, particularly a layer. About a [previous technique] The semiconductor integrated circuit (ΙΓ, , 1Cs) has a layer of patterned metal layers, and the different layers of the metal layer can be connected by an interconnect structure. For example, a cross trench in which a conductive material is embedded is formed. The process of forming a metal layer is generally a process: copper is usually selected as a material for forming a metal layer because of its good electrical conductivity. & The copper layer is usually plated by plating. The process is formed. A thin seed layer is deposited on: a semiconductor substrate or a dielectric layer. The substrate is provided with a seed layer in a plating solution or a chemical reaction chamber. Then, the layer is At the end of the Morrow, the car is thick and thick copper | ° then the 'copper layer is patterned to form the desired isoelectric structure. jl:b« Tian* Changhe 1, and 2 applications, need some very thick copper Layer, these thick copper layers pass through the problem of two or two 埝, small bulges" (HU1〇Ck). During the electroplating process, the mother granules grow toward the individual crystallizing directions. When growing, the gap between each of the upper and the full slabs is usually and at a similar speed. However, some grains find the early nucleation sites and lead to the formation of two cations along the crystal direction that can cause faster growth. This kind of sharp μ > The grain is defined as 1260714 J bulge. When the thickness of the copper layer increases, the problem of this "small bump" becomes more serious. When the thickness of the copper layer is less than 13 kA, the grain size of copper is relatively small, which does not cause serious problems to the copper layer. However, when the thickness of the copper layer is higher than 4 〇κ _ m, it may become a "small bump" and cause serious problems to the copper layer. "Small bumps, will cause some shortcomings, one disadvantage is that because of the "small bumps", the surface of the copper layer has an uneven speed, and the other disadvantage is that • φ f is integrated in the circuit package. When the copper layer is used in the process, the "small bumps" increase the possibility of failure of the bump process. "In this way, in the semiconductor process technology, there is a great need for a metal layer that does not cause small bumps' problem. Forming method. SUMMARY OF THE INVENTION An object of the present invention is to provide a method of forming a metal layer having a predetermined thickness on a substrate to avoid the problem of "small bumps".

本&月《Λ知例中’首先，電鍍底材以在底材上形 成”有部份之預設厚度的金屬層。然後，中斷電鍍 ==接著’恢復電鑛步驟以在底材上形成具有預設厚 度的至屬層，藉以改善金屬層的平坦度。 可 ^發明的操作方法與結構，連同附加的目的與優點 曰1下之實施例的說明與相配合的圖式來了解。 【實施方式】 7 1260714 第1圖係繪示習知電鍍製程中形成有金屬層106之半導 "*、、籌 〇的剖面示意圖。半導體結構100包含底材1〇2， 底材102可為半導體基材或介電層。種晶層104係形成在底 材102上。在電鍍製程期間，底材102連同種晶層1〇4 一起 放置於化學電鍍液或化學反應室中。接著，種晶層1 04成長 為/、有某一厚度的金屬層106。如上所述，當金屬層106的 厚度足夠大時，複數個金屬晶粒108會實質地延伸超過金屬 層106的表面並且變成不想要的“小凸起，，，而造成一些問 題，例如金屬層1〇6的表面上有不均勻的蝕刻速度；以及當 在積體電路封裝製程中使用金屬層106為結合墊時，凸塊製 程失敗的可能性較高。 第2圖與第3圖係繪示根據本發明之一較佳實施例形成 具有較小晶粒尺寸之金屬層的流程示意圖。第2圖係繪示半 導體結構200之剖面示意圖。半導體結構2〇〇包含底材 2〇2,底材202可為半導體基材或介電層，種晶層2〇4係形 成在底材202上。在電鍍製程期間，底材2〇2連同種晶層 • 204 一起放置於化學電鍍液或化學反應室中。接著，種晶層 2〇4成長為金屬層206,在金屬層2〇6成長為其最大的預設 厚度之前，中斷電鍍製程一段預設時間。 在本實施例中，金屬層206係由銅所製成，然而其他的 導電材料，例如鋁、鈦、鈕、鈷、鎳與上述之合金，都可以 選擇為金屬層206的材料；中斷之預設時間可以是比一秒還 多的任何時間；預設厚度是金屬層206經過第2圖和第3 圖之製程步驟完成之後的最後厚度，金屬層206的厚度只有 1260714 、曰又的。卩知，例如··當預設厚度是40K埃時，金屬 ^#之厚度，、有預設厚度的5〇% ，換言之，金屬層206 田旱二為为20K埃，其對應於整個預設厚度來說相對較薄， 而i屬層206之晶粒2〇8不會變成使金屬層2〇6表面不平 坦的小凸起。 在電鍍製程中斷的期間，半導體結構2〇〇自化學電鍍液 或化：反應至中移出，晶粒208的連續成長就會中斷。 弟3圖係繪示用來解釋恢復電鍍製程步驟之半導體結 • ·構_的剖面示意圖。在電鍍製程中斷之後，半導體結構 (如弟2圖所示）再置入至化學電鍍液或化學反應室中。 然後’恢復電鍍製程’而藉由增加金屬層2()6，使金屬層2〇6 .進—步地成長為最大的預設厚度。在本實施例中，預設厚度 的粑圍係實質介於W 100K埃之間。由於電鍍製程中斷的 緣故，新的成核位置會產生出來。在大多數的狀況中，電錢 產生的新金屬晶粒並不會繼續沿著原本金屬晶纟簡之相 同的結晶方向或位置（如第2圖所示）。增加的金屬層2〇6, 灸φ /、有與原本成長之金屬層206不同的晶粒結構，當晶粒304 ,增加的金屬層206,不平坦時，並不會呈現“小凸起，，的問 題。同樣地，當稀疏的晶粒3〇6從金屬層2〇6持續的成長， 也不會呈現顯著之“小凸起，，的問題。如此，金屬層2〇6，之 表面的平坦度便可獲得改善。 本發明的優點是：原本成長之金屬層與增加之金屬層的 整體不規則的程度低於以習知單_電鍍步驟所形成之金屬 層。本發明之金屬層之全部預設厚度可劃分為超過兩層具有 9 1260714 ^份預設厚度的金屬層。中斷與恢復電鍍製程的步驟可重複 2多次以形&沒有產生“小凸起，，且具有t求厚度的金屬 因此，本發明有助於提供具有均勻蝕刻速度之金屬層的 二：’亦有助於當在積體電路封裝製程中使用金屬層為結合 B守’減少凸塊製程失敗的可能性。 徵，多不同的實施例來實施本發明的不同特 明，：：：：：之7"件與步驟的描述係用來幫助闡明本發 .......非用以限定本發明的申請專利範圍。 雖然本發明已以一或數個較佳實施例揭露如上，秋 非用以限定本發明，扁不酚魅士 Λ …、/、並 之均a 之精神和中請專利範圍 之々·#乾圍内，當可作各種的修正與改變， 申請專利範圍中所提到的部份， < 寸之 利範圍是適當的，以與本發明的/^廣地解釋附加之申請專 ，、个知明的乾圍一致相符。 【圖式簡單說明】 為讓本發明之上述和直他 易懂，下文特夹八 、、特徵、和優點能更明顯 明如下： 並配s所附圖式，作詳細說 第1圖係緣示習知電錢势 半導體結構的剖面示意圖；中產生小凸起之金屬層之 第2圖係繪示依據本發明 設厚复之部份的全屬M 1 較铨實施例之具有一預 I仂的至屬層之半導體結立 第3圖係繪示依據本發 /面不思圖，以及 預設厚度之金屬層 < 半導 ~較佳實施例之具有- 導體、％構的剖面示意圖。 10 1260714 【主要元件符號說明】 100 ： 半導體結構 102 ： 104 ： 種晶層 106 ： 108 ： 晶粒 200 ： 202 ： 底材 204 ： 206 ： 金屬層 206, 208 ·· 晶粒 300 ： 304 ： 晶粒 306 ： 底材 金屬層 半導體結構 種晶層 :金屬層 半導體結構 稀疏的晶粒In this & month, in the case of 'first, the substrate is plated to form a metal layer with a predetermined thickness on the substrate. Then, the plating is interrupted == then 'recover the electro-metal step on the substrate The singular layer having a predetermined thickness is formed to improve the flatness of the metal layer. The method and structure of the invention can be understood by the description of the embodiment and the accompanying drawings. [Embodiment] 7 1260714 Fig. 1 is a schematic cross-sectional view showing a semi-conducting "*" of a metal layer 106 formed in a conventional electroplating process. The semiconductor structure 100 comprises a substrate 1〇2, and the substrate 102 can be The semiconductor substrate or dielectric layer is formed on the substrate 102. During the electroplating process, the substrate 102 is placed in the electroless plating solution or chemical reaction chamber together with the seed layer 1〇4. The seed layer 104 is grown to a metal layer 106 having a certain thickness. As described above, when the thickness of the metal layer 106 is sufficiently large, the plurality of metal crystal grains 108 substantially extend beyond the surface of the metal layer 106 and become Unwanted "small bumps,,, and Some problems are caused, such as uneven etching speed on the surface of the metal layer 1 ; 6; and when the metal layer 106 is used as a bonding pad in the integrated circuit packaging process, the possibility of bump processing is high. 2 and 3 are schematic flow diagrams showing the formation of a metal layer having a smaller grain size in accordance with a preferred embodiment of the present invention. Figure 2 is a schematic cross-sectional view showing the semiconductor structure 200. The semiconductor structure 2 includes a substrate 2〇2, the substrate 202 may be a semiconductor substrate or a dielectric layer, and the seed layer 2〇4 is formed on the substrate 202. During the electroplating process, the substrate 2〇2 is placed together with the seed layer • 204 in an electroless plating bath or chemical reaction chamber. Next, the seed layer 2〇4 is grown into the metal layer 206, and the plating process is interrupted for a predetermined period of time before the metal layer 2〇6 is grown to its maximum predetermined thickness. In the present embodiment, the metal layer 206 is made of copper, but other conductive materials, such as aluminum, titanium, button, cobalt, nickel, and the alloys described above, may be selected as the material of the metal layer 206; The set time can be any time longer than one second; the predetermined thickness is the final thickness of the metal layer 206 after the process steps of FIGS. 2 and 3 are completed, and the thickness of the metal layer 206 is only 1260714, and the thickness is only 。. I know, for example, when the preset thickness is 40K angstroms, the thickness of the metal ^#, which has a preset thickness of 5〇%, in other words, the metal layer 206 is 2K angstroms, which corresponds to the entire preset. The thickness is relatively thin, and the crystal grains 2〇8 of the i-type layer 206 do not become small bumps which make the surface of the metal layer 2〇6 uneven. During the interruption of the electroplating process, the semiconductor structure 2 is removed from the electroless plating solution or the reaction: the reaction is transferred to the middle, and the continuous growth of the crystal grains 208 is interrupted. Figure 3 is a schematic cross-sectional view showing the semiconductor junction of the electroplating process. After the electroplating process is interrupted, the semiconductor structure (shown in Figure 2) is reinserted into the electroless plating bath or chemical reaction chamber. Then, 'recovering the plating process' and by increasing the metal layer 2 () 6, the metal layer 2〇6 is further grown to the maximum predetermined thickness. In this embodiment, the thickness of the predetermined thickness is substantially between W 100K angstroms. A new nucleation site will be created due to the interruption of the plating process. In most cases, the new metal grains produced by the electricity money will not continue along the same crystal orientation or position as the original metal crystals (as shown in Figure 2). The increased metal layer 2〇6, moxibustion φ / has a different grain structure than the originally grown metal layer 206. When the crystal grains 304 and the added metal layer 206 are not flat, they do not exhibit "small bumps. The problem. Similarly, when the sparse grains 3〇6 continue to grow from the metal layer 2〇6, there is no significant "small bump" problem. Thus, the flatness of the surface of the metal layer 2〇6 can be improved. An advantage of the present invention is that the overall irregularity of the otherwise grown metal layer and the added metal layer is lower than that of the metal layer formed by the conventional single-plating step. The entire predetermined thickness of the metal layer of the present invention can be divided into more than two layers of metal layers having a predetermined thickness of 9 1260714 parts. The step of interrupting and restoring the electroplating process can be repeated two times to form & no "small bumps, and having a thickness of t. Therefore, the present invention contributes to providing a metal layer having a uniform etching speed:" It also helps to reduce the possibility of failure of the bump process when the metal layer is used in the integrated circuit packaging process. The different embodiments are used to implement the different features of the present invention::::: The description of the components and the steps is used to help clarify the scope of the present invention. The invention has been disclosed in the above-mentioned, one or several preferred embodiments. It is not intended to limit the invention, the spirit of the flat phenolic Λ ..., /, and the spirit of the patent, and the scope of the patent application, within the scope of the patent, can be used for various amendments and changes, in the scope of patent application In the part mentioned, the range of < inch is appropriate, in accordance with the invention, and the additional application of the application, and the well-defined dry circumference are consistent. [Simplified description of the drawing] The above and straightforward, he is easy to understand, the following special clip eight, The features and advantages can be more clearly as follows: And with the s drawing, for details, the first figure shows the cross-sectional schematic diagram of the structure of the electric semiconductor structure; the second picture of the metal layer with small protrusions The third embodiment of the semiconductor group having a pre-I 铨 铨 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 依据 , , , , , , , , , , , , And a metal layer of a predetermined thickness < semi-conductive to a preferred embodiment having a cross-section of a conductor and a % structure. 10 1260714 [Explanation of main component symbols] 100 : Semiconductor structure 102 : 104 : seed layer 106 : 108 : Grain 200 : 202 : Substrate 204 : 206 : Metal layer 206 , 208 · · Grain 300 : 304 : Grain 306 : Substrate metal layer Semiconductor structure Seed layer : Metal layer semiconductor structure sparse grain

1111

Claims (1)

1260714 十、申請專利範圍 藉以在一底材上形成具有 金屬層的形成方法至少包 L —種金屬層的形成方法， 一預設厚度之該金屬層，其中爷 含： 、〜 電錢該底材，以在該麻从l ^ 1 底材上形成具有部份之該預設厚度 的該金屬層； 進行一中斷步驟，以中斷:兮1260714 X. The scope of the patent application is to form a method for forming a metal layer on a substrate, at least a method for forming a metal layer, a metal layer of a predetermined thickness, wherein the master contains: Forming the metal layer having the portion of the predetermined thickness on the substrate from the substrate; performing an interruption step to interrupt: T Wf邊電錢该底材的步驟一段預設 時間；以及 進行-恢復步驟’以恢復該電鍍該底材的步驟以在該底 材上形成具有該預設厚度之該金屬層，藉以改善該金屬層的 平坦度。 2.如申請專利範圍第i項所述之金屬層的形成方法， 其中該金屬層為一銅層。 3·如申請專利範圍第i項所述之金屬層的形成方法， 其中該段預設時間至少是一秒。 4.如申請專利範圍第1項所述之金屬層的形成方法， 其中該預設厚度係實質介於1與100K埃之間。 5·如申請專利範圍第1項所述之金屬層的形成方法， 其中該電鍍該底材的步驟更至少包含： 12 1260714 置亥底材於—化學溶液或一化學反應室中。 用專利範圍第5項所述之金屬層的形成方法， 其中該中斷步驟更至少包含： 自該化學溶液或該化學反應室中移出該底材。 如申請專利範圍帛1項所述之金屬層的形成方法， 其中該中斷步驟與該恢復步驟係依據該預設厚度而重複進 φ 行複數次。 8_ 一種金屬層的形成方法，藉以在-底材上形成具有 -預設厚度之該金屬層，其中該金屬層的形成方法至少包 含： 放置該底材於一化學溶液或一化學反應室中； 電鑛該底材，以在該底材上形成具有部份之該預設厚度 的該金屬層； 自該化學溶液或該化學反應室移出該底材—段預設時 間； 放置該底材於該化學溶液或該化學反應室中；以及 恢復該電鑛該底材的步驟，以在該底材上形成具有該預 設厚度之該金屬層，藉以改善該金屬層的平坦度。 9·如申請專利範圍第8項所述之金屬層的形成方法， 其中該金屬層為一銅層。 1260714 I 〇·如申請專利範圍第8項所述之金屬層的形成方法， 其中該預設時間至少是一秒。 II ·如申請專利範圍第8項所述之金屬層的形成方法， 其中該預設厚度係實質介於i與100K埃之間。 12·如申請專利範圍第8項所述之金屬層的形成方法， 其中該移出該底材的步驟、該放置該底材的步驟與該恢復該 電鑛該底材的步驟係依據該預設厚度而重複複數次。 13. —種銅層的形成方法，藉以在一底材上形成具有一 預設厚度之該銅層，其中該銅層的形成方法至少包含： 放置該底材於一化學溶液或一化學反應室中； 電鍍該底材，以在該底材上形成具有部份之該預設厚度 的該銅層； 自該化學溶液或該化學反應室移出該底材一段預設時 間， 放置該底材於該化學溶液或該化學反應室中；以及 恢復戎電鍍該底材的步驟，以在該底材上形成具有該預 設厚度之該銅層，藉以改善該銅層的平坦度。 14. 如申請專利範圍第13項所述之銅層的形成方法， 其中該預設時間至少是一秒。 14 1260714 1 5.如申請專利範圍第1 3項所述之銅層的形成方法， 其中該預設厚度係實質介於1與100K埃之間。 1 6.如申請專利範圍第1 3項所述之銅層的形成方法， 其中該移出該底材的步驟、該放置該底材的步驟與該恢復该 電鍍該底材的步驟係依據該預設厚度而重複複數次。 15TWf the step of charging the substrate for a predetermined period of time; and performing a recovery step to restore the step of plating the substrate to form the metal layer having the predetermined thickness on the substrate, thereby improving the The flatness of the metal layer. 2. The method of forming a metal layer according to claim i, wherein the metal layer is a copper layer. 3. The method of forming a metal layer as described in claim i, wherein the predetermined period of time is at least one second. 4. The method of forming a metal layer according to claim 1, wherein the predetermined thickness is substantially between 1 and 100 K angstroms. 5. The method for forming a metal layer according to claim 1, wherein the step of plating the substrate further comprises: 12 1260714 The substrate is in a chemical solution or a chemical reaction chamber. The method for forming a metal layer according to claim 5, wherein the interrupting step further comprises: removing the substrate from the chemical solution or the chemical reaction chamber. The method for forming a metal layer according to claim 1, wherein the interrupting step and the restoring step are repeated φ a plurality of times according to the predetermined thickness. 8_ a method for forming a metal layer, wherein the metal layer having a predetermined thickness is formed on the substrate, wherein the metal layer is formed by at least: placing the substrate in a chemical solution or a chemical reaction chamber; Electrolyzing the substrate to form a portion of the predetermined thickness of the metal layer on the substrate; removing the substrate from the chemical solution or the chemical reaction chamber for a predetermined period of time; placing the substrate at And the step of recovering the substrate from the chemical solution or the chemical reaction chamber to form the metal layer having the predetermined thickness on the substrate, thereby improving the flatness of the metal layer. 9. The method of forming a metal layer according to claim 8, wherein the metal layer is a copper layer. The method of forming a metal layer according to item 8 of the patent application, wherein the preset time is at least one second. The method of forming a metal layer according to claim 8, wherein the predetermined thickness is substantially between i and 100K angstroms. 12. The method of forming a metal layer according to claim 8, wherein the step of removing the substrate, the step of placing the substrate, and the step of restoring the substrate are based on the preset Repeat the thickness several times. 13. A method of forming a copper layer, wherein the copper layer having a predetermined thickness is formed on a substrate, wherein the copper layer is formed by at least: placing the substrate in a chemical solution or a chemical reaction chamber Etching the substrate to form a portion of the predetermined thickness of the copper layer on the substrate; removing the substrate from the chemical solution or the chemical reaction chamber for a predetermined period of time, placing the substrate on The chemical solution or the chemical reaction chamber; and the step of recovering the ruthenium plating the substrate to form the copper layer having the predetermined thickness on the substrate, thereby improving the flatness of the copper layer. 14. The method of forming a copper layer according to claim 13, wherein the preset time is at least one second. The method of forming a copper layer according to claim 13 wherein the predetermined thickness is substantially between 1 and 100 K angstroms. 1. The method for forming a copper layer according to claim 13 wherein the step of removing the substrate, the step of placing the substrate, and the step of restoring the substrate are based on the pre-processing Repeat the number of times by setting the thickness. 15
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