1260631 五、發明說明（1) -- 【發明所屬之技術領域】 本發明係有關一種記憶體陣列結構，特別是有關一種 大幅降低消耗功率之隨機存取記憶體陣列結構。 【先前技術】 按’記憶體係用以儲存資料或數據的半導體元件，而 吕己k體可分隨機存取記憶體（Rand〇m-Access Memory， RAM)及唯讀記憶體（Rea(j — 〇nly Memory，ROM)。R〇M 是唯讀 的，薇商於ROM上放了電腦開啟時所需的指令，是不能更 改的。電腦需要RAM來跑系統及應用程式，及儲存資料， 可讀寫，然電源關掉時内容即消失。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory array structure, and more particularly to a random access memory array structure which greatly reduces power consumption. [Prior Art] According to the 'memory system for storing data or data semiconductor components, and the Lü〇k body can be divided into random access memory (Rand〇m-Access Memory, RAM) and read-only memory (Rea (j - 〇nly Memory, ROM). R〇M is read-only. Weishang puts the instructions needed to turn on the computer on the ROM and cannot change it. The computer needs RAM to run the system and application, and store the data. Read and write, but the content disappears when the power is turned off.
▲知傳統靜態隨機存取記憶體（Static RAM)陣列結 構’如第一圖所示，其係由複數個儲存記憶胞丨〇以陣歹3 方式排列組合而成，且於同行或同列的記憶胞丨〇則利用 同的導線加以串接，其中連接橫列上的記憶胞丨〇之導線 之為字元線12 (word 1 ine，WL )，而上下縱行的導線男 與數據傳輸有關稱之為位元線1 4 ( b i t 1 i ne，BL )，接 f子元線1 2連接一電源端1 6，使此靜態隨機存取記情 貧料的儲存及讀取。然而，當電源端丨6通電時在整^ 路上有漏電流的情況發生，此漏電流使此電路形 産、、 向偏壓（self-reverse biasing)的產生，、生 我 恶功率上非常多損耗，對於此缺點業界接屮 :月茶考弟二圖所示，此改良式靜態隨機存取記 在 源端1 6與記憶胞1 〇之間增加一電源閘j 8，心-糸在 达匕電源閘1 8係▲ Know the traditional static random access memory (Static RAM) array structure' as shown in the first figure, which is composed of a plurality of memory cells and arranged in a matrix of 3, and in the same or the same column of memory The cytoplasm is connected in series by the same wire, wherein the wire connecting the memory cells on the row is the word line 12 (word 1 ine, WL ), and the wire man in the upper and lower lining is related to the data transmission. The bit line 1 4 (bit 1 i ne, BL ) is connected to the f sub-line 1 2 and connected to a power terminal 16 to store and read the static random access memory. However, when the power supply terminal 通电6 is energized, there is a leakage current on the whole circuit. This leakage current causes the circuit to generate, self-reverse biasing, and a lot of power. Loss, for this shortcoming industry, as shown in the second picture of the monthly tea tester, this improved static random access memory adds a power gate j 8 between the source end 16 and the memory cell 1匕Power Gate 1 8 Series
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二極體連接式N型金氧半導髀 transistor)，雖然此故 ^體（Dl〇de—connected NM0S 壓的產生，請同時參閱\可以降低漏電流及自我反向偏 降至Vssl ，然而此改盖回所不，圖中功率損耗由VssO 率上的損耗VSS1，所二:式仍多少會造成了電路在動態功 對隨機存取記憶體的岑^，更降低漏電流及自我反向偏壓 亟需解決的困擾。心9糸刻不容緩的，也是目前業界所 有鑑於此，本發明 降低消耗功率之隨 产j之問題，提出一種大幅 予取A彳思體陣列結構。 【發明内容】 本發明之主要目 ^ 列結構，藉由將記糖咕係在提供一種隨機存取記憶體陣 資區塊分別有一專^雷、、列結構分為複數資料區塊且每一 存取的資料區塊電源。，源閘’使進行存取動作時只供給被 本發明之再_〜 用以大幅降低動態功率之消耗。 列結構，藉由在每二t二係在提供—種隨機存取記憶體陣 減少漏電流的產生。貝料區塊設置一專屬電源閘，使電路 根據本發明，_ 用一編碼裝置使一 機存取記憶體陣列結構，其係利 存取記憶體陣列結貧，進行儲存或讀取動作，此隨機 而成，接著將每一次祖由複數資料區塊以陣列之方式組合 塊與及閘之間串接二=塊連接-及，且在每一資料區 . 叹 电源閘。 底下藉由具髀每#/ 貝也列配合所附的圖式詳加說明，當更 1260631 五、發明說明（3) " 容易暸解本發明之目的、技術内容、特點及其所達成之功 效。 [實施方式】 本發明係一種隨機存取記憶體陣列結構，請參閱第四 圖所示，此隨機存取記憶體陣列結構係由複數資料區塊2 〇 以陣列之方式組合而成，每一資料區塊2〇包括二字元線22 及複數位元線24，此字元線22係連接橫列上的複數記憶胞 26，而位元線24則是縱向連接此記憶胞26，每一記憶 内設有複數電晶體2 8，每一電晶體2 8的源極係電連接至相 對的字元線22，而閘極及汲極則共同串接至相對之位元線 24並形連電連接。接著將每一資料區塊2〇分別連接一及閑 30，且在每一資料區塊20與及閘30(AND gate)之間設有一 電源閘3 2 ’此電源閘3 2係為一極體連接式N型金氧半導體 (Diode-connected NMOS transistor)。另外此隨機存取 記憶體陣列結構設有一編碼裝置，此編碼裝置包含一橫列 編碼器34及一縱行編碼器36。此外此隨機存取記憶體陣列 結構設有複數接腳38，用以插設在電腦主機板上接收資料 及電力，且此記憶體陣列結構記憶容量在不變情況下，、接 腳38數量係與每一資料區塊2〇的記憶容量成反比，也就是 接腳38數愈多，則每一資料區塊2〇的記憶容量愈小。 本創作使用時’將此隨機存取記憶體陣列結構插設在 電腦主機板上，藉由複數接腳將一數據資料接收，接收後 利用橫列編碼器34及一縱行編碼器36將此數據資料轉換， 接著此編碼裝置會選擇一資料區塊2〇將此數據資料存取，Diode-connected N-type MOS transistor, although this is the result of Dl〇de-connected NM0S voltage, please refer to \ can reduce leakage current and self-reverse bias to Vssl, however Replacing the cover back, the power loss in the figure is due to the loss of VSS1 at the VssO rate. The second: the type still causes the circuit to dynamically work on the random access memory, reducing the leakage current and self-reverse bias. It is urgent to solve the problem. It is also a matter of the current industry. In view of the above, the present invention reduces the power consumption of the production j, and proposes a large-scale pre-emptive array structure. The main purpose of the column structure is to provide a random access memory array by providing a random access memory, and the column structure is divided into a plurality of data blocks and each accessed data block. The power supply. The source gate' is only supplied to the re- _~ of the present invention for the purpose of greatly reducing the consumption of dynamic power. The column structure is provided by providing a random access memory in every two lines. Array to reduce leakage current The bead block is provided with a dedicated power gate, so that the circuit according to the present invention _ uses an encoding device to enable a machine to access the memory array structure, and the access memory array is depleted for storage or reading operations. This is randomly formed, and then each ancestor is composed of a plurality of data blocks in an array and a parallel connection between the block and the gate is connected to the block = and, in each data area, the power gate is sighed.髀######################################################################################################## The present invention is a random access memory array structure, as shown in the fourth figure, the random access memory array structure is composed of a plurality of data blocks 2 〇 in an array, each data block 2〇 includes a two-character line 22 and a plurality of bit lines 24, the word line 22 is connected to the plurality of memory cells 26 on the horizontal row, and the bit line 24 is connected longitudinally to the memory cell 26, and each memory is provided There are multiple transistors 2 8, each transistor 2 The source of 8 is electrically connected to the opposite word line 22, and the gate and the drain are connected in series to the opposite bit line 24 and are electrically connected. Then, each data block 2 is connected to one. And idle 30, and between each data block 20 and the AND gate 30 is provided with a power gate 3 2 'This power gate 3 2 is a pole-connected N-type metal oxide semiconductor (Diode-connected In addition, the random access memory array structure is provided with an encoding device, and the encoding device includes a horizontal encoder 34 and a vertical encoder 36. The random access memory array structure is provided with a plurality of pins. 38. For inserting data and power on the computer motherboard, and the memory capacity of the memory array structure is constant, the number of pins 38 is inversely proportional to the memory capacity of each data block. That is, the more the number of pins 38, the smaller the memory capacity of each data block. When the present invention is used, the random access memory array structure is inserted on a computer motherboard, and a data data is received by a plurality of pins. After receiving, the horizontal encoder 34 and a vertical encoder 36 are used for receiving. Data data conversion, and then the encoding device selects a data block 2 to access the data data.
1260631 五、發明說明（4)1260631 V. Description of invention (4)
其中此數據資料存取時，被選擇之資料區塊2〇的及閘會 將其所對應連接之電源閘32開啟，其餘在此隨機存取呓; 體陣列結構中未選擇之資料區塊2〇所對應之該電源間32則 係呈現關閉狀態。如此只有被選擇之資料區塊2〇產生極少 許漏電流，使此隨機存取記憶體陣列結構在動態功率消耗 上大幅降低，，請同時參閱第五圖所示，圖中本發明所消耗 的功率比先前的傳統技術下降88%及改良技術下降77%。另 外在此隨機存取記憶體陣列結構，除了一資料區塊2 〇設置 一電源閘32，也可依讀取或儲存需求改成複數資料區塊2〇 共同使用一電源閘2 0，如此可使此記憶體陣列結構的設計 更多兀化，使此隨機存取記憶體陣列結構可應用於動態隨 機存取記憶體（Dynamic Rand〇m Access Mem〇ry，DRAM)、 靜態隨機存取記憶體（Static Rand()m Aecess MemQFy， SRAM)、快閃記憶體（fiash mem〇ry)及快取記憶體㈧“以） 之中。 故，本創作藉由將此記憶體陣列結構分為複數資料區 塊20且每一資區塊20分別有一電源閘32，使進行存取動作 時只供給被存取的資料區塊2〇電源，使電路減少漏電流的 產生，進而大幅降低動態功率之消耗。 以上所述係藉由實施例說明本發明之特點，其目的在 使熟習该技術者旎暸解本發明之内容並據以實施，而非限 定本發明之專利範圍，故，凡其他未脫離本發明所揭示之 精神所完成之等效修飾或修改，仍應包含在以下所述之申 請專利範圍中。When the data data is accessed, the selected data block 2〇 and the gate will open the power gate 32 of the corresponding connection, and the rest is randomly accessed; the data block not selected in the body array structure 2 The power supply room 32 corresponding to the 呈现 is in a closed state. Therefore, only the selected data block 2〇 generates a very small leakage current, so that the random access memory array structure is greatly reduced in dynamic power consumption, please refer to the fifth figure, which is consumed by the present invention. The power is 88% lower than the previous conventional technology and the improved technology is 77% lower. In addition, in this random access memory array structure, in addition to a data block 2, a power gate 32 is provided, and a plurality of power blocks 2 can be changed according to reading or storage requirements, and a power gate 20 is commonly used. The design of the memory array structure is further reduced, so that the random access memory array structure can be applied to dynamic random access memory (DRAM), static random access memory. (Static Rand()m Aecess MemQFy, SRAM), flash memory (fiash mem〇ry), and cache memory (8) "I". Therefore, this creation is divided into multiple data by this memory array structure. The block 20 and each of the resource blocks 20 respectively have a power gate 32, so that only the accessed data block 2 〇 power is supplied during the access operation, so that the circuit reduces the leakage current, thereby greatly reducing the dynamic power consumption. The above description of the present invention is intended to be illustrative of the nature of the invention, and is intended to be invention Equivalent modifications or modifications made by the disclosed spirits should still be included in the scope of the claims described below.
第8頁 1260631 圖式簡單說明 【圖式簡單說明】 第一圖為先前技術之傳統式靜態隨機存取記憶體電路示意 圖。 第二圖為先前技術之改良式靜態隨機存取記憶體電路示意 第三圖為先前技術消耗電壓與時間之關係圖。 第四圖為本發明之隨機存取記憶體電路示意圖。 第五圖為本發明與先前技術所消耗動態功率之關係圖。 【主要元件符號說明】 10 記 憶 胞 12 字 元 線 14 位 元 線 16 電 源 端 18 電 源 閘 20 資 料 區 塊 22 字 元 線 24 位 元 線 26 記 憶 胞 28 電 晶 體 30 及 閘 32 電 源 閘 34 橫 列 編碼！§' 36 縱 行 編 碼器 38 接 腳Page 8 1260631 Schematic description of the drawing [Simple description of the diagram] The first figure is a schematic diagram of the conventional SRAM circuit of the prior art. The second figure is a schematic diagram of the improved static random access memory circuit of the prior art. The third figure is a graph of the prior art consumption voltage versus time. The fourth figure is a schematic diagram of a random access memory circuit of the present invention. The fifth graph is a graph of the dynamic power consumed by the present invention and prior art. [Main component symbol description] 10 Memory cell 12 word line 14 bit line 16 Power terminal 18 Power gate 20 Data block 22 Character line 24 bit line 26 Memory cell 28 Crystal 30 and gate 32 Power gate 34 course coding! §' 36 vertical encoder 38 pin
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