1259565 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種晶圓級晶片尺寸封裝結構（wafer level chip scale package，WLCSP)結構與其方法，尤指一種 利用堆疊晶圓方式達到系統封裝（system in package，SIP)之 晶圓級晶片尺寸封裝結構。 【先前技術】 在電子產品朝向功能強大的發展趨勢下，晶片的複雜度 曰益增加，甚至為了達到多功能的需求，電子產品往往需 要數個分別執行不同功能的晶片相互連接方能發揮完整功 能。而另一方面，對於輕薄短小的電子產品的需求帶動下， 微型化的封裝技術已是不可獲缺。目前晶圓級晶片尺寸封 籲 裝(wafer level chip scale package，WLCSP)已成為目前封裝 技術的主流’其中晶圓級晶片尺寸封裝的定義為封裝結構 之面積與裸晶（die)之面積相近或稍大於裸晶之面積（最多 約大於裸晶之面積百分之二十左右）。晶圓級晶片尺寸封裝 技術與傳統球閘陣列封裝（BGA)技術最大不同之處在於， 晶圓級晶片尺寸封裝技術係為進行切割製程之前直接對晶 圓進行封裝’並待晶圓封裝完畢後再進行切割製程以形成 1259565 封裝結構，而傳統封裝技術係切晶圓進行切割製程以形 成裸晶’再分別對裸晶進行封裝。 近年來’電子產品的電路設計日益複雜，且具有多功能 之微型電子產品的需求亦成為市場新寵，因此電子產品之 電路往往必須削複數個晶片之_連接所組成，若利用 傳統封裝技術進行封裝，必須待各別晶片封裝之後，再加 以連接以形成一完整電路，如此一來將大幅增加電子產品 之體積而無法滿足微型化之要求，有鑑於此，申請人提出 一種依據從事封裝多年經驗，提出一種晶圓級晶片尺寸之 系統封裝結構及其方法，利用堆疊晶圓方式於進行切割製 程前預先連接各晶圓内部之元件，隨後再進行切割製程以 形成封裝結構，藉此縮小封裝結構之尺寸、減小材料成本 與製程時間，並使封裂結構具有後續組裝之相容性。 【發明内容】 據此，本發明之主要目的在於提供一種晶圓級晶片尺寸 之系統封裝結構及其方法，以以縮小封裝結構之尺寸並使 封裝結構具有後續組裝之相容性。 6 1259565 根據本發明之申請專利範圍，係提供一種晶圓級晶片尺 寸封裝之方法。上述方法包含有進行下列步驟： 提供一第一晶圓，該第一晶圓包含一第一電路佈局設於 該第一晶圓内，以及複數個第一連接墊設於該第一 晶圓之一上表面，並與該第一電路佈局電連接； 提供一第二晶圓，該第二晶圓包含一第二電路佈局設於 該第二晶圓内，以及複數個第二連接墊設於該第二 • 晶圓之一下表面，並與該第二電路佈局電連接； 接合該第一晶圓之一下表面與該第二晶圓之一上表面； 由該第一晶圓之該上表面形成複數個孔洞，該等孔洞深 入该弟—晶5]，以及 於各該孔洞中形成一導電連接（conductive connection)， 該等導電連接同時與該第一電路佈局與該第二電 路佈局連接藉此該第一電路佈局與該第二電路佈 _ 局得以互相電連接。 根據本發明之申請專利範圍，同時提供一種晶圓級晶片 尺寸封裝結構。上述晶圓級晶片尺寸封裝結構至少包含： 一第一晶圓，該第一晶圓包含複數個第一電路佈局設於 該第一晶圓内，以及複數個第一連接墊設於該第一 晶圓之一上表面，並與該第一電路佈局電連接； 1259565 一第二晶圓，該第二晶圓之一上表面係接合於該第一晶 圓之一下表面，且該第二晶圓包含一第二電路佈局 設於該第二晶圓内，以及複數個第二連接墊設於該 第二晶圓之一下表面，並與該第二電路佈局電連 接；以及 複數個導電連接，自該第一晶圓之該上表面深入該第二 晶圓，該等導電連接同時與該第一電路佈局與該第 • 二電路佈局接觸，藉此該第一電路佈局與該第二電 路佈局得以互相電連接。 本發明之封裝結構不僅具有晶圓級晶片尺寸，同時利用 堆疊晶圓的作法更可達到系統封裝之功能，進而達到縮小 封裝結構體積、減少材料成本與提升後續組裝之相容性等 優點。 參 為讓本發明之上述目的、特徵、和優點能更明顯易懂， 下文特舉一較佳實施方式，並配合所附圖式，作詳細說明 如下。然而如下之較佳實施方式與圖式僅供參考與說明 用，並非用來對本發明加以限制者。 1259565 【實施方式】 請參考第1圖至第9圖。第1圖至第9圖為本發明之一 較佳實施例一種晶圓級晶片尺寸封裝之方法示意圖。如第 1圖所示，首先提供一第一晶圓10。第一晶圓10包含有一 第一電路佈局12、複數個第一連接墊（圖未示）電連接第一 電路佈局12，以及複數個第一重配置導電圖案14設於第 一晶圓10之上表面並與第一連接墊電連接。如第2圖所 • 示，接著提供一第二晶圓20。第二晶圓包含有一第二電路 佈局22、複數個第二連接墊（圖未示）電連接第二電路佈局 22，以及複數個第二重配置導電圖案24設於第二晶圓20 之下表面。其中，重配置導電圖案之作用在於將連接墊之 位置重新配置於晶圓表面適當之處，同時藉由後續形成之 凸塊下金屬層（under bump metallurgy layer，UBM layer)與 銲球等使晶圓對外作進一步連接，因此本發明之第一晶圓 • 10與第二晶圓20不限定於利用第一重配置導電圖案14與 第二重配置導電圖案24之設計，而可視電路佈局設計不同 而直接利用焊墊作法進行。隨後，利用一接合層30接合第 一晶圓10之下表面與第二晶圓20之上表面，其中第一晶 圓10之第一電路佈局12與第二晶圓20之第二電路佈局 22之位置於製作時即經精密設計，同時於接合第一晶圓10 與第二晶圓20時並利用對準記號(alignment mark)使第一 1259565 電路佈局12與第二電路佈局22精確對準。 如第3圖所示，接著由第一晶圓10之上表面形成複數 個深入第二晶圓20内之孔洞32。孔洞32之目的係用於製 作導電連接，以使第一電路佈局12與第二電路佈局22得 以互相電連接，而孔洞之深度可視電路設計與連接方式加 以調整，必要時可貫穿第二晶圓20。另外，孔洞32之形 • 成方式則可視效果採用雷射鑽孔或蝕刻等技術。如第4圖 所示，於孔洞32中形成導電連接34，以電連接第一電路 佈局12與第二電路佈局22。其中於本實施例中，導電連 接34係利用形成接觸插塞的方式來達到電連接第一電路 佈局12與第二電路佈局22，但本發明之導電連接34並不 侷限於此，導電連接34亦可為其他有效之電連接方式。 • 如第5圖所示，接著於第一晶圓10之第一重配置導電 圖案14表面形成錫球36，並於第二晶圓20之第二重配置 導電圖案24表面形成錫球38，以使第一晶圓10與第二晶 圓20對外作進一步之連接。如第6圖所示，於第一晶圓 10之上表面形成一助焊層40。如第7圖所示，提供一第三 晶圓50。第三晶圓50包含有一第三電路佈局52，以及複 數個與第三電路佈局52電連接之第三連接墊54。隨後於 10 1259565 第三連接墊54之表面形成複數個錫球56，並利用錫球56 與錫球36銲接第三晶圓50與第一晶圓10。其中第三晶圓 50與第一晶圓10之連接方式不限於透過第三連接墊54, 亦可端視需要利用重配置導電圖案等設計加以連接。 如第8圖所示，進行一迴銲製程，使第三晶圓50與第 一晶圓10緊密接合，如此一來，第三晶圓50即與第一晶 • 圓10與第二晶圓20電連接，使得第三電路佈局52與第一 電路佈局12與第二電路佈局22形成一完整之電路系統。 最後如第9圖所示，清除助銲層40，即製作出本發明之晶 圓級晶片尺寸封裝結構。另外，第二晶圓20之錫球38則 係用以連接印刷電路板（圖未示）或封裝基板（圖未示）等。 由上述可知，利用本發明晶圓級晶片尺寸封裝結構及其 • 方法，於進行切割製程前即利用堆疊晶圓方式，並透過導 電連接（例如利用接觸插塞）連接各晶圓内之電路佈局，如 此一來不僅可達到晶圓級晶片尺寸封裝之規格要求，同時 透過堆疊晶圓的方式更可達到系統封裝之優點，進而節省 材料成本並大幅縮小電子產品之體積。另外，本發明晶圓 級晶片尺寸封裝結構及其方法的主要特徵在於利用導電連 接連接位於不同晶圓内之電路佈局，至於與其他晶圓或印 1259565 刷電路板之連接方式則不限於利用錫球，亦可利用其他如 銲料凸塊（solder bump)或錫膏（solder paste)等方式加以連 接0 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖至第9圖為本發明之一較佳實施例一種晶圓級晶片 尺寸封裝之方法示意圖。 【主要元件符號說明】 10 第一晶圓 14 第一重配置導電圖案 22 第二電路佈局 30 接合層 34 導電連接 38 錫球 50 第三晶圓 54 第三連接墊 12 第一電路佈局 20 弟二晶圓 24 第二重配置導電圖案 32 孔洞 36 錫球 40 助焊層 52 第三電路佈局 56 錫球1259565 IX. Description of the Invention: [Technical Field] The present invention relates to a wafer level chip scale package (WLCSP) structure and a method thereof, and more particularly to a system package by using a stacked wafer method ( System in package, SIP) wafer level wafer size package structure. [Prior Art] Under the trend of powerful electronic products, the complexity of the wafers has increased, and even in order to meet the needs of multi-functionality, electronic products often require several wafers that perform different functions to be connected to each other to fully function. . On the other hand, miniaturized packaging technology is indispensable for the demand for thin, light and small electronic products. At present, the wafer level chip scale package (WLCSP) has become the mainstream of current packaging technology. The wafer level wafer size package is defined as the area of the package structure is similar to the area of the die or Slightly larger than the area of the bare crystal (up to about 20% larger than the area of the bare crystal). Wafer-level wafer-scale packaging technology differs from traditional ball-grid array package (BGA) technology in that wafer-level wafer-scale packaging technology directly encapsulates the wafer before the cutting process is completed. The dicing process is then performed to form a 1265956 package structure, while the conventional packaging technique is to diced the wafer to perform a dicing process to form a bare crystal, and then separately package the bare crystal. In recent years, the circuit design of electronic products has become increasingly complex, and the demand for multifunctional electronic products has become the new darling of the market. Therefore, the circuit of electronic products often has to be formed by the combination of several wafers, if it is packaged by traditional packaging technology. After the individual chips are packaged, they are connected to form a complete circuit, which will greatly increase the volume of the electronic products and cannot meet the requirements of miniaturization. In view of this, the applicant has proposed a basis for years of experience in packaging. A system package structure and a method for wafer-level wafer size are proposed. The stacked wafers are used to pre-connect components inside each wafer before the cutting process, and then a dicing process is performed to form a package structure, thereby reducing the package structure. Size, material cost and process time are reduced, and the fracture structure is compatible with subsequent assembly. SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a system package structure and method for wafer level wafer size to reduce the size of the package structure and to provide subsequent assembly compatibility with the package structure. 6 1259565 A method of wafer level wafer size packaging is provided in accordance with the scope of the invention. The method includes the following steps: providing a first wafer, the first wafer includes a first circuit layout disposed in the first wafer, and a plurality of first connection pads disposed on the first wafer An upper surface electrically connected to the first circuit layout; providing a second wafer, the second wafer including a second circuit layout disposed in the second wafer, and a plurality of second connection pads disposed on a lower surface of the second wafer and electrically connected to the second circuit layout; bonding a lower surface of the first wafer to an upper surface of the second wafer; and the upper surface of the first wafer Forming a plurality of holes that penetrate the ridge 5] and forming a conductive connection in each of the holes, the conductive connections being simultaneously connected to the first circuit layout and the second circuit layout The first circuit layout and the second circuit board are electrically connected to each other. In accordance with the scope of the present invention, a wafer level wafer size package structure is also provided. The wafer level wafer size package structure includes: a first wafer, the first wafer includes a plurality of first circuit layouts disposed in the first wafer, and a plurality of first connection pads are disposed on the first An upper surface of the wafer and electrically connected to the first circuit layout; 1259565 a second wafer, an upper surface of the second wafer is bonded to a lower surface of the first wafer, and the second crystal The circle includes a second circuit layout disposed in the second wafer, and a plurality of second connection pads are disposed on a lower surface of the second wafer and electrically connected to the second circuit layout; and a plurality of conductive connections, The first surface of the first wafer penetrates the second wafer, and the conductive connections are simultaneously in contact with the second circuit layout and the second circuit layout, whereby the first circuit layout and the second circuit layout They are electrically connected to each other. The package structure of the present invention not only has a wafer-level wafer size, but also utilizes the method of stacking wafers to achieve the function of the system package, thereby achieving the advantages of reducing the package structure volume, reducing the material cost, and improving the compatibility of subsequent assembly. The above described objects, features, and advantages of the present invention will become more apparent from the description of the appended claims. However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the invention. 1259565 [Embodiment] Please refer to Figures 1 to 9. 1 to 9 are schematic views showing a method of wafer level wafer size packaging according to a preferred embodiment of the present invention. As shown in Fig. 1, a first wafer 10 is first provided. The first wafer 10 includes a first circuit layout 12, a plurality of first connection pads (not shown) electrically connected to the first circuit layout 12, and a plurality of first relocation conductive patterns 14 disposed on the first wafer 10. The upper surface is electrically connected to the first connection pad. As shown in Fig. 2, a second wafer 20 is then provided. The second wafer includes a second circuit layout 22, a plurality of second connection pads (not shown) electrically connected to the second circuit layout 22, and a plurality of second relocation conductive patterns 24 disposed under the second wafer 20. surface. Wherein, the function of reconfiguring the conductive pattern is to reposition the position of the connection pad on the surface of the wafer, and at the same time, the crystal is formed by a subsequently formed under bump metallurgy layer (UBM layer) and a solder ball. The circle is further connected to the outside, so the first wafer 10 and the second wafer 20 of the present invention are not limited to the design using the first reconfigurable conductive pattern 14 and the second reconfigurable conductive pattern 24, and the visual circuit layout design is different. Directly using the solder pad method. Subsequently, the lower surface of the first wafer 10 and the upper surface of the second wafer 20 are bonded by a bonding layer 30, wherein the first circuit layout 12 of the first wafer 10 and the second circuit layout 22 of the second wafer 20 The position is precisely designed at the time of fabrication, and the first 1256956 circuit layout 12 and the second circuit layout 22 are precisely aligned when the first wafer 10 and the second wafer 20 are bonded and aligned by an alignment mark. . As shown in Fig. 3, a plurality of holes 32 deep into the second wafer 20 are then formed from the upper surface of the first wafer 10. The purpose of the hole 32 is to make a conductive connection so that the first circuit layout 12 and the second circuit layout 22 are electrically connected to each other, and the depth of the hole can be adjusted according to the circuit design and connection mode, and if necessary, can penetrate the second wafer. 20. In addition, the shape of the hole 32 is formed by means of laser drilling or etching. As shown in FIG. 4, a conductive connection 34 is formed in the hole 32 to electrically connect the first circuit layout 12 with the second circuit layout 22. In this embodiment, the conductive connection 34 is electrically connected to the first circuit layout 12 and the second circuit layout 22 by forming a contact plug. However, the conductive connection 34 of the present invention is not limited thereto, and the conductive connection 34 is not limited thereto. It can also be other effective electrical connections. As shown in FIG. 5, a solder ball 36 is formed on the surface of the first relocation conductive pattern 14 of the first wafer 10, and a solder ball 38 is formed on the surface of the second relocation conductive pattern 24 of the second wafer 20, The first wafer 10 and the second wafer 20 are further connected to each other. As shown in Fig. 6, a solder layer 40 is formed on the upper surface of the first wafer 10. As shown in Fig. 7, a third wafer 50 is provided. The third wafer 50 includes a third circuit layout 52 and a plurality of third connection pads 54 electrically coupled to the third circuit layout 52. Then, a plurality of solder balls 56 are formed on the surface of the third connection pad 54 at 10 1259565, and the third wafer 50 and the first wafer 10 are soldered by the solder balls 56 and the solder balls 36. The manner in which the third wafer 50 is connected to the first wafer 10 is not limited to being transmitted through the third connection pad 54 or may be connected by design such as a reconfigurable conductive pattern. As shown in FIG. 8, a reflow process is performed to tightly bond the third wafer 50 with the first wafer 10, so that the third wafer 50 and the first wafer 10 and the second wafer are The electrical connections are such that the third circuit layout 52 forms a complete circuit system with the first circuit layout 12 and the second circuit layout 22. Finally, as shown in Fig. 9, the solder layer 40 is removed, i.e., the wafer-level package structure of the present invention is fabricated. In addition, the solder balls 38 of the second wafer 20 are used to connect a printed circuit board (not shown) or a package substrate (not shown). It can be seen from the above that, by using the wafer level wafer size package structure and the method of the present invention, the stacked wafer method is used before the cutting process, and the circuit layout in each wafer is connected through a conductive connection (for example, by using a contact plug). In this way, not only the specification of the wafer level wafer size package can be achieved, but also the advantages of the system package can be achieved by stacking the wafers, thereby saving material cost and greatly reducing the volume of the electronic product. In addition, the main feature of the wafer level wafer size package structure and method of the present invention is that the circuit layouts located in different wafers are connected by using conductive connections, and the connection with other wafers or printed 1259565 brush boards is not limited to using tin. The ball may also be connected by other means such as solder bump or solder paste. The above is only a preferred embodiment of the present invention, and the equivalent of the scope of the patent application of the present invention Variations and modifications are intended to be within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 through 9 are schematic views showing a method of wafer level wafer size packaging according to a preferred embodiment of the present invention. [Main component symbol description] 10 First wafer 14 First relocation conductive pattern 22 Second circuit layout 30 Bonding layer 34 Conductive connection 38 Tin ball 50 Third wafer 54 Third connection pad 12 First circuit layout 20 Wafer 24 Second Relocation Conductive Pattern 32 Hole 36 Tin Ball 40 Solder Layer 52 Third Circuit Layout 56 Tin Ball
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