TWI257701B

TWI257701B - Method for fabricating a vertical bipolar junction transistor

Info

Publication number: TWI257701B
Application number: TW92132904A
Authority: TW
Inventors: Jing-Horng Gau; Anchor Chen
Original assignee: United Microelectronics Corp
Priority date: 2003-11-24
Filing date: 2003-11-24
Publication date: 2006-07-01
Also published as: TW200518342A

Abstract

A semiconductor wafer includes a first doping region of a first conductivity type, a second doping region of a second conductivity type, and a plurality of isolated structures positioned on surfaces of the first doping region and the second doping region. A third doping region of the first conductivity type is formed at an upper portion of the second doping region. A shielding layer is formed on the semiconductor wafer. A portion of the shielding layer is then removed to form an opening within the shielding layer to expose a portion of the third doping region. Subsequently, a doping layer of the second conductivity type is formed on a surface of the third doping region. A self-aligned silicidation process is performed to form a silicide layer on the surfaces of the second doping region, the third doping region and the doping layer, the silicide layer functioning as a contact region of a vertical bipolar junction transistor.

Description

12577011257701

五、發明說明（1) 【技術領域】本發明係關於一種製造垂直式（vertical)雙載子電晶體 (bipolar junction transistor，BJT)的方法，特別係才匕一種利用自我對準金屬矽化製程（self — al igne(i ''曰 silicidation， salicide)，以形成垂直式雙載子雷曰* 之接觸區的方法。阳體【先前技術】V. INSTRUCTION DESCRIPTION (1) [Technical Field] The present invention relates to a method for manufacturing a vertical bipolar junction transistor (BJT), in particular, a self-aligned metal deuteration process ( Self — al igne(i ''曰silicidation, salicide), a method of forming a contact zone of a vertical two-carrier Thunder*.

雙載子電晶體為半導體之重要元件，其主要分為侧向式 (lateral )與垂直式兩種型式。側向式雙載子電晶體的流流動方向為平行電晶體的表面，而垂直式雙載子的電流流動方向則垂直電晶體的表面。 M 請參照第一圖，第一圖係為習知垂直式雙載子電晶體的面圖。依此圖為例，習知之PNp垂直式雙載子電晶體係設置於一半導體晶片！〇〇，且半導體晶片i 〇〇包含有一 p型半導體基板11〇，一顧摻雜層113設於p型半導方，一用來作為雙載子電晶體集極區之？型蟲晶 0上 (epi taxial )層1 15設於N型摻雜層n3與半導體基板n 〇上方，以及至少一 N型槽（“η1〇116設於p型磊晶層lis中。N 型槽116係由Ρ型磊晶層U5表面延伸至難摻雜層ιΐ3表面，以於Ρ型磊晶層U5中定義出一 Ρ型井（well )1 17,並隔The bipolar transistor is an important component of the semiconductor, and it is mainly divided into two types: lateral and vertical. The flow direction of the lateral bipolar transistor is parallel to the surface of the transistor, while the current flow direction of the vertical bimodal is perpendicular to the surface of the transistor. M Please refer to the first figure, which is a plan view of a conventional vertical type bipolar transistor. Taking this figure as an example, the conventional PNp vertical dual-carrier electro-crystal system is placed on a semiconductor wafer!半导体〇, and the semiconductor wafer i 〇〇 includes a p-type semiconductor substrate 11 〇, a doped layer 113 is provided on the p-type semi-conductor, and one is used as a bi-carrier transistor collector region? An epitaxal layer 1 15 is disposed over the N-type doped layer n3 and the semiconductor substrate n ,, and at least one N-type groove ("η1 〇 116 is disposed in the p-type epitaxial layer lis. N type The groove 116 extends from the surface of the 磊-type epitaxial layer U5 to the surface of the hard-doped layer ι 3 to define a well in the 磊-type epitaxial layer U5.

第8頁 1257701 [^五、發明說明（2) — 離垂直式雙載子電晶體於水平方向的不同元件。此外，型磊晶層115表面另設有一罩幕119，且罩幕119呈有一口（〇pening)121，以曝露出部分之？型井117，用來義^ 載子電晶體之基極圖案。水疋義又 P型磊晶層1 1 5中包含有一經由開口 i 2丨將雜質摻雜至雜層11 3上方所形成之p型集極增強區丨2 3，以及一經由夕口 121將雜質摻雜至集極增強區123上 g二區125。N型基極區125表面包含有一由多晶石夕成之陁基極二0成的射極接觸區127,而射極接觸區127 Lt另外it125之部分表面則設有一阳射極區設於賭基極in電/面體還包含有一N型基極接觸區m 1 34抓於N刑A扣r 1表面’以及複數個集極接觸區1 33、 134δ又於N型基極區125以外之p型井117表面。晶體中用來作為集層，且習知製作垂晶層上方之開口進刀別於爲晶層中形觸區等多層次結構與丨米度中精確控制接觸區等多層次結基極、射極以及基多次熱處理擴散^ 極區之蠢直式雙載行繁複多成集極增，因此不上述集極構之位極接觸區更難以精由於上述習知垂直式雙載子電晶層大多僅為一層薄薄的磊晶子電日日體的方法又必須透過蠢次之摻雜以及熱處理製程，以強區、基極、射極以及基極接僅不容易於磊晶層之有限寬度增強區、基極、射極以及基^ 置，且植入上述集極增強區、等多層次結構中之雜質在經過Page 8 1257701 [^5, invention description (2) - different components from the vertical bipolar transistor in the horizontal direction. In addition, a mask 119 is further disposed on the surface of the epitaxial layer 115, and the mask 119 has a 〇pening 121 to expose a portion thereof. The well 117 is used to define the base pattern of the carrier transistor. The water-based and P-type epitaxial layer 1 15 includes a p-type collector enhancement region 丨2 3 formed by doping impurities to the impurity layer 11 3 via the opening i 2 , and a via 121 Impurities are doped to the g-region 125 on the collector enhancement region 123. The surface of the N-type base region 125 includes an emitter contact region 127 which is formed by the base of the polycrystalline spine, and a portion of the surface of the emitter contact region 127 Lt and other it 125 is provided with a positive emitter region. The gambling base in the electric/face body further comprises an N-type base contact region m 1 34 captured by the N-A-r1 surface and a plurality of collector contact regions 1 33, 134δ and outside the N-type base region 125 The surface of the p-type well 117. The crystal is used as a collecting layer, and the opening of the opening above the floating layer is conventionally formed into a multi-layer structure such as a contact zone in the crystal layer and a multi-level base and the like in precisely controlling the contact area in the glutinous rice. The poles and the multiple heat treatments of the diffusion region are extremely complicated, and therefore the pole contact regions of the collectors are not more difficult to be fined due to the above-mentioned conventional vertical double-carrier electronization layer. Most of the methods are only a thin layer of epitaxial electrons and the method of doping and heat treatment. The strong region, the base, the emitter and the base are not easy to be limited to the finite width of the epitaxial layer. The enhancement region, the base, the emitter, and the substrate are implanted in the above-mentioned collector enhancement region, and the impurities in the multi-layer structure are passed through

五、發明說明（3) 確控制其遺择 -— 表現大受影ΐ:，進而導致垂直式雙載子電晶體之電性【内容】，此’本發明之主要日日體之方法，，係提供一種製造垂直間之高精密定間化製程，並提供電日曰i載子電在本發明：以果。 ^曰體之各元件上形成—j車U施例中，該方法於一半的第二摻雜區包型式的第一摻雜區域，—第曰_曰片之基板及第二摻雜及ί數個間隔物”第式面形成-遮蔽層，雜區域。隨後，&半導：曰2 $雜區域。接下來；層中形成-開口通ί3表摻雜區域第取利用-自行對準金丄導電型 μ ra 弟二摻雜區域與換灿陆了蜀7化製程於第二曰’用來作為垂直式雙載子‘ = = : =成-金屬矽化物电晶體之接觸區。 =:本發明是利用間隔物 ^，雜區域（基極）的位置，自動定義出雙載子電晶體之第製雙载子電晶體之射極，H = = f板表面之摻雜層乂有效避免習知方法利用| =體之接觸區，因此本發明可 ’、贺多次之摻雜以及熱處理製程V. Description of invention (3) It is indeed controlled by its choice - the performance is greatly affected: and thus the electrical properties of the vertical double-carrier transistor, the method of the main Japanese-Japanese body of the invention, The invention provides a high-precision intercalation process for manufacturing vertical and provides electric electricity to the present invention in the present invention: In the case of forming a component of the body, the method is applied to the first doped region of the second doped region, the substrate of the second chip and the second doping and Several spacers "the first surface forms - the shielding layer, the impurity region. Subsequently, & semi-conducting: 曰 2 $ miscellaneous region. Next; the formation in the layer - the opening of the doping region - the first use - self-alignment The gold-conducting type μ ra di-doped region is replaced with a di-can be used in the second 曰 'used as a vertical double-carrier ' = = : = into a metal-telluride transistor contact region. The invention utilizes the position of the spacer ^, the impurity region (base) to automatically define the emitter of the second bipolar transistor of the bipolar transistor, and the doping layer on the surface of the plate is effective. Avoiding the conventional method of using the contact area of the body of the body, so the present invention can be used for many times of doping and heat treatment processes.

第10頁 1257701 五、發明說明（4) 於磊晶層t形成集等多層次結構所衍4二強£、基極、射極以及A朽桩^ ^ ,,^ "订生的元件定位以；》:曲由久巷極接觸區 i、黾晶體之各元件間之资 =又控制等問題，提簡化製程，改善元株=精山疋位效果，同時更可以右 C件之電性表現。了又』以有效而為讓本發明之μ、+、 ^ ^ ^ . 上迷目的、特徵、和優ϋ < 下文特舉較佳實施 =俊^硓更明顯易懂，下。乃式，亚配合所附圖式，你> α刃® Γ 作坪細說明如【實施方法】請參照第二較佳實施方圖。如第二半導體晶片 -摻雜區域及複數個間域2 1 6表面《型，且第二第一導電型第雜區第一摻雜區第二摻雜區其他電子元 j至第五圖，第二圖至第五 ^ i w造：垂直式雙載子電晶體ί i ί明ί 一圖所不，本發明係先提供一=方法不思 200，並於基板212上形一二有基板21 2的 214, 一第二導電型式的第二择·'導電型式的第隔物218設於第一摻雜區域21二雜區域2上6，以 ‘在本發明之較佳實施例及/一払雜區導電型式為N型。麸而太恭日日=—¥電型式為P 式亦可為N型，且’第二:並於此， 216係用來定義錐:早=f =式為P型。此外， 2 1 4係環繞於第=狹，日日體之集極位置，且 216,避免第弟雜區21 6周圍，以用來隔絕件中。間隔物―^區216中之離子水平擴散至物218可以利用淺溝隔離（shaU〇w 1257701 五、發明說明（5) hem isolation，Sm方式或局域性石夕氧化（i〇cai SUiC〇n，Lf〇S)方式形成，且間隔物218 第一杉雜區21 6表面定義出至少一預定作雙載子電晶體之基極。匕3用木& 接著述預來作濃度 -互進行時，體晶製程程可以使之單發明利用製程件之成一電材其他，利用一離子佈植製程，於第二摻雜區域216中之上定區域形成一第一導電型式的第三摻雜區域22〇，用為雙載子電晶體之基極。根據產品之電性要求（摻質要求）’第二摻雜區域2 2 0之離子佈植製程可以選擇、與補式金氧半導體（CMOS)電晶體之源極/汲極製程同時、 $雜’例如當雙載子電晶體需要承受較高操作電壓第三摻雜區域2 2 0之離子佈植製程可以與製作於半導片2 0 0上之C Μ 0 S電晶體之輕摻雜汲極以及源極/汲極等同時進行摻雜’否則第三摻雜區域2 2 0之離子佈植製以僅與CMOS電晶體之輕摻雜汲極製程同時進行摻雜，雙載子電晶體具有一較窄之基極寬度，並且獲得較佳 —增盈頻率（unity-gain frequency，Ft)。此外，本亦可以另外利用一道光罩來製作第三摻雜區域22〇，特殊之摻質濃度來進行第三摻雜區域2 2 0之離子佈植，以使雙載子電晶體可以提供不同的崩潰電壓，使元電性表現達到最佳化。隨後，於該半導體晶片表面形遮蔽層2 2 2，遮蔽層2 2 2可由氧化物及/或氮化石夕等介/ 料形成，用來保護半導體晶片2 0 0上之CMOS電晶體或電子元件。 <Page 10 1257701 V. Description of invention (4) The formation of a multi-level structure such as a set of layers in the epitaxial layer t, the second strongest £, the base, the emitter and the A dead pile ^ ^ , , ^ "";": The song from the long contact area i, the elements of the crystal between the elements = control and other issues, to simplify the process, improve the Yuanzhu = Jingshan position, but also the right C piece of electricity which performed. In order to make the μ, +, ^ ^ ^ of the present invention effective, the features, characteristics, and advantages of the present invention are as follows: 1. The following is a better implementation = Jun ^ ^ is more obvious and easy to understand, the next. For the formula, you can refer to the drawing, and you can refer to the second preferred embodiment. For example, the second semiconductor wafer-doped region and the plurality of inter-domains 2 1 6 surface type, and the second first conductivity type first impurity region first doping region second doping region other electron elements j to fifth, The second figure to the fifth ^ iw made: vertical type double carrier transistor ί i ί ί 一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一一2, 214, a second conductivity type second conductivity type of the first spacer 218 is disposed on the first doped region 21 on the second impurity region 2, 6 in the preferred embodiment of the present invention and / The conductivity type of the doping area is N type. Bran and Taigong Day = - ¥ electric type is P type can also be N type, and 'second: and here, 216 is used to define the cone: early = f = formula is P type. In addition, the 2 1 4 series surrounds the narrow position of the Japanese body, and 216, avoids the surrounding area of the first and second miscellaneous areas 21 6 for use in the insulation. The ion level diffusion in the spacer-^ region 216 can be separated by shallow trenches (shaU〇w 1257701, invention description (5) hem isolation, Sm mode or localized shixi oxidation (i〇cai SUiC〇n , Lf〇S) is formed, and the surface of the spacer 218 first fir region 21 6 defines at least one base which is intended to be a bipolar transistor. 匕3 uses wood & In the second doping region 216, a first doped region of the first conductivity type is formed in the upper region of the second doped region 216 by using an ion implantation process. 22〇, used as the base of the bipolar transistor. According to the electrical requirements of the product (doping requirements) 'The second doping region 2 2 0 ion implantation process can be selected, and complementary MOS (CMOS) The source/drain process of the transistor is simultaneous, for example, when the bipolar transistor needs to withstand a higher operating voltage, the third doping region 2 2 0 ion implantation process can be fabricated on the semi-conductive sheet 2 0 0 之 0 电 0 S transistor lightly doped bungee and The source/drain electrodes and the like are simultaneously doped. Otherwise, the ion implantation of the third doped region 2 2 0 is simultaneously doped only with the lightly doped drain process of the CMOS transistor, and the bipolar transistor has a a narrower base width and a better unity-gain frequency (Ft). In addition, a mask can be additionally used to fabricate the third doped region 22〇, the specific dopant concentration. Ion implantation of the third doped region 220 is performed so that the bipolar transistor can provide different breakdown voltages to optimize the electrical performance. Subsequently, the shielding layer 2 2 is formed on the surface of the semiconductor wafer. 2, the shielding layer 2 2 2 may be formed of an oxide and/or a nitride or the like to protect the CMOS transistor or electronic component on the semiconductor wafer 2000.

第12頁 1257701 ~—__ 五、發明說明（6) ίί三面於遮，層T中形成-開口 m通達雜區域22〇上方形成—第；2 : : : J =，接著於第三摻部分之遮蔽層222。摻雜^ 雜層226，並移除射極，其可利用蟲晶作為雙載子電晶體之降低摻雜層226之阻值，:/ 03/之持料形成’且為了再於摻雜層2 2 6中植入高ju 實施例中建議可來說，當本較佳實施例之雙夂載體=型式離子。舉例則射極22 6之製作可盥主戟子體為一 PNP電晶體，之基極製程结a ’亦即^¥田體晶片200上之其他NPN電晶體之阻值利： = 製程來降低二者例之雙載子雷曰栌η 案。此外，當本較佳實施 i5日日n之其他ρνρ電晶體之基極製程結合，亦即 =同- Ν型摻雜製程來降低二者之阻值，之後再利用亦」晶體 :Ϊ = i ί刻製程來同時定義射極22 6之圖案與ΝΡΝ電 <暴極圖案。％Page 12 1257701 ~ -__ V. Description of the invention (6) ίί three sides in the cover, formed in the layer T - the opening m passes through the impurity region 22 形成 formed above - the second; 2 : : : J =, followed by the third admixture The shielding layer 222. Doping the impurity layer 226 and removing the emitter, which can utilize the insect crystal as the resistance of the doped layer 226 of the bipolar transistor, : / 03 / the holding material forms ' and in order to re-doped layer 2 2 6 implantation high ju is suggested in the embodiment, when the double 夂 carrier of the preferred embodiment = type ion. For example, the emitter 22 6 can be fabricated as a PNP transistor, and the base process node a', that is, the resistance of other NPN transistors on the field wafer 200: = process to reduce The two cases of the double carrier Thunder η case. In addition, when the base process of the other ρνρ transistors of the preferred embodiment i5 is combined, that is, the same- Ν type doping process is used to reduce the resistance of the two, and then the crystal is used: Ϊ = i The process is defined to define both the pattern of the emitter 22 and the & 暴 violent pattern. %

J著’如第四圖所示，於摻雜層226之侧壁表面形成一侧二t 228結構。側壁子228主要係用來保護摻雜層226之部 ^ 面4»以避免後續之自行對準金屬矽化製程使得摻雜層產生不必要之接觸區，造成電晶體短路之缺陷。As shown in the fourth figure, a side two t 228 structure is formed on the sidewall surface of the doped layer 226. The sidewall spacers 228 are primarily used to protect the portions of the doped layer 226 from the surface 4» to avoid subsequent self-alignment of the metal deuteration process such that the doped layers create unnecessary contact regions, causing defects in the transistor short circuit.

第13頁 1257701 五、發明說明（7) 之後，如第五圖所示，利用一自行八 —摻雜區域214、第二摻雜區域==石夕化製程於第摻雜層2 2 6表面形成一全屬矽化舲一彳乡雜區域2 2 0與 2300(^ 230Β^^：Γί ) 230^ 晶體之金屬接觸區。而上述之接2式雙載子電圖為依本發明第一較佳實施方A制士弟/、圖所示，第六晶體的金屬接觸區俯視圖。依:圖二直f雙載子電 :方式使用自行對準金屬矽化製；=實電晶體之射極接觸區23〇 A、基極t 直/雙載子換nvn其他電性需求的接觸區，例如設於第-^雜£域214表面之接觸區23〇〇。 ί:明Ϊ參以圖至第十一圖’第七圖至第十-圖係為法實施方式之製$垂直式雙載子《晶體的方 412的〜半導ν°ΛΛ圖所示，本發明係先提供一包含有基板式的#牛¥體曰曰片400，並於基板41 2上形成一第一導電型 ^416，弟、一換-雜區域414，一第二導電型式的第二換雜區域二’以。及複數個間隔物4 1 8設於第一摻雜區域4 1 4以及第電^，區域4 1 6表面。在本發明之較佳實施例中，第一導並於此為f型，且第二導電型式為Ν型。然而本發明並不限型::第—導電型式亦可為N型，且第二導電型式為p 置1第=接雜區41 6係用來定義雙載子電晶體之集極位來隔ί ϊ Γ摻雜區414係環繞於第二摻雜區416周圍，以用岡、、、巴弟二摻雜區4 1 6，避免第二摻雜區4 1 6中之離子水平Page 13 1257701 V. Inventive Note (7) Thereafter, as shown in the fifth figure, a self-octa doped region 214, a second doped region == Shi Xihua process is used on the surface of the doped layer 2 2 6 Forming a metal contact zone of the crystals of the 2nd and 2300 (^ 230Β^^: Γί) 230^ regions of the 彳舲彳彳彳彳. The above-mentioned two-type double-carrier electrogram is a top view of the metal contact region of the sixth crystal according to the first preferred embodiment of the present invention. According to: Figure 2: direct f double carrier power: the method uses self-aligned metal bismuth; = the contact area of the emitter contact area of the solid crystal 23 〇 A, the base t straight / double carrier for nvn other electrical requirements For example, it is provided in the contact area 23〇〇 on the surface of the first-period 214. ί: Ϊ Ϊ 以以以第第第第 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' 第七第七第七第七第七第七第七第七第七第七垂直垂直垂直垂直垂直垂直垂直垂直垂直垂直垂直The present invention first provides a substrate-type #牛¥体曰曰片400, and forms a first conductivity type 416 on the substrate 41 2, a dipole-differential region 414, and a second conductivity type. The second change zone is 'two. And a plurality of spacers 4 1 8 are disposed on the surface of the first doped region 4 1 4 and the first region 4 1 6 . In a preferred embodiment of the invention, the first conductivity is f-type and the second conductivity pattern is Ν-type. However, the present invention is not limited to the following: the first conductivity type may also be an N type, and the second conductivity type is p. The first = junction region 41 is used to define the collector position of the bipolar transistor. ί Γ doped region 414 surrounds the second doped region 416 to avoid ion levels in the second doped region 4 16 using the doping region 421

第14頁 1257701 五、發明說明（8) 擴散至其他電子元件中。此少一第二導電型式的高濃表面亦石夕氧化方式形成，且間隔物“ ΓΪ隔Ϊ方 2，表面定義出至少一預定區域上H二二摻雜體之基極。水衣作雙载子電晶，後，利用一離子佈植製程於第二摻 =區域形成一第—導電型式的之上述 :為雙載子電晶體之基極。根據產品之=來互補式金氧半導體電晶體^&選擇與一雜，例如當雙載子電；二ά製程同時進行摻摻雜區域420之離子佈曰植製而7又父兩操作電壓時，第三上之CMOS電晶體之輕摻雜"^ I作於半導體晶片400 進行摻雜，否則第三源極/沒極等製程同時與CMOS電晶體之輕摻雜汲極製程^之離子佈植製程可以僅 :電晶體具有一較窄之基極&门雜，以使雙載盈頻率。此外，本發明亦可以^ 彳又得較佳之單一增三摻雜區域42 0，利用特殊之摻利用一道光罩來製作第域42 0之離子佈植製程，以雔二，辰度來進行第三摻雜區的崩潰電壓，使元件之電性矣又載子電晶體可以提供不同導體晶片4 0 0表面形成—第5 #達到最佳化。隨後，於半 4 2 3，用來保護半導體晶片蔽層4 2 1與苐一遮蔽層之CMOS電晶體或其他電子Page 14 1257701 V. INSTRUCTIONS (8) Diffusion into other electronic components. The high-concentration surface of the second conductivity type is also formed by the oxidation process, and the spacer "is separated from the square 2, and the surface defines the base of the H-two dopant on at least one predetermined region. Carrier electron crystal, and then using an ion implantation process to form a first conductivity type in the second doped region: the base of the bipolar transistor; the complementary MOS device according to the product = The crystal ^& selects with a hybrid, for example, when the double carrier is charged; the second process simultaneously performs the ion implantation of the doped region 420 while the seventh and the parent operating voltages, the light of the third CMOS transistor The doping " ^ I is applied to the semiconductor wafer 400 for doping, otherwise the third source/no-pole process and the CMOS transistor are lightly doped with a drain process. The ion implantation process can be: only the transistor has one The narrower base & gates are used to make the double carrier frequency. In addition, the present invention can also provide a preferred single-increasing three-doped region 42 0, using a special mask to make the first domain. 42 0 ion implantation process, the second doping with 雔二,辰度The breakdown voltage of the region allows the device to be electrically charged and the carrier transistor can provide different conductor wafers for surface formation - the fifth # is optimized. Subsequently, in the half 4 2 3, to protect the semiconductor wafer mask 4 2 1 CMOS transistor or other electron with a mask

1257701 五、發明說明（9) 兀件。第一遮蔽層係以氧化物4 2 1形成，第二遮蔽層係以氮化矽4 2 3形成。然後，如第八圖所示，於第一遮蔽層421與第二遮蔽層423 中形成一開口 425通達至第三摻雜區域42〇表面。如第九圖所示’接著於第三摻雜區域42〇上方，形成一第二導電型式的摻雜層42 6，並移除部分之第一遮蔽層42丨與第二遮蔽層423。摻雜層42 6可利用磊晶/非晶矽/多晶矽之材料形成0 ^ =十圖所示’於摻雜層42 6之部分表面形成一自行對準而梆^化物阻播層（SAB ) 4 2 7，以及於掺雜層4 2 6之侧壁表古丄r ~側壁子4 2 8結構。自行對準金屬石夕化物阻播層4 2 7 於換來保護摻雜層42 6之部分表面，以避免後續形成 I 426表面之金屬矽化物層過度深入摻雜層42 6，甚隼^ η =雜層426與第三摻雜區域42 0間之接面（即基極盥 =製作方法係先於基板_ 之部分％续ί再利用回蝕刻製程去除摻雜層42 6表面以外屬石夕化：；；二=摻f層42 6表面形子似。此外雜層426之側壁表面形成側壁 400上製作在之其他實施例中，亦可以在半導體曰曰：於本發明之、PN二雙載子電晶體之射極（N型摻雜層）時，評又載子電晶體之射極（P型摻雜層）426之部1257701 V. Description of invention (9) Conditions. The first masking layer is formed of oxide 4 2 1 and the second masking layer is formed of tantalum nitride 4 23 . Then, as shown in the eighth figure, an opening 425 is formed in the first shielding layer 421 and the second shielding layer 423 to reach the surface of the third doping region 42. Next to the third doped region 42A, a doped layer 42 6 of a second conductivity type is formed and a portion of the first mask layer 42 and the second mask layer 423 are removed. The doped layer 42 6 can be formed by using a material of epitaxial/amorphous germanium/polycrystalline germanium to form a self-aligned and silicide blocking layer (SAB) on a portion of the surface of the doped layer 42 6 . 4 2 7, and on the side wall of the doped layer 4 2 6 surface 丄r ~ ~ side wall 4 2 8 structure. Self-aligning the metallization layer 4 2 7 to protect a portion of the surface of the doped layer 42 6 to prevent the subsequent formation of the metal telluride layer on the surface of the I 426 from excessively deep into the doped layer 42 6 = junction between the impurity layer 426 and the third doped region 42 0 (ie, the base 盥 = fabrication method is prior to the portion of the substrate _ continued) and then the etch back process is used to remove the surface of the doped layer 42 6 The second surface of the impurity layer 426 is formed on the side wall 400. In other embodiments, it can also be used in the semiconductor device: in the present invention, the PN two double When the emitter of the carrier transistor (N-type doped layer) is evaluated, the emitter (P-doped layer) 426 of the carrier transistor is evaluated.

1257701 _________ 五、發明說明（10) i ί τ=步形ϊ 一 n型摻雜層，並且利用此—n型換雜於& Μϋ述,1行對準金屬石夕化物阻擔層4 2 7，之後層來 ^ϊ；^ί：Γί：ΐ#^ 426^ 订後，之自仃對準金屬矽化製程。 '^後，如第十一圖所示，利用一自行弟一摻雜區域4丨4、第一拎一、，屬矽化製程於與摻雜層426表面形三摻雜區域420 式雙載子電晶體之接觸區屬夕化物層430,用來作為垂直 Ξ ί! ΐ: 易；；特以第：二圖至第十六圖說 ;直式pNp雙載子Y晶體' 體揭之露隹依么^ ΐί ί Π〇戶ίΛ’Λ發Λ係先提供一包含有基板512的半 5"與一4二第並於/JV12上形成-一Ν型的第-摻雜區域含二？型的高濃产離%^/域%6，第二摻雜區域516可另包 514以及ί : = 摻雜區域517。且於第一摻雜區域 :^:ϊ:”6係用來定義雙載子電晶體之集極：V: 絕第二摻雜【514係:第二摻雜區516周圍，以用來隔至其他電3 = m免弟二摻雜區516中之離子水平擴散疋件中。間隔物5 1 8可以利用淺溝隔離方式或1257701 _________ V. INSTRUCTION DESCRIPTION (10) i ί τ = step shape ϊ an n-type doped layer, and using this -n type to be mixed with & description, 1 row alignment metallization resist layer 4 2 7, after the layer to ^ ϊ; ^ ί: Γ ί: ΐ # ^ 426 ^ After the order, the self-alignment of the metal smashing process. After ^^, as shown in FIG. 11, using a self-doping-doped region 4丨4, the first one, is a three-doped region 420 type double carrier on the surface of the doped layer 426. The contact region of the transistor belongs to the layer 430, which is used as a vertical Ξ ! ΐ: 易;; special to the second: to the sixteenth figure; straight pNp double carrier Y crystal 'body reveals the dew么^ ΐί ί Π〇 Λ Λ Λ Λ Λ Λ Λ 先先先先先先先先先先 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 512 The high concentration of the type is from %^/domain%6, and the second doped region 516 can be further packaged 514 and ί: = doped region 517. And in the first doped region: ^: ϊ: "6 is used to define the collector of the bipolar transistor: V: the second doping [514: around the second doped region 516, to separate To the other electrodes 3 = m in the ion-diffused element in the doped region 516. The spacers 5 1 8 can be isolated by shallow trench isolation or

Η Ή 第17頁 1257701 -——^_ 五、發明說明（11) 〜一^— ____ 局域性矽氧化方式形成，且表面定義出至少一預定區域=上1 8係於第二摻雜區516 極。束製作雙載子電晶體之基接著，利用一離子佈植製程於預定區域形成一 N型的第三摻雜弟—摻f區域516中之上述電晶體之基極。根據產品之電性要或5:用來作為雙載子半導體電晶體之源極巧-互補式金氧載子電晶體需要承受較高操衣作 =時進二^ 之離子佈植製程可以與製作於半導‘ θΘ f二f雜區域520 晶體之輕摻雜汲極以及源極曰上之CMOS電否則第三摻雜區域52〇之離子佈夺，行摻雜， f之^摻雜汲極製程同時進行摻雜，以使較窄之基極寬度’並且獲得較佳之單J =體：卜，本發明亦可以另外利用一道光罩來製作;:;雜你^制利用特殊之摻質濃度來進行第三摻雜區域一52%之ϋ ^植$程，以使雙載子電晶體可以提供不同的崩潰電】子使疋件之電性表現達到最佳化。隨後，於半形成一第一遮蔽層521與一第二遮蔽層523， Τ日日面體晶片5 0 0上之CMOS電晶體或其他電子元件’。來相半導係以氧化物521形A，第二遮蔽層係以氮化矽二遮成献。- 然後，如第十三圖所示，於第-遮蔽層521與第二遮蔽層Η Ή Page 17 1257701 -——^_ V. INSTRUCTIONS (11) 〜一^— ____ Localized 矽 oxidation is formed, and the surface defines at least one predetermined area = upper 18 is in the second doping area 516 poles. Bundling the base of the bipolar transistor Next, an ion implantation process is used to form a base of the above-mentioned transistor in the N-type third doping-doped region 516 in a predetermined region. According to the electrical properties of the product or 5: used as a source of bi-carrier semiconductor transistors - the complementary metal oxide carrier transistor needs to withstand higher operation of the machine = time into the second ^ ion implantation process can be Manufactured in the lightly doped 汲 of the semiconducting ' θ Θ f f 杂区域 520 520 crystal and the CMOS on the source 否则 or the ion doping of the third doped region 52 行, doping, f doping 汲The pole process is simultaneously doped to make the narrow base width 'and obtain a better single J = body: 卜, the present invention can also be additionally fabricated using a reticle; The concentration is used to perform a 52% process of the third doped region, so that the bipolar transistor can provide different thermal currents to optimize the electrical performance of the device. Subsequently, a first shielding layer 521 and a second shielding layer 523 are formed on the surface of the CMOS transistor or other electronic component on the solar wafer 500. The phase-conducting layer is made of oxide 521-shaped A, and the second shielding layer is made of tantalum nitride. - then, as shown in the thirteenth figure, at the first shielding layer 521 and the second shielding layer

第18頁 1257701 五、發明說明（12) 5 2 3中形成一開口 5 2 5通達至第三摻雜區域5 2 〇表面。如第十四圖所示，接著於第三摻雜區域52 0上方，形成一 p型摻雜層526，並移除部分之第一遮蔽層521與第二遮蔽層 5 2 3。摻雜層5 26可利用磊晶/非晶矽/多晶矽之材料形成。如第十五圖所示，於摻雜層52 6之部分表面形成一自行對準至屬石夕化物阻擔層（SAB)527，以及於摻雜層52 6之側壁表面形成一側壁子528結構。 ί後换如第十六圖所示，利用一自行對準金屬矽化製程於 ίίίϊί域514、第二摻雜區域516、第三摻雜區域52〇 H摻雜層52 6表面形成一金屬矽化物層53〇α、5讓、、530D，用來作為ΡΝΡ垂直式雙載子電晶體之金 =第而接觸區如第十七圖所示，第十七圖為依才 ^月弟二較佳貫施方式所製造之垂直式雙載子 = ;依此圖顯示本發明第三較佳實：… 對準金屬矽化製程，製造出垂直式雙載子電曰辦戈及提供觸區53〇B、集極接觸區5二、, 5"表面之V觸Page 18 1257701 V. INSTRUCTION DESCRIPTION (12) An opening 5 2 5 is formed in 5 2 5 to reach the surface of the third doped region 5 2 . As shown in Fig. 14, a p-doped layer 526 is formed over the third doped region 520, and a portion of the first masking layer 521 and the second masking layer 523 are removed. The doped layer 526 can be formed using a material of epitaxial/amorphous germanium/polysilicon. As shown in the fifteenth figure, a self-aligned to the stellate resistive layer (SAB) 527 is formed on a portion of the surface of the doped layer 526, and a sidewall 528 is formed on the sidewall of the doped layer 526. structure. Then, as shown in FIG. 16, a metal telluride is formed on the surface of the λ-doped region 516 by using a self-aligned metal etch process, the second doped region 516, and the third doped region 52. Layers 53〇α, 5 let, 530D, used as the gold of the vertical double-carrier transistor = the first contact area is shown in Figure 17, and the seventeenth picture is the best The vertical type of double carrier manufactured by the method of the present invention is shown in the figure. The third preferred embodiment of the present invention is shown in the figure: Aligning the metal deuteration process, manufacturing a vertical double-carrier electric device and providing a contact area 53〇B , collector contact area 5 2,, 5 " surface V touch

相較於習知利用間隔物 (基極）的位之製造垂直來自動定義置，利用形式雙載子電出雙载子電成於基板表晶體之方法晶體之第三面之摻雜層 ’本發明是摻雜區域 I作為雙載The doping layer of the third side of the crystal is automatically defined by the vertical manufacturing of the spacer (base) by using the spacer of the spacer (base). The present invention is doped region I as a double load

第19頁 1257701 五、發明說明（13) 子電晶體之射極，並且利用自我對準金屬矽化製程來形成垂直式雙載子電晶體之接觸區，因此本發明可以有效避免習知方法利用繁複多次之摻雜以及熱處理製程於磊晶層中形成集極增強區、基極、射極以及基極接觸區等多層次結構所衍生的元件定位以及濃度控制等問題，提供電晶體之各元件間之高精密定位效果，同時更可以有效簡化製程，改善元件之電性表現。Page 19 1257701 V. Description of Invention (13) The emitter of the sub-crystal, and using a self-aligned metal deuteration process to form the contact area of the vertical bipolar transistor, so the present invention can effectively avoid the complicated use of the conventional method. Multiple doping and heat treatment processes provide element positioning and concentration control problems in the epitaxial layer to form a collector enhancement region, a base, an emitter, and a base contact region, and provide various components of the transistor. The high precision positioning effect can simplify the process and improve the electrical performance of components.

然而，以上所述僅為本發明之較佳實施方式，凡依本發明申請專利範圍所做之均等變化與修飾，應屬本發明專利之涵盖範圍。However, the above description is only a preferred embodiment of the present invention, and the equivalent variations and modifications made by the scope of the present invention should be covered by the present invention.

第20頁 1257701 圖式簡單說明圖式之簡單說明第一圖為係為習知垂直式雙載子電晶體的剖面圖。第二圖至第五圖係為本發明第一較佳實施方式之製造垂直式雙載子電晶體的方法示意圖。第六圖為依本發明第一較佳實施方式所製造之垂直式雙載子電晶體的金屬接觸區俯視圖。第七圖至第十一圖係為本發明第二較佳實施方式之製造垂直式雙載子電晶體的方法示意圖。第十二圖至第十六圖係為本發明第三較佳實施方式之製造垂直式雙載子電晶體的方法示意圖。第十七圖為依本發明第三較佳實施方式所製造之垂直式雙載子電晶體的金屬接觸區俯視圖。圖式之符號說明 100 半導體晶片 110 半導體基板 113 N型換雜層 115 P型蟲晶層 117 P型井 119 罩幕 121 開口 123 P型集極增強區 125 N型基極區 127 射極接觸區 129 P型射極區 131 N型基極接觸區 133〜 1 3 4 集極接觸區 200 半導體晶片 212 基板Page 20 1257701 Brief Description of the Drawings Brief Description of the Drawings The first figure is a cross-sectional view of a conventional vertical bipolar transistor. 2 to 5 are schematic views showing a method of manufacturing a vertical type double carrier transistor according to a first preferred embodiment of the present invention. Figure 6 is a plan view of a metal contact region of a vertical bipolar transistor fabricated in accordance with a first preferred embodiment of the present invention. 7 to 11 are schematic views showing a method of manufacturing a vertical bipolar transistor according to a second preferred embodiment of the present invention. Twelfth to sixteenth views are schematic views showing a method of manufacturing a vertical bipolar transistor according to a third preferred embodiment of the present invention. Figure 17 is a plan view showing a metal contact region of a vertical type bipolar transistor manufactured in accordance with a third preferred embodiment of the present invention. DESCRIPTION OF SYMBOLS 100 semiconductor wafer 110 semiconductor substrate 113 N-type impurity layer 115 P type insect layer 117 P type well 119 mask 121 opening 123 P type collector enhancement region 125 N type base region 127 emitter contact region 129 P-type emitter region 131 N-type base contact region 133~1 3 4 collector contact region 200 semiconductor wafer 212 substrate

第21頁 1257701 圖式簡單說明 214 第一導電型式的第， -摻雜區域 216 第二導電型式的第- 二摻雜區域 218 間隔物 220 第一導電型式的第- 三摻雜區域 222 遮蔽層 224 開 π 226 換雜層 228 側壁子 230 金屬矽化物層 301 射極接觸 303 基極接觸區 305 集極接觸區 307 提供其他電性需求的接觸區 400 半導體晶片 412 基板 414 第導電型式的第一摻雜區域 416 第二導電型式的第二摻雜區域 418 間隔物 420 第 — 導電型式的第三摻雜區域 421 第一遮蔽層 423 第二遮蔽層 425 開 V 426 摻雜層 427 白行對準金屬矽化物阻擋層 428 側壁子 430 金屬石夕化物層 500 半導體晶片 512 基板 514 N型第- -摻雜區域 516 P型第二摻雜區域 518 間隔物 520 N型第三摻雜區域 521 第 —一遮蔽層 523 第二遮蔽層 526 摻雜層Page 21 1257701 Brief description of the pattern 214 of the first conductivity type, - doped region 216, second doped region of the second conductivity type 218 spacer 220 first conductivity type of the third - doped region 222 shielding layer 224 open π 226 change layer 228 sidewall spacer 230 metal germanide layer 301 emitter contact 303 base contact region 305 collector contact region 307 contact region 400 providing other electrical requirements semiconductor wafer 412 substrate 414 first conductivity type Doped region 416 second doped region second doped region 418 spacer 420 first conductive type third doped region 421 first shielding layer 423 second shielding layer 425 open V 426 doped layer 427 white line alignment Metal telluride barrier layer 428 sidewall spacer 430 metallization layer 500 semiconductor wafer 512 substrate 514 N-type - - doped region 516 P-type second doping Region 518 spacer 520 N-type third doped region 521 first-first mask layer 523 second mask layer 526 doped layer

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1257701 圖式簡單說明 5 2 7 自行對準金屬矽化物阻擋層 5 2 8 側壁子 5 3 0 金屬矽化物層 601 射極接觸區 6 0 3 基極接觸區 6 0 5 集極接觸區 6 0 7 提供其他電性需求的接觸區1257701 Schematic description 5 2 7 self-aligned metal telluride barrier 5 2 8 sidewall 5 3 0 metal telluride layer 601 emitter contact region 6 0 3 base contact region 6 0 5 collector contact region 6 0 7 Contact area providing other electrical requirements

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Claims

1257701 六、申睛專利範圍 1 · 一種於一半導法’該半導體晶域，一第二導電設於該第一摻雜含有下列步驟：於該第二摻雜區域；於該半導體晶片去除部分之該遮該第三摻雜區域於該第三摻雜區及利用一自行對準 si 1 icidation，雜區域與該摻雜垂直式雙載子電體晶片上製造一垂古片包含有一第一導雙載子電晶體的方型式的第二摻雜區】型式的第一摻雜區區域以及該第二择=，以及複數個間隔物，雜區域表面，該方法包域上方形成一第—導型式的第三摻雜區表面形成一遮蔽層； ;以於該遮蔽層中形成一開口通達至域上方形成一第二導電型式的摻雜層；以金屬石夕化製程（self —aligned sal icide)於該第二摻雜區域、該第三摻層表面形成一金屬矽化物層，用來作為該晶體之接觸區。 it I印ΐ範圍第1項所述之製造垂直式雙載子電晶體的万汝’其中該間隔物係以淺溝隔離（shallow trench isolation，STI)方式形成。 3 ·如申請專利範圍第1項所述之製造垂直式雙載子電晶體的方法’其中該間隔物係以局域性矽氧化（丨〇ca 1 oxidation of Siiic〇n， L〇c〇s)方式形成。1257701 6. The scope of the patent application is as follows: 1. In a semiconductor method, a second conductivity is provided in the first doping, and the first doping comprises the following steps: in the second doped region; The third doped region is covered in the third doped region and a self-aligned si 1 icidation is used, and the dummy region and the doped vertical bipolar sub-electrode wafer are fabricated with a first guide. a first doped region region of the square type of the bipolar transistor, and the second doped region, and the plurality of spacers, the surface of the impurity region, and a first guide is formed above the method packet region Forming a masking layer on the surface of the third doped region; forming an opening in the shielding layer to form a doping layer of a second conductivity type above the domain; and using a metal slab process (self-aligned salicide) Forming a metal telluride layer on the second doped region and the surface of the third doped layer to serve as a contact region of the crystal. It is described in the first aspect of the invention that the vertical bipolar transistor is fabricated in which the spacer is formed by shallow trench isolation (STI). 3. The method of manufacturing a vertical bipolar transistor according to claim 1, wherein the spacer is oxidized by local enthalpy (丨〇ca 1 oxidation of Siiic〇n, L〇c〇s) ) The way is formed.

第24頁 1257701 六、申請專利範圍 4. 如申請專利範圍第1項所述之製造垂直式雙載子電晶體的方法，其中該第二摻雜區域另包含至少一第二導電型式的高濃度離子摻雜區域。 5. 如申請專利範圍第1項所述之製造垂直式雙載子電晶體的方法，其中該遮蔽層包含有氧化物及/或氮化石夕。 6 ·如申請專利範圍第1項所述之製造垂直式雙載子電晶體的方法’其中该換雜層係以選自蠢晶/非晶碎/多晶碎之材料形成。 7. 如申請專利範圍第1項所述之製造垂直式雙載子電晶體的方法，其中該方法於進行該自行對準金屬矽化製程之前，另包含於該摻雜層之部分表面形成一自行對準金屬石夕化物阻擋層，以及於該摻雜層之側壁表面形成一側壁子結構。 8. 如申請專利範圍第1所述之製造垂直式雙載子電晶體的方法，其中該第一導電型式為P型，且第二導電型式為N 型〇 9 ·如申請專利範圍第1所述之製造垂直式雙載子電晶體的方法，其中該第一導電型式為N型，且第二導電型式為PThe method of manufacturing a vertical bipolar transistor according to claim 1, wherein the second doped region further comprises a high concentration of at least one second conductivity type. Ion doped region. 5. The method of manufacturing a vertical bipolar transistor according to claim 1, wherein the shielding layer comprises an oxide and/or a nitride. 6. The method of manufacturing a vertical bipolar transistor according to claim 1, wherein the alternating layer is formed of a material selected from the group consisting of stupid crystal/amorphous/polycrystalline. 7. The method of manufacturing a vertical bipolar transistor according to claim 1, wherein the method further comprises forming a self on a part of the surface of the doped layer before performing the self-aligned metal deuteration process. The metallization barrier layer is aligned, and a sidewall substructure is formed on the sidewall surface of the doped layer. 8. The method of manufacturing a vertical bipolar transistor according to claim 1, wherein the first conductivity type is a P type, and the second conductivity type is an N type 〇9. A method of fabricating a vertical bipolar transistor, wherein the first conductivity type is N type, and the second conductivity type is P

第25頁第圍範利專請申如的導體二晶第電之子度載濃雙高式入直植。垂層值造雜阻製摻之之該層述於雜 lm含摻包該另低法降方以該，中子其離 ,式法型方電 1257701 六、申請專利範圍贺〇 1 0 .如申請專利範圍第1所述之製造垂直式雙載子電晶體的方法，其中該方法另包含於該半導體晶片表面製造至少一互補式金氧半導體電晶體，且該第三摻雜區域係與該互補式金氧半導體電晶體之至少一源極/汲極利用同一離子佈植製程形成。 12.—種於一半導體晶片上製造一垂直式雙載子電晶體的方法，該半導體晶片包含有一 N型的第一摻雜區域，一 P型的第二摻雜區域，以及複數個間隔物設於該第一摻雜區域以及該第二摻雜區域表面，該方法包含有下列步驟：於該第二離子區域上方形成一 N型的第三摻雜區域；於該半導體晶片表面形成一遮蔽層；去除部分之該遮蔽層，以於該遮蔽層中形成一開口通達至該第三離子區域；於該第三摻雜區域上方形成一 P型的摻雜層；以及利用一自行對準金屬矽化製程於該第二摻雜區域、該第三摻雜區域與該摻雜層表面形成一金屬矽化物層，用來作為該垂直式雙載子電晶體之接觸區。Page 25 Circumference Fan Li Dedicated to the application of the second crystal of the conductor, the density of the double-height type into the direct planting. The layer is mixed with the impurity layer and is mixed with the layer of lm containing the other low method to reduce the neutron. The neutron is separated from the formula, and the type of the patent is 1257771. The method of manufacturing a vertical bipolar transistor according to claim 1, wherein the method further comprises: fabricating at least one complementary MOS transistor on the surface of the semiconductor wafer, and the third doped region is At least one source/drain of the complementary MOS transistor is formed using the same ion implantation process. 12. A method of fabricating a vertical bipolar transistor on a semiconductor wafer, the semiconductor wafer comprising an N-type first doped region, a P-type second doped region, and a plurality of spacers Provided on the first doped region and the second doped region surface, the method includes the steps of: forming an N-type third doped region over the second ion region; forming a mask on the surface of the semiconductor wafer a portion of the shielding layer is removed to form an opening in the shielding layer to the third ion region; a P-type doped layer is formed over the third doped region; and a self-aligned metal is utilized The deuteration process forms a metal telluride layer on the second doped region, the third doped region and the surface of the doped layer to serve as a contact region of the vertical bipolar transistor.

第26頁 1257701 六、申請專利範圍 1 3 .如申請專利範圍第1 2項所述之製造垂直式雙載子電晶體的方法，其中該間隔物係以淺溝隔離方式形成。 1 4.如申請專利範圍第1 2項所述之製造垂直式雙載子電晶體的方法，其中該間隔物係以局域性矽氧化方式形成。 1 5 .如申請專利範圍第1 2項所述之製造垂直式雙載子電晶體的方法，其中該第二摻雜區域另包含至少一 P型的高濃度離子摻雜區域。 1 6 .如申請專利範圍第1 2項所述之製造垂直式雙載子電晶體的方法，其中該遮蔽層包含有氧化物及/或氮化矽。 1 7.如申請專利範圍第1 2項所述之製造垂直式雙載子電晶體的方法，其中該摻雜層係以選自磊晶/非晶矽/多晶矽之材料形成。 1 8 .如申請專利範圍第1 2項所述之製造垂直式雙載子電晶體的方法，其中該方法於進行該自行對準金屬矽化製程之前，另包含於該摻雜層之部分表面形成一自行對準金屬石夕化物阻擋層，以及於該摻雜層之側壁表面形成一側壁子結構0。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。 The method of producing a vertical bipolar carrier crystal according to claim 12, wherein the spacer is formed by localized ruthenium oxidation. The method of fabricating a vertical bipolar carrier crystal according to claim 12, wherein the second doped region further comprises at least one P-type high concentration ion doped region. A method of producing a vertical bipolar carrier crystal according to claim 12, wherein the masking layer comprises an oxide and/or a tantalum nitride. The method of producing a vertical bipolar carrier crystal according to claim 12, wherein the doped layer is formed of a material selected from the group consisting of epitaxial/amorphous germanium/polycrystalline germanium. The method of manufacturing a vertical bipolar transistor according to claim 12, wherein the method is further formed on a surface of the doped layer before performing the self-aligned metal deuteration process. Self-aligning the metal-shield barrier layer and forming a sidewall substructure on the sidewall surface of the doped layer

第27頁 1257701 六、申請專利範圍 1 9 .如申請專利範圍第1 2項所述之製造垂直式雙載子電晶體的方法，其中該方法另包含於該半導體晶片表面製造至少一互補式金氧半導體電晶體，且該第三摻雜係與該互補式金氧半導體電晶體之至少一源極/汲極利用同一離子佈植製程形成。 2 0 .如申請專利範圍第1 2項所述之製造垂直式雙載子電晶體的方法，其中該方法另包含於該摻雜層植入高濃度之P 型離子，以降低該摻雜層之阻值。The method of manufacturing a vertical bipolar transistor according to claim 12, wherein the method further comprises fabricating at least one complementary gold on the surface of the semiconductor wafer. An oxy-semiconductor transistor, and the third doping system and the at least one source/drain of the complementary MOS transistor are formed by the same ion implantation process. The method of manufacturing a vertical bipolar transistor according to claim 12, wherein the method further comprises implanting a high concentration of P-type ions in the doped layer to reduce the doped layer. Resistance value.

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