1255552 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種矽覆絕緣金屬氧化半導體裝置及其製 作方法，詳言之，係關於一種具優質本體缚點之矽覆絕緣 金屬氧化半導體裝置及其製作方法。 【先前技術】 隨著微電子技術的日益發展，力求電子元件必須具備更 佳之性能’在元件尺寸逐漸縮小下，由於傳統之本體金屬 氧化物半導體場效電晶體（Bulk MOSFET)元件結構無法有 效克服超短通道效應（ultra_short channel effect)及因寄生 PN接面電容而產生的漏電流；所以近年來不論是工業界戍 者是學界都逐漸朝向具超薄矽薄層之矽覆絕緣金氧半場效 體（USBSOI)發展。 參考圖1所示，為習知之薄膜電晶體示意圖，其係 一種使用下閘極（Bottom Gate)之矽覆絕緣薄膜電晶體裝置 1〇，其包括·一玻璃基板11、一閘極層12 、一邊襯13、一 閘極氧化層14、一通道本體（channel) 15、一具導電之半導 體層16、一保護層17、一源極接觸端18及一沒極接觸端19。 該閘極層12形成於該玻璃基板11之上。該邊襯13形成於 該閘極層12之側邊及該基板11之上，該閘極氧化層14地毯 式形成於該閘極層12上。該具導電之半導體層16形成於該 邊襯13及該閘極氧化層14之上。該半導體層μ具有一通道 本體15、一源極部1 61、一汲極部162、一源極接面i 63及一 汲極接面164。該通道本體15係於該閘極氧化層14上之相對 100434.doc 1255552 位置。忒源極部1 6 1及該汲極部162係於該通道本體1 5之側 邊。 口為4通道本體15沒有與源極接觸端1 8 —併接在一起形 成本體4點’所以造成元件有嚴重的浮體效應、PN接面形 成漏弘’瓜、崩潰電壓偏低，及因閘極層12與汲極部162彼此 罪付太近4成米勒電容（Miller Capacitance)太大，進而減 損元件性能。 白知之石夕覆絕緣金氧半場效體（s〇I MOSFET)有比傳統 之Bulk MOSFET更佳之性能，例如：（1)具有較佳之抗輻射能 力，減少的軟式錯誤（soft-error)、（2)較低的寄生電容且具 有增強的載子移動率，電流驅動力大使得元件具有較佳之 #作速度、（3)受短通道影響較小、元件較易微縮（scaled d〇Wn)。所以習知之Bulk MOSFET元件日漸式微，逐步被SOI MOSFET 取代。 雖然SOI MOSFET具有上述之優點，但SOI MOSFET在矽 晶膜（silicon fiim)與基底之間多了一層熱傳導係數不佳之 埋入氧化層，且通道本體無法直接與基底一起接地，產生 通道載子自體加熱問題，使元件和系統之性能也因此大幅 降低，所以SOI MOSFET有其與生倶來（inherent)的問題： (1)全空乏式SOI (Fully Depleted SOI):雖然沒有傳統本 體互補金氧半（Bulk CMOS)的閂鎖（Latch-up)問題，但卻有 單一雙極性電晶體的單閂鎖（Single Latch-up)問題，使崩潰 電壓降低。並且，元件中多了 一層熱傳導係數不佳之埋入 氧化層，導致有嚴重之「自體加熱效應（self-heating)」。 100434.doc 1255552 (2)部分空乏式SOI(Partial Depleted SOI):因矽晶膜足夠 厚，使其具有假中性區（Pseudo Neutral Region)，造成浮體 效應（floating body effect)讓元件的輸出特性曲線具有紐結 (Kink)而使得輸出電阻下降，且仍具有自體加熱效應問題。 此外，傳統的SOI晶片價格較昂貴，約為一般晶片的1〇 倍左右。為了節省成本，可利用傳統晶片製作矽覆絕緣金 氧半系統，且可發展未來3D立體製程技術整合，將元件一 層一層地製作在傳統晶片上。目的在使縮小元件彼此之間 的距離和接線長度減少、節省更多的空間、增加集積度及 降低製作元件的整體成本。 傳統之SOI MOSFET在元件尺寸縮小下，門檻電壓仍會有 下降的情形，這是因為閘極與汲極為爭奪空乏區之控制能 力『電荷共享（charge sharing)』所致。 以上所述皆會降低元件之性能，其最根本的原因就是因 為傳統SOI MOSFET之本體（Body)是浮接的（floating)，缺少 一個接觸電極能將熱及在假中性區累積之電洞排掉；所以 必須讓元件有效地將熱排出，在元件尺寸縮小下又能使元 件保持較佳的性能使門檻電壓不致下降得很嚴重且又能夠 與3D立體製程技術整合，使元件有效地降低製程成本 (cost) 〇 目前有解決浮接通道本體之專利及論文被提出（參考美 國專利第4,946,799號、第5,317，181號、第6,746,937號、第 6，7 94，716 號、’’ Smart Body Contact for SOI MOSFETs’’，Matloubian, M·; SOS/SOI Technology Conference，1989·，1989 IEEE，3-5 Oct· 1989，，f A New 100434.doc 12555521255552 IX. Description of the Invention: [Technical Field] The present invention relates to a silicon-covered insulating metal oxide semiconductor device and a method of fabricating the same, and more particularly to a silicon-covered insulating metal oxide semiconductor device having a high-quality body-bound point And its production method. [Prior Art] With the development of microelectronics technology, electronic components must have better performance. 'Because the size of components is gradually reduced, the structure of traditional bulk metal oxide semiconductor field effect transistor (Bulk MOSFET) cannot be effectively overcome. Ultra-short channel effect and leakage current due to parasitic PN junction capacitance; therefore, in recent years, both industrialists and academics have gradually turned to the ultra-thin thin layer of the over-insulated insulating metal oxide half-field effect. Body (USBSOI) development. Referring to FIG. 1 , it is a schematic diagram of a conventional thin film transistor, which is a bottom insulating film transistor device using a bottom gate, comprising a glass substrate 11 and a gate layer 12 . A side liner 13, a gate oxide layer 14, a channel body 15, a conductive semiconductor layer 16, a protective layer 17, a source contact terminal 18 and a gate contact terminal 19. The gate layer 12 is formed on the glass substrate 11. The edge liner 13 is formed on the side of the gate layer 12 and on the substrate 11. The gate oxide layer 14 is carpet-formed on the gate layer 12. The electrically conductive semiconductor layer 16 is formed over the edge liner 13 and the gate oxide layer 14. The semiconductor layer μ has a channel body 15, a source portion 161, a drain portion 162, a source junction i 63, and a drain junction 164. The channel body 15 is attached to the gate oxide layer 14 at a relative position of 100434.doc 1255552. The source pole portion 161 and the drain pole portion 162 are attached to the side of the channel body 15. The mouth of the 4-channel body 15 is not connected with the source contact end 18 - 8 to form the body 4 points ', so that the component has a serious floating body effect, the PN junction surface is leaky, the breakdown voltage is low, and The gate layer 12 and the drain portion 162 are too close to each other to have a Miller Capacitance too large, thereby detracting from component performance. Bai Zhizhi Shishi Insulated Gold Oxide Half Field Effect (s〇I MOSFET) has better performance than traditional Bulk MOSFET, for example: (1) has better radiation resistance, reduced soft-error, ( 2) Lower parasitic capacitance and enhanced carrier mobility, large current driving force makes the component have better speed, (3) less affected by short channel, and easier to scale (d ddWn). Therefore, the conventional Bulk MOSFET components are gradually becoming smaller and gradually replaced by SOI MOSFETs. Although the SOI MOSFET has the above advantages, the SOI MOSFET has a buried oxide layer with poor thermal conductivity between the silicon fiim and the substrate, and the channel body cannot be directly grounded with the substrate, resulting in a channel carrier. The problem of bulk heating, so that the performance of components and systems is greatly reduced, so SOI MOSFET has its own problems with (inherent): (1) Fully Depleted SOI (Fully Depleted SOI): Although there is no traditional bulk complementary gold oxide A half (Bulk CMOS) latch-up problem, but with a single Lpolar-on-single Latch-up problem that reduces the breakdown voltage. Moreover, a layer of buried oxide layer with poor thermal conductivity is added to the component, resulting in severe "self-heating". 100434.doc 1255552 (2) Partial Depleted SOI (Partial Depleted SOI): Because the twin film is thick enough to have a Pseudo Neutral Region, causing the floating body effect to let the component output The characteristic curve has a kink that causes the output resistance to drop and still has the problem of self-heating effect. In addition, conventional SOI wafers are relatively expensive, about one-twice the size of a typical wafer. In order to save costs, traditional silicon wafers can be fabricated using a conventional wafer, and future 3D process technology integration can be developed to fabricate components on a conventional wafer layer by layer. The purpose is to reduce the distance and wiring length between the reduced components, save more space, increase the degree of accumulation, and reduce the overall cost of manufacturing components. In the case of conventional SOI MOSFETs, the threshold voltage will still decrease as the component size is reduced. This is because the gate and the gate compete for the control capability of the depletion zone, "charge sharing." All of the above will reduce the performance of the component. The most fundamental reason is that the body of the traditional SOI MOSFET is floating, lacking a contact electrode that can heat and accumulate holes in the pseudo-neutral zone. Discharged; therefore, the component must be effectively exhausted. When the component size is reduced, the component can maintain better performance so that the threshold voltage does not fall seriously and can be integrated with the 3D process technology, so that the component is effectively reduced. Process Costs 〇 There are currently patents and papers addressing the floating channel body (see U.S. Patent Nos. 4,946,799, 5,317,181, 6,746,937, 6, 7 94,716, '' Smart Body Contact for SOI MOSFETs'', Matloubian, M.; SOS/SOI Technology Conference, 1989, 1989 IEEE, 3-5 Oct. 1989,, f A New 100434.doc 1255552
Approach Implement O.lum MOSFET on Thin-Film SOI Substrate with Self-Aligned Source Body Contact’’，Chen，V.M.C·; Woo，J.C.S·; Electron Devices Meeting，1994. Technical Digest，International，11-14 Dec. 1994)。 然此些專利大都是利用上閘極（TOP Gate)之傳統矽覆絕緣 金氧半架構，不是利用極浪費面積及成本之本體缚點技術， 就是需要複雜且較昂貴之挖深溝槽技術來形成本體缚點。 無法有效降低製程成本。 另外，Bottom Gate架構的專利有（參考美國專利第 6，160,268號和第6,380,01 1號），雖然可達到舒緩門檻電壓下 降的目的，但此兩件專利有著傳統Bottom Gate架構，源極 端之金屬接觸端並未被設計與通道本體接觸，造成元件具 有嚴重的浮體效應、且具有太大截面積之PN接面，形成較 大的寄生電容和較大的漏電流路徑、其崩潰電壓也因此偏 低。同時因閘極層12與汲極部162彼此靠得太近造成Miller Capacitance太大減損元件交流性能的缺點。 因此，有必要提供一種創新且具進步性的矽覆絕緣金屬 氧化半導體裝置，以解決上述問題。 【發明内容】 本發明之目的在於提供一種具優質本體缚點之矽覆絕緣 金屬氧化半導體裝置，包括：一基板、一閘極層、一閘極 氧化層、一邊襯、一具導電之半導體層及一第一金屬電極。 該閘極層形成於該基板上。該閘極氧化層形成於該閘極層 上。該邊襯形成於該閘極層之侧邊。該具導電之半導體層 形成於該閘極氧化層及該邊襯之上。該半導體層具有一通 100434.doc 1255552 道本體、一源極部及一汲極部。該第一金屬電極形成於部 分之該通道本體上，用以與該通道本體接觸。 本發明之另一目的在於提供一種具優質本體缚點之矽覆 =緣金屬氧化半導體裝置之製作方法，包括以下步驟：（勾 提供一基板；（b)形成一閘極層於該基板之上；（c)形成一邊 襯於忒閘極層之側邊，（d)形成一閘極氧化層於該閘極層之 上；（e)形成一具導電之半導體層於該閘極氧化層、該邊襯 上，該具導電之半導體層具有一通道本體、一源極部及一 汲極部，及（f)形成一第一金屬電極於部分之該通道本體 上’用以與該通道本體接觸。 本發明之具優質本體缚點之矽覆絕緣金屬氧化半導體裝 置，使該第一金屬電極直接與該通道本體接觸，為一種無 須浪費面積之優質本體缚點，且可使裝置兼顧到能與未來 之3D立體製程技術整合，讓製程成本大大降低。同時也舒 緩自體加熱的問題及增加元件崩潰電壓。此外，也解決部 分空乏式SOI(Partial Depleted SOI MOSFET)因假中性區聚 積碰撞游離載子所造成之輸出特性曲線有紐結（Kink)的現 象。因此，本發明之具優質本體缚點之矽覆絕緣金屬氧化 半導體裝置不論為全空乏式S〇I(Fully Depleted SOI MOSFET)或部分空乏式SOI，都完全解決所謂的浮體效應 (Floating Body Effect) 〇 【實施方式】 請參閱圖2，其顯示本發明第一實施例之具優質本體缚點 (Smart body tie)之矽覆絕緣（SOI)金屬氧化半導體裝置2〇之 100434.doc 1255552 不意圖，其包括··一基板21、一閘極層22、一邊襯23、一 閘極氧化層24、一具導電之半導體層26、一保護層27、一 弟一金屬電極28及一第二金屬電極29。 該基板21可為矽覆絕緣（SC)I)基板（如SIM〇x，beSOI，或 SmartCut等SOI基板）、鍺覆絕緣⑴⑴）基板、晶圓基板、玻 璃基板、塑膠基板、藍寶石（Sapphire)基板、鑽石基板或m —V族基板等。也可以是利用3D立體製程技術將元件一層 一層地做在晶圓上，而最上面為低〖之中間介電層的基板。 另外，有些基板（例如SOI基板）其最下面為一基底層，中 間為絕緣埋層，其上面具有可導電之半導體層。再者，有 些基板（如玻璃基板）具有一絕緣基底，其上具有或可成長一 層導電之半導體薄層。而傳統普通晶圓基板，其基板即為 基底，必須先成長埋入氧化層，而可導電之半導體層就直 接再形成於該埋入氧化層上。 本發明第一實施例之該基板21具有一基底211及一埋入 氧化層212。該埋入氧化層212形成於該基底211之上。該閘 極層22形成於該基板21之該埋入氧化層212之上。該邊襯係 形成於該閘極層22之側邊。該閘極氧化層24形成於閘極層 22之上。該閘極層22可為製程允許之多層架構，例如··具 有一多晶矽層及一金屬矽化物層，該金屬矽化物層係於該 多晶矽層上。 該具導電之半導體層26形成於該邊襯23、該閘極氧化層 24之上。該具導電之半導體層26具有一通道本體25、一源 極部26卜一汲極部262、一源極接面263及一汲極接面264。 100434.doc -10- 1255552 該通道本體25係於該閘極氧化層24上之相對位置。該源極 部261及該汲極部262係於該通道本體25之側邊。該源極接 面263係為該通道本體25與該源極部261間之接面，該汲極 接面264係為該通道本體乃與該汲極部262間之接面。 該第一金屬電極28係為一源極接觸端，其形成於部分之 該通道本體25及部分之該源極部261上。該第二金屬電極29 係為；及極接觸端’形成於部分之該沒極部2 6 2上。該保護 層27係形成於部分之該通道本體25、部分之該源極部261 及部分之該汲極部2 6 2上。 由於該第一金屬電極28與該通道本體25接觸，為一種無 須浪費面積之優質本體缚點，因此本發明第一實施例之具 優貝本體缚點之矽覆絕緣金屬氧化半導體裝置2〇具有消除 浮體效應、ι-ν特性曲線也無紐結現象（Kink_effect)且具有 朋/貝電壓車父大、雙極性抓回崩潰（Bip〇lar_snap breakdown)延後發生等優點，因此可應用在傳統低成本之 石夕晶圓基板上，大幅降低製作高性能電路單晶片系統之成 本。 本發明第一實施例之具優質本體缚點之矽覆絕緣金屬氧 化半導體裝置20，其製作方式首先提供一矽晶圓基板2 j， 接著在基板上形成一絕緣埋入氧化層212，然後地毯式沉積 多晶矽且定義閘極形成約1〇 nm至300 nm(奈米）之閘極層 22 ’該閘極層22具有適當高摻雜濃度以使門檻電壓 (Threshold Voltage)最佳化。 该邊襯23及該閘極氧化層24可利用相同之製程一併形 100434.doc -11 - 1255552 成’ 5亥邊襯23及該閘極氧化層之沉積厚度約為〇. 5 nm至2Ο〇 nm之間。該具導電之半導體層26可利用如低溫低壓之化學 氣相沉積（LPCVD)方法、濺鍍、或電漿加強化學氣相沈積 等方法形成，並且係地毯式地形成於該邊襯23及該閘極氧 化層24之上’其厚度約為nm至300 nm。 利用一活性主動區之光罩（Mask)保護該通道本體25和該 閘極層22，再進行源極與汲極之離子佈植，俾於該具導電 之半導體層26中界定該通道本體25、該源極部261及該汲極 部262。為了有效降低源/汲極之串接電阻，離子佈植方法 的能量和劑量需要作適當的調整，以便在緊接著的適當溫 度下進行熱修護（Thermal Annealing)製程，以形成最適當之 該源極接面263及該汲極接面264。 接著沉積厚度約1〇〇 11111至5〇〇 nm之間之TEOS保護層 27 ’該保護層27可為含硼，含氟，或含硼磷之二氧化矽層 或適當之低K值材質。該保護層27係形成於部分之該通道本 體25、部分之該源極部26丨及部分之該汲極部262上。然後 形成该第一金屬電極28於部分之該通道本體25及部分之該 源極部261上，並且形成該第二金屬電極29於部分之該汲極 部262上。最後沉積並定義金屬層作為連線和焊墊（ρ“），以 構成本發明第一實施例之具優質本體缚點之矽覆絕緣金屬 氧化半導體裝置20。 參考圖3，其顯示本發明第二實施例之具優質本體缚點之 石夕覆纟巴緣金屬氧化半導體裝置3〇之示意圖。相較於第一實 施例之具優質本體缚點之矽覆絕緣金屬氧化半導體裝置 100434.doc -12- 1255552 20 ’本發明第二實施例之具優質本體缚點之矽覆絕緣金屬 氧化半導體裝置3〇係另利用一電漿活性離子蝕刻步驟，用 以削薄鄰近該源極接面363之部分該源極部36 1與部分該通 道本體35 ’以及削薄鄰近該汲極接面364之部分該汲極部 362與部分該通道本體35。 由於本發明第一實施例之具優質本體缚點之矽覆絕緣金 屬氧化半導體装置2〇中無任何PN接面區域（例如源極接面 及汲極接面）被氧化層所取代，因此pN接面面積太大導致有 漏電流和PN接面電容問題。因此，本發明第二實施例之具 優質本體缚點之矽覆絕緣金屬氧化半導體裝置3 0挖除鄰近 該源極接面363之部分該源極部361與部分該通道本體35， 以形成該第一金屬電極，並且挖除鄰近該汲極接面364之部 分該汲極部362與部分該通道本體35，以供置入絕緣材質材 料如二氧化矽、氮化矽或低尺值材質等。因此，本發明第二 貫施例之具優質本體缚點之矽覆絕緣金屬氧化半導體裝置 2〇可去除大部分通道本體35與源極部361及汲極部362接觸 之PN接面區域，使漏電流及接面電容大幅降低。 麥考圖4，其顯示本發明第三實施例之具優質本體缚點之 石夕覆絕緣金屬氧化半導體裝置4G之示意圖。相較於第二實 轭例之具優質本體缚點之矽覆絕緣金屬氧化半導體裝置 30本發明第二實施例之具優質本體缚點之矽覆絕緣金屬 虱化半導體裝置40係僅削薄鄰近該源極接面463之部分該 源極邛461與部分該通道本體45。本發明第三實施例之具優 為本體缚點之矽覆絕緣金屬氧化半導體裝置4〇仍能具有上 100434.doc -13- 1255552 述第二實施例之具優質本體缚點之矽覆絕緣金屬氧化半導 體裝置30之功效，然而元件可能變成不具對稱性。 請苓閱圖5，其顯示本發明第四實施例之具優質本體缚點 之石夕覆絕緣金屬氧化半導體裝置50之示意圖。相較於之前 之第一至第三實施例，本發明第四實施例之具優質本體缚 二占之秒復絕緣金屬氧化半導體裝置5 0具有一較大之邊概 5 3 形成於该閘極層52之側邊，以降低嚴重之MillerApproach Implement O.lum MOSFET on Thin-Film SOI Substrate with Self-Aligned Source Body Contact'',Chen,VMC·; Woo,JCS·; Electron Devices Meeting,1994. Technical Digest,International,11-14 Dec. 1994) . However, most of these patents use the traditional 矽 Gate's traditional 绝缘-insulated gold-oxide half-architecture. They are not using the extremely wasteful area and cost of the bulk-bound technology, which requires complicated and expensive deep trench technology to form. The body is bound. Unable to effectively reduce process costs. In addition, the Bottom Gate architecture patents (refer to US Patent Nos. 6,160,268 and 6,380,01 1), although the purpose of soothing the threshold voltage drop can be achieved, but the two patents have the traditional Bottom Gate architecture, the source of extreme The metal contact end is not designed to be in contact with the channel body, causing the component to have a serious floating body effect and a PN junction having a large cross-sectional area, forming a large parasitic capacitance and a large leakage current path, and the breakdown voltage thereof Therefore it is low. At the same time, because the gate layer 12 and the drain portion 162 are too close to each other, the Miller Capacitance is too large to detract from the communication performance of the component. Therefore, it is necessary to provide an innovative and progressive insulating metal oxide semiconductor device to solve the above problems. SUMMARY OF THE INVENTION An object of the present invention is to provide a high-quality bulk-bonded insulated metal oxide semiconductor device comprising: a substrate, a gate layer, a gate oxide layer, a side liner, and a conductive semiconductor layer And a first metal electrode. The gate layer is formed on the substrate. The gate oxide layer is formed on the gate layer. The edge liner is formed on a side of the gate layer. The electrically conductive semiconductor layer is formed over the gate oxide layer and the lining. The semiconductor layer has a pass 100434.doc 1255552 track body, a source portion and a drain portion. The first metal electrode is formed on a portion of the channel body for contacting the channel body. Another object of the present invention is to provide a method for fabricating a germanium-covered metal oxide semiconductor device having a high-quality body point, comprising the steps of: (providing a substrate; (b) forming a gate layer on the substrate; (c) forming a side lining the side of the gate layer, (d) forming a gate oxide layer over the gate layer; (e) forming a conductive semiconductor layer on the gate oxide layer, The conductive semiconductor layer has a channel body, a source portion and a drain portion, and (f) a first metal electrode is formed on the portion of the channel body to serve with the channel body The present invention has a high-quality body-bonded-covered insulating metal oxide semiconductor device, so that the first metal electrode directly contacts the channel body, which is a high-quality body binding point without waste of area, and can make the device take into consideration Integration with future 3D process technology, which greatly reduces the cost of the process. It also relieves the problem of self-heating and increases the component breakdown voltage. In addition, it also solves the problem of partially depleted SOI (Partial Depleted SOI MOSFET). The output characteristic curve caused by the accumulation of the pseudo-neutral zone colliding with the free carrier has a Kink phenomenon. Therefore, the present invention has a high-quality bulk-bonded insulating metal oxide semiconductor device, regardless of the full-vacancy type S〇I. (Fully Depleted SOI MOSFET) or partially depleted SOI, completely solve the so-called floating body effect 实施 [Embodiment] Please refer to FIG. 2, which shows the high-quality body binding point of the first embodiment of the present invention ( Smart body tie (SOI) metal oxide semiconductor device 2 〇 100434.doc 1255552 It is not intended to include a substrate 21, a gate layer 22, a side liner 23, a gate oxide layer 24, a conductive semiconductor layer 26, a protective layer 27, a second metal electrode 28 and a second metal electrode 29. The substrate 21 can be a blanket insulated (SC) I) substrate (such as SIM〇x, beSOI, or SOI substrate such as SmartCut), insulating (1) (1) substrate, wafer substrate, glass substrate, plastic substrate, sapphire substrate, diamond substrate or m-V substrate. It is also possible to use a 3D stereo process technology to layer the components layer by layer on the wafer, and at the top is a substrate with a low dielectric layer. In addition, some substrates (e.g., SOI substrates) have a base layer at the bottom and an insulating buried layer at the bottom with an electrically conductive semiconductor layer thereon. Further, some of the substrates (e.g., glass substrates) have an insulating substrate having or capable of growing a thin layer of electrically conductive semiconductor. In the conventional conventional wafer substrate, the substrate is a substrate, and the oxide layer must be buried first, and the conductive semiconductor layer is directly formed on the buried oxide layer. The substrate 21 of the first embodiment of the present invention has a substrate 211 and a buried oxide layer 212. The buried oxide layer 212 is formed over the substrate 211. The gate layer 22 is formed over the buried oxide layer 212 of the substrate 21. The edge liner is formed on the side of the gate layer 22. The gate oxide layer 24 is formed over the gate layer 22. The gate layer 22 can be a multilayer structure that is allowed in the process, for example, having a polysilicon layer and a metal halide layer, the metal halide layer being attached to the polysilicon layer. The conductive semiconductor layer 26 is formed on the edge liner 23 and the gate oxide layer 24. The conductive semiconductor layer 26 has a channel body 25, a source portion 26, a drain portion 262, a source junction 263 and a drain junction 264. 100434.doc -10- 1255552 The channel body 25 is in a relative position on the gate oxide layer 24. The source portion 261 and the drain portion 262 are attached to the side of the channel body 25. The source contact surface 263 is a junction between the channel body 25 and the source portion 261. The gate contact surface 264 is a junction between the channel body and the drain portion 262. The first metal electrode 28 is a source contact end formed on a portion of the channel body 25 and a portion of the source portion 261. The second metal electrode 29 is formed; and the pole contact end is formed on the portion of the non-pole portion 262. The protective layer 27 is formed on a portion of the channel body 25, a portion of the source portion 261, and a portion of the drain portion 262. Because the first metal electrode 28 is in contact with the channel body 25, it is a high-quality body binding point that does not need to waste area. Therefore, the first embodiment of the present invention has a 贝 本体 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘Eliminating the floating body effect, the ι-ν characteristic curve also has no kink phenomenon (Kink_effect) and has the advantages of a big/birth voltage, a bipolar retraction collapse (Bip〇lar_snap breakdown), and so on, so it can be applied to the traditional On the low-cost Shihwa wafer substrate, the cost of producing a high-performance circuit single-wafer system is greatly reduced. The first embodiment of the present invention has a high-quality body-bonded insulating metal oxide semiconductor device 20, which is firstly provided with a germanium wafer substrate 2 j, and then an insulating buried oxide layer 212 is formed on the substrate, and then the carpet is The polysilicon is deposited and the gate is formed to form a gate layer 22' of about 1 〇 nm to 300 nm (nano). The gate layer 22 has a suitably high doping concentration to optimize the Threshold Voltage. The edge liner 23 and the gate oxide layer 24 can be formed by the same process 100432.doc -11 - 1255552 into a '5 sided lining 23 and the gate oxide layer has a deposition thickness of about 5. 5 nm to 2 Ο. 〇nm between. The conductive semiconductor layer 26 can be formed by a method such as low temperature and low pressure chemical vapor deposition (LPCVD), sputtering, or plasma enhanced chemical vapor deposition, and is formed on the side liner 23 and the carpet. Above the gate oxide layer 24, its thickness is about nm to 300 nm. The channel body 25 and the gate layer 22 are protected by a mask of an active active region, and ion implantation of the source and the drain is performed, and the channel body 25 is defined in the conductive semiconductor layer 26. The source portion 261 and the drain portion 262. In order to effectively reduce the source/drain connection resistance, the energy and dose of the ion implantation method need to be appropriately adjusted to perform a thermal Annealing process at an appropriate temperature immediately thereafter to form the most appropriate one. The source junction 263 and the drain junction 264. Next, a TEOS protective layer 27' having a thickness of between about 1 〇〇 11111 and 5 Å is deposited. The protective layer 27 can be a boron-containing, fluorine-containing, or boron-containing phosphorus-containing cerium oxide layer or a suitable low-k material. The protective layer 27 is formed on a portion of the channel body 25, a portion of the source portion 26, and a portion of the drain portion 262. The first metal electrode 28 is then formed on a portion of the channel body 25 and a portion of the source portion 261, and the second metal electrode 29 is formed on the portion of the drain portion 262. Finally, a metal layer is deposited and defined as a wiring and a pad (ρ") to constitute a high-quality bulk-bonded insulating metal oxide semiconductor device 20 of the first embodiment of the present invention. Referring to FIG. 3, the present invention is shown. A schematic diagram of a metal oxide semiconductor device having a high-quality body-bonded point of the embodiment of the present invention. The insulating metal oxide semiconductor device having a high-quality body-bound point is compared with the first embodiment 100434.doc - 12- 1255552 20 'The second embodiment of the present invention has a high-quality body-bonded-clad insulating metal oxide semiconductor device 3, which further utilizes a plasma active ion etching step for thinning adjacent to the source junction 363 a portion of the source portion 36 1 and a portion of the channel body 35 ′ and a portion of the drain portion 362 and a portion of the channel body 35 that are thinned adjacent to the drain contact surface 364. Because of the high quality of the first embodiment of the present invention No PN junction region (such as source junction and drain junction) is replaced by an oxide layer, so the pN junction area is too large to cause leakage current and PN. The problem of the junction capacitance. Therefore, the insulating metal oxide semiconductor device 30 with the high-quality body-bound point of the second embodiment of the present invention digs a portion of the source portion 361 adjacent to the source junction 363 and a portion of the channel body 35, to form the first metal electrode, and to remove a portion of the drain portion 362 and a portion of the channel body 35 adjacent to the drain contact surface 364 for placing an insulating material such as cerium oxide, tantalum nitride or Therefore, the second embodiment of the present invention has a high-quality body-bonded insulating metal oxide semiconductor device 2 that can remove most of the channel body 35 from the source portion 361 and the drain portion 362. The PN junction region greatly reduces the leakage current and the junction capacitance. McCorm 4, which shows a schematic diagram of a high-quality body-bonded ferrule-insulated metal oxide semiconductor device 4G according to the third embodiment of the present invention. The second embodiment of the present invention provides a high-quality bulk-bonded insulating metal oxide semiconductor device 30. The second embodiment of the present invention has a high-quality bulk-bonded insulating metal germanium semiconductor device 40 which is thinned only adjacent to the source. The portion of the surface 463 is the source 邛 461 and a portion of the channel body 45. The 绝缘-insulated metal oxide semiconductor device 4 of the third embodiment of the present invention having excellent body-bound points can still have the upper 100434.doc -13 - 1255552 The second embodiment has the effect of covering the insulating metal oxide semiconductor device 30 with a high-quality body-bound point, but the element may become non-symmetric. Please refer to FIG. 5, which shows a high-quality body of the fourth embodiment of the present invention. A schematic diagram of a point-insulated insulating metal oxide semiconductor device 50. Compared with the first to third embodiments, the fourth embodiment of the present invention has a high-quality bulk-bonded second-time complex insulating metal oxide semiconductor device 50. There is a larger side 5 3 formed on the side of the gate layer 52 to reduce the serious Miller
Capacitance 問題。 另外，本發明第四實施例之具優質本體缚點之矽覆絕緣 金屬氧化半導體裝置5〇係削薄鄰近該源極接面563之部分 該源極部561與全部之該通道本體55，以及削薄鄰近該汲極 接面564之部分該汲極部562。因此，本發明第四實施例之 具優質本體缚點之矽覆絕緣金屬氧化半導體裝置5 〇仍能達 成上述第二實施例之具優質本體缚點之矽覆絕緣金屬氧化 半導體裝置30之功效。 ί考圖6A至圖6D，其顯示本發明第四實施例之具優質本 體缚點之石夕覆絕緣金屬氧化半導體裝置5〇之製作方法示意 圖。參考圖6Α，首先提供—基板5卜基板51具有-基底511 及一埋入氧化層512。閘極層52形成於基板51之上。該閉極 ri可為單純尚摻雜多晶矽層。閘極層52亦可為製程允 才之夕層架構例如：具有—多晶石夕層及一金屬石夕化物層之 組合。開極層52係形成相對於該基板51位置之埋入氧:層 512之上。5亥閘極層52具有適當高摻雜濃度或在製程考量;亏 染許可下用適當功函數（work function)之單層或多層之不 u 100434.doc 14 1255552 同金屬來取代，以使門檻電壓（丁匕以11〇1(1%1仏#)最佳化。 苓考圖6B，利用邊襯（spacer)技術在該閘極層62之側邊形 成一邊襯53。參考圖6C，該閘極氧化層54係利用熱氧化技 術地毯式形成於該閘極層52之上。該具導電之半導體層 56，可利用如低溫低壓之化學氣相沉積（LpcvD)方法、濺 鍍、或電漿加強化學氣相沈積等方法形成，且係形成於該 基板5 1、该邊襯5 3及該閘極氧化層5 4之上。再利用活性離 子蝕刻（RIE)技術定義出該具導電之半導體層兄中間之薄 層區61。此薄層區61厚度愈小愈好，可類似超薄矽層之s〇I 金氧半元件之本體。 爹考圖6D，為進行源極部561與汲極部562之離子佈植， 首先地毯式蒸鍍一層離子佈植散射用之二氧化石夕層62(或 其它他低κ值材質），定義一光罩63以保護該閘極層52與該 通道本體層55。隨後利用離子佈植技術於該具導電之半導 體層56形成一源極部561及一汲極部562。該源極部561及没 極部562之中間為該通道本體55。 為了有效降低源/汲極之串接電阻，離子佈植方法的能量 和劑量需要作適當的調整，以便在緊接著之後的適當高溫 下進行熱修護（Thermal Annealing)製程，以形成最適當的該 源極接面563及該汲極接面564。 该具導電之半導體層56之該通道本體（channel)55係形成 於閘極氧化層54之上，該源極部561及該汲極部562係分別 形成於該通道本體（channel)5 5之側邊，且於部分埋入氧化 層512之上。具導電之半導體層56之厚度為3〇 nm或更大。 100434.doc -15- !255552 邊具導電之半導體層56係選自由第四族或m_v族材料所組 成之群，如S!，Ge、SlC、SiGe、."GaAs等以增加金屬氧化 半導體裝置之移動率。亦可形成雙或多層來形成制張力或 " 縮力（Strain)來加強金屬氧化半導體裝置通道層之载子移動 • 率。 夕 * 苓考圖5，接著沉積厚度約100 nm至500 nm之間之TE〇s 保護層57，該保護層57可為含硼，含氟，或含硼磷之二氧 φ 化矽層或適當之低K值材質。該保護層57係形成於部分之該 通道本體55、部分之該源極部561及部分之該汲極部 上。然後形成該第一金屬電極58於部分之該通道本體55及 部分之該源極部561上，並且形成該第二金屬電極59於部分 之該汲極部562上，以構成本發明第四實施例之具優質本體 缚點之矽覆絕緣金屬氧化半導體裝置5〇。 因此，本發明具優質本體縛點之矽覆絕緣金屬氧化半導 體裝置具有低漏電流、低寄生接面電容、無浮體效應和紐 結效應（Kink effect)，且易舒緩因自體加熱而產生之熱能， 以解決自體加熱之問題。此外，可增加崩潰電壓及能壓制 超短通道效應，且能舒緩因元件尺寸縮小而使得門檻電壓 下降的情形。另外，利用本發明之製作方法，可以簡化製 程步驟，並可應用於3D立體製程技術。 另外值得注意的是為了克服因閘極與汲極為爭奪空乏區 之控制能力『電荷共享（charge sharing)』所造成之門檻電 壓下降（Vth Roll-off)，本發明具優質本體缚點之矽覆絕緣 金屬氧化半導體裝置利用接地的局部超薄通道層本體來克 100434.doc -16- 1255552 服超短通道效應，使得本發明具優質本體缚點之石夕覆絕緣 金屬氧化半導體裝置之門檻電壓變化是僅隨著該局部通道 薄層（thnifUm)之厚度遞減而些許增加。換言之，本發明具 優質本體缚點之矽覆絕緣金屬氧化半導體裝置之門檻電壓 不官是長通道、或是甚至極短之1〇奈米通道都有接近相等 的值，幾無超短通道效應，亦即幾無傳統此仏m〇sfei^ 傳統SOIMOSFET之門檻電壓嚴重遞減iR〇11 〇ff現象。 惟上述實施例僅為說明本發明之原理及其功效，而非用 以限制本發明。因此，習於此技術之人士可在不達背本發 明之精神對上述實施例進行修改及變化。本發明之權利範 圍應如後述之申請專利範圍所列。 【圖式簡單說明】 圖1為習知之薄膜電晶體示意圖； 圖2為本發明第一實施例之具優質本體缚點之石夕覆絕緣 金屬氧化半導體裝置之示意圖； 圖3為本發明第二實施例之具優質本體缚點之石夕覆絕緣 金屬氧化半導體裝置之示意圖； 圖4為本發明第三實施例之具優質本體缚點之石夕覆絕緣 金屬氧化半導體裝置之示意圖； 圖5為本發明第四實施例之具優質本體缚點之石夕覆絕緣 金屬氧化半導體裝置之示意圖； 圖6A至6D為本發明第四實施例之具優質本體縛點之石夕 覆絕緣金屬氧化半導體裝置之製作方法示意圖。 【主要元件符號說明】 100434.doc -17- 習知之薄膜電晶體 基板 閘極層 邊襯 閘極氧化層 通道本體 具導電之半導體層 保護層 源極接觸端 汲極接觸端 本發明第一實施例之具優質本體缚點之矽覆 絕緣金屬氧化半導體裝置 基板 閘極層 邊概 閘極氧化層 通道本體 具導電之半導體層 保護層 第一金屬電極 第二金屬電極 (§) 本發明第二實施例之具優質本體缚點之矽覆 絕緣金屬氧化半導體裝置 通道本體 -18- 1255552 40 本發明第三實施例之具優質本體縛點之矽覆 絕緣金屬氧化半導體裝置 45 通道本體 50 本發明第四實施例之具優質本體缚點之矽覆 絕緣金屬氧化半導體裝置 51 基板 52 閘極層 5 3 邊概Capacitance issue. In addition, in the fourth embodiment of the present invention, the insulating metal oxide semiconductor device 5 having a high-quality body-bonding point is used to thin the portion of the source portion 561 adjacent to the source contact surface 563 and all of the channel body 55, and A portion of the drain portion 562 adjacent to the drain contact 564 is thinned. Therefore, the overlying insulating metal oxide semiconductor device 5 of the fourth embodiment of the present invention having the high-quality bulk point can still achieve the effect of the above-described second embodiment of the insulating metal oxide semiconductor device 30 having the high-quality bulk point. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 6A to Fig. 6D are views showing a manufacturing method of a stellite-insulated insulating metal oxide semiconductor device 5 of a fourth embodiment of the present invention. Referring to FIG. 6A, first, the substrate 5 is provided with a substrate 511 and a buried oxide layer 512. The gate layer 52 is formed over the substrate 51. The closed-pole ri can be a simple doped polysilicon layer. The gate layer 52 can also be a process layer structure, for example, having a combination of a polycrystalline layer and a metal layer. The open layer 52 is formed over the buried oxygen: layer 512 at a location relative to the substrate 51. The 5th gate layer 52 has a suitable high doping concentration or is considered in the process; under the permission of the dyeing, a single layer or a plurality of layers of a work function is used instead of 100434.doc 14 1255552 to replace the metal to make the threshold The voltage (Ding is optimized by 11〇1 (1%1仏#). Referring to Fig. 6B, a side liner 53 is formed on the side of the gate layer 62 by a spacer technique. Referring to Fig. 6C, The gate oxide layer 54 is formed on the gate layer 52 by a thermal oxidation technique. The conductive semiconductor layer 56 can be subjected to a low temperature and low pressure chemical vapor deposition (LpcvD) method, sputtering, or electricity. Formed by slurry enhanced chemical vapor deposition, etc., and formed on the substrate 51, the edge liner 53 and the gate oxide layer 54. The conductive ion etching (RIE) technique is used to define the conductive The thin layer region 61 in the middle of the semiconductor layer brother. The thickness of the thin layer region 61 is as small as possible, and can be similar to the body of the s〇I gold-oxygen half element of the ultra-thin layer. Referring to FIG. 6D, the source portion 561 is used. The ion implantation of the bungee portion 562, firstly, a carpet-type evaporation of a layer of ion dioxide implants for the ion dioxide layer 62 ( Or other low-k materials, a mask 63 is defined to protect the gate layer 52 and the channel body layer 55. Then, a source portion 561 and a source portion 56 are formed on the conductive semiconductor layer 56 by ion implantation. The drain portion 562. The middle of the source portion 561 and the non-polar portion 562 is the channel body 55. In order to effectively reduce the source/drain connection resistance, the energy and dose of the ion implantation method need to be appropriately adjusted so that A Thermal Annealing process is performed at a suitable high temperature immediately thereafter to form the most appropriate source junction 563 and the gate junction 564. The channel body of the conductive semiconductor layer 56 (channel) 55 is formed on the gate oxide layer 54. The source portion 561 and the drain portion 562 are respectively formed on the side of the channel 55 and partially buried on the oxide layer 512. The conductive semiconductor layer 56 has a thickness of 3 〇 nm or more. 100434.doc -15- !255552 The conductive semiconductor layer 56 is selected from the group consisting of Group 4 or m_v materials, such as S! , Ge, SlC, SiGe, ."GaAs, etc. to increase metal oxide semiconductivity The mobility of the device. It is also possible to form two or more layers to form a tension or "Strain" to enhance the carrier mobility of the channel layer of the metal oxide semiconductor device. ** 苓 Figure 5, followed by a deposition thickness of about 100 The TE〇s protective layer 57 between nm and 500 nm, the protective layer 57 may be a boron-containing, fluorine-containing, or boron-containing phosphorus-dioxide layer or a suitable low-k material. Formed on a portion of the channel body 55, a portion of the source portion 561, and a portion of the drain portion. The first metal electrode 58 is then formed on a portion of the channel body 55 and a portion of the source portion 561, and the second metal electrode 59 is formed on the portion of the drain portion 562 to form a fourth embodiment of the present invention. For example, a high-quality body-bound point is covered with an insulating metal oxide semiconductor device. Therefore, the overlying insulated metal oxide semiconductor device with high quality body-bound points has low leakage current, low parasitic junction capacitance, no floating body effect and Kink effect, and is easy to be relieved by self-heating. The heat energy to solve the problem of self-heating. In addition, the breakdown voltage can be increased and the ultra-short channel effect can be suppressed, and the threshold voltage can be reduced due to the reduction in the size of the device. In addition, with the manufacturing method of the present invention, the process steps can be simplified and applied to the 3D stereo process technology. It is also worth noting that in order to overcome the threshold voltage drop (Vth Roll-off) caused by the gate charge and the enthalpy, which is the control capability of the charge-free zone, the present invention has a high-quality body-bound point. The insulating metal oxide semiconductor device utilizes a grounded local ultra-thin channel layer body to provide an ultrashort channel effect of 100434.doc -16 - 1255552, so that the threshold voltage of the invented metal oxide semiconductor device with high quality body binding points of the present invention is changed. It is only slightly increased as the thickness of the local channel thin layer (thnifUm) decreases. In other words, the threshold voltage of the insulated metal oxide semiconductor device with high-quality body-bound points of the present invention is a long channel, or even a very short one. The nanochannels have nearly equal values, and there are few ultra-short channel effects. That is, there is no such thing as this 仏m〇sfei^ The threshold voltage of the conventional SOIMOSFET is seriously decremented iR〇11 〇ff phenomenon. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, those skilled in the art can make modifications and changes to the above embodiments without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a conventional thin film transistor; FIG. 2 is a schematic view of a stone-covered insulating metal oxide semiconductor device having a high-quality body binding point according to a first embodiment of the present invention; FIG. 4 is a schematic diagram of a stellite-insulated metal oxide semiconductor device having a high-quality body binding point according to a third embodiment of the present invention; FIG. FIG. 6A to FIG. 6D are schematic diagrams showing a high-quality body-bound point of a stone-covered insulating metal oxide semiconductor device according to a fourth embodiment of the present invention; Schematic diagram of the production method. [Description of main component symbols] 100434.doc -17- A conventional thin film transistor substrate gate layer lining gate oxide layer channel body with conductive semiconductor layer protection layer source contact terminal drain contact end of the first embodiment of the present invention High-quality body-bonded layer-covered insulating metal oxide semiconductor device substrate gate layer side gate oxide layer channel body conductive semiconductor layer protective layer first metal electrode second metal electrode (§)矽 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 绝缘 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 -18 Example of a high-quality body-bonded 矽-covered insulating metal oxide semiconductor device 51 substrate 52 gate layer 5 3
54 閘極氧化層 55 通道本體 56 具導電之半導體層 57 保護層 58 第一金屬電極 59 第二金屬電極 61 薄層區 62 二氧化矽層 63 光罩 161 源極部 162 汲極部 163 源極接面 164 汲極接面 211 基底 212 埋入氧化層 261 源極部 100434.doc -19- 125555254 gate oxide layer 55 channel body 56 with conductive semiconductor layer 57 protective layer 58 first metal electrode 59 second metal electrode 61 thin layer region 62 ruthenium dioxide layer 63 photomask 161 source portion 162 bungee portion 163 source Junction 164, drain junction 211, substrate 212, buried oxide layer 261, source portion 100434.doc -19- 1255552
262 汲極部 263 源極接面 264 汲極接面 361 源極部 362 汲極部 363 源極接面 364 汲極接面 461 源極部 463 源極接面 511 基底 512 埋入氧化層 561 源極部 562 汲極部 563 源極接面 564 汲極接面262 汲 263 263 source junction 264 drain junction 361 source portion 362 drain portion 363 source junction 364 drain junction 461 source portion 463 source junction 511 substrate 512 buried oxide layer 561 source Pole part 562 bungee part 563 source junction 564 bungee junction
100434.doc -20-100434.doc -20-