TWI252571B - Wire bonding process - Google Patents

Wire bonding process Download PDF

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Publication number
TWI252571B
TWI252571B TW093132004A TW93132004A TWI252571B TW I252571 B TWI252571 B TW I252571B TW 093132004 A TW093132004 A TW 093132004A TW 93132004 A TW93132004 A TW 93132004A TW I252571 B TWI252571 B TW I252571B
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Taiwan
Prior art keywords
wire
wafer
bonding
pads
pad
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TW093132004A
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Chinese (zh)
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TW200614472A (en
Inventor
Cheng-Lan Tseng
Cheng-Tsung Hsu
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Advanced Semiconductor Eng
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Priority to TW093132004A priority Critical patent/TWI252571B/en
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Publication of TWI252571B publication Critical patent/TWI252571B/en
Publication of TW200614472A publication Critical patent/TW200614472A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48475—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball
    • H01L2224/48476—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area
    • H01L2224/48477—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding)
    • H01L2224/48481—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a ball bond, i.e. ball on pre-ball
    • H01L2224/48482—Connecting portions connected to auxiliary connecting means on the bonding areas, e.g. pre-ball, wedge-on-ball, ball-on-ball between the wire connector and the bonding area being a pre-ball (i.e. a ball formed by capillary bonding) the connecting portion being a ball bond, i.e. ball on pre-ball on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85009—Pre-treatment of the connector or the bonding area
    • H01L2224/85051—Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

A wire bonding process is disclosed. A chip and a chip carrier are provided. The chip has at least one bonding pad. The chip carrier has at least one contact. A buffer bump is formed on the bonding pad of the chip. A bonding wire is formed by wire-bonding, to connect the buffer bump and the contact of the chip carrier. The hardness of the buffer bump is smaller than the hardness of the bonding wire for preventing damaging the bonding pad of the chip while wire-bonding.

Description

12525711252571

【發明所屬之技術領域】 本發明係有關於一種打線製程，特別係有關於一種防 止在打線時損傷晶片之打線製程及利用該打[Technical Field] The present invention relates to a wire bonding process, and more particularly to a wire bonding process for preventing damage to a wafer during wire bonding and using the same

半導體裝置。 I 【先前技術】Semiconductor device. I [Prior Art]

習知IC封裝製程中，係以複數個銲線連接一晶片與一 載板，该些銲線之連接穩定度之良窳，係關係到一電子產 口口之口口質’·§知打線製程，其係直接將該些銲線連接至該 晶^之複數個銲墊，因此使得該些銲墊直接承受打線時之 二壓二衝擊，而造成晶片受損，習知之打線製程如下，請 二閱第14圖、，其係提供_晶片11()及—晶片載板12()，該晶 a 具有複數個銲墊111，該晶片載板120具有複數個連 接，121，該晶片載板12〇係承載該晶片11();之後，請參 閱第1B圖，其係將穿過一銲針13〇之一銲線14〇(如金線）， 子點火等方式使該銲線14〇形成有一結球端141，並以 该銲針130將該結球端141熱壓合在該晶片11〇之該些銲墊 jii上:再移動該銲針130以引導該銲線14〇至該晶片載板 之^對應該些連接墊12 1，並在該些連接墊121上熱壓合 七7该銲線140而形成一尾端142，當該銲線14〇形成該結 =端141時，該銲針13〇係以一垂直向之壓合力撞擊該些銲 ^11，再以一水平向之拉力引導該銲線140，而使該銲線 上呈弧形’然而該銲針1 3 〇水平向引導該銲線1 4 0時，會 =f』知墊1 11承受一水平震動力，且由於該銲線丨4〇係被 ’有相當之硬度，以避免受模流造成沖線，當該銲線In the conventional IC packaging process, a plurality of bonding wires are used to connect a wafer and a carrier plate, and the connection stability of the bonding wires is good, which is related to the mouth quality of an electronic product mouth. The process is that the wire is directly connected to the plurality of pads of the crystal, so that the pads directly withstand the impact of the second pressure on the wire, and the wafer is damaged. The conventional wire bonding process is as follows, please Referring to Figure 14, there is provided a wafer 11 () and a wafer carrier 12 (), the crystal a has a plurality of pads 111, the wafer carrier 120 has a plurality of connections, 121, the wafer carrier 12〇 carries the wafer 11(); after that, please refer to FIG. 1B, which will pass through a soldering wire 13〇 one of the bonding wires 14〇 (such as gold wire), sub-ignition or the like to make the bonding wire 14〇 Forming a ball end 141, and thermally bonding the ball end 141 to the pads ji of the wafer 11 by the solder pin 130: moving the solder pin 130 to guide the wire 14 to the wafer The board is corresponding to the connection pads 12 1, and the bonding wires 140 are thermally pressed on the connection pads 121 to form a tail end 142, and the bonding wire 1 is formed. 4〇 When the junction=end 141 is formed, the soldering pin 13 strikes the soldering wires 11 with a vertical pressing force, and then guides the bonding wire 140 with a horizontal pulling force, so that the bonding wire is arced. However, when the welding pin 13 3 〇 horizontally guides the bonding wire 1 400, it will know that the pad 1 11 is subjected to a horizontal vibration force, and since the wire bonding wire 4 is 'having a considerable hardness, To avoid the punching caused by the mold flow, when the wire is

12525711252571

五、發明說明（2) 140之硬度被要求越高，則該些銲墊lu受該結球端141之 垂直向撞擊力及引導該銲線140之水平向震動力將會越 大’因此將對該晶片110之該些銲墊造成損傷/特別是 低介電常數（low-K)之晶片時，在該晶片内且接近該主^ 面之低介電常數介電層將更為跪性，不财應力，極易在打 線時發生銲墊或介電層破裂之情形，而導致電性連接不 良。 為提升電子產品之電性連接良率，我國專利公告第 465064號「打線製程及其結構」係揭示有—種先於&數 銲塾上形成堆疊之二凸塊後’再進行逆打線（revise bonding。)之製程，請參閱第2A圖，其係提供一晶片2ι〇及 一承載器220，該晶片21〇係具有複數個銲墊211，該 器220係具有複數個接點221，之後，請參閱第⑼圖/，7以一 打線機（圖未纟會出）進行二次垂直熱壓合動作，以 — 墊211先後形成一第一凸塊231與一第二凸塊2犯，並且'旱 该些第二凸塊2 3 2係堆疊於對應之該些第一凸塊2 3工， 著，請參閱第2C圖，再以相同之該打線機進行一打= 程，以形成複數個導線240 ,該打線機係自該承載器^·: 該些接點221移動至對應之該些第二凸塊232，每一σ 240係具有一結球端241與一尾端242，該些結球端“I _ 接於該承載器220之該些接點221，該些尾端24? “ 對應之該些第二凸塊232，即該些導線24〇係連接該承於哭 220之該些接點221至對應之該些第二凸塊㈡^，以二為 打線在堆疊凸塊上之半導體裝置200，由於該打線：：： 1252571 五、發明說明（3) 以熱壓合方式截斷該些導線24〇，以使該些導線24〇之尾端 2 4 2壓合連接該些第二凸塊2 3 2，因此該晶片2 i g之該㈣ 塾211係承文该打線機之三次之熱壓合，極 2 1 0之該些銲墊2 11損傷。 、力乂 乂日日月 【發明内容】 本發明之主要目的係在於提供一種打線製程，其係提 供一晶片及一晶片載板，該晶片係具有至少一銲墊，爷曰曰 片載板係具有至少一對應該鲜塾之接點，接著形成_緩二 凸塊於邊晶片之該銲墊，之後打線形成一銲線，以連接該 緩衝凸塊與該晶片載板之該接點，其中該緩衝凸塊之硬^ 係小於該銲線之硬度，由於該緩衝凸塊係先形成於該銲 墊，因此/當一銲針以較硬之該銲線之一結球端熱壓合銲 接於該緩衝凸塊時，該緩衝凸塊係可避免該結球端直接撞 擊該晶片之該銲墊，所以該打線製程係可被運用於以 電常數（low-K)製程所形成之晶片之打線連接，以防止咳 晶片之該銲墊受損。 ^V. Description of the Invention (2) The higher the hardness of 140 is required, the greater the impact force of the soldering pads lu by the ball end 141 and the horizontal vibration force guiding the bonding wire 140 will be When the pads of the wafer 110 cause damage/especially a low-k (low-K) wafer, the low-k dielectric layer in the wafer and close to the main surface will be more flexible. Without financial stress, it is easy to break the solder pad or the dielectric layer when the wire is wound, resulting in poor electrical connection. In order to improve the electrical connection yield of electronic products, China Patent Publication No. 465064 "Wire-laying Process and Structure" reveals that there is a type of bump that precedes the formation of a stack of solder bumps. For the process of revise bonding, please refer to FIG. 2A, which provides a wafer 2 〇 and a carrier 220. The wafer 21 has a plurality of pads 211, and the device 220 has a plurality of contacts 221, and then Please refer to the figure (9) /, 7 to perform a second vertical thermal pressing action with a wire punching machine (the figure is not shown), and the pad 211 successively forms a first bump 231 and a second bump 2, And a plurality of second bumps 2 3 2 are stacked on the corresponding first bumps 2, and please refer to FIG. 2C, and then a dozen strokes are performed by the same wire machine to form a plurality of wires 240 from the carrier ^·: the contacts 221 are moved to the corresponding second bumps 232, each σ 240 has a ball end 241 and a tail end 242, The ball ends "I _ are connected to the contacts 221 of the carrier 220, and the tail ends 24?" corresponding to the second bumps 23 2, that is, the wires 24 are connected to the contacts 221 of the crying 220 to the corresponding second bumps (2), and the second is the semiconductor device 200 on the stacked bumps. ::: 1252571 V. DESCRIPTION OF THE INVENTION (3) The wires 24 are cut off by thermocompression so that the ends 24 of the wires 24 are press-bonded to the second bumps 2 3 2 The (4) 塾 211 of the wafer 2 ig is the thermal compression of the wire bonding machine three times, and the pads 2 11 of the pole 2 10 are damaged. SUMMARY OF THE INVENTION The main object of the present invention is to provide a wire bonding process for providing a wafer and a wafer carrier having at least one bonding pad and a carrier film carrier. Having at least one pair of contacts that should be fresh, and then forming the pads of the second bumps on the edge wafer, and then bonding wires to form a bonding wire to connect the bump bumps to the contacts of the wafer carrier, wherein The hardness of the buffer bump is smaller than the hardness of the soldering wire. Since the buffer bump is formed on the solder pad first, when a soldering pin is soldered to the ball end of one of the hard soldering wires In the buffer bump, the buffer bump can prevent the ball end directly hitting the pad of the wafer, so the wire bonding process can be applied to the wire bonding of the wafer formed by the low-K process. To prevent damage to the solder pad of the cough chip. ^

本發明之次一目的係在於提供一種打線連接之半導體 衣置，其係包含有一晶片、一晶片載板、複數個緩衝凸塊 與複數個銲線，該晶片係具有複數個銲墊，該些緩衝凸塊 係形成於該晶片之對應該些銲塾，該些打線形成之銲線係 連接該些緩衝凸塊與該晶片载板之對應複數個接點，由於 該些銲線之硬度係大於該些緩衝凸塊之硬度，因此該些焊 線之線弧度較穩定並具有較長之線長能力，達到較佳之抗 模流能力，又因該些緩衝凸塊係間隔該些銲線與該些銲A second object of the present invention is to provide a wire bonding semiconductor device comprising a wafer, a wafer carrier, a plurality of buffer bumps and a plurality of bonding wires, the wafer having a plurality of pads, The buffer bumps are formed on the corresponding solder bumps of the wafer, and the solder wires formed by the wires are connected to the corresponding plurality of contacts of the buffer bumps and the wafer carrier, because the hardness of the solder wires is greater than The hardness of the buffer bumps, so that the wire arcs of the soldering wires are relatively stable and have a long line length capability, thereby achieving better resistance to mold flow, and because the buffer bumps are spaced apart from the solder lines Some welding

1252571 五、發明說明（4) "'〜 塾’以避免該些銲線直接熱壓合該些銲墊。 依本發明之打線製程，包含有，提供一晶片及一晶片 載板’該晶片係具有至少一銲墊，該晶片載板係具有至少 一對應該銲墊之接點；接著，形成一緩衝凸塊於該晶片之 該銲墊；之後，打線形成一銲線，以連接該緩衝凸塊與該 曰曰片載板之該接點，其中該緩衝凸塊之硬度係小於該銲線 f硬度’以防止打線時該晶片之該銲墊受衝擊及震動而損 壞’較佳地’邊銲線係以一結球端連接該緩衝凸塊。 【實施方式】 參閱所附圖式，本發明將列舉以下之實施例說明。 依本發明之一具體實施例，一種打線製程係被揭露如 下’請筝閱第3A圖，分別提供一晶片31 〇及一晶片載板 3 2 0 ’該晶片3 1 0係包含有至少一介電層3丨1，用以分隔不 同層之積體電路，在該介電層311上係形成有至少一銲墊 3 1 2 ’以供對外電性連接，在本實施例中，該晶片3丨〇係為 以低介電常數（1 ow -K )製程形成之晶片，故該介電層3丨1係 由低電#數材料所彡儿積形成’例如氣妙玻璃 (Fluorinated Silicate Glass，FSG)、黑鑽石（black diamond) 、BLOK(Barrier Low K)或FLARETM(fluorinated poly(arylethers))，通常一保護層313係形成於該介電層 311之上方並顯露該銲墊312。該晶片載板320係具有至少 一對應該銲墊31 2之接點321，該晶片31 〇係以黏著方式設 置於該晶片載板32 0上；請再參閱第3B圖，形成一緩衝凸 塊3 3 0於该晶片3 1 0之邊鲜塾31 2，在本實施例中，該缓衝1252571 V. Inventive Note (4) "'~ 塾' to avoid direct soldering of these pads to these pads. The wire bonding process of the present invention includes providing a wafer and a wafer carrier having at least one pad having at least one pair of pads to be soldered; and then forming a buffer bump Blocking the pad on the wafer; then, bonding the wire to form a bonding wire to connect the buffer bump to the contact of the die carrier, wherein the hardness of the buffer bump is less than the hardness of the wire f In order to prevent the pad of the wafer from being damaged by impact and vibration when the wire is struck, the 'better' edge wire is connected to the buffer bump by a ball end. [Embodiment] The present invention will be described by way of the following examples. According to an embodiment of the present invention, a wire bonding process is disclosed as follows: Please refer to FIG. 3A to provide a wafer 31 and a wafer carrier 3 2 0 respectively. The wafer 3 1 0 includes at least one medium. The electrical layer 3丨1 is used to separate the integrated circuits of different layers, and at least one pad 3 1 2 ′ is formed on the dielectric layer 311 for external electrical connection. In the embodiment, the wafer 3 is The tantalum is a wafer formed by a low dielectric constant (1 ow -K ) process, so the dielectric layer 3丨1 is formed by a low-powered material such as Fluorinated Silicate Glass. FSG), black diamond, BLOK (Barrier Low K) or FLARETM (fluorinated poly (arylethers)), usually a protective layer 313 is formed over the dielectric layer 311 and the pad 312 is exposed. The wafer carrier 320 has at least one pair of contacts 321 of the pads 31 2, and the wafers 31 are adhesively disposed on the wafer carrier 32 0; please refer to FIG. 3B to form a buffer bump. 3 3 0 is on the side of the wafer 3 10 0 , 31 2, in this embodiment, the buffer

第9頁 1252571 五、發明說明（5) 凸塊330之材質係包含有99. 9%以上之金，且該緩衝凸塊 330係以一第一銲針1〇打線形成，通常該第一銲針ι〇係能 =線形成線徑約在1. 〇mi 1且斷裂強度在丨〇g以下之軟線； 5月再芩閱第3C圖，將穿過一第二銲針2〇之一銲線34〇以電 子點火（Electronic Flame-Off, EF〇)或氫焰（Hydr〇gen 之方式，使該銲線34〇之—端燒結形成—結球端 地j，再將該結球端341以一壓合力熱壓合銲接於該缓衝凸 =30。在本實施射，由該第二銲聊所形成之鲜線34〇 係為線徑約在l.0mil且斷裂強度在14g以下之硬線。由 =旦該緩衝凸塊330與該銲線34〇之材質係參雜不同比例之 f置元素作適當之軟硬度調整，以使該緩衝凸塊33〇之硬 於該銲線340，以達到柔軟緩衝之功效。故該缓衝 凸係能吸收該銲線34〇之該結球端341熱壓合之垂直 力Λ亚可避免該結球端341直接撞擊該晶片310之該 二说㈣’请再參閱第3D圖’移動該第二鲜針20以引導該 ^線340至該接點321，並以該第二銲針2〇熱壓合該鲜線 H f321 ,以使該銲線340銲接於該接點32丨上，較 二夫關線340係成弧形連接該銲墊312與該接點321 ; 口月爹閱第3 Ε圖，以該繁-程料9 Π A + aw 々弟一卸針在该接點321上截斷該銲 線340，而使該銲線34〇形成有一尾端。 半導第3Ε圖，利用上述打線製程完成打線連接之 福射個ί你，其係包含該晶片3 1 0、該晶片載板320、 俜Λ 及複數個打線形成之銲線340，該晶片 1〇係八有稷數個銲墊312及該保護層313，該晶片載板32〇 1252571 五、發明說明（6) 係具有複數個接點321，該些緩衝凸塊330係形成於該晶片 310之該些銲墊312，每一銲線340係具有一結球端341及一 尾端342，該些結球端341係連接於對應之該些緩衝凸塊 330，該些尾端342係連接於對應之該些接點32i，即該些 銲線340係連接該些緩衝凸塊33〇與該晶片載板32〇之對應 該些接點3 2 1。 〜 在上述之打線製程中，由於該緩衝凸塊33〇係先形成 於該銲墊312，因此，當該第二銲針2〇以較硬之該銲線34〇 之该結球端341熱壓合銲接於該缓衝凸塊33〇時，該緩 3〇畫係^避敏免§亥鲜塾31 2直接承受熱慶合該結球端341時 310之該銲墊312受損;1由於該打線連接4=匕片 線弧度較為穩定且具有較此該些銲線340之 力較強。 另杈長之線長旎力，並且其抗模流能 本發明之保護範圍當滿銘 為準，任何熟知此項技藝：後：：申請專利範圍所界定者 圍内所作之任何變化與修脫離本發明之精神和範 " ’句屬於本發明之保護範圍。Page 9 1252571 V. Description of the Invention (5) The material of the bump 330 is more than 99.9% of the gold, and the buffer bump 330 is formed by a first soldering pin 1 , usually the first solder Needle 〇 能 = = line forming a wire diameter of about 1. 〇mi 1 and breaking strength below 丨〇g soft line; May then read the 3C figure, will pass through a second welding pin 2 焊 one The line 34〇 is formed by electronic ignition (Electronic Flame-Off, EF〇) or hydrogen flame (Hydr〇gen, so that the end of the wire 34 is sintered to form a ball end j, and then the ball end 341 is The pressing force is thermocompression welded to the cushioning convexity=30. In the present embodiment, the fresh wire 34 formed by the second welding is a hard wire having a wire diameter of about 1.0 mil and a breaking strength of 14 g or less. The buffering bumps 330 and the bonding wires 34 are made of different proportions of the f-position elements for proper softness adjustment so that the buffering bumps 33 are harder than the bonding wires 340. In order to achieve the soft buffering effect, the buffering convex system can absorb the vertical force of the ball bonding end 341 of the bonding wire 34, and the ball bonding end 341 can directly hit the wafer. The second said 310 (4) 'Please refer to FIG. 3D' to move the second fresh needle 20 to guide the wire 340 to the contact point 321 and heat-press the fresh wire H f321 with the second welding pin 2 So that the bonding wire 340 is soldered to the contact 32, and the soldering pad 312 and the contact 321 are connected in an arc shape compared with the two-off line 340; The material 9 Π A + aw 々 一 一 卸 在 在 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321 321福 个 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , 313, the wafer carrier 32〇1252571 5. The invention (6) has a plurality of contacts 321 formed on the pads 312 of the wafer 310, each of the bonding wires 340 having a ball end 341 and a tail end 342 are connected to the corresponding buffer bumps 330, and the tail ends 342 are connected to the corresponding contacts 32i, that is, the soldering The line 340 is connected to the buffer bumps 33 〇 and the wafer carrier 32 对 corresponds to the contacts 3 2 1 . 〜 In the above-mentioned wire bonding process, since the buffer bumps 33 are first formed on the pads 312. Therefore, when the second soldering pin 2 is thermally pressed and welded to the buffer bump 33 by the hardened wire 34 〇, the slow 3〇 painting is avoided. §Hai Xian 塾 31 2 directly withstands the thermal compositing of the ball end 341 when the pad 312 is damaged; 1 because the wire connection 4 = 匕 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线 线Strong. In addition, the length of the line is long, and its resistance to mold flow can be determined by the full scope of the invention. Anyone who knows this skill: After:: Any changes and repairs made within the scope defined by the scope of application for patents The spirit and scope of the present invention are within the scope of the present invention.

尺l%中一晶片之截 — 在習知堆疊凸彿夕士〜在,戴面不意圖； 且凸塊之打線製程中一日u 1252571 圖式簡單說明 【圖式簡單說明】 第1A至1B圖 第2A至2C圖 示意圖；及 日日片之戴面 第3A至3E圖 截面示意圖 依本發明之一 打線製程，一 片在製程中之 元件符號簡單說明 10 第一銲針 1 0 0 打線連接之半 11 0 晶片 120晶片載板 130 銲針 140 銲線 2 0 0打線在堆疊凸 2 1 0 晶片 2 2 0承載器 231第一凸塊 240 導線 3 0 0 打線連接之半 3 1 0晶片 3 1 3 保護層 3 2 0晶片載板 3 3 0緩衝凸塊 2 0 第二銲針 導體裝置 111 銲墊 1 2 1接點 1 41 結球端 塊上之半導體裝置 211 銲墊 221接點 232 第二凸塊 2 4 1 結球端 導體裝置 311 介電層 3 2 1接點The cut of a wafer in the ruler l% - in the conventional stacking convex Buddha ~ in, wearing the face is not intended; and the bumping process in the day u 1252571 simple description [simplified diagram] 1A to 1B 2A to 2C are schematic views; and the cross-sectional views of the 3D to 3E drawings of the Japanese film are in accordance with one of the wire-drawing processes of the present invention, and a component symbol in the process is simply described. 10 The first soldering pin 1 0 0 is connected by a wire. Half 11 0 wafer 120 wafer carrier 130 solder pin 140 bonding wire 2 0 0 wire in stacking convex 2 1 0 2 2 0 carrier 231 first bump 240 wire 3 0 wire bonding half 3 1 0 wafer 3 1 3 protective layer 3 2 0 wafer carrier 3 3 0 buffer bump 2 0 second soldering conductor device 111 pad 1 2 1 contact 1 41 semiconductor device 211 on the ball end block pad 221 contact 232 second convex Block 2 4 1 ball end conductor device 311 dielectric layer 3 2 1 contact

142尾端 M2尾端 312銲墊142 end M2 tail 312 pad

1252571 圖式簡單說明 340 銲線 3 41 結球端 342 尾端 l^n 第13頁1252571 Simple description of the drawing 340 Bonding wire 3 41 Ball end 342 End l^n Page 13

Claims (1)

12525711252571 六、申請專利範圍 【申請專利範圍】 1、一種打線製程，包含： 提供一晶片，該晶片係具有至少一銲墊； 提供一晶片載板，該晶片載板係具有至少一對應該銲 墊之接點； 形成一緩衝凸塊於該晶片之該銲墊；及 打線形成一銲線，該銲線係具有一結球端及一尾端， 該結球端係連接於對應之該緩衝凸塊，該尾端係連接於對 應之^接點’以連接該緩衝凸塊與該晶片載板之該接點， 其中4緩衝凸塊之硬度係小於該銲線之硬度，以避免打線 時該晶片受損。 2、 如申請 凸塊係以打 3、 如申請 係為ΙίΛ低介 4、 如申請 係包含有至 介電常數介 5、 一種打 曰曰 片 一晶片 複數個 複數個 尾端，該 專利範圍第1項所述之打線製程 線形成。 專利範圍第1項所述之打線製程 電常數（low-K)製程形成之晶片 專利乾圍第3項所述之打線製程 夕低介電常數介電層，該銲墊係形成於該低 電層上。 線連接之半導體裝置，包含： ’其係具有複數個銲墊；其係具有複數個對應該些銲墊之接點； 打後开，ϊ，其係形成於該晶片之該些銲墊；及 線，每—辉線係具有-結球端及 ；〃連接於對應之該些緩衝凸塊，該些 其中該緩衝 其中該晶片 其中該晶片Scope of application for patents [Scope of application] 1. A wire bonding process comprising: providing a wafer having at least one pad; providing a wafer carrier having at least one pair of pads a bonding pad is formed on the pad of the wafer; and the bonding wire forms a bonding wire, the bonding wire has a ball end and a tail end, and the ball end is connected to the corresponding buffering bump, The tail end is connected to the corresponding contact point ' to connect the buffer bump to the contact point of the wafer carrier, wherein the hardness of the 4 buffer bump is less than the hardness of the bonding wire to avoid damage of the wafer when the wire is wound . 2. If applying for a bump to play 3, if the application is for ΙίΛ, 4, if the application system contains a dielectric constant 5, a smashing chip, a plurality of wafer ends, the patent scope The wire-forming process line described in item 1 is formed. The wire-cut process electric constant (low-K) process described in the first aspect of the patent is formed by the low-k dielectric layer of the wire-cut process described in the third paragraph of the wafer patent dry circumference, and the pad is formed in the low-voltage On the floor. a wire-connected semiconductor device comprising: 'the system has a plurality of pads; the plurality of pads having a plurality of pads; the post-opening, ϊ, which are formed on the pads of the wafer; and a wire, each of which has a ball end; and a wire is connected to the corresponding buffer bumps, wherein the wafer is buffered therein 12525711252571 案號 93132004 六、申請專利範圍 尾端係連接於對應之該歧接 晶片載板之對應該此接點：中；；接該些緩衝凸塊與該 於該些銲線之硬度丨中該些緩衝凸塊之硬度係小 置 圍第5項所述之打線連接之半導體裝 八中β亥二緩衝凸塊係以打線形成。 置 片 如申明專利範圍第5項所述之打線連接之半導體裝 其中該晶片係為以低介電常數（1〇w —κ)製程形成^晶 8、如申請專利範圍第7項所述之打線連接之半導體裝 置，其中該晶片係包含有至少一低介電常數介電層，該銲 墊係形成於該低介電常數介電層上。 9 ^Case No. 93132004 6. The end of the patent application range is connected to the corresponding contact wafer carrier corresponding to the contact: middle; and the buffer bumps and the hardness of the solder wires The hardness of the buffer bump is smaller than that of the wire-bonded semiconductor device described in item 5, which is formed by wire bonding. A semiconductor device according to the fifth aspect of the invention, wherein the wafer is formed by a low dielectric constant (1 〇 w — κ) process, as described in claim 7 A wire-bonded semiconductor device, wherein the wafer includes at least one low-k dielectric layer, the pad being formed on the low-k dielectric layer. 9 ^
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8134240B2 (en) 2006-07-27 2012-03-13 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method for the same
WO2017166308A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Wire bond connection with intermediate contact structure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8134240B2 (en) 2006-07-27 2012-03-13 Fujitsu Semiconductor Limited Semiconductor device and manufacturing method for the same
WO2017166308A1 (en) * 2016-04-01 2017-10-05 Intel Corporation Wire bond connection with intermediate contact structure
US10438916B2 (en) 2016-04-01 2019-10-08 Intel Corporation Wire bond connection with intermediate contact structure

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