1252393 九、發明說明： 先前專利申請案 本專利申㈣主張源自在2GG3年9月8日提交之第2003_ 62863號韓國專利案的㈣權，該專利申請案在此納 入供參酌。 【發明所屬之技術領域】 本發明係關於__種展頻時脈產生器與—種產生展頻時脈 之方法。 【先前技術】 諸如圖1中的丨0所示之時脈產生器一般包括一時脈源1〇〇 與鎖相環路（phase-locked loop PLL)l〇2。此產生器1〇產生 一般為方波且工作週期為50%的系統時脈。該系統時脈則 使用於許多種不同的系統中，譬如包括記憶體模組14和記 憶體控制器12的記憶體系統。 像這樣的糸統時脈是不利的電磁干擾（electr〇magnetk interference EMI)來源。電磁干擾會在電子電路中造成問 題’因為其會干擾信號的傳輸。隨著技術的進步，電路可 以更快的速率運作，也因此需要更快的時脈，從而產生更 多的電磁干擾。減輕電磁干擾的一種技術是使用展頻時脈 產生器（spread spectrum clock generators SSCG)。這此時 脈被稱為展頻的原因是其頻率擴展在不同的頻率上，從而 可避免時脈邊緣處的能量峰值。在某些情況下，展頻時脈 產生係使用下文所述之美國專利中所示的鎖相環路實 施。鎖相環路改變施加給一電壓控制震盪器（v〇ltage 95055.doc 1252393 controlled oscillator VCO)之電壓，從而改變時脈内的延遲 量。 此種方法之範例顯示於1997年5月20日頒發之第 5,631，920號美國專利；2001年9月18日頒發之第5,692,5〇7 號美國專利；與2002年2月26日頒發之第6,351，485號美國 專利。鎖相環路的使用一般是讓一時脈循環在兩個頻率極 限之間切換，在二頻率極限之間往返調整時脈頻率。這種 方法夕y有些限制，因為其僅容許使用兩個固定頻率而不 容許做編程控制。 另一種方法顯示於2002年12月 美國專利。如圖2中所示，此方法有兩個電容器，該二電 容器被使用當做由計數器—序列器2〇切換的負載，該計數 器一序列器由固定時脈（flxed clock fclk)做時脈驅動。計 數器一序列器20驅動第一控制信號CTU到第一負載切換 電晶體22之閘極，並驅動第二控制信號ctl2到第二負載 切換電晶體24之閘極。當CTL1為高電位時，電容器加 須在達到輸出緩衝器3 G的邏輯臨限值之前被輸人緩衝器2 8 充電與放電，從而延遲時脈邊緣。當CTL2為高電位時， 電容器二必須在達到輸出緩衝器3〇的邏輯臨限值之前被輸 入緩衝A 28充電與放電’從而也延遲時脈邊緣。當^⑴ 每CTL2 一者冑為高電位日夺，兩個電容器都必須被充電， 從而進—步延遲時脈邊緣。但是這些負載無法被線性改變 以隨需要調整時脈頻率。 【實施方式】 95055.doc 1252393 圖3顯示未調變時脈信號之問題癥結。 之能量尖波振幅可能超過已調變〜 ”文恰脈 幅2-8 dB。此差異造成了更高程度的磁：：時脈信號振 件與諸如記憶體㈣等系、統有負面影響。2而對電子零 係針對記憶體纟統零件與方法 ^之犯例 明，所以咬，*立女π na 仁”目的只在做範例說 所山本务明之應用不揭限於記憶體***。 此種系統的-個範例顯示於圖4中。時脈產生㈣ 一固定頻科脈FCLK，該時脈由展料脈^ 42使用。SSCG 42產生一展 (SC〇) Μ展頻盼脈’該展頻時脈則由電子 電路裝置44a-44n使用。在記憶體系統中，裝置仏·仏可 =㈣區段或記憶體模組或用來儲存資料之記憶 或暫存器。 圖5與6中顯示採用展頻時脈產生器之記憶體系統的替代 實施例。在圖5中，時脈產生㈣包括固定頻率時脈觸與 鎖相環路902。記憶體模組94包括個別的記憶體模組和展 頻時脈產生器904。 圖7以更詳細的實施例顯示展頻時脈產生器。在此種實 施例中’ SSCG 42有控制電路5G、可編程延遲電路52和暫 存器電路54 °暫存器電路54保有可對延遲電路52做編程控 制的控制碼。控制電路5G提供位址給暫存器電路^，而暫 存器電路54則提供控制碼給延遲電路。這使延遲電路可改 變施加給固定時脈FCLK的延遲時段長短，並從而改變時 脈頻率以減輕週期性時脈的電磁干擾程度。 可、、扁耘延遲電路可由許多組延遲構件之一來實施。圖心 95055.doc 1252393 與8b顯示兩種範例，但請注意其僅為延遲構件的範例。本 發明之實施例一般是提供可由暫存器電路提供之控制碼選 擇的之構件，以使能對展頻時脈產生器内之延遲做精確的 控制。在圖8a之範例中，延遲元件是反向安排的電容器， 譬如是NMOS與PMOS電容器。固定頻率時脈FCLK藉將輸 入緩衝器60反相而做緩衝。若FCLK信號為高位準，則反 相信號為低位準。這會使PMOS電容器62a，62b與62c的一 個端點上有一低位準信號。若某一構件之控制碼為低位 準，則該構件之PMOS電容會提供其電容之100%，從而使 延遲時段等於該構件之充電時間。 譬如，若控制碼C01為低位準，則電容器62a提供其電 容的100%，該100%電容在信號可遞交給輸出反相器66之 前必須被充電。若控制碼C01為高位準，則電容器62a提 供其電容的大約1/3，該1/3電容在信號可遞交給輸出反相 器66之前必須被充電。 若時脈信號FCLK為低位準，則反相器60之輸出為高位 準。這會使NMOS電容器64a-64c成為信號到達輸出反相器 66之前的導線負載。依此方法，延遲時間量可連同輸入時 脈信號FCLK由控制碼加以編程控制。 延遲電路的另一種範例顯示於圖8b中。此實施例中的各 延遲構件有諸如72a之存取電晶體和諸如74a之電容器。當 某一構件之控制碼為高位準時，存取電晶體導通且電容器 充電，從而造成一延遲。譬如，若控制碼C01為高位準， 則電晶體72a導通且電容器74a充電。這會造成信號從輸入 95055.doc 1252393 反相緩衝器70傳輸到輸出 出一個導通的電晶體就會 段增長。 反相緩衝器76的傳輸延遲。每多 曰加包4盗充電，藉此使延遲時 圖8a|4 8b之电谷為的電容值 ^辟丄 此都一樣，也可能電容值 都不一樣。譬如，各電容器 炙兄包呤間都可有等於一延遲 早位id。或者，各電容器 兄屯柃間也可加以控制以等 於一二進位等同量。譬如，，a，電定哭 私备裔之充電時間可等於一 延遲單位量d。’b’電容哭之右+ ^士 Ba 、私今°。之充電時間可等於延遲單位量的 兩倍，即2d或d+Ι。，c，電容器之充雪 口口 <元私¥間可等於延遲單位 量的四倍，即4d或d+3。 現在轉而描述SSCG之控制電路5〇，目9中顯示其一種實 施例。控制單元50可包括—分頻器8〇以產生_較低頻率的 時脈DFCLK與一位址產生器82。位址產生器可實施成一狀 態機器，纟中一新位址信號之輸出會造成該機器改變狀態 成為次一個狀態。所需之位址數目可為已知，因為控制碼 數值的組合一或控制字組一之數目是有限的。 吕如，可月b僅使用四個控制”字組來活化延遲電路。可 使用四個位址1000，0100，〇〇1〇與〇〇〇1。圖1〇中顯示產生該 等位址的位址產生器。當施加一重設信號rESEt時，位址 信號A1- A4被產生為1 〇〇〇。產生位址信號a 1之正反器因應 於一重設信號SE產生一高位準信號。一旦產生了位址信號 A1，只要被分頻之時脈DFCLK被觸發，A1信號之高位準 資料就被移位到次一位址信號。如此可形成信號A1-A4 0100, 0010與0001。當一正向致能信號FCON被致能時，這 95055.doc •10- 1252393 些信號以此順序被致能。 當最後一個位址A4(A1-A4 0001)被活化之後，一逆向致 能信號BCON被致能。這使A4信號之高位準資料可以相反 次序輸出’ A3，A2然後A1。所以，位址信號A1-A4被改變 成諸如00 10，01 (^與丨000之次序。切換可為正向切換 FSW1-FSW3或為逆向切換BSW1-BSW3。此種位址產生程 序被連續重複以便因應於被分頻之時脈DFCLK產生位址信 號。延遲負載的值可隨著邊緣變化而改變，這將於下文中 參考圖11討論。 在圖U中顯示用於位址產生之信號的時程圖。重設信號 開始該程序。該圖也顯示兩個時脈信號FCLK與被分頻之 時脈信號DFCLK。在此特定的實施例中，DFCLK之頻率 為固定時脈信號頻率之半。當然也可使用其他的頻率除 法。 正向控制與逆向控制信號FC0N與BC0N如圖1〇中所示般 由B2F與F2B信號產生。其相關計時信號如圖1〇中所示。 其結果之展頻時脈信號SSCLK有與其關聯之延遲。譬如， 時段T是目定㈣信號之週期加—延遲單㈣。力口至時脈信 说之延遲單位數目可被編程控制以根據系統設計者之需要 而改變。在圖11之範例中，時段丁+1之延遲時間為;時 段T+2之延遲時間為d+3，且時段丁+丨之延遲時間為权4。 當位址逆向循環時，延遲時間也逆向循環，如圖u中所示 般。 圖中所示的延遲由駐留在位址A1 - A 4内之控制信號決 95055.doc -11 - 1252393 定。下表以控制”字組，，鱼爱 、/、對應位址顯示控制 C02與C03。回頭看圖7， fiUOH， 图頌不提供給位址電路之位灿 σ上文所述般造成提供給 控制信號 C01 下 位址 0001 0 |〇 0010 ------ 1 0 ——-------- 0100 ---------— 1000 ------ --— 0 〇 ---——— -甘+ ^ 屹遲構件之特定控制碼。下表顯 不某些控制碼的範例。 衣，、、、負 C021252393 IX. STATEMENT OF RELATED APPLICATIONS: This patent application (4) claims to be derived from the (4) right of the Korean Patent No. 2003_62863 filed on September 8, 2, ug. 3, which is hereby incorporated by reference. TECHNICAL FIELD OF THE INVENTION The present invention relates to a method of generating a spread spectrum clock and a type of spread spectrum clock generator. [Prior Art] A clock generator such as 丨0 in Fig. 1 generally includes a clock source 1 〇〇 and a phase-locked loop PLL 〇2. This generator 1 produces a system clock that is typically a square wave with a duty cycle of 50%. The system clock is used in a variety of different systems, such as the memory system including memory module 14 and memory controller 12. A sinusoidal clock like this is a source of unfavorable electromagnetic interference (EMI). Electromagnetic interference can cause problems in electronic circuits because it can interfere with the transmission of signals. As technology advances, circuits can operate at a faster rate, and therefore require faster clocks, resulting in more electromagnetic interference. One technique for mitigating electromagnetic interference is to use spread spectrum clock generators (SSCG). The reason why this time pulse is called spread spectrum is that its frequency is spread at different frequencies, so that the energy peak at the edge of the clock can be avoided. In some cases, the spread spectrum clock generation is performed using a phase locked loop as shown in the U.S. patents described below. The phase-locked loop changes the voltage applied to a voltage-controlled oscillator (v〇ltage 95055.doc 1252393 controlled oscillator VCO), thereby changing the amount of delay in the clock. An example of such a method is shown in U.S. Patent No. 5,631,920 issued May 20, 1997; U.S. Patent No. 5,692,5,7, issued on September 18, 2001; issued on February 26, 2002 U.S. Patent No. 6,351,485. The use of a phase-locked loop typically allows a clock cycle to switch between two frequency limits, adjusting the clock frequency back and forth between the two frequency limits. This method is somewhat limited because it only allows the use of two fixed frequencies and does not allow for program control. Another method is shown in the December 2002 US patent. As shown in Figure 2, this method has two capacitors that are used as a load that is switched by a counter-serializer 2 that is clocked by a fixed clock (fxed clock fclk). The counter-sequencer 20 drives the first control signal CTU to the gate of the first load switching transistor 22 and drives the second control signal ctl2 to the gate of the second load switching transistor 24. When CTL1 is high, the capacitor must be charged and discharged by the input buffer 2 8 before reaching the logic threshold of the output buffer 3 G, thereby delaying the clock edge. When CTL2 is high, Capacitor 2 must be input to Buffer A 28 Charge and Discharge before reaching the logic threshold of Output Buffer 3〇, thereby also delaying the clock edge. When ^(1) is one of the high potentials per CTL2, both capacitors must be charged, thus delaying the edge of the clock. However, these loads cannot be linearly changed to adjust the clock frequency as needed. [Embodiment] 95055.doc 1252393 Figure 3 shows the problem of the unmodulated clock signal. The amplitude of the energy spike may exceed the amplitude of the modulated ~ ” Wencha pulse 2-8 dB. This difference causes a higher degree of magnetic:: the vibration of the clock signal and the system such as memory (4) have a negative impact. 2 For the electronic zero system for the memory system parts and methods ^ sin, so bite, * 立 female π na Ren" purpose is only to do the example that the application of Yamamoto is not limited to the memory system. An example of such a system is shown in Figure 4. The clock generates (4) a fixed frequency branch pulse FCLK, which is used by the material pulse 42. The SSCG 42 produces a display (SC〇), which is used by the electronic circuit devices 44a-44n. In a memory system, the device =·仏 can be (4) a segment or a memory module or a memory or register for storing data. An alternative embodiment of a memory system employing a spread spectrum clock generator is shown in Figures 5 and 6. In Fig. 5, the clock generation (4) includes a fixed frequency clock contact and a phase locked loop 902. The memory module 94 includes individual memory modules and a spread clock generator 904. Figure 7 shows a spread spectrum clock generator in a more detailed embodiment. In this embodiment, the SSCG 42 has a control circuit 5G, a programmable delay circuit 52, and a register circuit 54. The register circuit 54 holds a control code that can program the delay circuit 52. Control circuit 5G provides the address to the scratchpad circuit ^, while register circuit 54 provides the control code to the delay circuit. This allows the delay circuit to change the length of the delay period applied to the fixed clock FCLK and thereby change the clock frequency to mitigate the degree of electromagnetic interference from the periodic clock. The squaring delay circuit can be implemented by one of a plurality of sets of delay members. Figure 95055.doc 1252393 and 8b show two examples, but note that it is only an example of a delay component. Embodiments of the present invention generally provide a means for selection by a control code provided by a scratchpad circuit to enable precise control of delays in the spread spectrum clock generator. In the example of Figure 8a, the delay elements are reverse-arranged capacitors, such as NMOS and PMOS capacitors. The fixed frequency clock FCLK is buffered by inverting the input buffer 60. If the FCLK signal is at a high level, the inverted signal is at a low level. This causes a low level signal at one end of the PMOS capacitors 62a, 62b and 62c. If the control code of a component is low, the PMOS capacitor of the component provides 100% of its capacitance, so that the delay period is equal to the charging time of the component. For example, if control code C01 is low, capacitor 62a provides 100% of its capacitance, which must be charged before the signal can be delivered to output inverter 66. If control code C01 is high, capacitor 62a provides approximately 1/3 of its capacitance, which must be charged before the signal can be delivered to output inverter 66. If the clock signal FCLK is at a low level, the output of the inverter 60 is at a high level. This causes the NMOS capacitors 64a-64c to become the wire load before the signal reaches the output inverter 66. In this way, the amount of delay time can be programmed by the control code in conjunction with the input clock signal FCLK. Another example of a delay circuit is shown in Figure 8b. Each of the delay members in this embodiment has an access transistor such as 72a and a capacitor such as 74a. When the control code of a component is high, the access transistor is turned on and the capacitor is charged, causing a delay. For example, if the control code C01 is at a high level, the transistor 72a is turned on and the capacitor 74a is charged. This causes the signal to travel from the input 95055.doc 1252393 inverting buffer 70 to the output of a conducting transistor. The transmission delay of the inverting buffer 76. Each additional packet is charged with a thief, so that the capacitance value of the electric valley of Fig. 8a|4 8b is delayed. The same is true, and the capacitance values may be different. For example, each capacitor can have a delay equal to the early id. Alternatively, the capacitors can be controlled to wait for a binary equivalent. For example, a, the electric crying private charging time can be equal to a delay unit amount d. 'b' Capacitor Cries Right + ^ Ba Ba, Private Today °. The charging time can be equal to twice the delay unit amount, ie 2d or d+Ι. , c, capacitor snow filling mouth < yuan private ¥ can be equal to four times the delay unit, that is, 4d or d + 3. Turning now to the control circuit 5 of the SSCG, an embodiment thereof is shown in FIG. Control unit 50 may include a divider 〇 to generate _lower frequency clock DFCLK and address generator 82. The address generator can be implemented as a state machine, and the output of a new address signal in the frame causes the machine to change state to the next state. The number of addresses required may be known because the combination of control code values or the number of control blocks one is limited. Lu Ru, can use only four control "words to activate the delay circuit. Four addresses 1000, 0100, 〇〇1〇 and 〇〇〇1 can be used. Figure 1〇 shows the generation of these addresses. Address generator: When a reset signal rESEt is applied, the address signals A1 - A4 are generated as 1 〇〇〇. The flip-flop generating the address signal a 1 generates a high level signal in response to a reset signal SE. The address signal A1 is generated, and as long as the divided frequency clock DFCLK is triggered, the high level data of the A1 signal is shifted to the secondary address signal. Thus, signals A1-A4 0100, 0010 and 0001 can be formed. When the forward enable signal FCON is enabled, these signals are enabled in this order. When the last address A4 (A1-A4 0001) is activated, a reverse enable signal BCON is enabled. This enables the high level data of the A4 signal to output 'A3, A2 and then A1 in reverse order. Therefore, the address signals A1-A4 are changed to such as 00 10, 01 (the order of ^ and 丨000. The switching can be Forward switching FSW1-FSW3 or reverse switching BSW1-BSW3. This address generation procedure is repeated continuously The address signal is generated in response to the divided clock DFCLK. The value of the delayed load may change as the edge changes, as will be discussed below with reference to Figure 11. The signal for address generation is shown in Figure U. Time-history diagram. The reset signal begins the program. The figure also shows two clock signals FCLK and the divided clock signal DFCLK. In this particular embodiment, the frequency of DFCLK is half of the fixed clock signal frequency. Other frequency divisions can of course be used. The forward and reverse control signals FC0N and BC0N are generated by the B2F and F2B signals as shown in Figure 1A. The associated timing signals are shown in Figure 1A. The spread-spectrum clock signal SSCLK has a delay associated with it. For example, the time period T is the period (four) of the signal plus-delay single (four). The number of delay units of the force-to-clock signal can be programmed to be controlled according to the system designer. In the example of Fig. 11, the delay time of the period +1 is: the delay time of the period T+2 is d+3, and the delay time of the period 丨+丨 is the weight 4. When the address is reversed , the delay time is also reversed, as shown in the figure The delay shown in the figure is determined by the control signal residing in addresses A1 - A 4 by 95055.doc -11 - 1252393. The following table controls the "word group, fish love, /, corresponding The address display controls C02 and C03. Looking back at Figure 7, fiUOH, Figure 颂 is not provided to the address circuit. The σ is supplied to the control signal C01 under the address 0001 0 |〇0010 ----- - 1 0 ———————— 0100 ---------— 1000 ------ --- 0 〇---———— - Gan + ^ Specific control code. The table below shows examples of some control codes. Clothing,,,, and negative C02
此特別範例假設如圖8a_b中所示般有三個延遲構件。 但請注意可使用任何數目個延遲構件，也可使用任何數目 個控制碼。此外’控制碼的性質本身也是可改變的。控制 碼可為延遲時間的—& Y t _ 1 進位表不法，其中001的延遲控制碼 曰化成1的延遲，而100的延遲控制碼則造成4的延遲。 或者控制碼也可為等權重的表示法。控制碼i〇〇可為2This particular example assumes that there are three delay members as shown in Figures 8a-b. However, please note that any number of delay components can be used, and any number of control codes can be used. Furthermore, the nature of the 'control code itself is also changeable. The control code can be a delay time -& Y t _ 1 carry table, where the delay control code of 001 is degraded to a delay of 1, and the delay control code of 100 causes a delay of 4. Or the control code can also be an equal weight representation. The control code i〇〇 can be 2
95055.doc 1252393 控制碼均可代表延遲的重 不論是二種情況中的哪一種 複次數。 、 曰存器電路可予以略去， 當做控制碼。但是，铲样奋,站 而使用位址 乂樣會少掉—階的調變 一階調變功能可增加延遲 右有这 暫存器電路可被重新編程戋 “ 狂及以新的暫存器電路取 新的暫存n電路對預定位址可有不同的值。 μ 假設希望與位址〇〇〇丨關聯之延 f+ 1右I*、f π # i 為而非0。則可能容許 I、有上述控制碼之既有暫存器電路做移除或重新編程， 因為暫存Μ路從絲產生器分離。暫存器電路可為任何 類型之非揮發記憶體，像是電子可消除可編程唯讀記憶體 (⑽滅 elect職lcally programmable read only memory eeprom)、保險絲陣列、電子可編程唯讀記憶體 (EPR0M)、唯讀記憶體（ROM)等。 上文已經舉例說明並描述本發明之實施例的原理之後， 熟習本技術領域者可輕易地了解該等實施例可在結構上與 細節上做修改而不悖離這些原理。本發明之申請專利範圍 主張之範圍包括所有在所附申請專利範圍之精神與範疇内 之修改。 【圖式簡單說明】 本發明的前述與其他目的、特徵、和優點可從具體實例 的詳細描述而更輕易地了解，該具體實例引用了下列圖 式0 圖1顯示記憶體系統的一種以前技術實施例。 95055.doc -13 - 1252393 圖2顯+尸 ^、展頻時脈產生器的一種以前技術實施例。 圖3暴畐- μ ♦π不與時脈產生器關聯之能量脈衝的信號圖。 圖4蒸盲- 士 Μ、、不根據本發明之記憶體系統的一種實施例。 圖5昌盲； ·、、、…、使用根據本發明之展頻時脈產生器的記憶體系 統之〜種實施例。 Θ .、、、員示使用根據本發明之展頻時脈產生器的記憶體系 統之—種替代實施例。 圖7頭不根據本發明之展頻時脈產生器的一種實施例。 圖8a-8b顯示根據本發明之延遲電路的替代實施例。 圖9顯示根據本發明之展頻時脈產生器的控制電路之一 種實施例。 圖10顯示根據本發明之位址產生器的一種實施例。 圖11顯示根據本發明之展頻時脈產生器的計時圖。 【主要元件符號說明】 10 時脈產生器 12 記憶體控制器 14 記憶體模組 20 計數器一序列器 22 第一負載切換電晶體 24 弟一負載切換電晶體 26, 32 電容器 28 輸入緩衝器 30 輸出緩衝器 40 固定時脈產生器 95055.doc -14- 1252393 42 展頻時脈產生 器 44a， 44b， ···，44n 電子電路裝置 50 控制電路 52 可編程延遲電 路 54 暫存器電路 60 輸入緩衝器 62a， 62b， 62c PMOS電容器 64a， 64b， 64c NMOS電容器 66 輸出反相器 70 輸入反相緩衝 器 72a， 72b， 72c 存取電晶體 74a， 74b， 74c 電容器 76 輸出反相緩衝 器 80 分頻器 82 位址產生器 90 時脈產生器 92 記憶體控制器 94 記憶體模組 100 時脈源 102 鎖相環路 900 固定頻率時脈 902 鎖相環路 904 展頻時脈產生 器 95055.doc -15-95055.doc 1252393 The control code can represent the weight of the delay, regardless of which of the two cases. The buffer circuit can be omitted as a control code. However, if the shovel is used, the station will use less address. The first-order modulation function can increase the delay. The register circuit can be reprogrammed. "The mad and new register." The circuit takes a new temporary n circuit that can have different values for the predetermined address. μ Suppose that the delay f + 1 right I*, f π # i that is associated with the address 〇〇〇丨 is not 0. The temporary control circuit with the above control code is removed or reprogrammed because the temporary circuit is separated from the wire generator. The register circuit can be any type of non-volatile memory, such as electronically erasable. Programming read-only memory ((10) ecally programmable read only memory eeprom), fuse array, electronically programmable read-only memory (EPR0M), read-only memory (ROM), etc. The invention has been exemplified and described above The principles of the embodiments can be readily understood by those skilled in the art that the embodiments can be modified in structure and details without departing from the principles. Patent application scope BRIEF DESCRIPTION OF THE DRAWINGS [0009] The foregoing and other objects, features, and advantages of the present invention will be more readily understood from the Detailed Description of Description A prior art embodiment of a volume system. 95055.doc -13 - 1252393 Figure 2 shows a prior art embodiment of a sinusoidal, spread-spectrum clock generator. Figure 3 畐 畐 - μ ♦ π not with the clock generator Figure 4 is a diagram of the energy pulse of the associated energy. Figure 4: An example of a memory system not according to the present invention. Figure 5 is a blind; (,,, ..., using a spread spectrum clock according to the present invention) An embodiment of the memory system of the generator. An alternative embodiment of the memory system using the spread spectrum clock generator according to the present invention is shown. Figure 7 is not an exhibition according to the present invention. An embodiment of a frequency clock generator. Figures 8a-8b show an alternate embodiment of a delay circuit in accordance with the present invention.Figure 9 shows an embodiment of a control circuit for a spread spectrum clock generator in accordance with the present invention. According to the invention An embodiment of an address generator. Figure 11 shows a timing diagram of a spread spectrum clock generator according to the present invention. [Key element symbol description] 10 clock generator 12 memory controller 14 memory module 20 counter-sequence The first load switching transistor 24 is a load switching transistor 26, 32 capacitor 28 input buffer 30 output buffer 40 fixed clock generator 95055.doc -14- 1252393 42 spread spectrum clock generator 44a, 44b , ···, 44n electronic circuit device 50 control circuit 52 programmable delay circuit 54 register circuit 60 input buffer 62a, 62b, 62c PMOS capacitor 64a, 64b, 64c NMOS capacitor 66 output inverter 70 input inverting buffer 72a, 72b, 72c access transistor 74a, 74b, 74c capacitor 76 output inverting buffer 80 frequency divider 82 address generator 90 clock generator 92 memory controller 94 memory module 100 clock source 102 phase-locked loop 900 fixed frequency clock 902 phase-locked loop 904 spread spectrum clock production Health 95055.doc -15-